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Greg Kroah-Hartmanb2441312017-11-01 15:07:57 +01001/* SPDX-License-Identifier: GPL-2.0 */
Jiri Olsaacbe6132016-02-15 09:34:34 +01002#ifndef __PERF_MEM_EVENTS_H
3#define __PERF_MEM_EVENTS_H
4
5#include <stdbool.h>
Jiri Olsaaadddd62016-09-22 17:36:30 +02006#include <stdint.h>
7#include <stdio.h>
8#include <linux/types.h>
Arnaldo Carvalho de Melod3300a32019-08-30 15:09:54 -03009#include <linux/refcount.h>
10#include <linux/perf_event.h>
Jiri Olsaaadddd62016-09-22 17:36:30 +020011#include "stat.h"
Kan Liang2a57d402021-02-02 12:09:06 -080012#include "evsel.h"
Jiri Olsaacbe6132016-02-15 09:34:34 +010013
14struct perf_mem_event {
15 bool record;
Jiri Olsa54fbad52016-02-24 09:46:42 +010016 bool supported;
Jiri Olsace1e22b2016-02-15 09:34:35 +010017 const char *tag;
Jiri Olsaacbe6132016-02-15 09:34:34 +010018 const char *name;
Jiri Olsa54fbad52016-02-24 09:46:42 +010019 const char *sysfs_name;
Jiri Olsaacbe6132016-02-15 09:34:34 +010020};
21
Arnaldo Carvalho de Melod3300a32019-08-30 15:09:54 -030022struct mem_info {
23 struct addr_map_symbol iaddr;
24 struct addr_map_symbol daddr;
25 union perf_mem_data_src data_src;
26 refcount_t refcnt;
27};
28
Jiri Olsaacbe6132016-02-15 09:34:34 +010029enum {
30 PERF_MEM_EVENTS__LOAD,
31 PERF_MEM_EVENTS__STORE,
Leo Yan4ba24522020-11-06 17:48:47 +080032 PERF_MEM_EVENTS__LOAD_STORE,
Jiri Olsaacbe6132016-02-15 09:34:34 +010033 PERF_MEM_EVENTS__MAX,
34};
35
Jiri Olsab0d745b2016-06-14 20:19:11 +020036extern unsigned int perf_mem_events__loads_ldlat;
Jiri Olsaacbe6132016-02-15 09:34:34 +010037
Jiri Olsace1e22b2016-02-15 09:34:35 +010038int perf_mem_events__parse(const char *str);
Jiri Olsa54fbad52016-02-24 09:46:42 +010039int perf_mem_events__init(void);
Jiri Olsace1e22b2016-02-15 09:34:35 +010040
Jin Yaod2f327a2021-05-27 08:16:04 +080041char *perf_mem_events__name(int i, char *pmu_name);
Leo Yaneaf6aae2020-11-06 17:48:46 +080042struct perf_mem_event *perf_mem_events__ptr(int i);
Kan Liang2a57d402021-02-02 12:09:06 -080043bool is_mem_loads_aux_event(struct evsel *leader);
Jiri Olsa0c877d72016-02-24 09:46:46 +010044
Ian Rogersb027cc62020-05-07 15:06:04 -070045void perf_mem_events__list(void);
Jin Yao4a9086a2021-05-27 08:16:07 +080046int perf_mem_events__record_args(const char **rec_argv, int *argv_nr,
47 char **rec_tmp, int *tmp_nr);
Ian Rogersb027cc62020-05-07 15:06:04 -070048
Jiri Olsab1a5fbea2016-02-24 09:46:50 +010049int perf_mem__tlb_scnprintf(char *out, size_t sz, struct mem_info *mem_info);
Jiri Olsa96907562016-02-24 09:46:51 +010050int perf_mem__lvl_scnprintf(char *out, size_t sz, struct mem_info *mem_info);
Jiri Olsa149d7502016-02-24 09:46:52 +010051int perf_mem__snp_scnprintf(char *out, size_t sz, struct mem_info *mem_info);
Jiri Olsa8b0819c2016-02-24 09:46:53 +010052int perf_mem__lck_scnprintf(char *out, size_t sz, struct mem_info *mem_info);
Kan Lianga054c292021-02-02 12:09:07 -080053int perf_mem__blk_scnprintf(char *out, size_t sz, struct mem_info *mem_info);
Jiri Olsa69a77272016-02-24 09:46:49 +010054
Jiri Olsac19ac912016-02-24 09:46:54 +010055int perf_script__meminfo_scnprintf(char *bf, size_t size, struct mem_info *mem_info);
56
Jiri Olsaaadddd62016-09-22 17:36:30 +020057struct c2c_stats {
58 u32 nr_entries;
59
60 u32 locks; /* count of 'lock' transactions */
61 u32 store; /* count of all stores in trace */
62 u32 st_uncache; /* stores to uncacheable address */
63 u32 st_noadrs; /* cacheable store with no address */
64 u32 st_l1hit; /* count of stores that hit L1D */
65 u32 st_l1miss; /* count of stores that miss L1D */
66 u32 load; /* count of all loads in trace */
67 u32 ld_excl; /* exclusive loads, rmt/lcl DRAM - snp none/miss */
68 u32 ld_shared; /* shared loads, rmt/lcl DRAM - snp hit */
69 u32 ld_uncache; /* loads to uncacheable address */
70 u32 ld_io; /* loads to io address */
71 u32 ld_miss; /* loads miss */
72 u32 ld_noadrs; /* cacheable load with no address */
73 u32 ld_fbhit; /* count of loads hitting Fill Buffer */
74 u32 ld_l1hit; /* count of loads that hit L1D */
75 u32 ld_l2hit; /* count of loads that hit L2D */
76 u32 ld_llchit; /* count of loads that hit LLC */
77 u32 lcl_hitm; /* count of loads with local HITM */
78 u32 rmt_hitm; /* count of loads with remote HITM */
Jiri Olsadba8ab92016-11-21 22:33:29 +010079 u32 tot_hitm; /* count of loads with local and remote HITM */
Jiri Olsaaadddd62016-09-22 17:36:30 +020080 u32 rmt_hit; /* count of loads with remote hit clean; */
81 u32 lcl_dram; /* count of loads miss to local DRAM */
82 u32 rmt_dram; /* count of loads miss to remote DRAM */
Kan Liangd9d5d7672021-02-02 12:09:08 -080083 u32 blk_data; /* count of loads blocked by data */
84 u32 blk_addr; /* count of loads blocked by address conflict */
Ingo Molnar4d39c892021-03-23 17:09:15 +010085 u32 nomap; /* count of load/stores with no phys addrs */
Jiri Olsaaadddd62016-09-22 17:36:30 +020086 u32 noparse; /* count of unparsable data sources */
87};
88
89struct hist_entry;
90int c2c_decode_stats(struct c2c_stats *stats, struct mem_info *mi);
Jiri Olsa0a9a24c2016-09-22 17:36:31 +020091void c2c_add_stats(struct c2c_stats *stats, struct c2c_stats *add);
Jiri Olsaaadddd62016-09-22 17:36:30 +020092
Jiri Olsaacbe6132016-02-15 09:34:34 +010093#endif /* __PERF_MEM_EVENTS_H */