Greg Kroah-Hartman | b244131 | 2017-11-01 15:07:57 +0100 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0 |
Thomas Gleixner | a4633adc | 2006-06-29 02:24:48 -0700 | [diff] [blame] | 2 | /* |
Thomas Gleixner | a4633adc | 2006-06-29 02:24:48 -0700 | [diff] [blame] | 3 | * Copyright (C) 1992, 1998-2006 Linus Torvalds, Ingo Molnar |
| 4 | * Copyright (C) 2005-2006, Thomas Gleixner |
| 5 | * |
| 6 | * This file contains the IRQ-resend code |
| 7 | * |
| 8 | * If the interrupt is waiting to be processed, we try to re-run it. |
| 9 | * We can't directly run it from here since the caller might be in an |
| 10 | * interrupt-protected region. Not all irq controller chips can |
| 11 | * retrigger interrupts at the hardware level, so in those cases |
| 12 | * we allow the resending of IRQs via a tasklet. |
| 13 | */ |
| 14 | |
| 15 | #include <linux/irq.h> |
| 16 | #include <linux/module.h> |
| 17 | #include <linux/random.h> |
| 18 | #include <linux/interrupt.h> |
| 19 | |
| 20 | #include "internals.h" |
| 21 | |
| 22 | #ifdef CONFIG_HARDIRQS_SW_RESEND |
| 23 | |
| 24 | /* Bitmap to handle software resend of interrupts: */ |
Thomas Gleixner | c1ee626 | 2011-02-17 17:45:15 +0100 | [diff] [blame] | 25 | static DECLARE_BITMAP(irqs_resend, IRQ_BITMAP_BITS); |
Thomas Gleixner | a4633adc | 2006-06-29 02:24:48 -0700 | [diff] [blame] | 26 | |
| 27 | /* |
| 28 | * Run software resends of IRQ's |
| 29 | */ |
| 30 | static void resend_irqs(unsigned long arg) |
| 31 | { |
| 32 | struct irq_desc *desc; |
| 33 | int irq; |
| 34 | |
Yinghai Lu | 85c0f90 | 2008-08-19 20:49:47 -0700 | [diff] [blame] | 35 | while (!bitmap_empty(irqs_resend, nr_irqs)) { |
| 36 | irq = find_first_bit(irqs_resend, nr_irqs); |
Thomas Gleixner | a4633adc | 2006-06-29 02:24:48 -0700 | [diff] [blame] | 37 | clear_bit(irq, irqs_resend); |
Yinghai Lu | 08678b0 | 2008-08-19 20:50:05 -0700 | [diff] [blame] | 38 | desc = irq_to_desc(irq); |
Yunfeng Ye | eddf3e9 | 2019-09-04 20:46:25 +0800 | [diff] [blame] | 39 | if (!desc) |
| 40 | continue; |
Thomas Gleixner | 6a6de9e | 2006-06-29 02:24:51 -0700 | [diff] [blame] | 41 | local_irq_disable(); |
Thomas Gleixner | bd0b9ac | 2015-09-14 10:42:37 +0200 | [diff] [blame] | 42 | desc->handle_irq(desc); |
Thomas Gleixner | 6a6de9e | 2006-06-29 02:24:51 -0700 | [diff] [blame] | 43 | local_irq_enable(); |
Thomas Gleixner | a4633adc | 2006-06-29 02:24:48 -0700 | [diff] [blame] | 44 | } |
| 45 | } |
| 46 | |
| 47 | /* Tasklet to handle resend: */ |
| 48 | static DECLARE_TASKLET(resend_tasklet, resend_irqs, 0); |
| 49 | |
Thomas Gleixner | 1f85b1f | 2020-03-06 14:03:45 +0100 | [diff] [blame] | 50 | static int irq_sw_resend(struct irq_desc *desc) |
| 51 | { |
| 52 | unsigned int irq = irq_desc_get_irq(desc); |
| 53 | |
| 54 | /* |
| 55 | * Validate whether this interrupt can be safely injected from |
| 56 | * non interrupt context |
| 57 | */ |
| 58 | if (handle_enforce_irqctx(&desc->irq_data)) |
| 59 | return -EINVAL; |
| 60 | |
| 61 | /* |
| 62 | * If the interrupt is running in the thread context of the parent |
| 63 | * irq we need to be careful, because we cannot trigger it |
| 64 | * directly. |
| 65 | */ |
| 66 | if (irq_settings_is_nested_thread(desc)) { |
| 67 | /* |
| 68 | * If the parent_irq is valid, we retrigger the parent, |
| 69 | * otherwise we do nothing. |
| 70 | */ |
| 71 | if (!desc->parent_irq) |
| 72 | return -EINVAL; |
| 73 | irq = desc->parent_irq; |
| 74 | } |
| 75 | |
| 76 | /* Set it pending and activate the softirq: */ |
| 77 | set_bit(irq, irqs_resend); |
| 78 | tasklet_schedule(&resend_tasklet); |
| 79 | return 0; |
| 80 | } |
| 81 | |
| 82 | #else |
| 83 | static int irq_sw_resend(struct irq_desc *desc) |
| 84 | { |
| 85 | return -EINVAL; |
| 86 | } |
Thomas Gleixner | a4633adc | 2006-06-29 02:24:48 -0700 | [diff] [blame] | 87 | #endif |
| 88 | |
| 89 | /* |
| 90 | * IRQ resend |
| 91 | * |
| 92 | * Is called with interrupts disabled and desc->lock held. |
| 93 | */ |
Thomas Gleixner | acd26bc | 2020-03-06 14:03:47 +0100 | [diff] [blame] | 94 | int check_irq_resend(struct irq_desc *desc, bool inject) |
Thomas Gleixner | a4633adc | 2006-06-29 02:24:48 -0700 | [diff] [blame] | 95 | { |
Thomas Gleixner | da90921 | 2020-03-06 14:03:46 +0100 | [diff] [blame] | 96 | int err = 0; |
| 97 | |
Thomas Gleixner | a4633adc | 2006-06-29 02:24:48 -0700 | [diff] [blame] | 98 | /* |
Thomas Gleixner | 1f85b1f | 2020-03-06 14:03:45 +0100 | [diff] [blame] | 99 | * We do not resend level type interrupts. Level type interrupts |
| 100 | * are resent by hardware when they are still active. Clear the |
| 101 | * pending bit so suspend/resume does not get confused. |
Thomas Gleixner | 2464286 | 2007-08-12 15:46:35 +0000 | [diff] [blame] | 102 | */ |
Thomas Gleixner | d4dc0f9 | 2012-04-25 12:54:54 +0200 | [diff] [blame] | 103 | if (irq_settings_is_level(desc)) { |
| 104 | desc->istate &= ~IRQS_PENDING; |
Thomas Gleixner | 1f85b1f | 2020-03-06 14:03:45 +0100 | [diff] [blame] | 105 | return -EINVAL; |
Thomas Gleixner | d4dc0f9 | 2012-04-25 12:54:54 +0200 | [diff] [blame] | 106 | } |
Thomas Gleixner | 1f85b1f | 2020-03-06 14:03:45 +0100 | [diff] [blame] | 107 | |
Thomas Gleixner | 163ef30 | 2011-02-08 11:39:15 +0100 | [diff] [blame] | 108 | if (desc->istate & IRQS_REPLAY) |
Thomas Gleixner | 1f85b1f | 2020-03-06 14:03:45 +0100 | [diff] [blame] | 109 | return -EBUSY; |
| 110 | |
Thomas Gleixner | acd26bc | 2020-03-06 14:03:47 +0100 | [diff] [blame] | 111 | if (!(desc->istate & IRQS_PENDING) && !inject) |
Thomas Gleixner | da90921 | 2020-03-06 14:03:46 +0100 | [diff] [blame] | 112 | return 0; |
Thomas Gleixner | a4633adc | 2006-06-29 02:24:48 -0700 | [diff] [blame] | 113 | |
Thomas Gleixner | da90921 | 2020-03-06 14:03:46 +0100 | [diff] [blame] | 114 | desc->istate &= ~IRQS_PENDING; |
| 115 | |
| 116 | if (!desc->irq_data.chip->irq_retrigger || |
| 117 | !desc->irq_data.chip->irq_retrigger(&desc->irq_data)) |
| 118 | err = irq_sw_resend(desc); |
| 119 | |
| 120 | /* If the retrigger was successfull, mark it with the REPLAY bit */ |
| 121 | if (!err) |
| 122 | desc->istate |= IRQS_REPLAY; |
| 123 | return err; |
Thomas Gleixner | a4633adc | 2006-06-29 02:24:48 -0700 | [diff] [blame] | 124 | } |
Thomas Gleixner | acd26bc | 2020-03-06 14:03:47 +0100 | [diff] [blame] | 125 | |
| 126 | #ifdef CONFIG_GENERIC_IRQ_INJECTION |
| 127 | /** |
| 128 | * irq_inject_interrupt - Inject an interrupt for testing/error injection |
| 129 | * @irq: The interrupt number |
| 130 | * |
| 131 | * This function must only be used for debug and testing purposes! |
| 132 | * |
| 133 | * Especially on x86 this can cause a premature completion of an interrupt |
| 134 | * affinity change causing the interrupt line to become stale. Very |
| 135 | * unlikely, but possible. |
| 136 | * |
| 137 | * The injection can fail for various reasons: |
| 138 | * - Interrupt is not activated |
| 139 | * - Interrupt is NMI type or currently replaying |
| 140 | * - Interrupt is level type |
| 141 | * - Interrupt does not support hardware retrigger and software resend is |
| 142 | * either not enabled or not possible for the interrupt. |
| 143 | */ |
| 144 | int irq_inject_interrupt(unsigned int irq) |
| 145 | { |
| 146 | struct irq_desc *desc; |
| 147 | unsigned long flags; |
| 148 | int err; |
| 149 | |
| 150 | /* Try the state injection hardware interface first */ |
| 151 | if (!irq_set_irqchip_state(irq, IRQCHIP_STATE_PENDING, true)) |
| 152 | return 0; |
| 153 | |
| 154 | /* That failed, try via the resend mechanism */ |
| 155 | desc = irq_get_desc_buslock(irq, &flags, 0); |
| 156 | if (!desc) |
| 157 | return -EINVAL; |
| 158 | |
| 159 | /* |
| 160 | * Only try to inject when the interrupt is: |
| 161 | * - not NMI type |
| 162 | * - activated |
| 163 | */ |
| 164 | if ((desc->istate & IRQS_NMI) || !irqd_is_activated(&desc->irq_data)) |
| 165 | err = -EINVAL; |
| 166 | else |
| 167 | err = check_irq_resend(desc, true); |
| 168 | |
| 169 | irq_put_desc_busunlock(desc, flags); |
| 170 | return err; |
| 171 | } |
| 172 | EXPORT_SYMBOL_GPL(irq_inject_interrupt); |
| 173 | #endif |