Thomas Gleixner | 5b497af | 2019-05-29 07:18:09 -0700 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Dan Williams | 4d88a97 | 2015-05-31 14:41:48 -0400 | [diff] [blame] | 2 | /* |
| 3 | * Copyright(c) 2013-2015 Intel Corporation. All rights reserved. |
Dan Williams | 4d88a97 | 2015-05-31 14:41:48 -0400 | [diff] [blame] | 4 | */ |
| 5 | #ifndef __ND_H__ |
| 6 | #define __ND_H__ |
Dan Williams | 1f7df6f | 2015-06-09 20:13:14 -0400 | [diff] [blame] | 7 | #include <linux/libnvdimm.h> |
Dan Williams | 200c79d | 2016-03-22 00:22:16 -0700 | [diff] [blame] | 8 | #include <linux/badblocks.h> |
Dan Williams | f0dc089 | 2015-05-16 12:28:53 -0400 | [diff] [blame] | 9 | #include <linux/blkdev.h> |
Dan Williams | 4d88a97 | 2015-05-31 14:41:48 -0400 | [diff] [blame] | 10 | #include <linux/device.h> |
| 11 | #include <linux/mutex.h> |
| 12 | #include <linux/ndctl.h> |
Dan Williams | bf9bccc | 2015-06-17 17:14:46 -0400 | [diff] [blame] | 13 | #include <linux/types.h> |
Dan Williams | 7199946 | 2016-02-18 10:29:49 -0800 | [diff] [blame] | 14 | #include <linux/nd.h> |
Dan Williams | 4a826c8 | 2015-06-09 16:09:36 -0400 | [diff] [blame] | 15 | #include "label.h" |
Dan Williams | 4d88a97 | 2015-05-31 14:41:48 -0400 | [diff] [blame] | 16 | |
Dan Williams | 8c2f7e8 | 2015-06-25 04:20:04 -0400 | [diff] [blame] | 17 | enum { |
Vishal Verma | 5212e11 | 2015-06-25 04:20:32 -0400 | [diff] [blame] | 18 | /* |
| 19 | * Limits the maximum number of block apertures a dimm can |
| 20 | * support and is an input to the geometry/on-disk-format of a |
| 21 | * BTT instance |
| 22 | */ |
| 23 | ND_MAX_LANES = 256, |
Vishal Verma | fcae695 | 2015-06-25 04:22:39 -0400 | [diff] [blame] | 24 | INT_LBASIZE_ALIGNMENT = 64, |
Vishal Verma | 3ae3d67 | 2017-05-10 15:01:30 -0600 | [diff] [blame] | 25 | NVDIMM_IO_ATOMIC = 1, |
Dan Williams | 8c2f7e8 | 2015-06-25 04:20:04 -0400 | [diff] [blame] | 26 | }; |
| 27 | |
Dan Williams | 4d88a97 | 2015-05-31 14:41:48 -0400 | [diff] [blame] | 28 | struct nvdimm_drvdata { |
| 29 | struct device *dev; |
Dan Williams | 02881768 | 2017-08-29 18:28:18 -0700 | [diff] [blame] | 30 | int nslabel_size; |
Dan Williams | 4d88a97 | 2015-05-31 14:41:48 -0400 | [diff] [blame] | 31 | struct nd_cmd_get_config_size nsarea; |
| 32 | void *data; |
Dan Williams | 4a826c8 | 2015-06-09 16:09:36 -0400 | [diff] [blame] | 33 | int ns_current, ns_next; |
| 34 | struct resource dpa; |
Dan Williams | bf9bccc | 2015-06-17 17:14:46 -0400 | [diff] [blame] | 35 | struct kref kref; |
Dan Williams | 4d88a97 | 2015-05-31 14:41:48 -0400 | [diff] [blame] | 36 | }; |
| 37 | |
Dan Williams | e5ae3b2 | 2016-06-07 17:00:04 -0700 | [diff] [blame] | 38 | struct nd_region_data { |
| 39 | int ns_count; |
| 40 | int ns_active; |
Dan Williams | 595c730 | 2016-09-23 17:53:52 -0700 | [diff] [blame] | 41 | unsigned int hints_shift; |
Gustavo A. R. Silva | 9106137 | 2020-03-19 18:09:37 -0500 | [diff] [blame] | 42 | void __iomem *flush_wpq[]; |
Dan Williams | 3d88002 | 2015-05-31 15:02:11 -0400 | [diff] [blame] | 43 | }; |
| 44 | |
Dan Williams | 595c730 | 2016-09-23 17:53:52 -0700 | [diff] [blame] | 45 | static inline void __iomem *ndrd_get_flush_wpq(struct nd_region_data *ndrd, |
| 46 | int dimm, int hint) |
| 47 | { |
| 48 | unsigned int num = 1 << ndrd->hints_shift; |
| 49 | unsigned int mask = num - 1; |
| 50 | |
| 51 | return ndrd->flush_wpq[dimm * num + (hint & mask)]; |
| 52 | } |
| 53 | |
| 54 | static inline void ndrd_set_flush_wpq(struct nd_region_data *ndrd, int dimm, |
| 55 | int hint, void __iomem *flush) |
| 56 | { |
| 57 | unsigned int num = 1 << ndrd->hints_shift; |
| 58 | unsigned int mask = num - 1; |
| 59 | |
| 60 | ndrd->flush_wpq[dimm * num + (hint & mask)] = flush; |
| 61 | } |
| 62 | |
Dan Williams | 4a826c8 | 2015-06-09 16:09:36 -0400 | [diff] [blame] | 63 | static inline struct nd_namespace_index *to_namespace_index( |
| 64 | struct nvdimm_drvdata *ndd, int i) |
| 65 | { |
| 66 | if (i < 0) |
| 67 | return NULL; |
| 68 | |
| 69 | return ndd->data + sizeof_namespace_index(ndd) * i; |
| 70 | } |
| 71 | |
| 72 | static inline struct nd_namespace_index *to_current_namespace_index( |
| 73 | struct nvdimm_drvdata *ndd) |
| 74 | { |
| 75 | return to_namespace_index(ndd, ndd->ns_current); |
| 76 | } |
| 77 | |
| 78 | static inline struct nd_namespace_index *to_next_namespace_index( |
| 79 | struct nvdimm_drvdata *ndd) |
| 80 | { |
| 81 | return to_namespace_index(ndd, ndd->ns_next); |
| 82 | } |
| 83 | |
Dan Williams | 564e871 | 2017-06-03 18:30:43 +0900 | [diff] [blame] | 84 | unsigned sizeof_namespace_label(struct nvdimm_drvdata *ndd); |
| 85 | |
| 86 | #define namespace_label_has(ndd, field) \ |
| 87 | (offsetof(struct nd_namespace_label, field) \ |
| 88 | < sizeof_namespace_label(ndd)) |
| 89 | |
Dan Williams | 4a826c8 | 2015-06-09 16:09:36 -0400 | [diff] [blame] | 90 | #define nd_dbg_dpa(r, d, res, fmt, arg...) \ |
| 91 | dev_dbg((r) ? &(r)->dev : (d)->dev, "%s: %.13s: %#llx @ %#llx " fmt, \ |
| 92 | (r) ? dev_name((d)->dev) : "", res ? res->name : "null", \ |
| 93 | (unsigned long long) (res ? resource_size(res) : 0), \ |
| 94 | (unsigned long long) (res ? res->start : 0), ##arg) |
| 95 | |
Dan Williams | bf9bccc | 2015-06-17 17:14:46 -0400 | [diff] [blame] | 96 | #define for_each_dpa_resource(ndd, res) \ |
| 97 | for (res = (ndd)->dpa.child; res; res = res->sibling) |
| 98 | |
Dan Williams | 4a826c8 | 2015-06-09 16:09:36 -0400 | [diff] [blame] | 99 | #define for_each_dpa_resource_safe(ndd, res, next) \ |
| 100 | for (res = (ndd)->dpa.child, next = res ? res->sibling : NULL; \ |
| 101 | res; res = next, next = next ? next->sibling : NULL) |
| 102 | |
Vishal Verma | 5212e11 | 2015-06-25 04:20:32 -0400 | [diff] [blame] | 103 | struct nd_percpu_lane { |
| 104 | int count; |
| 105 | spinlock_t lock; |
| 106 | }; |
| 107 | |
Dan Williams | c4703ce | 2019-04-30 21:51:21 -0700 | [diff] [blame] | 108 | enum nd_label_flags { |
| 109 | ND_LABEL_REAP, |
| 110 | }; |
Dan Williams | ae8219f | 2016-09-19 16:04:21 -0700 | [diff] [blame] | 111 | struct nd_label_ent { |
| 112 | struct list_head list; |
Dan Williams | c4703ce | 2019-04-30 21:51:21 -0700 | [diff] [blame] | 113 | unsigned long flags; |
Dan Williams | ae8219f | 2016-09-19 16:04:21 -0700 | [diff] [blame] | 114 | struct nd_namespace_label *label; |
| 115 | }; |
| 116 | |
| 117 | enum nd_mapping_lock_class { |
| 118 | ND_MAPPING_CLASS0, |
| 119 | ND_MAPPING_UUID_SCAN, |
| 120 | }; |
| 121 | |
Dan Williams | 44c462e | 2016-09-19 16:38:50 -0700 | [diff] [blame] | 122 | struct nd_mapping { |
| 123 | struct nvdimm *nvdimm; |
Dan Williams | 44c462e | 2016-09-19 16:38:50 -0700 | [diff] [blame] | 124 | u64 start; |
| 125 | u64 size; |
Dan Williams | 401c0a1 | 2017-08-04 17:20:16 -0700 | [diff] [blame] | 126 | int position; |
Dan Williams | ae8219f | 2016-09-19 16:04:21 -0700 | [diff] [blame] | 127 | struct list_head labels; |
| 128 | struct mutex lock; |
Dan Williams | 44c462e | 2016-09-19 16:38:50 -0700 | [diff] [blame] | 129 | /* |
| 130 | * @ndd is for private use at region enable / disable time for |
| 131 | * get_ndd() + put_ndd(), all other nd_mapping to ndd |
| 132 | * conversions use to_ndd() which respects enabled state of the |
| 133 | * nvdimm. |
| 134 | */ |
| 135 | struct nvdimm_drvdata *ndd; |
| 136 | }; |
| 137 | |
Dan Williams | 1f7df6f | 2015-06-09 20:13:14 -0400 | [diff] [blame] | 138 | struct nd_region { |
| 139 | struct device dev; |
Dan Williams | 1b40e09 | 2015-05-01 13:34:01 -0400 | [diff] [blame] | 140 | struct ida ns_ida; |
Dan Williams | 8c2f7e8 | 2015-06-25 04:20:04 -0400 | [diff] [blame] | 141 | struct ida btt_ida; |
Dan Williams | e145574 | 2015-07-30 17:57:47 -0400 | [diff] [blame] | 142 | struct ida pfn_ida; |
Dan Williams | cd03412 | 2016-03-11 10:15:36 -0800 | [diff] [blame] | 143 | struct ida dax_ida; |
Dan Williams | 004f1af | 2015-08-24 19:20:23 -0400 | [diff] [blame] | 144 | unsigned long flags; |
Dan Williams | bf9bccc | 2015-06-17 17:14:46 -0400 | [diff] [blame] | 145 | struct device *ns_seed; |
Dan Williams | 8c2f7e8 | 2015-06-25 04:20:04 -0400 | [diff] [blame] | 146 | struct device *btt_seed; |
Dan Williams | e145574 | 2015-07-30 17:57:47 -0400 | [diff] [blame] | 147 | struct device *pfn_seed; |
Dan Williams | cd03412 | 2016-03-11 10:15:36 -0800 | [diff] [blame] | 148 | struct device *dax_seed; |
Dan Williams | 2522afb | 2020-01-30 12:06:23 -0800 | [diff] [blame] | 149 | unsigned long align; |
Dan Williams | 1f7df6f | 2015-06-09 20:13:14 -0400 | [diff] [blame] | 150 | u16 ndr_mappings; |
| 151 | u64 ndr_size; |
| 152 | u64 ndr_start; |
Dan Williams | 8fc5c73 | 2018-11-09 12:43:07 -0800 | [diff] [blame] | 153 | int id, num_lanes, ro, numa_node, target_node; |
Dan Williams | 1f7df6f | 2015-06-09 20:13:14 -0400 | [diff] [blame] | 154 | void *provider_data; |
Toshi Kani | 975750a | 2017-06-12 16:25:11 -0600 | [diff] [blame] | 155 | struct kernfs_node *bb_state; |
Dave Jiang | 6a6bef9 | 2017-04-07 15:33:20 -0700 | [diff] [blame] | 156 | struct badblocks bb; |
Dan Williams | eaf9615 | 2015-05-01 13:11:27 -0400 | [diff] [blame] | 157 | struct nd_interleave_set *nd_set; |
Vishal Verma | 5212e11 | 2015-06-25 04:20:32 -0400 | [diff] [blame] | 158 | struct nd_percpu_lane __percpu *lane; |
Pankaj Gupta | c5d4355 | 2019-07-05 19:33:22 +0530 | [diff] [blame] | 159 | int (*flush)(struct nd_region *nd_region, struct bio *bio); |
Gustavo A. R. Silva | 9106137 | 2020-03-19 18:09:37 -0500 | [diff] [blame] | 160 | struct nd_mapping mapping[]; |
Dan Williams | 1f7df6f | 2015-06-09 20:13:14 -0400 | [diff] [blame] | 161 | }; |
| 162 | |
Ross Zwisler | 047fc8a | 2015-06-25 04:21:02 -0400 | [diff] [blame] | 163 | struct nd_blk_region { |
| 164 | int (*enable)(struct nvdimm_bus *nvdimm_bus, struct device *dev); |
Ross Zwisler | 047fc8a | 2015-06-25 04:21:02 -0400 | [diff] [blame] | 165 | int (*do_io)(struct nd_blk_region *ndbr, resource_size_t dpa, |
| 166 | void *iobuf, u64 len, int rw); |
| 167 | void *blk_provider_data; |
| 168 | struct nd_region nd_region; |
| 169 | }; |
| 170 | |
Dan Williams | 4a826c8 | 2015-06-09 16:09:36 -0400 | [diff] [blame] | 171 | /* |
| 172 | * Lookup next in the repeating sequence of 01, 10, and 11. |
| 173 | */ |
| 174 | static inline unsigned nd_inc_seq(unsigned seq) |
| 175 | { |
| 176 | static const unsigned next[] = { 0, 2, 3, 1 }; |
| 177 | |
| 178 | return next[seq & 3]; |
| 179 | } |
Dan Williams | f524bf2 | 2015-05-30 12:36:02 -0400 | [diff] [blame] | 180 | |
Vishal Verma | 5212e11 | 2015-06-25 04:20:32 -0400 | [diff] [blame] | 181 | struct btt; |
Dan Williams | 8c2f7e8 | 2015-06-25 04:20:04 -0400 | [diff] [blame] | 182 | struct nd_btt { |
| 183 | struct device dev; |
| 184 | struct nd_namespace_common *ndns; |
Vishal Verma | 5212e11 | 2015-06-25 04:20:32 -0400 | [diff] [blame] | 185 | struct btt *btt; |
Dan Williams | 8c2f7e8 | 2015-06-25 04:20:04 -0400 | [diff] [blame] | 186 | unsigned long lbasize; |
Vishal Verma | abe8b4e | 2016-07-27 16:38:59 -0600 | [diff] [blame] | 187 | u64 size; |
Dan Williams | 8c2f7e8 | 2015-06-25 04:20:04 -0400 | [diff] [blame] | 188 | u8 *uuid; |
| 189 | int id; |
Vishal Verma | 14e4945 | 2017-06-28 14:25:00 -0600 | [diff] [blame] | 190 | int initial_offset; |
| 191 | u16 version_major; |
| 192 | u16 version_minor; |
Dan Williams | 8c2f7e8 | 2015-06-25 04:20:04 -0400 | [diff] [blame] | 193 | }; |
| 194 | |
Dan Williams | e145574 | 2015-07-30 17:57:47 -0400 | [diff] [blame] | 195 | enum nd_pfn_mode { |
| 196 | PFN_MODE_NONE, |
| 197 | PFN_MODE_RAM, |
| 198 | PFN_MODE_PMEM, |
| 199 | }; |
| 200 | |
| 201 | struct nd_pfn { |
| 202 | int id; |
| 203 | u8 *uuid; |
| 204 | struct device dev; |
Dan Williams | 315c562 | 2015-12-10 14:45:23 -0800 | [diff] [blame] | 205 | unsigned long align; |
Dan Williams | e145574 | 2015-07-30 17:57:47 -0400 | [diff] [blame] | 206 | unsigned long npfns; |
| 207 | enum nd_pfn_mode mode; |
| 208 | struct nd_pfn_sb *pfn_sb; |
| 209 | struct nd_namespace_common *ndns; |
| 210 | }; |
| 211 | |
Dan Williams | cd03412 | 2016-03-11 10:15:36 -0800 | [diff] [blame] | 212 | struct nd_dax { |
| 213 | struct nd_pfn nd_pfn; |
| 214 | }; |
| 215 | |
Aneesh Kumar K.V | 8f4b01f | 2019-10-31 16:27:41 +0530 | [diff] [blame] | 216 | static inline u32 nd_info_block_reserve(void) |
| 217 | { |
| 218 | return ALIGN(SZ_8K, PAGE_SIZE); |
| 219 | } |
| 220 | |
Dan Williams | 4d88a97 | 2015-05-31 14:41:48 -0400 | [diff] [blame] | 221 | enum nd_async_mode { |
| 222 | ND_SYNC, |
| 223 | ND_ASYNC, |
| 224 | }; |
| 225 | |
Vishal Verma | 41cd8b7 | 2015-06-25 04:21:52 -0400 | [diff] [blame] | 226 | int nd_integrity_init(struct gendisk *disk, unsigned long meta_size); |
Dan Williams | bf9bccc | 2015-06-17 17:14:46 -0400 | [diff] [blame] | 227 | void wait_nvdimm_bus_probe_idle(struct device *dev); |
Dan Williams | 4d88a97 | 2015-05-31 14:41:48 -0400 | [diff] [blame] | 228 | void nd_device_register(struct device *dev); |
| 229 | void nd_device_unregister(struct device *dev, enum nd_async_mode mode); |
Dan Williams | 7199946 | 2016-02-18 10:29:49 -0800 | [diff] [blame] | 230 | void nd_device_notify(struct device *dev, enum nvdimm_event event); |
Dan Williams | bf9bccc | 2015-06-17 17:14:46 -0400 | [diff] [blame] | 231 | int nd_uuid_store(struct device *dev, u8 **uuid_out, const char *buf, |
| 232 | size_t len); |
Dan Williams | b2c48f9 | 2017-08-11 17:36:54 -0700 | [diff] [blame] | 233 | ssize_t nd_size_select_show(unsigned long current_size, |
Dan Williams | 1b40e09 | 2015-05-01 13:34:01 -0400 | [diff] [blame] | 234 | const unsigned long *supported, char *buf); |
Dan Williams | b2c48f9 | 2017-08-11 17:36:54 -0700 | [diff] [blame] | 235 | ssize_t nd_size_select_store(struct device *dev, const char *buf, |
| 236 | unsigned long *current_size, const unsigned long *supported); |
Dan Williams | 4d88a97 | 2015-05-31 14:41:48 -0400 | [diff] [blame] | 237 | int __init nvdimm_init(void); |
Dan Williams | 3d88002 | 2015-05-31 15:02:11 -0400 | [diff] [blame] | 238 | int __init nd_region_init(void); |
Dan Williams | b3fde74 | 2017-06-04 10:18:39 +0900 | [diff] [blame] | 239 | int __init nd_label_init(void); |
Dan Williams | 4d88a97 | 2015-05-31 14:41:48 -0400 | [diff] [blame] | 240 | void nvdimm_exit(void); |
Dan Williams | 3d88002 | 2015-05-31 15:02:11 -0400 | [diff] [blame] | 241 | void nd_region_exit(void); |
Dan Williams | bf9bccc | 2015-06-17 17:14:46 -0400 | [diff] [blame] | 242 | struct nvdimm; |
Dan Williams | adbb682 | 2019-11-12 17:00:24 -0800 | [diff] [blame] | 243 | extern const struct attribute_group nd_device_attribute_group; |
Dan Williams | e2f6a0e | 2019-11-19 09:51:54 -0800 | [diff] [blame] | 244 | extern const struct attribute_group nd_numa_attribute_group; |
Dan Williams | e755799a | 2019-11-12 17:08:56 -0800 | [diff] [blame] | 245 | extern const struct attribute_group *nvdimm_bus_attribute_groups[]; |
Dan Williams | bf9bccc | 2015-06-17 17:14:46 -0400 | [diff] [blame] | 246 | struct nvdimm_drvdata *to_ndd(struct nd_mapping *nd_mapping); |
Toshi Kani | aee6598 | 2016-08-16 13:08:40 -0600 | [diff] [blame] | 247 | int nvdimm_check_config_data(struct device *dev); |
Dan Williams | 4d88a97 | 2015-05-31 14:41:48 -0400 | [diff] [blame] | 248 | int nvdimm_init_nsarea(struct nvdimm_drvdata *ndd); |
| 249 | int nvdimm_init_config_data(struct nvdimm_drvdata *ndd); |
Alexander Duyck | 2d657d1 | 2018-10-10 16:39:20 -0700 | [diff] [blame] | 250 | int nvdimm_get_config_data(struct nvdimm_drvdata *ndd, void *buf, |
| 251 | size_t offset, size_t len); |
Dan Williams | f524bf2 | 2015-05-30 12:36:02 -0400 | [diff] [blame] | 252 | int nvdimm_set_config_data(struct nvdimm_drvdata *ndd, size_t offset, |
| 253 | void *buf, size_t len); |
Dan Williams | 59e6473 | 2016-03-08 07:16:07 -0800 | [diff] [blame] | 254 | long nvdimm_clear_poison(struct device *dev, phys_addr_t phys, |
| 255 | unsigned int len); |
Dan Williams | a0e3745 | 2020-01-30 12:06:18 -0800 | [diff] [blame] | 256 | void nvdimm_set_labeling(struct device *dev); |
Dan Williams | 8f078b3 | 2017-05-04 14:01:24 -0700 | [diff] [blame] | 257 | void nvdimm_set_locked(struct device *dev); |
Dan Williams | d34cb80 | 2017-09-25 11:01:31 -0700 | [diff] [blame] | 258 | void nvdimm_clear_locked(struct device *dev); |
Dan Williams | 1cd7386 | 2019-01-19 08:45:56 -0800 | [diff] [blame] | 259 | int nvdimm_security_setup_events(struct device *dev); |
Dave Jiang | 4c6926a | 2018-12-06 12:40:01 -0800 | [diff] [blame] | 260 | #if IS_ENABLED(CONFIG_NVDIMM_KEYS) |
| 261 | int nvdimm_security_unlock(struct device *dev); |
| 262 | #else |
| 263 | static inline int nvdimm_security_unlock(struct device *dev) |
| 264 | { |
| 265 | return 0; |
| 266 | } |
| 267 | #endif |
Dan Williams | 8c2f7e8 | 2015-06-25 04:20:04 -0400 | [diff] [blame] | 268 | struct nd_btt *to_nd_btt(struct device *dev); |
Dan Williams | e145574 | 2015-07-30 17:57:47 -0400 | [diff] [blame] | 269 | |
| 270 | struct nd_gen_sb { |
| 271 | char reserved[SZ_4K - 8]; |
| 272 | __le64 checksum; |
| 273 | }; |
| 274 | |
| 275 | u64 nd_sb_checksum(struct nd_gen_sb *sb); |
Dan Williams | 8c2f7e8 | 2015-06-25 04:20:04 -0400 | [diff] [blame] | 276 | #if IS_ENABLED(CONFIG_BTT) |
Dan Williams | 200c79d | 2016-03-22 00:22:16 -0700 | [diff] [blame] | 277 | int nd_btt_probe(struct device *dev, struct nd_namespace_common *ndns); |
Dan Williams | 8c2f7e8 | 2015-06-25 04:20:04 -0400 | [diff] [blame] | 278 | bool is_nd_btt(struct device *dev); |
| 279 | struct device *nd_btt_create(struct nd_region *nd_region); |
| 280 | #else |
Dan Williams | e32bc72 | 2016-03-17 18:23:09 -0700 | [diff] [blame] | 281 | static inline int nd_btt_probe(struct device *dev, |
Dan Williams | 200c79d | 2016-03-22 00:22:16 -0700 | [diff] [blame] | 282 | struct nd_namespace_common *ndns) |
Dan Williams | 8c2f7e8 | 2015-06-25 04:20:04 -0400 | [diff] [blame] | 283 | { |
| 284 | return -ENODEV; |
| 285 | } |
| 286 | |
| 287 | static inline bool is_nd_btt(struct device *dev) |
| 288 | { |
| 289 | return false; |
| 290 | } |
| 291 | |
| 292 | static inline struct device *nd_btt_create(struct nd_region *nd_region) |
| 293 | { |
| 294 | return NULL; |
| 295 | } |
Dan Williams | 8c2f7e8 | 2015-06-25 04:20:04 -0400 | [diff] [blame] | 296 | #endif |
Dan Williams | e145574 | 2015-07-30 17:57:47 -0400 | [diff] [blame] | 297 | |
| 298 | struct nd_pfn *to_nd_pfn(struct device *dev); |
| 299 | #if IS_ENABLED(CONFIG_NVDIMM_PFN) |
Oliver O'Halloran | 0dd6964 | 2017-06-27 19:56:33 +1000 | [diff] [blame] | 300 | |
Aneesh Kumar K.V | f537669 | 2019-09-05 21:16:03 +0530 | [diff] [blame] | 301 | #define MAX_NVDIMM_ALIGN 4 |
Oliver O'Halloran | 0dd6964 | 2017-06-27 19:56:33 +1000 | [diff] [blame] | 302 | |
Dan Williams | 200c79d | 2016-03-22 00:22:16 -0700 | [diff] [blame] | 303 | int nd_pfn_probe(struct device *dev, struct nd_namespace_common *ndns); |
Dan Williams | e145574 | 2015-07-30 17:57:47 -0400 | [diff] [blame] | 304 | bool is_nd_pfn(struct device *dev); |
| 305 | struct device *nd_pfn_create(struct nd_region *nd_region); |
Dan Williams | cd03412 | 2016-03-11 10:15:36 -0800 | [diff] [blame] | 306 | struct device *nd_pfn_devinit(struct nd_pfn *nd_pfn, |
| 307 | struct nd_namespace_common *ndns); |
Dan Williams | c5ed926 | 2016-05-18 14:50:12 -0700 | [diff] [blame] | 308 | int nd_pfn_validate(struct nd_pfn *nd_pfn, const char *sig); |
Dan Williams | 78c81cc | 2019-11-06 19:56:41 -0800 | [diff] [blame] | 309 | extern const struct attribute_group *nd_pfn_attribute_groups[]; |
Dan Williams | e145574 | 2015-07-30 17:57:47 -0400 | [diff] [blame] | 310 | #else |
Dan Williams | 200c79d | 2016-03-22 00:22:16 -0700 | [diff] [blame] | 311 | static inline int nd_pfn_probe(struct device *dev, |
| 312 | struct nd_namespace_common *ndns) |
Dan Williams | e145574 | 2015-07-30 17:57:47 -0400 | [diff] [blame] | 313 | { |
| 314 | return -ENODEV; |
| 315 | } |
| 316 | |
| 317 | static inline bool is_nd_pfn(struct device *dev) |
| 318 | { |
| 319 | return false; |
| 320 | } |
| 321 | |
| 322 | static inline struct device *nd_pfn_create(struct nd_region *nd_region) |
| 323 | { |
| 324 | return NULL; |
| 325 | } |
Dan Williams | 32ab0a3f | 2015-08-01 02:16:37 -0400 | [diff] [blame] | 326 | |
Dan Williams | c5ed926 | 2016-05-18 14:50:12 -0700 | [diff] [blame] | 327 | static inline int nd_pfn_validate(struct nd_pfn *nd_pfn, const char *sig) |
Dan Williams | 32ab0a3f | 2015-08-01 02:16:37 -0400 | [diff] [blame] | 328 | { |
| 329 | return -ENODEV; |
| 330 | } |
Dan Williams | e145574 | 2015-07-30 17:57:47 -0400 | [diff] [blame] | 331 | #endif |
| 332 | |
Dan Williams | cd03412 | 2016-03-11 10:15:36 -0800 | [diff] [blame] | 333 | struct nd_dax *to_nd_dax(struct device *dev); |
| 334 | #if IS_ENABLED(CONFIG_NVDIMM_DAX) |
Dan Williams | c5ed926 | 2016-05-18 14:50:12 -0700 | [diff] [blame] | 335 | int nd_dax_probe(struct device *dev, struct nd_namespace_common *ndns); |
Dan Williams | cd03412 | 2016-03-11 10:15:36 -0800 | [diff] [blame] | 336 | bool is_nd_dax(struct device *dev); |
| 337 | struct device *nd_dax_create(struct nd_region *nd_region); |
| 338 | #else |
Dan Williams | c5ed926 | 2016-05-18 14:50:12 -0700 | [diff] [blame] | 339 | static inline int nd_dax_probe(struct device *dev, |
| 340 | struct nd_namespace_common *ndns) |
| 341 | { |
| 342 | return -ENODEV; |
| 343 | } |
| 344 | |
Dan Williams | cd03412 | 2016-03-11 10:15:36 -0800 | [diff] [blame] | 345 | static inline bool is_nd_dax(struct device *dev) |
| 346 | { |
| 347 | return false; |
| 348 | } |
| 349 | |
| 350 | static inline struct device *nd_dax_create(struct nd_region *nd_region) |
| 351 | { |
| 352 | return NULL; |
| 353 | } |
| 354 | #endif |
| 355 | |
Dan Williams | 3d88002 | 2015-05-31 15:02:11 -0400 | [diff] [blame] | 356 | int nd_region_to_nstype(struct nd_region *nd_region); |
| 357 | int nd_region_register_namespaces(struct nd_region *nd_region, int *err); |
Dan Williams | c12c48c | 2017-06-04 10:59:15 +0900 | [diff] [blame] | 358 | u64 nd_region_interleave_set_cookie(struct nd_region *nd_region, |
| 359 | struct nd_namespace_index *nsindex); |
Dan Williams | 86ef58a | 2017-02-28 18:32:48 -0800 | [diff] [blame] | 360 | u64 nd_region_interleave_set_altcookie(struct nd_region *nd_region); |
Dan Williams | 3d88002 | 2015-05-31 15:02:11 -0400 | [diff] [blame] | 361 | void nvdimm_bus_lock(struct device *dev); |
| 362 | void nvdimm_bus_unlock(struct device *dev); |
| 363 | bool is_nvdimm_bus_locked(struct device *dev); |
Christoph Hellwig | 32f61d6 | 2020-09-01 17:57:47 +0200 | [diff] [blame] | 364 | void nvdimm_check_and_set_ro(struct gendisk *disk); |
Dan Williams | bf9bccc | 2015-06-17 17:14:46 -0400 | [diff] [blame] | 365 | void nvdimm_drvdata_release(struct kref *kref); |
| 366 | void put_ndd(struct nvdimm_drvdata *ndd); |
Dan Williams | 4a826c8 | 2015-06-09 16:09:36 -0400 | [diff] [blame] | 367 | int nd_label_reserve_dpa(struct nvdimm_drvdata *ndd); |
| 368 | void nvdimm_free_dpa(struct nvdimm_drvdata *ndd, struct resource *res); |
| 369 | struct resource *nvdimm_allocate_dpa(struct nvdimm_drvdata *ndd, |
| 370 | struct nd_label_id *label_id, resource_size_t start, |
| 371 | resource_size_t n); |
Dan Williams | 8c2f7e8 | 2015-06-25 04:20:04 -0400 | [diff] [blame] | 372 | resource_size_t nvdimm_namespace_capacity(struct nd_namespace_common *ndns); |
Dan Williams | 08e6b3c | 2018-06-13 09:08:36 -0700 | [diff] [blame] | 373 | bool nvdimm_namespace_locked(struct nd_namespace_common *ndns); |
Dan Williams | 8c2f7e8 | 2015-06-25 04:20:04 -0400 | [diff] [blame] | 374 | struct nd_namespace_common *nvdimm_namespace_common_probe(struct device *dev); |
Vishal Verma | 5212e11 | 2015-06-25 04:20:32 -0400 | [diff] [blame] | 375 | int nvdimm_namespace_attach_btt(struct nd_namespace_common *ndns); |
Dan Williams | 298f2bc | 2016-03-15 16:41:04 -0700 | [diff] [blame] | 376 | int nvdimm_namespace_detach_btt(struct nd_btt *nd_btt); |
Vishal Verma | 5212e11 | 2015-06-25 04:20:32 -0400 | [diff] [blame] | 377 | const char *nvdimm_namespace_disk_name(struct nd_namespace_common *ndns, |
| 378 | char *name); |
Dan Williams | f979b13 | 2017-06-04 12:12:07 +0900 | [diff] [blame] | 379 | unsigned int pmem_sector_size(struct nd_namespace_common *ndns); |
Dan Williams | a4574f6 | 2020-10-13 16:50:29 -0700 | [diff] [blame] | 380 | struct range; |
Dan Williams | a390180 | 2016-04-07 20:02:06 -0700 | [diff] [blame] | 381 | void nvdimm_badblocks_populate(struct nd_region *nd_region, |
Dan Williams | a4574f6 | 2020-10-13 16:50:29 -0700 | [diff] [blame] | 382 | struct badblocks *bb, const struct range *range); |
Aneesh Kumar K.V | 8f4b01f | 2019-10-31 16:27:41 +0530 | [diff] [blame] | 383 | int devm_namespace_enable(struct device *dev, struct nd_namespace_common *ndns, |
| 384 | resource_size_t size); |
| 385 | void devm_namespace_disable(struct device *dev, |
| 386 | struct nd_namespace_common *ndns); |
Dan Williams | 200c79d | 2016-03-22 00:22:16 -0700 | [diff] [blame] | 387 | #if IS_ENABLED(CONFIG_ND_CLAIM) |
Aneesh Kumar K.V | e96f0bf | 2019-09-05 21:15:59 +0530 | [diff] [blame] | 388 | /* max struct page size independent of kernel config */ |
| 389 | #define MAX_STRUCT_PAGE_SIZE 64 |
Christoph Hellwig | e8d5134 | 2017-12-29 08:54:05 +0100 | [diff] [blame] | 390 | int nvdimm_setup_pfn(struct nd_pfn *nd_pfn, struct dev_pagemap *pgmap); |
Dan Williams | 200c79d | 2016-03-22 00:22:16 -0700 | [diff] [blame] | 391 | #else |
Christoph Hellwig | e8d5134 | 2017-12-29 08:54:05 +0100 | [diff] [blame] | 392 | static inline int nvdimm_setup_pfn(struct nd_pfn *nd_pfn, |
| 393 | struct dev_pagemap *pgmap) |
Dan Williams | ac515c0 | 2016-03-22 00:29:43 -0700 | [diff] [blame] | 394 | { |
Christoph Hellwig | e8d5134 | 2017-12-29 08:54:05 +0100 | [diff] [blame] | 395 | return -ENXIO; |
Dan Williams | ac515c0 | 2016-03-22 00:29:43 -0700 | [diff] [blame] | 396 | } |
Dan Williams | 200c79d | 2016-03-22 00:22:16 -0700 | [diff] [blame] | 397 | #endif |
Ross Zwisler | 047fc8a | 2015-06-25 04:21:02 -0400 | [diff] [blame] | 398 | int nd_blk_region_init(struct nd_region *nd_region); |
Dan Williams | e5ae3b2 | 2016-06-07 17:00:04 -0700 | [diff] [blame] | 399 | int nd_region_activate(struct nd_region *nd_region); |
Dan Williams | 200c79d | 2016-03-22 00:22:16 -0700 | [diff] [blame] | 400 | static inline bool is_bad_pmem(struct badblocks *bb, sector_t sector, |
| 401 | unsigned int len) |
| 402 | { |
| 403 | if (bb->count) { |
| 404 | sector_t first_bad; |
| 405 | int num_bad; |
| 406 | |
| 407 | return !!badblocks_check(bb, sector, len / 512, &first_bad, |
| 408 | &num_bad); |
| 409 | } |
| 410 | |
| 411 | return false; |
| 412 | } |
Ross Zwisler | 047fc8a | 2015-06-25 04:21:02 -0400 | [diff] [blame] | 413 | resource_size_t nd_namespace_blk_validate(struct nd_namespace_blk *nsblk); |
Vishal Verma | 6ec6895 | 2015-07-29 14:58:09 -0600 | [diff] [blame] | 414 | const u8 *nd_dev_to_uuid(struct device *dev); |
Dan Williams | 004f1af | 2015-08-24 19:20:23 -0400 | [diff] [blame] | 415 | bool pmem_should_map_pages(struct device *dev); |
Dan Williams | 4d88a97 | 2015-05-31 14:41:48 -0400 | [diff] [blame] | 416 | #endif /* __ND_H__ */ |