Laszlo Ersek | 53275a6 | 2015-01-07 18:42:54 +0100 | [diff] [blame] | 1 | * QEMU Firmware Configuration bindings for ARM |
| 2 | |
| 3 | QEMU's arm-softmmu and aarch64-softmmu emulation / virtualization targets |
| 4 | provide the following Firmware Configuration interface on the "virt" machine |
| 5 | type: |
| 6 | |
| 7 | - A write-only, 16-bit wide selector (or control) register, |
| 8 | - a read-write, 64-bit wide data register. |
| 9 | |
| 10 | QEMU exposes the control and data register to ARM guests as memory mapped |
| 11 | registers; their location is communicated to the guest's UEFI firmware in the |
| 12 | DTB that QEMU places at the bottom of the guest's DRAM. |
| 13 | |
Gabriel Somlo | 92aed5d | 2016-01-28 09:23:14 -0500 | [diff] [blame] | 14 | The authoritative guest-side hardware interface documentation to the fw_cfg |
| 15 | device can be found in "docs/specs/fw_cfg.txt" in the QEMU source tree. |
Laszlo Ersek | 53275a6 | 2015-01-07 18:42:54 +0100 | [diff] [blame] | 16 | |
Laszlo Ersek | 53275a6 | 2015-01-07 18:42:54 +0100 | [diff] [blame] | 17 | |
| 18 | Required properties: |
| 19 | |
| 20 | - compatible: "qemu,fw-cfg-mmio". |
| 21 | |
| 22 | - reg: the MMIO region used by the device. |
| 23 | * Bytes 0x0 to 0x7 cover the data register. |
| 24 | * Bytes 0x8 to 0x9 cover the selector register. |
| 25 | * Further registers may be appended to the region in case of future interface |
| 26 | revisions / feature bits. |
| 27 | |
| 28 | Example: |
| 29 | |
| 30 | / { |
| 31 | #size-cells = <0x2>; |
| 32 | #address-cells = <0x2>; |
| 33 | |
| 34 | fw-cfg@9020000 { |
| 35 | compatible = "qemu,fw-cfg-mmio"; |
| 36 | reg = <0x0 0x9020000 0x0 0xa>; |
| 37 | }; |
| 38 | }; |