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review.shift-gmbh.com / SHIFTPHONES / mainline / linux / f82796214a95b1ec00c2f121c1080d10f2b099a1 / . / arch / powerpc / boot / dts / mpc8548cds.dts
blob: 205598d51f2560134f9d5939f171dc731c2cc410 [file] [log] [blame]
Andy Fleming2654d632006-08-18 18:04:34 -0500[diff] [blame]1/*
Roy Zang02edff52007-07-10 18:46:47 +0800[diff] [blame]2 * MPC8548 CDS Device Tree Source
Andy Fleming2654d632006-08-18 18:04:34 -0500[diff] [blame]3 *
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]4 * Copyright 2006, 2008 Freescale Semiconductor Inc.
Andy Fleming2654d632006-08-18 18:04:34 -0500[diff] [blame]5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
10 */
11
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]12/dts-v1/;
Andy Fleming2654d632006-08-18 18:04:34 -0500[diff] [blame]13
14/ {
15 model = "MPC8548CDS";
Kumar Gala52094872007-02-17 16:04:23 -0600[diff] [blame]16 compatible = "MPC8548CDS", "MPC85xxCDS";
Andy Fleming2654d632006-08-18 18:04:34 -0500[diff] [blame]17 #address-cells = <1>;
18 #size-cells = <1>;
Andy Fleming2654d632006-08-18 18:04:34 -0500[diff] [blame]19
Kumar Galaea082fa2007-12-12 01:46:12 -0600[diff] [blame]20 aliases {
21 ethernet0 = &enet0;
22 ethernet1 = &enet1;
23/*
24 ethernet2 = &enet2;
25 ethernet3 = &enet3;
26*/
27 serial0 = &serial0;
28 serial1 = &serial1;
29 pci0 = &pci0;
30 pci1 = &pci1;
31 pci2 = &pci2;
32 };
33
Andy Fleming2654d632006-08-18 18:04:34 -0500[diff] [blame]34 cpus {
Andy Fleming2654d632006-08-18 18:04:34 -0500[diff] [blame]35 #address-cells = <1>;
36 #size-cells = <0>;
Andy Fleming2654d632006-08-18 18:04:34 -0500[diff] [blame]37
38 PowerPC,8548@0 {
39 device_type = "cpu";
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]40 reg = <0x0>;
41 d-cache-line-size = <32>; // 32 bytes
42 i-cache-line-size = <32>; // 32 bytes
43 d-cache-size = <0x8000>; // L1, 32K
44 i-cache-size = <0x8000>; // L1, 32K
Andy Fleming2654d632006-08-18 18:04:34 -0500[diff] [blame]45 timebase-frequency = <0>; // 33 MHz, from uboot
46 bus-frequency = <0>; // 166 MHz
47 clock-frequency = <0>; // 825 MHz, from uboot
Kumar Galac0540652008-05-30 13:43:43 -0500[diff] [blame]48 next-level-cache = <&L2>;
Andy Fleming2654d632006-08-18 18:04:34 -0500[diff] [blame]49 };
50 };
51
52 memory {
53 device_type = "memory";
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]54 reg = <0x0 0x8000000>; // 128M at 0x0
Andy Fleming2654d632006-08-18 18:04:34 -0500[diff] [blame]55 };
56
57 soc8548@e0000000 {
58 #address-cells = <1>;
59 #size-cells = <1>;
Andy Fleming2654d632006-08-18 18:04:34 -0500[diff] [blame]60 device_type = "soc";
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]61 ranges = <0x0 0xe0000000 0x100000>;
62 reg = <0xe0000000 0x1000>; // CCSRBAR
Andy Fleming2654d632006-08-18 18:04:34 -0500[diff] [blame]63 bus-frequency = <0>;
64
Dave Jiang50cf6702007-05-10 10:03:05 -0700[diff] [blame]65 memory-controller@2000 {
66 compatible = "fsl,8548-memory-controller";
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]67 reg = <0x2000 0x1000>;
Dave Jiang50cf6702007-05-10 10:03:05 -0700[diff] [blame]68 interrupt-parent = <&mpic>;
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]69 interrupts = <18 2>;
Dave Jiang50cf6702007-05-10 10:03:05 -0700[diff] [blame]70 };
71
Kumar Galac0540652008-05-30 13:43:43 -0500[diff] [blame]72 L2: l2-cache-controller@20000 {
Dave Jiang50cf6702007-05-10 10:03:05 -0700[diff] [blame]73 compatible = "fsl,8548-l2-cache-controller";
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]74 reg = <0x20000 0x1000>;
75 cache-line-size = <32>; // 32 bytes
76 cache-size = <0x80000>; // L2, 512K
Dave Jiang50cf6702007-05-10 10:03:05 -0700[diff] [blame]77 interrupt-parent = <&mpic>;
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]78 interrupts = <16 2>;
Dave Jiang50cf6702007-05-10 10:03:05 -0700[diff] [blame]79 };
80
Andy Fleming2654d632006-08-18 18:04:34 -0500[diff] [blame]81 i2c@3000 {
Kumar Galaec9686c2007-12-11 23:17:24 -0600[diff] [blame]82 #address-cells = <1>;
83 #size-cells = <0>;
84 cell-index = <0>;
Andy Fleming2654d632006-08-18 18:04:34 -0500[diff] [blame]85 compatible = "fsl-i2c";
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]86 reg = <0x3000 0x100>;
87 interrupts = <43 2>;
Kumar Gala52094872007-02-17 16:04:23 -0600[diff] [blame]88 interrupt-parent = <&mpic>;
Andy Fleming2654d632006-08-18 18:04:34 -0500[diff] [blame]89 dfsrr;
90 };
91
Kumar Galaec9686c2007-12-11 23:17:24 -0600[diff] [blame]92 i2c@3100 {
93 #address-cells = <1>;
94 #size-cells = <0>;
95 cell-index = <1>;
96 compatible = "fsl-i2c";
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]97 reg = <0x3100 0x100>;
98 interrupts = <43 2>;
Kumar Galaec9686c2007-12-11 23:17:24 -0600[diff] [blame]99 interrupt-parent = <&mpic>;
100 dfsrr;
101 };
102
Andy Fleming2654d632006-08-18 18:04:34 -0500[diff] [blame]103 mdio@24520 {
104 #address-cells = <1>;
105 #size-cells = <0>;
Kumar Galae77b28e2007-12-12 00:28:35 -0600[diff] [blame]106 compatible = "fsl,gianfar-mdio";
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]107 reg = <0x24520 0x20>;
Kumar Galae77b28e2007-12-12 00:28:35 -0600[diff] [blame]108
Kumar Gala52094872007-02-17 16:04:23 -0600[diff] [blame]109 phy0: ethernet-phy@0 {
110 interrupt-parent = <&mpic>;
Kumar Gala58fe2552007-07-03 03:05:58 -0500[diff] [blame]111 interrupts = <5 1>;
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]112 reg = <0x0>;
Andy Fleming2654d632006-08-18 18:04:34 -0500[diff] [blame]113 device_type = "ethernet-phy";
114 };
Kumar Gala52094872007-02-17 16:04:23 -0600[diff] [blame]115 phy1: ethernet-phy@1 {
116 interrupt-parent = <&mpic>;
Kumar Gala58fe2552007-07-03 03:05:58 -0500[diff] [blame]117 interrupts = <5 1>;
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]118 reg = <0x1>;
Andy Fleming2654d632006-08-18 18:04:34 -0500[diff] [blame]119 device_type = "ethernet-phy";
120 };
Kumar Gala52094872007-02-17 16:04:23 -0600[diff] [blame]121 phy2: ethernet-phy@2 {
122 interrupt-parent = <&mpic>;
Kumar Gala58fe2552007-07-03 03:05:58 -0500[diff] [blame]123 interrupts = <5 1>;
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]124 reg = <0x2>;
Andy Fleming2654d632006-08-18 18:04:34 -0500[diff] [blame]125 device_type = "ethernet-phy";
126 };
Kumar Gala52094872007-02-17 16:04:23 -0600[diff] [blame]127 phy3: ethernet-phy@3 {
128 interrupt-parent = <&mpic>;
Kumar Gala58fe2552007-07-03 03:05:58 -0500[diff] [blame]129 interrupts = <5 1>;
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]130 reg = <0x3>;
Andy Fleming2654d632006-08-18 18:04:34 -0500[diff] [blame]131 device_type = "ethernet-phy";
132 };
133 };
134
Kumar Galae77b28e2007-12-12 00:28:35 -0600[diff] [blame]135 enet0: ethernet@24000 {
136 cell-index = <0>;
Andy Fleming2654d632006-08-18 18:04:34 -0500[diff] [blame]137 device_type = "network";
138 model = "eTSEC";
139 compatible = "gianfar";
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]140 reg = <0x24000 0x1000>;
Timur Tabieae98262007-06-22 14:33:15 -0500[diff] [blame]141 local-mac-address = [ 00 00 00 00 00 00 ];
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]142 interrupts = <29 2 30 2 34 2>;
Kumar Gala52094872007-02-17 16:04:23 -0600[diff] [blame]143 interrupt-parent = <&mpic>;
144 phy-handle = <&phy0>;
Andy Fleming2654d632006-08-18 18:04:34 -0500[diff] [blame]145 };
146
Kumar Galae77b28e2007-12-12 00:28:35 -0600[diff] [blame]147 enet1: ethernet@25000 {
148 cell-index = <1>;
Andy Fleming2654d632006-08-18 18:04:34 -0500[diff] [blame]149 device_type = "network";
150 model = "eTSEC";
151 compatible = "gianfar";
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]152 reg = <0x25000 0x1000>;
Timur Tabieae98262007-06-22 14:33:15 -0500[diff] [blame]153 local-mac-address = [ 00 00 00 00 00 00 ];
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]154 interrupts = <35 2 36 2 40 2>;
Kumar Gala52094872007-02-17 16:04:23 -0600[diff] [blame]155 interrupt-parent = <&mpic>;
156 phy-handle = <&phy1>;
Andy Fleming2654d632006-08-18 18:04:34 -0500[diff] [blame]157 };
158
Kumar Gala52094872007-02-17 16:04:23 -0600[diff] [blame]159/* eTSEC 3/4 are currently broken
Kumar Galae77b28e2007-12-12 00:28:35 -0600[diff] [blame]160 enet2: ethernet@26000 {
161 cell-index = <2>;
Andy Fleming2654d632006-08-18 18:04:34 -0500[diff] [blame]162 device_type = "network";
163 model = "eTSEC";
164 compatible = "gianfar";
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]165 reg = <0x26000 0x1000>;
Timur Tabieae98262007-06-22 14:33:15 -0500[diff] [blame]166 local-mac-address = [ 00 00 00 00 00 00 ];
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]167 interrupts = <31 2 32 2 33 2>;
Kumar Gala52094872007-02-17 16:04:23 -0600[diff] [blame]168 interrupt-parent = <&mpic>;
169 phy-handle = <&phy2>;
Andy Fleming2654d632006-08-18 18:04:34 -0500[diff] [blame]170 };
171
Kumar Galae77b28e2007-12-12 00:28:35 -0600[diff] [blame]172 enet3: ethernet@27000 {
173 cell-index = <3>;
Andy Fleming2654d632006-08-18 18:04:34 -0500[diff] [blame]174 device_type = "network";
175 model = "eTSEC";
176 compatible = "gianfar";
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]177 reg = <0x27000 0x1000>;
Timur Tabieae98262007-06-22 14:33:15 -0500[diff] [blame]178 local-mac-address = [ 00 00 00 00 00 00 ];
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]179 interrupts = <37 2 38 2 39 2>;
Kumar Gala52094872007-02-17 16:04:23 -0600[diff] [blame]180 interrupt-parent = <&mpic>;
181 phy-handle = <&phy3>;
Andy Fleming2654d632006-08-18 18:04:34 -0500[diff] [blame]182 };
183 */
184
Kumar Galaea082fa2007-12-12 01:46:12 -0600[diff] [blame]185 serial0: serial@4500 {
186 cell-index = <0>;
Andy Fleming2654d632006-08-18 18:04:34 -0500[diff] [blame]187 device_type = "serial";
188 compatible = "ns16550";
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]189 reg = <0x4500 0x100>; // reg base, size
Randy Vinson6af01252007-07-17 16:37:12 -0700[diff] [blame]190 clock-frequency = <0>; // should we fill in in uboot?
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]191 interrupts = <42 2>;
Kumar Gala52094872007-02-17 16:04:23 -0600[diff] [blame]192 interrupt-parent = <&mpic>;
Andy Fleming2654d632006-08-18 18:04:34 -0500[diff] [blame]193 };
194
Kumar Galaea082fa2007-12-12 01:46:12 -0600[diff] [blame]195 serial1: serial@4600 {
196 cell-index = <1>;
Andy Fleming2654d632006-08-18 18:04:34 -0500[diff] [blame]197 device_type = "serial";
198 compatible = "ns16550";
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]199 reg = <0x4600 0x100>; // reg base, size
Randy Vinson6af01252007-07-17 16:37:12 -0700[diff] [blame]200 clock-frequency = <0>; // should we fill in in uboot?
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]201 interrupts = <42 2>;
Kumar Gala52094872007-02-17 16:04:23 -0600[diff] [blame]202 interrupt-parent = <&mpic>;
Andy Fleming2654d632006-08-18 18:04:34 -0500[diff] [blame]203 };
204
Roy Zang68fb0d22007-06-13 17:13:42 +0800[diff] [blame]205 global-utilities@e0000 { //global utilities reg
206 compatible = "fsl,mpc8548-guts";
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]207 reg = <0xe0000 0x1000>;
Roy Zang68fb0d22007-06-13 17:13:42 +0800[diff] [blame]208 fsl,has-rstcr;
209 };
210
Kumar Gala52094872007-02-17 16:04:23 -0600[diff] [blame]211 mpic: pic@40000 {
Andy Fleming2654d632006-08-18 18:04:34 -0500[diff] [blame]212 interrupt-controller;
213 #address-cells = <0>;
214 #interrupt-cells = <2>;
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]215 reg = <0x40000 0x40000>;
Andy Fleming2654d632006-08-18 18:04:34 -0500[diff] [blame]216 compatible = "chrp,open-pic";
217 device_type = "open-pic";
Andy Fleming2654d632006-08-18 18:04:34 -0500[diff] [blame]218 };
219 };
Kumar Gala1b3c5cda2007-09-12 18:23:46 -0500[diff] [blame]220
Kumar Galaea082fa2007-12-12 01:46:12 -0600[diff] [blame]221 pci0: pci@e0008000 {
222 cell-index = <0>;
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]223 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
Kumar Gala1b3c5cda2007-09-12 18:23:46 -0500[diff] [blame]224 interrupt-map = <
225 /* IDSEL 0x4 (PCIX Slot 2) */
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]226 0x2000 0x0 0x0 0x1 &mpic 0x0 0x1
227 0x2000 0x0 0x0 0x2 &mpic 0x1 0x1
228 0x2000 0x0 0x0 0x3 &mpic 0x2 0x1
229 0x2000 0x0 0x0 0x4 &mpic 0x3 0x1
Kumar Gala1b3c5cda2007-09-12 18:23:46 -0500[diff] [blame]230
231 /* IDSEL 0x5 (PCIX Slot 3) */
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]232 0x2800 0x0 0x0 0x1 &mpic 0x1 0x1
233 0x2800 0x0 0x0 0x2 &mpic 0x2 0x1
234 0x2800 0x0 0x0 0x3 &mpic 0x3 0x1
235 0x2800 0x0 0x0 0x4 &mpic 0x0 0x1
Kumar Gala1b3c5cda2007-09-12 18:23:46 -0500[diff] [blame]236
237 /* IDSEL 0x6 (PCIX Slot 4) */
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]238 0x3000 0x0 0x0 0x1 &mpic 0x2 0x1
239 0x3000 0x0 0x0 0x2 &mpic 0x3 0x1
240 0x3000 0x0 0x0 0x3 &mpic 0x0 0x1
241 0x3000 0x0 0x0 0x4 &mpic 0x1 0x1
Kumar Gala1b3c5cda2007-09-12 18:23:46 -0500[diff] [blame]242
243 /* IDSEL 0x8 (PCIX Slot 5) */
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]244 0x4000 0x0 0x0 0x1 &mpic 0x0 0x1
245 0x4000 0x0 0x0 0x2 &mpic 0x1 0x1
246 0x4000 0x0 0x0 0x3 &mpic 0x2 0x1
247 0x4000 0x0 0x0 0x4 &mpic 0x3 0x1
Kumar Gala1b3c5cda2007-09-12 18:23:46 -0500[diff] [blame]248
249 /* IDSEL 0xC (Tsi310 bridge) */
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]250 0x6000 0x0 0x0 0x1 &mpic 0x0 0x1
251 0x6000 0x0 0x0 0x2 &mpic 0x1 0x1
252 0x6000 0x0 0x0 0x3 &mpic 0x2 0x1
253 0x6000 0x0 0x0 0x4 &mpic 0x3 0x1
Kumar Gala1b3c5cda2007-09-12 18:23:46 -0500[diff] [blame]254
255 /* IDSEL 0x14 (Slot 2) */
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]256 0xa000 0x0 0x0 0x1 &mpic 0x0 0x1
257 0xa000 0x0 0x0 0x2 &mpic 0x1 0x1
258 0xa000 0x0 0x0 0x3 &mpic 0x2 0x1
259 0xa000 0x0 0x0 0x4 &mpic 0x3 0x1
Kumar Gala1b3c5cda2007-09-12 18:23:46 -0500[diff] [blame]260
261 /* IDSEL 0x15 (Slot 3) */
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]262 0xa800 0x0 0x0 0x1 &mpic 0x1 0x1
263 0xa800 0x0 0x0 0x2 &mpic 0x2 0x1
264 0xa800 0x0 0x0 0x3 &mpic 0x3 0x1
265 0xa800 0x0 0x0 0x4 &mpic 0x0 0x1
Kumar Gala1b3c5cda2007-09-12 18:23:46 -0500[diff] [blame]266
267 /* IDSEL 0x16 (Slot 4) */
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]268 0xb000 0x0 0x0 0x1 &mpic 0x2 0x1
269 0xb000 0x0 0x0 0x2 &mpic 0x3 0x1
270 0xb000 0x0 0x0 0x3 &mpic 0x0 0x1
271 0xb000 0x0 0x0 0x4 &mpic 0x1 0x1
Kumar Gala1b3c5cda2007-09-12 18:23:46 -0500[diff] [blame]272
273 /* IDSEL 0x18 (Slot 5) */
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]274 0xc000 0x0 0x0 0x1 &mpic 0x0 0x1
275 0xc000 0x0 0x0 0x2 &mpic 0x1 0x1
276 0xc000 0x0 0x0 0x3 &mpic 0x2 0x1
277 0xc000 0x0 0x0 0x4 &mpic 0x3 0x1
Kumar Gala1b3c5cda2007-09-12 18:23:46 -0500[diff] [blame]278
279 /* IDSEL 0x1C (Tsi310 bridge PCI primary) */
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]280 0xe000 0x0 0x0 0x1 &mpic 0x0 0x1
281 0xe000 0x0 0x0 0x2 &mpic 0x1 0x1
282 0xe000 0x0 0x0 0x3 &mpic 0x2 0x1
283 0xe000 0x0 0x0 0x4 &mpic 0x3 0x1>;
Kumar Gala1b3c5cda2007-09-12 18:23:46 -0500[diff] [blame]284
285 interrupt-parent = <&mpic>;
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]286 interrupts = <24 2>;
Kumar Gala1b3c5cda2007-09-12 18:23:46 -0500[diff] [blame]287 bus-range = <0 0>;
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]288 ranges = <0x2000000 0x0 0x80000000 0x80000000 0x0 0x10000000
289 0x1000000 0x0 0x0 0xe2000000 0x0 0x800000>;
290 clock-frequency = <66666666>;
Kumar Gala1b3c5cda2007-09-12 18:23:46 -0500[diff] [blame]291 #interrupt-cells = <1>;
292 #size-cells = <2>;
293 #address-cells = <3>;
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]294 reg = <0xe0008000 0x1000>;
Kumar Gala1b3c5cda2007-09-12 18:23:46 -0500[diff] [blame]295 compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci";
296 device_type = "pci";
297
298 pci_bridge@1c {
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]299 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
Kumar Gala1b3c5cda2007-09-12 18:23:46 -0500[diff] [blame]300 interrupt-map = <
301
302 /* IDSEL 0x00 (PrPMC Site) */
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]303 0000 0x0 0x0 0x1 &mpic 0x0 0x1
304 0000 0x0 0x0 0x2 &mpic 0x1 0x1
305 0000 0x0 0x0 0x3 &mpic 0x2 0x1
306 0000 0x0 0x0 0x4 &mpic 0x3 0x1
Kumar Gala1b3c5cda2007-09-12 18:23:46 -0500[diff] [blame]307
308 /* IDSEL 0x04 (VIA chip) */
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]309 0x2000 0x0 0x0 0x1 &mpic 0x0 0x1
310 0x2000 0x0 0x0 0x2 &mpic 0x1 0x1
311 0x2000 0x0 0x0 0x3 &mpic 0x2 0x1
312 0x2000 0x0 0x0 0x4 &mpic 0x3 0x1
Kumar Gala1b3c5cda2007-09-12 18:23:46 -0500[diff] [blame]313
314 /* IDSEL 0x05 (8139) */
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]315 0x2800 0x0 0x0 0x1 &mpic 0x1 0x1
Kumar Gala1b3c5cda2007-09-12 18:23:46 -0500[diff] [blame]316
317 /* IDSEL 0x06 (Slot 6) */
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]318 0x3000 0x0 0x0 0x1 &mpic 0x2 0x1
319 0x3000 0x0 0x0 0x2 &mpic 0x3 0x1
320 0x3000 0x0 0x0 0x3 &mpic 0x0 0x1
321 0x3000 0x0 0x0 0x4 &mpic 0x1 0x1
Kumar Gala1b3c5cda2007-09-12 18:23:46 -0500[diff] [blame]322
323 /* IDESL 0x07 (Slot 7) */
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]324 0x3800 0x0 0x0 0x1 &mpic 0x3 0x1
325 0x3800 0x0 0x0 0x2 &mpic 0x0 0x1
326 0x3800 0x0 0x0 0x3 &mpic 0x1 0x1
327 0x3800 0x0 0x0 0x4 &mpic 0x2 0x1>;
Kumar Gala1b3c5cda2007-09-12 18:23:46 -0500[diff] [blame]328
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]329 reg = <0xe000 0x0 0x0 0x0 0x0>;
Kumar Gala1b3c5cda2007-09-12 18:23:46 -0500[diff] [blame]330 #interrupt-cells = <1>;
331 #size-cells = <2>;
332 #address-cells = <3>;
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]333 ranges = <0x2000000 0x0 0x80000000
334 0x2000000 0x0 0x80000000
335 0x0 0x20000000
336 0x1000000 0x0 0x0
337 0x1000000 0x0 0x0
338 0x0 0x80000>;
339 clock-frequency = <33333333>;
Kumar Gala1b3c5cda2007-09-12 18:23:46 -0500[diff] [blame]340
341 isa@4 {
342 device_type = "isa";
343 #interrupt-cells = <2>;
344 #size-cells = <1>;
345 #address-cells = <2>;
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]346 reg = <0x2000 0x0 0x0 0x0 0x0>;
347 ranges = <0x1 0x0 0x1000000 0x0 0x0 0x1000>;
Kumar Gala1b3c5cda2007-09-12 18:23:46 -0500[diff] [blame]348 interrupt-parent = <&i8259>;
349
350 i8259: interrupt-controller@20 {
351 interrupt-controller;
352 device_type = "interrupt-controller";
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]353 reg = <0x1 0x20 0x2
354 0x1 0xa0 0x2
355 0x1 0x4d0 0x2>;
Kumar Gala1b3c5cda2007-09-12 18:23:46 -0500[diff] [blame]356 #address-cells = <0>;
357 #interrupt-cells = <2>;
358 compatible = "chrp,iic";
359 interrupts = <0 1>;
360 interrupt-parent = <&mpic>;
361 };
362
363 rtc@70 {
364 compatible = "pnpPNP,b00";
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]365 reg = <0x1 0x70 0x2>;
Kumar Gala1b3c5cda2007-09-12 18:23:46 -0500[diff] [blame]366 };
367 };
368 };
369 };
370
Kumar Galaea082fa2007-12-12 01:46:12 -0600[diff] [blame]371 pci1: pci@e0009000 {
372 cell-index = <1>;
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]373 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
Kumar Gala1b3c5cda2007-09-12 18:23:46 -0500[diff] [blame]374 interrupt-map = <
375
376 /* IDSEL 0x15 */
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]377 0xa800 0x0 0x0 0x1 &mpic 0xb 0x1
378 0xa800 0x0 0x0 0x2 &mpic 0x1 0x1
379 0xa800 0x0 0x0 0x3 &mpic 0x2 0x1
380 0xa800 0x0 0x0 0x4 &mpic 0x3 0x1>;
Kumar Gala1b3c5cda2007-09-12 18:23:46 -0500[diff] [blame]381
382 interrupt-parent = <&mpic>;
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]383 interrupts = <25 2>;
Kumar Gala1b3c5cda2007-09-12 18:23:46 -0500[diff] [blame]384 bus-range = <0 0>;
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]385 ranges = <0x2000000 0x0 0x90000000 0x90000000 0x0 0x10000000
386 0x1000000 0x0 0x0 0xe2800000 0x0 0x800000>;
387 clock-frequency = <66666666>;
Kumar Gala1b3c5cda2007-09-12 18:23:46 -0500[diff] [blame]388 #interrupt-cells = <1>;
389 #size-cells = <2>;
390 #address-cells = <3>;
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]391 reg = <0xe0009000 0x1000>;
Kumar Gala1b3c5cda2007-09-12 18:23:46 -0500[diff] [blame]392 compatible = "fsl,mpc8540-pci";
393 device_type = "pci";
394 };
395
Kumar Galaea082fa2007-12-12 01:46:12 -0600[diff] [blame]396 pci2: pcie@e000a000 {
397 cell-index = <2>;
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]398 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
Kumar Gala1b3c5cda2007-09-12 18:23:46 -0500[diff] [blame]399 interrupt-map = <
400
401 /* IDSEL 0x0 (PEX) */
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]402 00000 0x0 0x0 0x1 &mpic 0x0 0x1
403 00000 0x0 0x0 0x2 &mpic 0x1 0x1
404 00000 0x0 0x0 0x3 &mpic 0x2 0x1
405 00000 0x0 0x0 0x4 &mpic 0x3 0x1>;
Kumar Gala1b3c5cda2007-09-12 18:23:46 -0500[diff] [blame]406
407 interrupt-parent = <&mpic>;
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]408 interrupts = <26 2>;
409 bus-range = <0 255>;
410 ranges = <0x2000000 0x0 0xa0000000 0xa0000000 0x0 0x20000000
411 0x1000000 0x0 0x0 0xe3000000 0x0 0x8000000>;
412 clock-frequency = <33333333>;
Kumar Gala1b3c5cda2007-09-12 18:23:46 -0500[diff] [blame]413 #interrupt-cells = <1>;
414 #size-cells = <2>;
415 #address-cells = <3>;
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]416 reg = <0xe000a000 0x1000>;
Kumar Gala1b3c5cda2007-09-12 18:23:46 -0500[diff] [blame]417 compatible = "fsl,mpc8548-pcie";
418 device_type = "pci";
419 pcie@0 {
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]420 reg = <0x0 0x0 0x0 0x0 0x0>;
Kumar Gala1b3c5cda2007-09-12 18:23:46 -0500[diff] [blame]421 #size-cells = <2>;
422 #address-cells = <3>;
423 device_type = "pci";
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]424 ranges = <0x2000000 0x0 0xa0000000
425 0x2000000 0x0 0xa0000000
426 0x0 0x20000000
Kumar Gala1b3c5cda2007-09-12 18:23:46 -0500[diff] [blame]427
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]428 0x1000000 0x0 0x0
429 0x1000000 0x0 0x0
430 0x0 0x8000000>;
Kumar Gala1b3c5cda2007-09-12 18:23:46 -0500[diff] [blame]431 };
432 };
Andy Fleming2654d632006-08-18 18:04:34 -0500[diff] [blame]433};