Mauro Carvalho Chehab | f68ac62 | 2017-05-14 09:15:12 -0300 | [diff] [blame] | 1 | ======================== |
| 2 | The Common Clk Framework |
| 3 | ======================== |
| 4 | |
| 5 | :Author: Mike Turquette <mturquette@ti.com> |
Mike Turquette | 69fe8a8 | 2012-03-15 23:11:18 -0700 | [diff] [blame] | 6 | |
| 7 | This document endeavours to explain the common clk framework details, |
| 8 | and how to port a platform over to this framework. It is not yet a |
| 9 | detailed explanation of the clock api in include/linux/clk.h, but |
| 10 | perhaps someday it will include that information. |
| 11 | |
Mauro Carvalho Chehab | f68ac62 | 2017-05-14 09:15:12 -0300 | [diff] [blame] | 12 | Introduction and interface split |
| 13 | ================================ |
Mike Turquette | 69fe8a8 | 2012-03-15 23:11:18 -0700 | [diff] [blame] | 14 | |
| 15 | The common clk framework is an interface to control the clock nodes |
| 16 | available on various devices today. This may come in the form of clock |
| 17 | gating, rate adjustment, muxing or other operations. This framework is |
| 18 | enabled with the CONFIG_COMMON_CLK option. |
| 19 | |
| 20 | The interface itself is divided into two halves, each shielded from the |
| 21 | details of its counterpart. First is the common definition of struct |
| 22 | clk which unifies the framework-level accounting and infrastructure that |
| 23 | has traditionally been duplicated across a variety of platforms. Second |
| 24 | is a common implementation of the clk.h api, defined in |
| 25 | drivers/clk/clk.c. Finally there is struct clk_ops, whose operations |
| 26 | are invoked by the clk api implementation. |
| 27 | |
| 28 | The second half of the interface is comprised of the hardware-specific |
| 29 | callbacks registered with struct clk_ops and the corresponding |
| 30 | hardware-specific structures needed to model a particular clock. For |
| 31 | the remainder of this document any reference to a callback in struct |
| 32 | clk_ops, such as .enable or .set_rate, implies the hardware-specific |
| 33 | implementation of that code. Likewise, references to struct clk_foo |
| 34 | serve as a convenient shorthand for the implementation of the |
| 35 | hardware-specific bits for the hypothetical "foo" hardware. |
| 36 | |
| 37 | Tying the two halves of this interface together is struct clk_hw, which |
Andi Shyti | 6203a64 | 2016-08-12 14:41:25 +0200 | [diff] [blame] | 38 | is defined in struct clk_foo and pointed to within struct clk_core. This |
Sachin Kamat | 1354195 | 2013-06-10 10:02:39 +0530 | [diff] [blame] | 39 | allows for easy navigation between the two discrete halves of the common |
Mike Turquette | 69fe8a8 | 2012-03-15 23:11:18 -0700 | [diff] [blame] | 40 | clock interface. |
| 41 | |
Mauro Carvalho Chehab | f68ac62 | 2017-05-14 09:15:12 -0300 | [diff] [blame] | 42 | Common data structures and api |
| 43 | ============================== |
Mike Turquette | 69fe8a8 | 2012-03-15 23:11:18 -0700 | [diff] [blame] | 44 | |
Andi Shyti | 6203a64 | 2016-08-12 14:41:25 +0200 | [diff] [blame] | 45 | Below is the common struct clk_core definition from |
Mauro Carvalho Chehab | f68ac62 | 2017-05-14 09:15:12 -0300 | [diff] [blame] | 46 | drivers/clk/clk.c, modified for brevity:: |
Mike Turquette | 69fe8a8 | 2012-03-15 23:11:18 -0700 | [diff] [blame] | 47 | |
Andi Shyti | 6203a64 | 2016-08-12 14:41:25 +0200 | [diff] [blame] | 48 | struct clk_core { |
Mike Turquette | 69fe8a8 | 2012-03-15 23:11:18 -0700 | [diff] [blame] | 49 | const char *name; |
| 50 | const struct clk_ops *ops; |
| 51 | struct clk_hw *hw; |
Andi Shyti | 6203a64 | 2016-08-12 14:41:25 +0200 | [diff] [blame] | 52 | struct module *owner; |
| 53 | struct clk_core *parent; |
| 54 | const char **parent_names; |
| 55 | struct clk_core **parents; |
| 56 | u8 num_parents; |
| 57 | u8 new_parent_index; |
Mike Turquette | 69fe8a8 | 2012-03-15 23:11:18 -0700 | [diff] [blame] | 58 | ... |
| 59 | }; |
| 60 | |
| 61 | The members above make up the core of the clk tree topology. The clk |
| 62 | api itself defines several driver-facing functions which operate on |
| 63 | struct clk. That api is documented in include/linux/clk.h. |
| 64 | |
Andi Shyti | 6203a64 | 2016-08-12 14:41:25 +0200 | [diff] [blame] | 65 | Platforms and devices utilizing the common struct clk_core use the struct |
| 66 | clk_ops pointer in struct clk_core to perform the hardware-specific parts of |
Mauro Carvalho Chehab | f68ac62 | 2017-05-14 09:15:12 -0300 | [diff] [blame] | 67 | the operations defined in clk-provider.h:: |
Mike Turquette | 69fe8a8 | 2012-03-15 23:11:18 -0700 | [diff] [blame] | 68 | |
| 69 | struct clk_ops { |
| 70 | int (*prepare)(struct clk_hw *hw); |
| 71 | void (*unprepare)(struct clk_hw *hw); |
Andi Shyti | 6203a64 | 2016-08-12 14:41:25 +0200 | [diff] [blame] | 72 | int (*is_prepared)(struct clk_hw *hw); |
| 73 | void (*unprepare_unused)(struct clk_hw *hw); |
Mike Turquette | 69fe8a8 | 2012-03-15 23:11:18 -0700 | [diff] [blame] | 74 | int (*enable)(struct clk_hw *hw); |
| 75 | void (*disable)(struct clk_hw *hw); |
| 76 | int (*is_enabled)(struct clk_hw *hw); |
Andi Shyti | 6203a64 | 2016-08-12 14:41:25 +0200 | [diff] [blame] | 77 | void (*disable_unused)(struct clk_hw *hw); |
Mike Turquette | 69fe8a8 | 2012-03-15 23:11:18 -0700 | [diff] [blame] | 78 | unsigned long (*recalc_rate)(struct clk_hw *hw, |
| 79 | unsigned long parent_rate); |
Geert Uytterhoeven | 54e7301 | 2014-04-22 15:11:42 +0200 | [diff] [blame] | 80 | long (*round_rate)(struct clk_hw *hw, |
| 81 | unsigned long rate, |
| 82 | unsigned long *parent_rate); |
Boris Brezillon | 0817b62 | 2015-07-07 20:48:08 +0200 | [diff] [blame] | 83 | int (*determine_rate)(struct clk_hw *hw, |
| 84 | struct clk_rate_request *req); |
Mike Turquette | 69fe8a8 | 2012-03-15 23:11:18 -0700 | [diff] [blame] | 85 | int (*set_parent)(struct clk_hw *hw, u8 index); |
| 86 | u8 (*get_parent)(struct clk_hw *hw); |
Geert Uytterhoeven | 54e7301 | 2014-04-22 15:11:42 +0200 | [diff] [blame] | 87 | int (*set_rate)(struct clk_hw *hw, |
| 88 | unsigned long rate, |
| 89 | unsigned long parent_rate); |
Stephen Boyd | 3fa2252 | 2014-01-15 10:47:22 -0800 | [diff] [blame] | 90 | int (*set_rate_and_parent)(struct clk_hw *hw, |
| 91 | unsigned long rate, |
Geert Uytterhoeven | 54e7301 | 2014-04-22 15:11:42 +0200 | [diff] [blame] | 92 | unsigned long parent_rate, |
| 93 | u8 index); |
Boris BREZILLON | 5279fc4 | 2013-12-21 10:34:47 +0100 | [diff] [blame] | 94 | unsigned long (*recalc_accuracy)(struct clk_hw *hw, |
Geert Uytterhoeven | 54e7301 | 2014-04-22 15:11:42 +0200 | [diff] [blame] | 95 | unsigned long parent_accuracy); |
Andi Shyti | 6203a64 | 2016-08-12 14:41:25 +0200 | [diff] [blame] | 96 | int (*get_phase)(struct clk_hw *hw); |
| 97 | int (*set_phase)(struct clk_hw *hw, int degrees); |
Mike Turquette | 69fe8a8 | 2012-03-15 23:11:18 -0700 | [diff] [blame] | 98 | void (*init)(struct clk_hw *hw); |
Stephen Boyd | d75d50c | 2018-06-01 21:42:07 -0700 | [diff] [blame] | 99 | void (*debug_init)(struct clk_hw *hw, |
Geert Uytterhoeven | 54e7301 | 2014-04-22 15:11:42 +0200 | [diff] [blame] | 100 | struct dentry *dentry); |
Mike Turquette | 69fe8a8 | 2012-03-15 23:11:18 -0700 | [diff] [blame] | 101 | }; |
| 102 | |
Mauro Carvalho Chehab | f68ac62 | 2017-05-14 09:15:12 -0300 | [diff] [blame] | 103 | Hardware clk implementations |
| 104 | ============================ |
Mike Turquette | 69fe8a8 | 2012-03-15 23:11:18 -0700 | [diff] [blame] | 105 | |
Andi Shyti | 6203a64 | 2016-08-12 14:41:25 +0200 | [diff] [blame] | 106 | The strength of the common struct clk_core comes from its .ops and .hw pointers |
Mike Turquette | 69fe8a8 | 2012-03-15 23:11:18 -0700 | [diff] [blame] | 107 | which abstract the details of struct clk from the hardware-specific bits, and |
| 108 | vice versa. To illustrate consider the simple gateable clk implementation in |
Mauro Carvalho Chehab | f68ac62 | 2017-05-14 09:15:12 -0300 | [diff] [blame] | 109 | drivers/clk/clk-gate.c:: |
Mike Turquette | 69fe8a8 | 2012-03-15 23:11:18 -0700 | [diff] [blame] | 110 | |
Mauro Carvalho Chehab | f68ac62 | 2017-05-14 09:15:12 -0300 | [diff] [blame] | 111 | struct clk_gate { |
| 112 | struct clk_hw hw; |
| 113 | void __iomem *reg; |
| 114 | u8 bit_idx; |
| 115 | ... |
| 116 | }; |
Mike Turquette | 69fe8a8 | 2012-03-15 23:11:18 -0700 | [diff] [blame] | 117 | |
| 118 | struct clk_gate contains struct clk_hw hw as well as hardware-specific |
| 119 | knowledge about which register and bit controls this clk's gating. |
| 120 | Nothing about clock topology or accounting, such as enable_count or |
| 121 | notifier_count, is needed here. That is all handled by the common |
Andi Shyti | 6203a64 | 2016-08-12 14:41:25 +0200 | [diff] [blame] | 122 | framework code and struct clk_core. |
Mike Turquette | 69fe8a8 | 2012-03-15 23:11:18 -0700 | [diff] [blame] | 123 | |
Mauro Carvalho Chehab | f68ac62 | 2017-05-14 09:15:12 -0300 | [diff] [blame] | 124 | Let's walk through enabling this clk from driver code:: |
Mike Turquette | 69fe8a8 | 2012-03-15 23:11:18 -0700 | [diff] [blame] | 125 | |
| 126 | struct clk *clk; |
| 127 | clk = clk_get(NULL, "my_gateable_clk"); |
| 128 | |
| 129 | clk_prepare(clk); |
| 130 | clk_enable(clk); |
| 131 | |
Mauro Carvalho Chehab | f68ac62 | 2017-05-14 09:15:12 -0300 | [diff] [blame] | 132 | The call graph for clk_enable is very simple:: |
Mike Turquette | 69fe8a8 | 2012-03-15 23:11:18 -0700 | [diff] [blame] | 133 | |
Mauro Carvalho Chehab | f68ac62 | 2017-05-14 09:15:12 -0300 | [diff] [blame] | 134 | clk_enable(clk); |
| 135 | clk->ops->enable(clk->hw); |
| 136 | [resolves to...] |
| 137 | clk_gate_enable(hw); |
| 138 | [resolves struct clk gate with to_clk_gate(hw)] |
| 139 | clk_gate_set_bit(gate); |
Mike Turquette | 69fe8a8 | 2012-03-15 23:11:18 -0700 | [diff] [blame] | 140 | |
Mauro Carvalho Chehab | f68ac62 | 2017-05-14 09:15:12 -0300 | [diff] [blame] | 141 | And the definition of clk_gate_set_bit:: |
Mike Turquette | 69fe8a8 | 2012-03-15 23:11:18 -0700 | [diff] [blame] | 142 | |
Mauro Carvalho Chehab | f68ac62 | 2017-05-14 09:15:12 -0300 | [diff] [blame] | 143 | static void clk_gate_set_bit(struct clk_gate *gate) |
| 144 | { |
| 145 | u32 reg; |
Mike Turquette | 69fe8a8 | 2012-03-15 23:11:18 -0700 | [diff] [blame] | 146 | |
Mauro Carvalho Chehab | f68ac62 | 2017-05-14 09:15:12 -0300 | [diff] [blame] | 147 | reg = __raw_readl(gate->reg); |
| 148 | reg |= BIT(gate->bit_idx); |
| 149 | writel(reg, gate->reg); |
| 150 | } |
Mike Turquette | 69fe8a8 | 2012-03-15 23:11:18 -0700 | [diff] [blame] | 151 | |
Mauro Carvalho Chehab | f68ac62 | 2017-05-14 09:15:12 -0300 | [diff] [blame] | 152 | Note that to_clk_gate is defined as:: |
Mike Turquette | 69fe8a8 | 2012-03-15 23:11:18 -0700 | [diff] [blame] | 153 | |
Mauro Carvalho Chehab | f68ac62 | 2017-05-14 09:15:12 -0300 | [diff] [blame] | 154 | #define to_clk_gate(_hw) container_of(_hw, struct clk_gate, hw) |
Mike Turquette | 69fe8a8 | 2012-03-15 23:11:18 -0700 | [diff] [blame] | 155 | |
| 156 | This pattern of abstraction is used for every clock hardware |
| 157 | representation. |
| 158 | |
Mauro Carvalho Chehab | f68ac62 | 2017-05-14 09:15:12 -0300 | [diff] [blame] | 159 | Supporting your own clk hardware |
| 160 | ================================ |
Mike Turquette | 69fe8a8 | 2012-03-15 23:11:18 -0700 | [diff] [blame] | 161 | |
Andi Shyti | 6203a64 | 2016-08-12 14:41:25 +0200 | [diff] [blame] | 162 | When implementing support for a new type of clock it is only necessary to |
Mauro Carvalho Chehab | f68ac62 | 2017-05-14 09:15:12 -0300 | [diff] [blame] | 163 | include the following header:: |
Mike Turquette | 69fe8a8 | 2012-03-15 23:11:18 -0700 | [diff] [blame] | 164 | |
Mauro Carvalho Chehab | f68ac62 | 2017-05-14 09:15:12 -0300 | [diff] [blame] | 165 | #include <linux/clk-provider.h> |
Mike Turquette | 69fe8a8 | 2012-03-15 23:11:18 -0700 | [diff] [blame] | 166 | |
Mike Turquette | 69fe8a8 | 2012-03-15 23:11:18 -0700 | [diff] [blame] | 167 | To construct a clk hardware structure for your platform you must define |
Mauro Carvalho Chehab | f68ac62 | 2017-05-14 09:15:12 -0300 | [diff] [blame] | 168 | the following:: |
Mike Turquette | 69fe8a8 | 2012-03-15 23:11:18 -0700 | [diff] [blame] | 169 | |
Mauro Carvalho Chehab | f68ac62 | 2017-05-14 09:15:12 -0300 | [diff] [blame] | 170 | struct clk_foo { |
| 171 | struct clk_hw hw; |
| 172 | ... hardware specific data goes here ... |
| 173 | }; |
Mike Turquette | 69fe8a8 | 2012-03-15 23:11:18 -0700 | [diff] [blame] | 174 | |
| 175 | To take advantage of your data you'll need to support valid operations |
Mauro Carvalho Chehab | f68ac62 | 2017-05-14 09:15:12 -0300 | [diff] [blame] | 176 | for your clk:: |
Mike Turquette | 69fe8a8 | 2012-03-15 23:11:18 -0700 | [diff] [blame] | 177 | |
Luca Ceresoli | 889aa9c | 2019-05-31 16:30:16 +0200 | [diff] [blame] | 178 | struct clk_ops clk_foo_ops = { |
| 179 | .enable = &clk_foo_enable, |
| 180 | .disable = &clk_foo_disable, |
Mauro Carvalho Chehab | f68ac62 | 2017-05-14 09:15:12 -0300 | [diff] [blame] | 181 | }; |
Mike Turquette | 69fe8a8 | 2012-03-15 23:11:18 -0700 | [diff] [blame] | 182 | |
Mauro Carvalho Chehab | f68ac62 | 2017-05-14 09:15:12 -0300 | [diff] [blame] | 183 | Implement the above functions using container_of:: |
Mike Turquette | 69fe8a8 | 2012-03-15 23:11:18 -0700 | [diff] [blame] | 184 | |
Mauro Carvalho Chehab | f68ac62 | 2017-05-14 09:15:12 -0300 | [diff] [blame] | 185 | #define to_clk_foo(_hw) container_of(_hw, struct clk_foo, hw) |
Mike Turquette | 69fe8a8 | 2012-03-15 23:11:18 -0700 | [diff] [blame] | 186 | |
Mauro Carvalho Chehab | f68ac62 | 2017-05-14 09:15:12 -0300 | [diff] [blame] | 187 | int clk_foo_enable(struct clk_hw *hw) |
| 188 | { |
| 189 | struct clk_foo *foo; |
Mike Turquette | 69fe8a8 | 2012-03-15 23:11:18 -0700 | [diff] [blame] | 190 | |
Mauro Carvalho Chehab | f68ac62 | 2017-05-14 09:15:12 -0300 | [diff] [blame] | 191 | foo = to_clk_foo(hw); |
Mike Turquette | 69fe8a8 | 2012-03-15 23:11:18 -0700 | [diff] [blame] | 192 | |
Mauro Carvalho Chehab | f68ac62 | 2017-05-14 09:15:12 -0300 | [diff] [blame] | 193 | ... perform magic on foo ... |
Mike Turquette | 69fe8a8 | 2012-03-15 23:11:18 -0700 | [diff] [blame] | 194 | |
Mauro Carvalho Chehab | f68ac62 | 2017-05-14 09:15:12 -0300 | [diff] [blame] | 195 | return 0; |
| 196 | }; |
Mike Turquette | 69fe8a8 | 2012-03-15 23:11:18 -0700 | [diff] [blame] | 197 | |
| 198 | Below is a matrix detailing which clk_ops are mandatory based upon the |
Eduardo Valentin | a368a6a | 2013-02-28 09:59:07 -0400 | [diff] [blame] | 199 | hardware capabilities of that clock. A cell marked as "y" means |
Mike Turquette | 69fe8a8 | 2012-03-15 23:11:18 -0700 | [diff] [blame] | 200 | mandatory, a cell marked as "n" implies that either including that |
Eduardo Valentin | a368a6a | 2013-02-28 09:59:07 -0400 | [diff] [blame] | 201 | callback is invalid or otherwise unnecessary. Empty cells are either |
Mike Turquette | 69fe8a8 | 2012-03-15 23:11:18 -0700 | [diff] [blame] | 202 | optional or must be evaluated on a case-by-case basis. |
| 203 | |
Mauro Carvalho Chehab | f68ac62 | 2017-05-14 09:15:12 -0300 | [diff] [blame] | 204 | .. table:: clock hardware characteristics |
| 205 | |
| 206 | +----------------+------+-------------+---------------+-------------+------+ |
| 207 | | | gate | change rate | single parent | multiplexer | root | |
| 208 | +================+======+=============+===============+=============+======+ |
| 209 | |.prepare | | | | | | |
| 210 | +----------------+------+-------------+---------------+-------------+------+ |
| 211 | |.unprepare | | | | | | |
| 212 | +----------------+------+-------------+---------------+-------------+------+ |
| 213 | +----------------+------+-------------+---------------+-------------+------+ |
| 214 | |.enable | y | | | | | |
| 215 | +----------------+------+-------------+---------------+-------------+------+ |
| 216 | |.disable | y | | | | | |
| 217 | +----------------+------+-------------+---------------+-------------+------+ |
| 218 | |.is_enabled | y | | | | | |
| 219 | +----------------+------+-------------+---------------+-------------+------+ |
| 220 | +----------------+------+-------------+---------------+-------------+------+ |
| 221 | |.recalc_rate | | y | | | | |
| 222 | +----------------+------+-------------+---------------+-------------+------+ |
| 223 | |.round_rate | | y [1]_ | | | | |
| 224 | +----------------+------+-------------+---------------+-------------+------+ |
| 225 | |.determine_rate | | y [1]_ | | | | |
| 226 | +----------------+------+-------------+---------------+-------------+------+ |
| 227 | |.set_rate | | y | | | | |
| 228 | +----------------+------+-------------+---------------+-------------+------+ |
| 229 | +----------------+------+-------------+---------------+-------------+------+ |
| 230 | |.set_parent | | | n | y | n | |
| 231 | +----------------+------+-------------+---------------+-------------+------+ |
| 232 | |.get_parent | | | n | y | n | |
| 233 | +----------------+------+-------------+---------------+-------------+------+ |
| 234 | +----------------+------+-------------+---------------+-------------+------+ |
| 235 | |.recalc_accuracy| | | | | | |
| 236 | +----------------+------+-------------+---------------+-------------+------+ |
| 237 | +----------------+------+-------------+---------------+-------------+------+ |
| 238 | |.init | | | | | | |
| 239 | +----------------+------+-------------+---------------+-------------+------+ |
| 240 | |
| 241 | .. [1] either one of round_rate or determine_rate is required. |
Mike Turquette | 69fe8a8 | 2012-03-15 23:11:18 -0700 | [diff] [blame] | 242 | |
| 243 | Finally, register your clock at run-time with a hardware-specific |
| 244 | registration function. This function simply populates struct clk_foo's |
| 245 | data and then passes the common struct clk parameters to the framework |
Mauro Carvalho Chehab | f68ac62 | 2017-05-14 09:15:12 -0300 | [diff] [blame] | 246 | with a call to:: |
Mike Turquette | 69fe8a8 | 2012-03-15 23:11:18 -0700 | [diff] [blame] | 247 | |
Mauro Carvalho Chehab | f68ac62 | 2017-05-14 09:15:12 -0300 | [diff] [blame] | 248 | clk_register(...) |
Mike Turquette | 69fe8a8 | 2012-03-15 23:11:18 -0700 | [diff] [blame] | 249 | |
Mauro Carvalho Chehab | f68ac62 | 2017-05-14 09:15:12 -0300 | [diff] [blame] | 250 | See the basic clock types in ``drivers/clk/clk-*.c`` for examples. |
Mike Turquette | 69fe8a8 | 2012-03-15 23:11:18 -0700 | [diff] [blame] | 251 | |
Mauro Carvalho Chehab | f68ac62 | 2017-05-14 09:15:12 -0300 | [diff] [blame] | 252 | Disabling clock gating of unused clocks |
| 253 | ======================================= |
Olof Johansson | 1e43525 | 2013-04-27 14:10:18 -0700 | [diff] [blame] | 254 | |
| 255 | Sometimes during development it can be useful to be able to bypass the |
| 256 | default disabling of unused clocks. For example, if drivers aren't enabling |
| 257 | clocks properly but rely on them being on from the bootloader, bypassing |
| 258 | the disabling means that the driver will remain functional while the issues |
| 259 | are sorted out. |
| 260 | |
| 261 | To bypass this disabling, include "clk_ignore_unused" in the bootargs to the |
| 262 | kernel. |
Laurent Pinchart | 843bad8 | 2014-02-28 13:40:56 +0100 | [diff] [blame] | 263 | |
Mauro Carvalho Chehab | f68ac62 | 2017-05-14 09:15:12 -0300 | [diff] [blame] | 264 | Locking |
| 265 | ======= |
Laurent Pinchart | 843bad8 | 2014-02-28 13:40:56 +0100 | [diff] [blame] | 266 | |
| 267 | The common clock framework uses two global locks, the prepare lock and the |
| 268 | enable lock. |
| 269 | |
| 270 | The enable lock is a spinlock and is held across calls to the .enable, |
Dong Aisheng | 5bc5673 | 2018-01-19 21:37:15 +0800 | [diff] [blame] | 271 | .disable operations. Those operations are thus not allowed to sleep, |
| 272 | and calls to the clk_enable(), clk_disable() API functions are allowed in |
| 273 | atomic context. |
| 274 | |
| 275 | For clk_is_enabled() API, it is also designed to be allowed to be used in |
| 276 | atomic context. However, it doesn't really make any sense to hold the enable |
| 277 | lock in core, unless you want to do something else with the information of |
| 278 | the enable state with that lock held. Otherwise, seeing if a clk is enabled is |
| 279 | a one-shot read of the enabled state, which could just as easily change after |
| 280 | the function returns because the lock is released. Thus the user of this API |
| 281 | needs to handle synchronizing the read of the state with whatever they're |
| 282 | using it for to make sure that the enable state doesn't change during that |
| 283 | time. |
Laurent Pinchart | 843bad8 | 2014-02-28 13:40:56 +0100 | [diff] [blame] | 284 | |
| 285 | The prepare lock is a mutex and is held across calls to all other operations. |
| 286 | All those operations are allowed to sleep, and calls to the corresponding API |
| 287 | functions are not allowed in atomic context. |
| 288 | |
| 289 | This effectively divides operations in two groups from a locking perspective. |
| 290 | |
| 291 | Drivers don't need to manually protect resources shared between the operations |
| 292 | of one group, regardless of whether those resources are shared by multiple |
| 293 | clocks or not. However, access to resources that are shared between operations |
| 294 | of the two groups needs to be protected by the drivers. An example of such a |
| 295 | resource would be a register that controls both the clock rate and the clock |
| 296 | enable/disable state. |
| 297 | |
| 298 | The clock framework is reentrant, in that a driver is allowed to call clock |
| 299 | framework functions from within its implementation of clock operations. This |
| 300 | can for instance cause a .set_rate operation of one clock being called from |
| 301 | within the .set_rate operation of another clock. This case must be considered |
| 302 | in the driver implementations, but the code flow is usually controlled by the |
| 303 | driver in that case. |
| 304 | |
| 305 | Note that locking must also be considered when code outside of the common |
| 306 | clock framework needs to access resources used by the clock operations. This |
| 307 | is considered out of scope of this document. |