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review.shift-gmbh.com / SHIFTPHONES / mainline / linux / f66c0447cca1281116224d474cdb37d6a18e4b5b / . / Documentation / devicetree / bindings / mmc / renesas,sdhi.txt
blob: dd08d038a65c2abf9d5aa9505230660844186a63 [file] [log] [blame]
Masahiro Yamada1cdca162019-06-24 16:03:45 +0900[diff] [blame]1* Renesas SDHI SD/MMC controller
Guennadi Liakhovetskid8048202013-02-15 16:13:55 +0100[diff] [blame]2
Guennadi Liakhovetskidf1d0582013-08-29 17:14:49 +0200[diff] [blame]3Required properties:
Simon Horman54839d02017-10-18 09:00:22 +0200[diff] [blame]4- compatible: should contain one or more of the following:
Guennadi Liakhovetskidf1d0582013-08-29 17:14:49 +0200[diff] [blame]5 "renesas,sdhi-sh73a0" - SDHI IP on SH73A0 SoC
Chris Brandt0963dd52016-09-12 10:15:07 -0400[diff] [blame]6 "renesas,sdhi-r7s72100" - SDHI IP on R7S72100 SoC
Chris Brandtbb169562018-10-24 17:23:01 -0500[diff] [blame]7 "renesas,sdhi-r7s9210" - SDHI IP on R7S9210 SoC
Guennadi Liakhovetskidf1d0582013-08-29 17:14:49 +0200[diff] [blame]8 "renesas,sdhi-r8a73a4" - SDHI IP on R8A73A4 SoC
9 "renesas,sdhi-r8a7740" - SDHI IP on R8A7740 SoC
Biju Das34292312017-08-21 13:25:11 +0100[diff] [blame]10 "renesas,sdhi-r8a7743" - SDHI IP on R8A7743 SoC
Biju Dasbd451c2d2018-09-25 18:23:07 +0100[diff] [blame]11 "renesas,sdhi-r8a7744" - SDHI IP on R8A7744 SoC
Biju Das34292312017-08-21 13:25:11 +0100[diff] [blame]12 "renesas,sdhi-r8a7745" - SDHI IP on R8A7745 SoC
Fabrizio Castro722c68a2018-08-14 13:34:34 +0100[diff] [blame]13 "renesas,sdhi-r8a774a1" - SDHI IP on R8A774A1 SoC
Fabrizio Castroab409be2018-12-13 20:22:09 +0000[diff] [blame]14 "renesas,sdhi-r8a774c0" - SDHI IP on R8A774C0 SoC
Fabrizio Castrobe6f8db2018-10-08 09:51:47 +0100[diff] [blame]15 "renesas,sdhi-r8a77470" - SDHI IP on R8A77470 SoC
16 "renesas,sdhi-mmc-r8a77470" - SDHI/MMC IP on R8A77470 SoC
Guennadi Liakhovetskidf1d0582013-08-29 17:14:49 +0200[diff] [blame]17 "renesas,sdhi-r8a7778" - SDHI IP on R8A7778 SoC
18 "renesas,sdhi-r8a7779" - SDHI IP on R8A7779 SoC
19 "renesas,sdhi-r8a7790" - SDHI IP on R8A7790 SoC
Geert Uytterhoevenbf797842014-07-09 14:23:34 +0200[diff] [blame]20 "renesas,sdhi-r8a7791" - SDHI IP on R8A7791 SoC
Geert Uytterhoevena6386402014-08-28 10:07:19 +0200[diff] [blame]21 "renesas,sdhi-r8a7792" - SDHI IP on R8A7792 SoC
22 "renesas,sdhi-r8a7793" - SDHI IP on R8A7793 SoC
23 "renesas,sdhi-r8a7794" - SDHI IP on R8A7794 SoC
Wolfram Sanga72e8b12016-02-15 16:01:48 +0100[diff] [blame]24 "renesas,sdhi-r8a7795" - SDHI IP on R8A7795 SoC
Ai Kyuse7428e0b2016-09-06 12:38:38 +0200[diff] [blame]25 "renesas,sdhi-r8a7796" - SDHI IP on R8A7796 SoC
Masaharu Hayakawacaeffcf2018-05-09 21:38:48 +0900[diff] [blame]26 "renesas,sdhi-r8a77965" - SDHI IP on R8A77965 SoC
Sergei Shtylyov00c65272018-08-21 22:14:12 +0300[diff] [blame]27 "renesas,sdhi-r8a77970" - SDHI IP on R8A77970 SoC
Sergei Shtylyovb6386022018-04-16 21:30:02 +0300[diff] [blame]28 "renesas,sdhi-r8a77980" - SDHI IP on R8A77980 SoC
Wolfram Sange432e4202018-07-21 13:14:49 +0200[diff] [blame]29 "renesas,sdhi-r8a77990" - SDHI IP on R8A77990 SoC
Ulrich Hecht448f2f82017-11-15 16:25:49 +0100[diff] [blame]30 "renesas,sdhi-r8a77995" - SDHI IP on R8A77995 SoC
Simon Horman54839d02017-10-18 09:00:22 +0200[diff] [blame]31 "renesas,sdhi-shmobile" - a generic sh-mobile SDHI controller
32 "renesas,rcar-gen1-sdhi" - a generic R-Car Gen1 SDHI controller
Fabrizio Castrobe6f8db2018-10-08 09:51:47 +0100[diff] [blame]33 "renesas,rcar-gen2-sdhi" - a generic R-Car Gen2 and RZ/G1 SDHI
34 (not SDHI/MMC) controller
Fabrizio Castro722c68a2018-08-14 13:34:34 +0100[diff] [blame]35 "renesas,rcar-gen3-sdhi" - a generic R-Car Gen3 or RZ/G2
36 SDHI controller
Simon Horman54839d02017-10-18 09:00:22 +0200[diff] [blame]37
38
39 When compatible with the generic version, nodes must list
40 the SoC-specific version corresponding to the platform
41 first followed by the generic version.
Guennadi Liakhovetskidf1d0582013-08-29 17:14:49 +0200[diff] [blame]42
Chris Brandt62a4cde2017-01-25 15:28:09 -0500[diff] [blame]43- clocks: Most controllers only have 1 clock source per channel. However, on
44 some variations of this controller, the internal card detection
45 logic that exists in this controller is sectioned off to be run by a
46 separate second clock source to allow the main core clock to be turned
47 off to save power.
48 If 2 clocks are specified by the hardware, you must name them as
49 "core" and "cd". If the controller only has 1 clock, naming is not
50 required.
Biju Das34292312017-08-21 13:25:11 +0100[diff] [blame]51 Devices which have more than 1 clock are listed below:
Chris Brandtbb169562018-10-24 17:23:01 -0500[diff] [blame]52 2: R7S72100, R7S9210
Chris Brandt62a4cde2017-01-25 15:28:09 -0500[diff] [blame]53
Guennadi Liakhovetskid8048202013-02-15 16:13:55 +0100[diff] [blame]54Optional properties:
Wolfram Sang057a4592016-04-01 17:44:37 +0200[diff] [blame]55- pinctrl-names: should be "default", "state_uhs"
56- pinctrl-0: should contain default/high speed pin ctrl
57- pinctrl-1: should contain uhs mode pin ctrl
Simon Horman95e91ad2017-10-18 09:00:21 +0200[diff] [blame]58
59Example: R8A7790 (R-Car H2) SDHI controller nodes
60
61 sdhi0: sd@ee100000 {
Simon Horman54839d02017-10-18 09:00:22 +0200[diff] [blame]62 compatible = "renesas,sdhi-r8a7790", "renesas,rcar-gen2-sdhi";
Simon Horman95e91ad2017-10-18 09:00:21 +0200[diff] [blame]63 reg = <0 0xee100000 0 0x328>;
64 interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
65 clocks = <&cpg CPG_MOD 314>;
66 dmas = <&dmac0 0xcd>, <&dmac0 0xce>,
67 <&dmac1 0xcd>, <&dmac1 0xce>;
68 dma-names = "tx", "rx", "tx", "rx";
69 max-frequency = <195000000>;
70 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
71 resets = <&cpg 314>;
Simon Horman95e91ad2017-10-18 09:00:21 +0200[diff] [blame]72 };
73
74 sdhi1: sd@ee120000 {
Simon Horman54839d02017-10-18 09:00:22 +0200[diff] [blame]75 compatible = "renesas,sdhi-r8a7790", "renesas,rcar-gen2-sdhi";
Simon Horman95e91ad2017-10-18 09:00:21 +0200[diff] [blame]76 reg = <0 0xee120000 0 0x328>;
77 interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
78 clocks = <&cpg CPG_MOD 313>;
79 dmas = <&dmac0 0xc9>, <&dmac0 0xca>,
80 <&dmac1 0xc9>, <&dmac1 0xca>;
81 dma-names = "tx", "rx", "tx", "rx";
82 max-frequency = <195000000>;
83 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
84 resets = <&cpg 313>;
Simon Horman95e91ad2017-10-18 09:00:21 +0200[diff] [blame]85 };
86
87 sdhi2: sd@ee140000 {
Simon Horman54839d02017-10-18 09:00:22 +0200[diff] [blame]88 compatible = "renesas,sdhi-r8a7790", "renesas,rcar-gen2-sdhi";
Simon Horman95e91ad2017-10-18 09:00:21 +0200[diff] [blame]89 reg = <0 0xee140000 0 0x100>;
90 interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
91 clocks = <&cpg CPG_MOD 312>;
92 dmas = <&dmac0 0xc1>, <&dmac0 0xc2>,
93 <&dmac1 0xc1>, <&dmac1 0xc2>;
94 dma-names = "tx", "rx", "tx", "rx";
95 max-frequency = <97500000>;
96 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
97 resets = <&cpg 312>;
Simon Horman95e91ad2017-10-18 09:00:21 +0200[diff] [blame]98 };
99
100 sdhi3: sd@ee160000 {
Simon Horman54839d02017-10-18 09:00:22 +0200[diff] [blame]101 compatible = "renesas,sdhi-r8a7790", "renesas,rcar-gen2-sdhi";
Simon Horman95e91ad2017-10-18 09:00:21 +0200[diff] [blame]102 reg = <0 0xee160000 0 0x100>;
103 interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
104 clocks = <&cpg CPG_MOD 311>;
105 dmas = <&dmac0 0xd3>, <&dmac0 0xd4>,
106 <&dmac1 0xd3>, <&dmac1 0xd4>;
107 dma-names = "tx", "rx", "tx", "rx";
108 max-frequency = <97500000>;
109 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
110 resets = <&cpg 311>;
Simon Horman95e91ad2017-10-18 09:00:21 +0200[diff] [blame]111 };