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Thomas Gleixner03761482019-05-28 09:57:24 -07001// SPDX-License-Identifier: GPL-2.0-only
Mattias Wallin489bcce2011-05-27 10:30:12 +02002/*
3 * Copyright (C) ST-Ericsson SA 2011
4 *
Mattias Wallin489bcce2011-05-27 10:30:12 +02005 * Author: Mattias Wallin <mattias.wallin@stericsson.com> for ST-Ericsson
6 * Author: Sundar Iyer for ST-Ericsson
7 * sched_clock implementation is based on:
8 * plat-nomadik/timer.c Linus Walleij <linus.walleij@stericsson.com>
9 *
10 * DBx500-PRCMU Timer
11 * The PRCMU has 5 timers which are available in a always-on
12 * power domain. We use the Timer 4 for our always-on clock
Fabio Baltieri807eba52013-01-21 13:09:32 +010013 * source on DB8500.
Mattias Wallin489bcce2011-05-27 10:30:12 +020014 */
Linus Walleij9d2aa8c2015-12-01 15:00:24 +010015#include <linux/of.h>
16#include <linux/of_address.h>
Mattias Wallin489bcce2011-05-27 10:30:12 +020017#include <linux/clockchips.h>
Mattias Wallin489bcce2011-05-27 10:30:12 +020018
Mattias Wallin489bcce2011-05-27 10:30:12 +020019#define RATE_32K 32768
20
21#define TIMER_MODE_CONTINOUS 0x1
22#define TIMER_DOWNCOUNT_VAL 0xffffffff
23
24#define PRCMU_TIMER_REF 0
25#define PRCMU_TIMER_DOWNCOUNT 0x4
26#define PRCMU_TIMER_MODE 0x8
27
Linus Walleijb1e3be062011-10-03 09:30:20 +020028static void __iomem *clksrc_dbx500_timer_base;
Mattias Wallin489bcce2011-05-27 10:30:12 +020029
Thomas Gleixnera5a1d1c2016-12-21 20:32:01 +010030static u64 notrace clksrc_dbx500_prcmu_read(struct clocksource *cs)
Mattias Wallin489bcce2011-05-27 10:30:12 +020031{
Rabin Vincent53028222013-01-21 13:09:31 +010032 void __iomem *base = clksrc_dbx500_timer_base;
Mattias Wallin489bcce2011-05-27 10:30:12 +020033 u32 count, count2;
34
35 do {
Rabin Vincent53028222013-01-21 13:09:31 +010036 count = readl_relaxed(base + PRCMU_TIMER_DOWNCOUNT);
37 count2 = readl_relaxed(base + PRCMU_TIMER_DOWNCOUNT);
Mattias Wallin489bcce2011-05-27 10:30:12 +020038 } while (count2 != count);
39
40 /* Negate because the timer is a decrementing counter */
41 return ~count;
42}
43
44static struct clocksource clocksource_dbx500_prcmu = {
45 .name = "dbx500-prcmu-timer",
Linus Walleijbc0750e2018-11-15 14:32:02 +010046 .rating = 100,
Mattias Wallin489bcce2011-05-27 10:30:12 +020047 .read = clksrc_dbx500_prcmu_read,
Mattias Wallin489bcce2011-05-27 10:30:12 +020048 .mask = CLOCKSOURCE_MASK(32),
Linus Walleijbc0750e2018-11-15 14:32:02 +010049 .flags = CLOCK_SOURCE_IS_CONTINUOUS | CLOCK_SOURCE_SUSPEND_NONSTOP,
Mattias Wallin489bcce2011-05-27 10:30:12 +020050};
51
Daniel Lezcano108a4ed2016-06-02 19:44:34 +020052static int __init clksrc_dbx500_prcmu_init(struct device_node *node)
Mattias Wallin489bcce2011-05-27 10:30:12 +020053{
Linus Walleij9d2aa8c2015-12-01 15:00:24 +010054 clksrc_dbx500_timer_base = of_iomap(node, 0);
Linus Walleijb1e3be062011-10-03 09:30:20 +020055
Mattias Wallin489bcce2011-05-27 10:30:12 +020056 /*
57 * The A9 sub system expects the timer to be configured as
58 * a continous looping timer.
59 * The PRCMU should configure it but if it for some reason
60 * don't we do it here.
61 */
62 if (readl(clksrc_dbx500_timer_base + PRCMU_TIMER_MODE) !=
63 TIMER_MODE_CONTINOUS) {
64 writel(TIMER_MODE_CONTINOUS,
65 clksrc_dbx500_timer_base + PRCMU_TIMER_MODE);
66 writel(TIMER_DOWNCOUNT_VAL,
67 clksrc_dbx500_timer_base + PRCMU_TIMER_REF);
68 }
Daniel Lezcano108a4ed2016-06-02 19:44:34 +020069 return clocksource_register_hz(&clocksource_dbx500_prcmu, RATE_32K);
Mattias Wallin489bcce2011-05-27 10:30:12 +020070}
Daniel Lezcano17273392017-05-26 16:56:11 +020071TIMER_OF_DECLARE(dbx500_prcmu, "stericsson,db8500-prcmu-timer-4",
Linus Walleij9d2aa8c2015-12-01 15:00:24 +010072 clksrc_dbx500_prcmu_init);