Thomas Gleixner | 0376148 | 2019-05-28 09:57:24 -0700 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0-only |
Mattias Wallin | 489bcce | 2011-05-27 10:30:12 +0200 | [diff] [blame] | 2 | /* |
| 3 | * Copyright (C) ST-Ericsson SA 2011 |
| 4 | * |
Mattias Wallin | 489bcce | 2011-05-27 10:30:12 +0200 | [diff] [blame] | 5 | * Author: Mattias Wallin <mattias.wallin@stericsson.com> for ST-Ericsson |
| 6 | * Author: Sundar Iyer for ST-Ericsson |
| 7 | * sched_clock implementation is based on: |
| 8 | * plat-nomadik/timer.c Linus Walleij <linus.walleij@stericsson.com> |
| 9 | * |
| 10 | * DBx500-PRCMU Timer |
| 11 | * The PRCMU has 5 timers which are available in a always-on |
| 12 | * power domain. We use the Timer 4 for our always-on clock |
Fabio Baltieri | 807eba5 | 2013-01-21 13:09:32 +0100 | [diff] [blame] | 13 | * source on DB8500. |
Mattias Wallin | 489bcce | 2011-05-27 10:30:12 +0200 | [diff] [blame] | 14 | */ |
Linus Walleij | 9d2aa8c | 2015-12-01 15:00:24 +0100 | [diff] [blame] | 15 | #include <linux/of.h> |
| 16 | #include <linux/of_address.h> |
Mattias Wallin | 489bcce | 2011-05-27 10:30:12 +0200 | [diff] [blame] | 17 | #include <linux/clockchips.h> |
Mattias Wallin | 489bcce | 2011-05-27 10:30:12 +0200 | [diff] [blame] | 18 | |
Mattias Wallin | 489bcce | 2011-05-27 10:30:12 +0200 | [diff] [blame] | 19 | #define RATE_32K 32768 |
| 20 | |
| 21 | #define TIMER_MODE_CONTINOUS 0x1 |
| 22 | #define TIMER_DOWNCOUNT_VAL 0xffffffff |
| 23 | |
| 24 | #define PRCMU_TIMER_REF 0 |
| 25 | #define PRCMU_TIMER_DOWNCOUNT 0x4 |
| 26 | #define PRCMU_TIMER_MODE 0x8 |
| 27 | |
Linus Walleij | b1e3be06 | 2011-10-03 09:30:20 +0200 | [diff] [blame] | 28 | static void __iomem *clksrc_dbx500_timer_base; |
Mattias Wallin | 489bcce | 2011-05-27 10:30:12 +0200 | [diff] [blame] | 29 | |
Thomas Gleixner | a5a1d1c | 2016-12-21 20:32:01 +0100 | [diff] [blame] | 30 | static u64 notrace clksrc_dbx500_prcmu_read(struct clocksource *cs) |
Mattias Wallin | 489bcce | 2011-05-27 10:30:12 +0200 | [diff] [blame] | 31 | { |
Rabin Vincent | 5302822 | 2013-01-21 13:09:31 +0100 | [diff] [blame] | 32 | void __iomem *base = clksrc_dbx500_timer_base; |
Mattias Wallin | 489bcce | 2011-05-27 10:30:12 +0200 | [diff] [blame] | 33 | u32 count, count2; |
| 34 | |
| 35 | do { |
Rabin Vincent | 5302822 | 2013-01-21 13:09:31 +0100 | [diff] [blame] | 36 | count = readl_relaxed(base + PRCMU_TIMER_DOWNCOUNT); |
| 37 | count2 = readl_relaxed(base + PRCMU_TIMER_DOWNCOUNT); |
Mattias Wallin | 489bcce | 2011-05-27 10:30:12 +0200 | [diff] [blame] | 38 | } while (count2 != count); |
| 39 | |
| 40 | /* Negate because the timer is a decrementing counter */ |
| 41 | return ~count; |
| 42 | } |
| 43 | |
| 44 | static struct clocksource clocksource_dbx500_prcmu = { |
| 45 | .name = "dbx500-prcmu-timer", |
Linus Walleij | bc0750e | 2018-11-15 14:32:02 +0100 | [diff] [blame] | 46 | .rating = 100, |
Mattias Wallin | 489bcce | 2011-05-27 10:30:12 +0200 | [diff] [blame] | 47 | .read = clksrc_dbx500_prcmu_read, |
Mattias Wallin | 489bcce | 2011-05-27 10:30:12 +0200 | [diff] [blame] | 48 | .mask = CLOCKSOURCE_MASK(32), |
Linus Walleij | bc0750e | 2018-11-15 14:32:02 +0100 | [diff] [blame] | 49 | .flags = CLOCK_SOURCE_IS_CONTINUOUS | CLOCK_SOURCE_SUSPEND_NONSTOP, |
Mattias Wallin | 489bcce | 2011-05-27 10:30:12 +0200 | [diff] [blame] | 50 | }; |
| 51 | |
Daniel Lezcano | 108a4ed | 2016-06-02 19:44:34 +0200 | [diff] [blame] | 52 | static int __init clksrc_dbx500_prcmu_init(struct device_node *node) |
Mattias Wallin | 489bcce | 2011-05-27 10:30:12 +0200 | [diff] [blame] | 53 | { |
Linus Walleij | 9d2aa8c | 2015-12-01 15:00:24 +0100 | [diff] [blame] | 54 | clksrc_dbx500_timer_base = of_iomap(node, 0); |
Linus Walleij | b1e3be06 | 2011-10-03 09:30:20 +0200 | [diff] [blame] | 55 | |
Mattias Wallin | 489bcce | 2011-05-27 10:30:12 +0200 | [diff] [blame] | 56 | /* |
| 57 | * The A9 sub system expects the timer to be configured as |
| 58 | * a continous looping timer. |
| 59 | * The PRCMU should configure it but if it for some reason |
| 60 | * don't we do it here. |
| 61 | */ |
| 62 | if (readl(clksrc_dbx500_timer_base + PRCMU_TIMER_MODE) != |
| 63 | TIMER_MODE_CONTINOUS) { |
| 64 | writel(TIMER_MODE_CONTINOUS, |
| 65 | clksrc_dbx500_timer_base + PRCMU_TIMER_MODE); |
| 66 | writel(TIMER_DOWNCOUNT_VAL, |
| 67 | clksrc_dbx500_timer_base + PRCMU_TIMER_REF); |
| 68 | } |
Daniel Lezcano | 108a4ed | 2016-06-02 19:44:34 +0200 | [diff] [blame] | 69 | return clocksource_register_hz(&clocksource_dbx500_prcmu, RATE_32K); |
Mattias Wallin | 489bcce | 2011-05-27 10:30:12 +0200 | [diff] [blame] | 70 | } |
Daniel Lezcano | 1727339 | 2017-05-26 16:56:11 +0200 | [diff] [blame] | 71 | TIMER_OF_DECLARE(dbx500_prcmu, "stericsson,db8500-prcmu-timer-4", |
Linus Walleij | 9d2aa8c | 2015-12-01 15:00:24 +0100 | [diff] [blame] | 72 | clksrc_dbx500_prcmu_init); |