Thomas Gleixner | caab277 | 2019-06-03 07:44:50 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Mark Rutland | 8a4da6e | 2012-11-12 14:33:44 +0000 | [diff] [blame] | 2 | /* |
| 3 | * Copyright (C) 2012 ARM Ltd. |
Mark Rutland | 8a4da6e | 2012-11-12 14:33:44 +0000 | [diff] [blame] | 4 | */ |
| 5 | #ifndef __CLKSOURCE_ARM_ARCH_TIMER_H |
| 6 | #define __CLKSOURCE_ARM_ARCH_TIMER_H |
| 7 | |
Fu Wei | 831610c0 | 2017-01-18 21:25:28 +0800 | [diff] [blame] | 8 | #include <linux/bitops.h> |
Richard Cochran | 74d23cc | 2014-12-21 19:46:56 +0100 | [diff] [blame] | 9 | #include <linux/timecounter.h> |
Mark Rutland | 8a4da6e | 2012-11-12 14:33:44 +0000 | [diff] [blame] | 10 | #include <linux/types.h> |
| 11 | |
Fu Wei | 831610c0 | 2017-01-18 21:25:28 +0800 | [diff] [blame] | 12 | #define ARCH_TIMER_TYPE_CP15 BIT(0) |
| 13 | #define ARCH_TIMER_TYPE_MEM BIT(1) |
| 14 | |
Mark Rutland | 8a4da6e | 2012-11-12 14:33:44 +0000 | [diff] [blame] | 15 | #define ARCH_TIMER_CTRL_ENABLE (1 << 0) |
| 16 | #define ARCH_TIMER_CTRL_IT_MASK (1 << 1) |
| 17 | #define ARCH_TIMER_CTRL_IT_STAT (1 << 2) |
| 18 | |
Marc Zyngier | 1431af3 | 2015-10-19 16:32:20 +0100 | [diff] [blame] | 19 | #define CNTHCTL_EL1PCTEN (1 << 0) |
| 20 | #define CNTHCTL_EL1PCEN (1 << 1) |
| 21 | #define CNTHCTL_EVNTEN (1 << 2) |
| 22 | #define CNTHCTL_EVNTDIR (1 << 3) |
| 23 | #define CNTHCTL_EVNTI (0xF << 4) |
| 24 | |
Stephen Boyd | e09f3cc | 2013-07-18 16:59:28 -0700 | [diff] [blame] | 25 | enum arch_timer_reg { |
| 26 | ARCH_TIMER_REG_CTRL, |
| 27 | ARCH_TIMER_REG_TVAL, |
| 28 | }; |
Mark Rutland | 8a4da6e | 2012-11-12 14:33:44 +0000 | [diff] [blame] | 29 | |
Fu Wei | 831610c0 | 2017-01-18 21:25:28 +0800 | [diff] [blame] | 30 | enum arch_timer_ppi_nr { |
| 31 | ARCH_TIMER_PHYS_SECURE_PPI, |
| 32 | ARCH_TIMER_PHYS_NONSECURE_PPI, |
| 33 | ARCH_TIMER_VIRT_PPI, |
| 34 | ARCH_TIMER_HYP_PPI, |
Hector Martin | 86332e9 | 2021-02-14 16:11:30 +0900 | [diff] [blame] | 35 | ARCH_TIMER_HYP_VIRT_PPI, |
Fu Wei | 831610c0 | 2017-01-18 21:25:28 +0800 | [diff] [blame] | 36 | ARCH_TIMER_MAX_TIMER_PPI |
| 37 | }; |
| 38 | |
Fu Wei | 097cd14 | 2017-01-18 21:25:29 +0800 | [diff] [blame] | 39 | enum arch_timer_spi_nr { |
| 40 | ARCH_TIMER_PHYS_SPI, |
| 41 | ARCH_TIMER_VIRT_SPI, |
| 42 | ARCH_TIMER_MAX_TIMER_SPI |
| 43 | }; |
| 44 | |
Mark Rutland | 8a4da6e | 2012-11-12 14:33:44 +0000 | [diff] [blame] | 45 | #define ARCH_TIMER_PHYS_ACCESS 0 |
| 46 | #define ARCH_TIMER_VIRT_ACCESS 1 |
Stephen Boyd | 2200699 | 2013-07-18 16:59:32 -0700 | [diff] [blame] | 47 | #define ARCH_TIMER_MEM_PHYS_ACCESS 2 |
| 48 | #define ARCH_TIMER_MEM_VIRT_ACCESS 3 |
Mark Rutland | 8a4da6e | 2012-11-12 14:33:44 +0000 | [diff] [blame] | 49 | |
Fu Wei | b3251b8 | 2017-04-01 01:50:59 +0800 | [diff] [blame] | 50 | #define ARCH_TIMER_MEM_MAX_FRAMES 8 |
| 51 | |
Sudeep KarkadaNagesha | 2806175 | 2013-08-13 13:43:26 +0100 | [diff] [blame] | 52 | #define ARCH_TIMER_USR_PCT_ACCESS_EN (1 << 0) /* physical counter */ |
| 53 | #define ARCH_TIMER_USR_VCT_ACCESS_EN (1 << 1) /* virtual counter */ |
| 54 | #define ARCH_TIMER_VIRT_EVT_EN (1 << 2) |
| 55 | #define ARCH_TIMER_EVT_TRIGGER_SHIFT (4) |
| 56 | #define ARCH_TIMER_EVT_TRIGGER_MASK (0xF << ARCH_TIMER_EVT_TRIGGER_SHIFT) |
| 57 | #define ARCH_TIMER_USR_VT_ACCESS_EN (1 << 8) /* virtual timer registers */ |
| 58 | #define ARCH_TIMER_USR_PT_ACCESS_EN (1 << 9) /* physical timer registers */ |
| 59 | |
Julien Thierry | 7b77452e | 2017-10-13 14:32:56 +0100 | [diff] [blame] | 60 | #define ARCH_TIMER_EVT_STREAM_PERIOD_US 100 |
| 61 | #define ARCH_TIMER_EVT_STREAM_FREQ \ |
| 62 | (USEC_PER_SEC / ARCH_TIMER_EVT_STREAM_PERIOD_US) |
Will Deacon | 037f637 | 2013-08-23 15:32:29 +0100 | [diff] [blame] | 63 | |
Julien Grall | b4d6ce9 | 2016-04-11 16:32:51 +0100 | [diff] [blame] | 64 | struct arch_timer_kvm_info { |
| 65 | struct timecounter timecounter; |
Julien Grall | d9b5e41 | 2016-04-11 16:32:52 +0100 | [diff] [blame] | 66 | int virtual_irq; |
Andre Przywara | ee79304 | 2018-07-06 09:11:50 +0100 | [diff] [blame] | 67 | int physical_irq; |
Julien Grall | b4d6ce9 | 2016-04-11 16:32:51 +0100 | [diff] [blame] | 68 | }; |
| 69 | |
Fu Wei | b3251b8 | 2017-04-01 01:50:59 +0800 | [diff] [blame] | 70 | struct arch_timer_mem_frame { |
| 71 | bool valid; |
| 72 | phys_addr_t cntbase; |
| 73 | size_t size; |
| 74 | int phys_irq; |
| 75 | int virt_irq; |
| 76 | }; |
| 77 | |
| 78 | struct arch_timer_mem { |
| 79 | phys_addr_t cntctlbase; |
| 80 | size_t size; |
| 81 | struct arch_timer_mem_frame frame[ARCH_TIMER_MEM_MAX_FRAMES]; |
| 82 | }; |
| 83 | |
Mark Rutland | 8a4da6e | 2012-11-12 14:33:44 +0000 | [diff] [blame] | 84 | #ifdef CONFIG_ARM_ARCH_TIMER |
| 85 | |
Mark Rutland | 8a4da6e | 2012-11-12 14:33:44 +0000 | [diff] [blame] | 86 | extern u32 arch_timer_get_rate(void); |
Stephen Boyd | 2200699 | 2013-07-18 16:59:32 -0700 | [diff] [blame] | 87 | extern u64 (*arch_timer_read_counter)(void); |
Julien Grall | b4d6ce9 | 2016-04-11 16:32:51 +0100 | [diff] [blame] | 88 | extern struct arch_timer_kvm_info *arch_timer_get_kvm_info(void); |
Julien Thierry | ec5c8e4 | 2017-10-13 14:32:55 +0100 | [diff] [blame] | 89 | extern bool arch_timer_evtstrm_available(void); |
Mark Rutland | 8a4da6e | 2012-11-12 14:33:44 +0000 | [diff] [blame] | 90 | |
| 91 | #else |
| 92 | |
Mark Rutland | 8a4da6e | 2012-11-12 14:33:44 +0000 | [diff] [blame] | 93 | static inline u32 arch_timer_get_rate(void) |
| 94 | { |
| 95 | return 0; |
| 96 | } |
| 97 | |
| 98 | static inline u64 arch_timer_read_counter(void) |
| 99 | { |
| 100 | return 0; |
| 101 | } |
| 102 | |
Julien Thierry | ec5c8e4 | 2017-10-13 14:32:55 +0100 | [diff] [blame] | 103 | static inline bool arch_timer_evtstrm_available(void) |
| 104 | { |
| 105 | return false; |
| 106 | } |
| 107 | |
Mark Rutland | 8a4da6e | 2012-11-12 14:33:44 +0000 | [diff] [blame] | 108 | #endif |
| 109 | |
| 110 | #endif |