Thomas Gleixner | 2874c5f | 2019-05-27 08:55:01 +0200 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0-or-later |
Heiko Schocher | 3015fb3 | 2012-05-30 12:19:03 +0200 | [diff] [blame] | 2 | /* |
3 | * Device Tree for AM1808 EnBW CMC board | ||||
4 | * | ||||
5 | * Copyright 2012 DENX Software Engineering GmbH | ||||
6 | * Heiko Schocher <hs@denx.de> | ||||
Heiko Schocher | 3015fb3 | 2012-05-30 12:19:03 +0200 | [diff] [blame] | 7 | */ |
8 | /dts-v1/; | ||||
Philip Avinash | a2bcd77 | 2013-06-14 15:15:53 +0530 | [diff] [blame] | 9 | #include "da850.dtsi" |
Heiko Schocher | 3015fb3 | 2012-05-30 12:19:03 +0200 | [diff] [blame] | 10 | |
11 | / { | ||||
12 | compatible = "enbw,cmc", "ti,da850"; | ||||
13 | model = "EnBW CMC"; | ||||
14 | |||||
David Lechner | c2a3b4b | 2016-04-01 17:42:03 +0200 | [diff] [blame] | 15 | soc@1c00000 { |
16 | serial0: serial@42000 { | ||||
Heiko Schocher | 3015fb3 | 2012-05-30 12:19:03 +0200 | [diff] [blame] | 17 | status = "okay"; |
18 | }; | ||||
David Lechner | c2a3b4b | 2016-04-01 17:42:03 +0200 | [diff] [blame] | 19 | serial1: serial@10c000 { |
Heiko Schocher | 3015fb3 | 2012-05-30 12:19:03 +0200 | [diff] [blame] | 20 | status = "okay"; |
21 | }; | ||||
David Lechner | c2a3b4b | 2016-04-01 17:42:03 +0200 | [diff] [blame] | 22 | serial2: serial@10d000 { |
Heiko Schocher | 3015fb3 | 2012-05-30 12:19:03 +0200 | [diff] [blame] | 23 | status = "okay"; |
24 | }; | ||||
David Lechner | 5209a8f | 2016-04-16 12:00:19 -0500 | [diff] [blame] | 25 | mdio: mdio@224000 { |
26 | status = "okay"; | ||||
27 | }; | ||||
28 | eth0: ethernet@220000 { | ||||
29 | status = "okay"; | ||||
30 | }; | ||||
Heiko Schocher | 3015fb3 | 2012-05-30 12:19:03 +0200 | [diff] [blame] | 31 | }; |
32 | }; | ||||
Peter Ujfalusi | 7a7faed | 2015-12-17 15:27:48 +0200 | [diff] [blame] | 33 | |
David Lechner | 3652e27 | 2018-05-18 11:48:29 -0500 | [diff] [blame] | 34 | &ref_clk { |
35 | clock-frequency = <24000000>; | ||||
36 | }; | ||||
37 | |||||
Peter Ujfalusi | 7a7faed | 2015-12-17 15:27:48 +0200 | [diff] [blame] | 38 | &edma0 { |
39 | ti,edma-reserved-slot-ranges = <32 50>; | ||||
40 | }; | ||||
Peter Ujfalusi | b47a856 | 2015-12-17 15:27:49 +0200 | [diff] [blame] | 41 | |
42 | &edma1 { | ||||
43 | ti,edma-reserved-slot-ranges = <32 90>; | ||||
44 | }; |