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Rob Herring30058672013-01-28 16:13:14 +00001menuconfig MAILBOX
2 bool "Mailbox Hardware Support"
3 help
4 Mailbox is a framework to control hardware communication between
5 on-chip processors through queued messages and interrupt driven
6 signals. Say Y if your platform supports hardware mailboxes.
7
8if MAILBOX
Jassi Braree23d662014-06-26 19:09:42 +05309
10config ARM_MHU
11 tristate "ARM MHU Mailbox"
12 depends on ARM_AMBA
13 help
14 Say Y here if you want to build the ARM MHU controller driver.
15 The controller has 3 mailbox channels, the last of which can be
16 used in Secure mode only.
17
Oleksij Rempel2bb70052018-08-03 07:29:19 +020018config IMX_MBOX
19 tristate "i.MX Mailbox"
20 depends on ARCH_MXC || COMPILE_TEST
21 help
22 Mailbox implementation for i.MX Messaging Unit (MU).
23
Neil Armstrongad3a2122016-08-18 12:10:25 +020024config PLATFORM_MHU
25 tristate "Platform MHU Mailbox"
26 depends on OF
27 depends on HAS_IOMEM
28 help
29 Say Y here if you want to build a platform specific variant MHU
30 controller driver.
31 The controller has a maximum of 3 mailbox channels, the last of
32 which can be used in Secure mode only.
33
Rob Herring30058672013-01-28 16:13:14 +000034config PL320_MBOX
35 bool "ARM PL320 Mailbox"
36 depends on ARM_AMBA
37 help
38 An implementation of the ARM PL320 Interprocessor Communication
39 Mailbox (IPCM), tailored for the Calxeda Highbank. It is used to
40 send short messages between Highbank's A9 cores and the EnergyCore
41 Management Engine, primarily for cpufreq. Say Y here if you want
42 to use the PL320 IPCM support.
43
Suman Annac869c752013-03-12 17:55:29 -050044config OMAP2PLUS_MBOX
45 tristate "OMAP2+ Mailbox framework support"
46 depends on ARCH_OMAP2PLUS
Suman Annac869c752013-03-12 17:55:29 -050047 help
48 Mailbox implementation for OMAP family chips with hardware for
49 interprocessor communication involving DSP, IVA1.0 and IVA2 in
50 OMAP2/3; or IPU, IVA HD and DSP in OMAP4/5. Say Y here if you
51 want to use OMAP2+ Mailbox framework support.
52
53config OMAP_MBOX_KFIFO_SIZE
54 int "Mailbox kfifo default buffer size (bytes)"
Suman Anna79859092014-06-24 19:43:38 -050055 depends on OMAP2PLUS_MBOX
Suman Annac869c752013-03-12 17:55:29 -050056 default 256
57 help
58 Specify the default size of mailbox's kfifo buffers (bytes).
59 This can also be changed at runtime (via the mbox_kfifo_size
60 module parameter).
Ashwin Chaugule86c22f82014-11-12 19:59:38 -050061
Caesar Wangf70ed3b2015-10-27 15:31:45 +080062config ROCKCHIP_MBOX
63 bool "Rockchip Soc Intergrated Mailbox Support"
64 depends on ARCH_ROCKCHIP || COMPILE_TEST
65 help
66 This driver provides support for inter-processor communication
67 between CPU cores and MCU processor on Some Rockchip SOCs.
68 Please check it that the Soc you use have Mailbox hardware.
69 Say Y here if you want to use the Rockchip Mailbox support.
70
Ashwin Chaugule86c22f82014-11-12 19:59:38 -050071config PCC
72 bool "Platform Communication Channel Driver"
73 depends on ACPI
Ashwin Chauguleb6fc6072015-08-05 09:40:31 -040074 default n
Ashwin Chaugule86c22f82014-11-12 19:59:38 -050075 help
76 ACPI 5.0+ spec defines a generic mode of communication
77 between the OS and a platform such as the BMC. This medium
78 (PCC) is typically used by CPPC (ACPI CPU Performance management),
79 RAS (ACPI reliability protocol) and MPST (ACPI Memory power
80 states). Select this driver if your platform implements the
81 PCC clients mentioned above.
82
Ley Foon Tanf62092f2015-02-04 16:32:18 +080083config ALTERA_MBOX
84 tristate "Altera Mailbox"
Richard Weinberger59dd3f02015-05-04 20:59:46 +020085 depends on HAS_IOMEM
Ley Foon Tanf62092f2015-02-04 16:32:18 +080086 help
87 An implementation of the Altera Mailbox soft core. It is used
88 to send message between processors. Say Y here if you want to use the
89 Altera mailbox support.
Lubomir Rintel0bae6af2015-05-05 13:27:45 -070090
91config BCM2835_MBOX
92 tristate "BCM2835 Mailbox"
93 depends on ARCH_BCM2835
94 help
95 An implementation of the BCM2385 Mailbox. It is used to invoke
96 the services of the Videocore. Say Y here if you want to use the
97 BCM2835 Mailbox.
98
Lee Jones9ef45462015-10-16 08:21:28 +010099config STI_MBOX
100 tristate "STI Mailbox framework support"
101 depends on ARCH_STI && OF
102 help
103 Mailbox implementation for STMicroelectonics family chips with
104 hardware for interprocessor communication.
105
Nishanth Menonaace66b2016-03-16 19:23:14 -0500106config TI_MESSAGE_MANAGER
107 tristate "Texas Instruments Message Manager Driver"
Nishanth Menoncfc0f7a2018-08-27 19:53:11 -0500108 depends on ARCH_KEYSTONE || ARCH_K3
Nishanth Menonaace66b2016-03-16 19:23:14 -0500109 help
110 An implementation of Message Manager slave driver for Keystone
Nishanth Menoncfc0f7a2018-08-27 19:53:11 -0500111 and K3 architecture SoCs from Texas Instruments. Message Manager
112 is a communication entity found on few of Texas Instrument's keystone
113 and K3 architecture SoCs. These may be used for communication between
Nishanth Menonaace66b2016-03-16 19:23:14 -0500114 multiple processors within the SoC. Select this driver if your
115 platform has support for the hardware block.
116
Kaihua Zhong41c0e932018-02-28 12:54:54 +0800117config HI3660_MBOX
Daniel Lezcanof83d1cf2018-05-22 22:54:49 +0200118 tristate "Hi3660 Mailbox" if EXPERT
119 depends on (ARCH_HISI || COMPILE_TEST)
120 depends on OF
121 default ARCH_HISI
Kaihua Zhong41c0e932018-02-28 12:54:54 +0800122 help
123 An implementation of the hi3660 mailbox. It is used to send message
124 between application processors and other processors/MCU/DSP. Select
125 Y here if you want to use Hi3660 mailbox controller.
126
Leo Yan9c384182016-02-15 21:50:24 +0800127config HI6220_MBOX
Daniel Lezcanof83d1cf2018-05-22 22:54:49 +0200128 tristate "Hi6220 Mailbox" if EXPERT
129 depends on (ARCH_HISI || COMPILE_TEST)
130 depends on OF
131 default ARCH_HISI
Leo Yan9c384182016-02-15 21:50:24 +0800132 help
133 An implementation of the hi6220 mailbox. It is used to send message
134 between application processors and MCU. Say Y here if you want to
135 build Hi6220 mailbox controller driver.
136
Lee Jones8ea44842015-10-16 08:21:30 +0100137config MAILBOX_TEST
138 tristate "Mailbox Test Client"
139 depends on OF
Richard Weinberger65d3b042016-01-25 23:24:09 +0100140 depends on HAS_IOMEM
Lee Jones8ea44842015-10-16 08:21:30 +0100141 help
142 Test client to help with testing new Controller driver
143 implementations.
144
Bjorn Andersson25bfee12017-05-27 16:14:04 -0700145config QCOM_APCS_IPC
146 tristate "Qualcomm APCS IPC driver"
147 depends on ARCH_QCOM || COMPILE_TEST
148 help
149 Say y here to enable support for the APCS IPC mailbox driver,
150 providing an interface for invoking the inter-process communication
151 signals from the application processor to other masters.
152
Thierry Reding0fe88462016-08-19 19:19:39 +0200153config TEGRA_HSP_MBOX
154 bool "Tegra HSP (Hardware Synchronization Primitives) Driver"
Arnd Bergmann85bd2de2018-03-13 13:11:43 +0100155 depends on ARCH_TEGRA
Thierry Reding0fe88462016-08-19 19:19:39 +0200156 help
157 The Tegra HSP driver is used for the interprocessor communication
158 between different remote processors and host processors on Tegra186
159 and later SoCs. Say Y here if you want to have this support.
160 If unsure say N.
161
Duc Dangf700e842016-02-12 19:39:26 -0800162config XGENE_SLIMPRO_MBOX
163 tristate "APM SoC X-Gene SLIMpro Mailbox Controller"
164 depends on ARCH_XGENE
165 help
166 An implementation of the APM X-Gene Interprocessor Communication
167 Mailbox (IPCM) between the ARM 64-bit cores and SLIMpro controller.
168 It is used to send short messages between ARM64-bit cores and
169 the SLIMpro Management Engine, primarily for PM. Say Y here if you
170 want to use the APM X-Gene SLIMpro IPCM support.
Rob Ricea24532f2016-06-30 15:59:23 -0400171
172config BCM_PDC_MBOX
Steve Linfc2041c2017-02-23 09:49:50 -0500173 tristate "Broadcom FlexSparx DMA Mailbox"
174 depends on ARCH_BCM_IPROC || COMPILE_TEST
Rob Ricea24532f2016-06-30 15:59:23 -0400175 help
Steve Linfc2041c2017-02-23 09:49:50 -0500176 Mailbox implementation for the Broadcom FlexSparx DMA ring manager,
Rob Ricea24532f2016-06-30 15:59:23 -0400177 which provides access to various offload engines on Broadcom
Steve Linfc2041c2017-02-23 09:49:50 -0500178 SoCs, including FA2/FA+ on Northstar Plus and PDC on Northstar 2.
Anup Pateldbc049e2017-03-15 12:10:00 +0530179
180config BCM_FLEXRM_MBOX
181 tristate "Broadcom FlexRM Mailbox"
Anup Patel73874912017-03-29 11:00:55 +0530182 depends on ARM64
Scott Branden8f821212017-10-03 10:51:50 +0530183 depends on ARCH_BCM_IPROC || COMPILE_TEST
Anup Pateldbc049e2017-03-15 12:10:00 +0530184 select GENERIC_MSI_IRQ_DOMAIN
Anup Patel22d28b02017-10-03 10:51:52 +0530185 default m if ARCH_BCM_IPROC
Anup Pateldbc049e2017-03-15 12:10:00 +0530186 help
187 Mailbox implementation of the Broadcom FlexRM ring manager,
188 which provides access to various offload engines on Broadcom
189 SoCs. Say Y here if you want to use the Broadcom FlexRM.
Fabien Dessenneffbded72018-05-31 10:27:25 +0200190
191config STM32_IPCC
192 tristate "STM32 IPCC Mailbox"
193 depends on MACH_STM32MP157
194 help
195 Mailbox implementation for STMicroelectonics STM32 family chips
196 with hardware for Inter-Processor Communication Controller (IPCC)
197 between processors. Say Y here if you want to have this support.
Houlong Wei623a6142018-07-25 09:26:40 +0800198
199config MTK_CMDQ_MBOX
200 tristate "MediaTek CMDQ Mailbox Support"
201 depends on ARCH_MEDIATEK || COMPILE_TEST
202 select MTK_INFRACFG
203 help
204 Say yes here to add support for the MediaTek Command Queue (CMDQ)
205 mailbox driver. The CMDQ is used to help read/write registers with
206 critical time limitation, such as updating display configuration
207 during the vblank.
Wendy Liang4981b822019-02-21 16:36:33 -0800208
209config ZYNQMP_IPI_MBOX
210 bool "Xilinx ZynqMP IPI Mailbox"
211 depends on ARCH_ZYNQMP && OF
212 help
213 Say yes here to add support for Xilinx IPI mailbox driver.
214 This mailbox driver is used to send notification or short message
215 between processors with Xilinx ZynqMP IPI. It will place the
216 message to the IPI buffer and will access the IPI control
217 registers to kick the other processor or enquire status.
218
Rob Herring30058672013-01-28 16:13:14 +0000219endif