| Jim Quinlan | d552dde | 2021-12-09 15:47:24 -0500 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ |
| Kevin Cernekee | d666cd0 | 2014-10-20 21:28:05 -0700 | [diff] [blame] | 2 | |
| Kevin Cernekee | d666cd0 | 2014-10-20 21:28:05 -0700 | [diff] [blame] | 3 | #include <linux/types.h> |
| Christoph Hellwig | d59098a | 2018-06-15 13:08:52 +0200 | [diff] [blame] | 4 | #include <asm/bmips.h> |
| Jim Quinlan | d552dde | 2021-12-09 15:47:24 -0500 | [diff] [blame] | 5 | #include <asm/io.h> |
| Kevin Cernekee | d666cd0 | 2014-10-20 21:28:05 -0700 | [diff] [blame] | 6 | |
| Christoph Hellwig | 56e35f9 | 2019-11-07 18:03:11 +0100 | [diff] [blame] | 7 | void arch_sync_dma_for_cpu_all(void) |
| Christoph Hellwig | d59098a | 2018-06-15 13:08:52 +0200 | [diff] [blame] | 8 | { |
| 9 | void __iomem *cbr = BMIPS_GET_CBR(); |
| 10 | u32 cfg; |
| 11 | |
| 12 | if (boot_cpu_type() != CPU_BMIPS3300 && |
| 13 | boot_cpu_type() != CPU_BMIPS4350 && |
| 14 | boot_cpu_type() != CPU_BMIPS4380) |
| 15 | return; |
| 16 | |
| 17 | /* Flush stale data out of the readahead cache */ |
| 18 | cfg = __raw_readl(cbr + BMIPS_RAC_CONFIG); |
| 19 | __raw_writel(cfg | 0x100, cbr + BMIPS_RAC_CONFIG); |
| 20 | __raw_readl(cbr + BMIPS_RAC_CONFIG); |
| 21 | } |