Krzysztof Kozlowski | 84b2170 | 2017-12-25 20:54:32 +0100 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ |
| 2 | // |
| 3 | // Copyright (c) 2004-2005 Simtec Electronics |
| 4 | // http://www.simtec.co.uk/products/SWLINUX/ |
| 5 | // Ben Dooks <ben@simtec.co.uk> |
| 6 | // |
| 7 | // Common code for S3C24XX machines |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 8 | |
Sylwester Nawrocki | 971466b | 2016-08-04 11:56:12 +0200 | [diff] [blame] | 9 | #include <linux/dma-mapping.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 10 | #include <linux/init.h> |
| 11 | #include <linux/module.h> |
| 12 | #include <linux/interrupt.h> |
| 13 | #include <linux/ioport.h> |
Ben Dooks | b6d1f54 | 2006-12-17 23:22:26 +0100 | [diff] [blame] | 14 | #include <linux/serial_core.h> |
Tushar Behera | 334a1c7 | 2014-02-14 10:32:45 +0900 | [diff] [blame] | 15 | #include <linux/serial_s3c.h> |
Tomasz Figa | 1c161fd | 2013-04-12 21:17:22 +0200 | [diff] [blame] | 16 | #include <clocksource/samsung_pwm.h> |
Russell King | d052d1b | 2005-10-29 19:07:23 +0100 | [diff] [blame] | 17 | #include <linux/platform_device.h> |
Ben Dooks | 3c7d9c8 | 2008-04-16 00:15:20 +0100 | [diff] [blame] | 18 | #include <linux/delay.h> |
Russell King | fced80c | 2008-09-06 12:10:45 +0100 | [diff] [blame] | 19 | #include <linux/io.h> |
Krzysztof Kozlowski | b84e23f | 2020-08-06 20:20:23 +0200 | [diff] [blame] | 20 | #include <linux/platform_data/clk-s3c2410.h> |
Heiko Stuebner | f2dda07 | 2013-10-08 06:42:10 +0900 | [diff] [blame] | 21 | #include <linux/platform_data/dma-s3c24xx.h> |
Sam Van Den Berge | 34681d8 | 2016-09-22 20:51:15 +0200 | [diff] [blame] | 22 | #include <linux/dmaengine.h> |
Krzysztof Kozlowski | 16b17fc | 2020-08-04 21:26:43 +0200 | [diff] [blame] | 23 | #include <linux/clk/samsung.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 24 | |
Arnd Bergmann | c6ff132 | 2019-09-02 18:37:30 +0200 | [diff] [blame] | 25 | #include "hardware-s3c24xx.h" |
| 26 | #include "map.h" |
| 27 | #include "regs-clock.h" |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 28 | #include <asm/irq.h> |
Ben Dooks | 3c7d9c8 | 2008-04-16 00:15:20 +0100 | [diff] [blame] | 29 | #include <asm/cacheflush.h> |
David Howells | 9f97da7 | 2012-03-28 18:30:01 +0100 | [diff] [blame] | 30 | #include <asm/system_info.h> |
Olof Johansson | 86dfe44 | 2012-03-29 23:22:44 -0700 | [diff] [blame] | 31 | #include <asm/system_misc.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 32 | |
| 33 | #include <asm/mach/arch.h> |
| 34 | #include <asm/mach/map.h> |
| 35 | |
Arnd Bergmann | c6ff132 | 2019-09-02 18:37:30 +0200 | [diff] [blame] | 36 | #include "regs-gpio.h" |
| 37 | #include "dma-s3c24xx.h" |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 38 | |
Arnd Bergmann | c6ff132 | 2019-09-02 18:37:30 +0200 | [diff] [blame] | 39 | #include "cpu.h" |
| 40 | #include "devs.h" |
| 41 | #include "pwm-core.h" |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 42 | |
Arnd Bergmann | 71b9114 | 2019-09-02 17:47:55 +0200 | [diff] [blame] | 43 | #include "s3c24xx.h" |
Heiko Stuebner | e1a621d | 2013-02-08 10:31:28 -0800 | [diff] [blame] | 44 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 45 | /* table of supported CPUs */ |
| 46 | |
| 47 | static const char name_s3c2410[] = "S3C2410"; |
Ben Dooks | 68d9ab3 | 2006-06-24 21:21:27 +0100 | [diff] [blame] | 48 | static const char name_s3c2412[] = "S3C2412"; |
Ben Dooks | 63b1f51 | 2010-04-30 16:32:26 +0900 | [diff] [blame] | 49 | static const char name_s3c2416[] = "S3C2416/S3C2450"; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 50 | static const char name_s3c2440[] = "S3C2440"; |
Ben Dooks | 96ce238 | 2006-06-18 23:06:41 +0100 | [diff] [blame] | 51 | static const char name_s3c2442[] = "S3C2442"; |
Harald Welte | f5fb9b1 | 2009-09-22 21:40:39 +0100 | [diff] [blame] | 52 | static const char name_s3c2442b[] = "S3C2442B"; |
Ben Dooks | e4d06e3 | 2007-02-16 12:12:31 +0100 | [diff] [blame] | 53 | static const char name_s3c2443[] = "S3C2443"; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 54 | static const char name_s3c2410a[] = "S3C2410A"; |
| 55 | static const char name_s3c2440a[] = "S3C2440A"; |
| 56 | |
| 57 | static struct cpu_table cpu_ids[] __initdata = { |
| 58 | { |
| 59 | .idcode = 0x32410000, |
| 60 | .idmask = 0xffffffff, |
| 61 | .map_io = s3c2410_map_io, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 62 | .init_uarts = s3c2410_init_uarts, |
| 63 | .init = s3c2410_init, |
| 64 | .name = name_s3c2410 |
| 65 | }, |
| 66 | { |
| 67 | .idcode = 0x32410002, |
| 68 | .idmask = 0xffffffff, |
| 69 | .map_io = s3c2410_map_io, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 70 | .init_uarts = s3c2410_init_uarts, |
Ben Dooks | f017679 | 2009-07-30 23:23:38 +0100 | [diff] [blame] | 71 | .init = s3c2410a_init, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 72 | .name = name_s3c2410a |
| 73 | }, |
| 74 | { |
| 75 | .idcode = 0x32440000, |
| 76 | .idmask = 0xffffffff, |
Vasily Khoruzhick | 812c4e4 | 2010-12-01 08:29:23 +0200 | [diff] [blame] | 77 | .map_io = s3c2440_map_io, |
Ben Dooks | 96ce238 | 2006-06-18 23:06:41 +0100 | [diff] [blame] | 78 | .init_uarts = s3c244x_init_uarts, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 79 | .init = s3c2440_init, |
| 80 | .name = name_s3c2440 |
| 81 | }, |
| 82 | { |
| 83 | .idcode = 0x32440001, |
| 84 | .idmask = 0xffffffff, |
Vasily Khoruzhick | 812c4e4 | 2010-12-01 08:29:23 +0200 | [diff] [blame] | 85 | .map_io = s3c2440_map_io, |
Ben Dooks | 96ce238 | 2006-06-18 23:06:41 +0100 | [diff] [blame] | 86 | .init_uarts = s3c244x_init_uarts, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 87 | .init = s3c2440_init, |
| 88 | .name = name_s3c2440a |
Lucas Correia Villa Real | 83f755f | 2006-02-01 21:24:24 +0000 | [diff] [blame] | 89 | }, |
| 90 | { |
Ben Dooks | 96ce238 | 2006-06-18 23:06:41 +0100 | [diff] [blame] | 91 | .idcode = 0x32440aaa, |
| 92 | .idmask = 0xffffffff, |
Vasily Khoruzhick | 812c4e4 | 2010-12-01 08:29:23 +0200 | [diff] [blame] | 93 | .map_io = s3c2442_map_io, |
Ben Dooks | 96ce238 | 2006-06-18 23:06:41 +0100 | [diff] [blame] | 94 | .init_uarts = s3c244x_init_uarts, |
| 95 | .init = s3c2442_init, |
| 96 | .name = name_s3c2442 |
| 97 | }, |
| 98 | { |
Harald Welte | f5fb9b1 | 2009-09-22 21:40:39 +0100 | [diff] [blame] | 99 | .idcode = 0x32440aab, |
| 100 | .idmask = 0xffffffff, |
Vasily Khoruzhick | 812c4e4 | 2010-12-01 08:29:23 +0200 | [diff] [blame] | 101 | .map_io = s3c2442_map_io, |
Harald Welte | f5fb9b1 | 2009-09-22 21:40:39 +0100 | [diff] [blame] | 102 | .init_uarts = s3c244x_init_uarts, |
| 103 | .init = s3c2442_init, |
| 104 | .name = name_s3c2442b |
| 105 | }, |
| 106 | { |
Ben Dooks | 68d9ab3 | 2006-06-24 21:21:27 +0100 | [diff] [blame] | 107 | .idcode = 0x32412001, |
| 108 | .idmask = 0xffffffff, |
| 109 | .map_io = s3c2412_map_io, |
Ben Dooks | 68d9ab3 | 2006-06-24 21:21:27 +0100 | [diff] [blame] | 110 | .init_uarts = s3c2412_init_uarts, |
| 111 | .init = s3c2412_init, |
| 112 | .name = name_s3c2412, |
| 113 | }, |
Ben Dooks | d9bc55f | 2006-09-20 20:39:15 +0100 | [diff] [blame] | 114 | { /* a newer version of the s3c2412 */ |
| 115 | .idcode = 0x32412003, |
| 116 | .idmask = 0xffffffff, |
| 117 | .map_io = s3c2412_map_io, |
Ben Dooks | d9bc55f | 2006-09-20 20:39:15 +0100 | [diff] [blame] | 118 | .init_uarts = s3c2412_init_uarts, |
| 119 | .init = s3c2412_init, |
| 120 | .name = name_s3c2412, |
| 121 | }, |
Yauhen Kharuzhy | f1290a4 | 2010-04-28 18:09:01 +0900 | [diff] [blame] | 122 | { /* a strange version of the s3c2416 */ |
| 123 | .idcode = 0x32450003, |
| 124 | .idmask = 0xffffffff, |
| 125 | .map_io = s3c2416_map_io, |
Yauhen Kharuzhy | f1290a4 | 2010-04-28 18:09:01 +0900 | [diff] [blame] | 126 | .init_uarts = s3c2416_init_uarts, |
| 127 | .init = s3c2416_init, |
| 128 | .name = name_s3c2416, |
| 129 | }, |
Ben Dooks | 68d9ab3 | 2006-06-24 21:21:27 +0100 | [diff] [blame] | 130 | { |
Ben Dooks | e4d06e3 | 2007-02-16 12:12:31 +0100 | [diff] [blame] | 131 | .idcode = 0x32443001, |
| 132 | .idmask = 0xffffffff, |
| 133 | .map_io = s3c2443_map_io, |
Ben Dooks | e4d06e3 | 2007-02-16 12:12:31 +0100 | [diff] [blame] | 134 | .init_uarts = s3c2443_init_uarts, |
| 135 | .init = s3c2443_init, |
| 136 | .name = name_s3c2443, |
| 137 | }, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 138 | }; |
| 139 | |
| 140 | /* minimal IO mapping */ |
| 141 | |
Krzysztof Kozlowski | a066318 | 2020-09-10 17:41:50 +0200 | [diff] [blame] | 142 | static struct map_desc s3c_iodesc[] __initdata __maybe_unused = { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 143 | IODESC_ENT(GPIO), |
| 144 | IODESC_ENT(IRQ), |
| 145 | IODESC_ENT(MEMCTRL), |
| 146 | IODESC_ENT(UART) |
| 147 | }; |
| 148 | |
Ben Dooks | 74b265d | 2008-10-21 14:06:31 +0100 | [diff] [blame] | 149 | /* read cpu identificaiton code */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 150 | |
Ben Dooks | 68d9ab3 | 2006-06-24 21:21:27 +0100 | [diff] [blame] | 151 | static unsigned long s3c24xx_read_idcode_v5(void) |
| 152 | { |
Ben Dooks | d11a7d7 | 2010-04-28 18:00:07 +0900 | [diff] [blame] | 153 | #if defined(CONFIG_CPU_S3C2416) |
| 154 | /* s3c2416 is v5, with S3C24XX_GSTATUS1 instead of S3C2412_GSTATUS1 */ |
| 155 | |
| 156 | u32 gs = __raw_readl(S3C24XX_GSTATUS1); |
| 157 | |
| 158 | /* test for s3c2416 or similar device */ |
| 159 | if ((gs >> 16) == 0x3245) |
| 160 | return gs; |
| 161 | #endif |
| 162 | |
Krzysztof Kozlowski | f0f2f59 | 2017-07-17 07:48:07 +0200 | [diff] [blame] | 163 | #if defined(CONFIG_CPU_S3C2412) |
Ben Dooks | 68d9ab3 | 2006-06-24 21:21:27 +0100 | [diff] [blame] | 164 | return __raw_readl(S3C2412_GSTATUS1); |
| 165 | #else |
| 166 | return 1UL; /* don't look like an 2400 */ |
| 167 | #endif |
| 168 | } |
| 169 | |
| 170 | static unsigned long s3c24xx_read_idcode_v4(void) |
| 171 | { |
Ben Dooks | 68d9ab3 | 2006-06-24 21:21:27 +0100 | [diff] [blame] | 172 | return __raw_readl(S3C2410_GSTATUS1); |
Ben Dooks | 68d9ab3 | 2006-06-24 21:21:27 +0100 | [diff] [blame] | 173 | } |
| 174 | |
Nicolas Pitre | 9231127 | 2011-08-03 11:34:59 -0400 | [diff] [blame] | 175 | static void s3c24xx_default_idle(void) |
| 176 | { |
Cong Ding | 813f13e | 2013-01-18 08:58:23 -0800 | [diff] [blame] | 177 | unsigned long tmp = 0; |
Nicolas Pitre | 9231127 | 2011-08-03 11:34:59 -0400 | [diff] [blame] | 178 | int i; |
| 179 | |
| 180 | /* idle the system by using the idle mode which will wait for an |
| 181 | * interrupt to happen before restarting the system. |
| 182 | */ |
| 183 | |
| 184 | /* Warning: going into idle state upsets jtag scanning */ |
| 185 | |
| 186 | __raw_writel(__raw_readl(S3C2410_CLKCON) | S3C2410_CLKCON_IDLE, |
| 187 | S3C2410_CLKCON); |
| 188 | |
| 189 | /* the samsung port seems to do a loop and then unset idle.. */ |
| 190 | for (i = 0; i < 50; i++) |
| 191 | tmp += __raw_readl(S3C2410_CLKCON); /* ensure loop not optimised out */ |
| 192 | |
| 193 | /* this bit is not cleared on re-start... */ |
| 194 | |
| 195 | __raw_writel(__raw_readl(S3C2410_CLKCON) & ~S3C2410_CLKCON_IDLE, |
| 196 | S3C2410_CLKCON); |
| 197 | } |
| 198 | |
Tomasz Figa | 1c161fd | 2013-04-12 21:17:22 +0200 | [diff] [blame] | 199 | static struct samsung_pwm_variant s3c24xx_pwm_variant = { |
| 200 | .bits = 16, |
| 201 | .div_base = 1, |
| 202 | .has_tint_cstat = false, |
| 203 | .tclk_mask = (1 << 4), |
| 204 | }; |
| 205 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 206 | void __init s3c24xx_init_io(struct map_desc *mach_desc, int size) |
| 207 | { |
Nicolas Pitre | 9231127 | 2011-08-03 11:34:59 -0400 | [diff] [blame] | 208 | arm_pm_idle = s3c24xx_default_idle; |
| 209 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 210 | /* initialise the io descriptors we need for initialisation */ |
Ben Dooks | 74b265d | 2008-10-21 14:06:31 +0100 | [diff] [blame] | 211 | iotable_init(mach_desc, size); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 212 | iotable_init(s3c_iodesc, ARRAY_SIZE(s3c_iodesc)); |
| 213 | |
Ben Dooks | 68d9ab3 | 2006-06-24 21:21:27 +0100 | [diff] [blame] | 214 | if (cpu_architecture() >= CPU_ARCH_ARMv5) { |
Kukjin Kim | c06af3c | 2011-08-20 02:18:18 +0900 | [diff] [blame] | 215 | samsung_cpu_id = s3c24xx_read_idcode_v5(); |
Ben Dooks | 68d9ab3 | 2006-06-24 21:21:27 +0100 | [diff] [blame] | 216 | } else { |
Kukjin Kim | c06af3c | 2011-08-20 02:18:18 +0900 | [diff] [blame] | 217 | samsung_cpu_id = s3c24xx_read_idcode_v4(); |
Ben Dooks | 68d9ab3 | 2006-06-24 21:21:27 +0100 | [diff] [blame] | 218 | } |
Lucas Correia Villa Real | 83f755f | 2006-02-01 21:24:24 +0000 | [diff] [blame] | 219 | |
Kukjin Kim | c06af3c | 2011-08-20 02:18:18 +0900 | [diff] [blame] | 220 | s3c_init_cpu(samsung_cpu_id, cpu_ids, ARRAY_SIZE(cpu_ids)); |
Tomasz Figa | 1c161fd | 2013-04-12 21:17:22 +0200 | [diff] [blame] | 221 | |
| 222 | samsung_pwm_set_platdata(&s3c24xx_pwm_variant); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 223 | } |
Heiko Stuebner | 618ae08 | 2012-05-12 16:22:17 +0900 | [diff] [blame] | 224 | |
Krzysztof Kozlowski | a1342f6 | 2020-08-20 22:42:03 +0200 | [diff] [blame] | 225 | void __init s3c24xx_set_timer_source(unsigned int event, unsigned int source) |
Tomasz Figa | 4280506 | 2013-04-28 02:25:01 +0200 | [diff] [blame] | 226 | { |
| 227 | s3c24xx_pwm_variant.output_mask = BIT(SAMSUNG_PWM_NUM) - 1; |
| 228 | s3c24xx_pwm_variant.output_mask &= ~(BIT(event) | BIT(source)); |
| 229 | } |
| 230 | |
Krzysztof Kozlowski | a1342f6 | 2020-08-20 22:42:03 +0200 | [diff] [blame] | 231 | void __init s3c24xx_timer_init(void) |
Tomasz Figa | 4280506 | 2013-04-28 02:25:01 +0200 | [diff] [blame] | 232 | { |
| 233 | unsigned int timer_irqs[SAMSUNG_PWM_NUM] = { |
| 234 | IRQ_TIMER0, IRQ_TIMER1, IRQ_TIMER2, IRQ_TIMER3, IRQ_TIMER4, |
| 235 | }; |
| 236 | |
| 237 | samsung_pwm_clocksource_init(S3C_VA_TIMER, |
| 238 | timer_irqs, &s3c24xx_pwm_variant); |
| 239 | } |
| 240 | |
Heiko Stuebner | 618ae08 | 2012-05-12 16:22:17 +0900 | [diff] [blame] | 241 | /* Serial port registrations */ |
| 242 | |
Arnd Bergmann | 9ee51f0 | 2013-04-11 02:04:48 +0200 | [diff] [blame] | 243 | #define S3C2410_PA_UART0 (S3C24XX_PA_UART) |
| 244 | #define S3C2410_PA_UART1 (S3C24XX_PA_UART + 0x4000 ) |
| 245 | #define S3C2410_PA_UART2 (S3C24XX_PA_UART + 0x8000 ) |
| 246 | #define S3C2443_PA_UART3 (S3C24XX_PA_UART + 0xC000 ) |
| 247 | |
Heiko Stuebner | 618ae08 | 2012-05-12 16:22:17 +0900 | [diff] [blame] | 248 | static struct resource s3c2410_uart0_resource[] = { |
Tushar Behera | 99dbdd9 | 2012-05-12 16:24:59 +0900 | [diff] [blame] | 249 | [0] = DEFINE_RES_MEM(S3C2410_PA_UART0, SZ_16K), |
| 250 | [1] = DEFINE_RES_NAMED(IRQ_S3CUART_RX0, \ |
| 251 | IRQ_S3CUART_ERR0 - IRQ_S3CUART_RX0 + 1, \ |
| 252 | NULL, IORESOURCE_IRQ) |
Heiko Stuebner | 618ae08 | 2012-05-12 16:22:17 +0900 | [diff] [blame] | 253 | }; |
| 254 | |
| 255 | static struct resource s3c2410_uart1_resource[] = { |
Tushar Behera | 99dbdd9 | 2012-05-12 16:24:59 +0900 | [diff] [blame] | 256 | [0] = DEFINE_RES_MEM(S3C2410_PA_UART1, SZ_16K), |
| 257 | [1] = DEFINE_RES_NAMED(IRQ_S3CUART_RX1, \ |
| 258 | IRQ_S3CUART_ERR1 - IRQ_S3CUART_RX1 + 1, \ |
| 259 | NULL, IORESOURCE_IRQ) |
Heiko Stuebner | 618ae08 | 2012-05-12 16:22:17 +0900 | [diff] [blame] | 260 | }; |
| 261 | |
| 262 | static struct resource s3c2410_uart2_resource[] = { |
Tushar Behera | 99dbdd9 | 2012-05-12 16:24:59 +0900 | [diff] [blame] | 263 | [0] = DEFINE_RES_MEM(S3C2410_PA_UART2, SZ_16K), |
| 264 | [1] = DEFINE_RES_NAMED(IRQ_S3CUART_RX2, \ |
| 265 | IRQ_S3CUART_ERR2 - IRQ_S3CUART_RX2 + 1, \ |
| 266 | NULL, IORESOURCE_IRQ) |
Heiko Stuebner | 618ae08 | 2012-05-12 16:22:17 +0900 | [diff] [blame] | 267 | }; |
| 268 | |
| 269 | static struct resource s3c2410_uart3_resource[] = { |
Tushar Behera | 99dbdd9 | 2012-05-12 16:24:59 +0900 | [diff] [blame] | 270 | [0] = DEFINE_RES_MEM(S3C2443_PA_UART3, SZ_16K), |
| 271 | [1] = DEFINE_RES_NAMED(IRQ_S3CUART_RX3, \ |
| 272 | IRQ_S3CUART_ERR3 - IRQ_S3CUART_RX3 + 1, \ |
| 273 | NULL, IORESOURCE_IRQ) |
Heiko Stuebner | 618ae08 | 2012-05-12 16:22:17 +0900 | [diff] [blame] | 274 | }; |
| 275 | |
| 276 | struct s3c24xx_uart_resources s3c2410_uart_resources[] __initdata = { |
| 277 | [0] = { |
| 278 | .resources = s3c2410_uart0_resource, |
| 279 | .nr_resources = ARRAY_SIZE(s3c2410_uart0_resource), |
| 280 | }, |
| 281 | [1] = { |
| 282 | .resources = s3c2410_uart1_resource, |
| 283 | .nr_resources = ARRAY_SIZE(s3c2410_uart1_resource), |
| 284 | }, |
| 285 | [2] = { |
| 286 | .resources = s3c2410_uart2_resource, |
| 287 | .nr_resources = ARRAY_SIZE(s3c2410_uart2_resource), |
| 288 | }, |
| 289 | [3] = { |
| 290 | .resources = s3c2410_uart3_resource, |
| 291 | .nr_resources = ARRAY_SIZE(s3c2410_uart3_resource), |
| 292 | }, |
| 293 | }; |
Heiko Stuebner | 2473f71 | 2012-05-12 16:22:18 +0900 | [diff] [blame] | 294 | |
Sylwester Nawrocki | 971466b | 2016-08-04 11:56:12 +0200 | [diff] [blame] | 295 | #define s3c24xx_device_dma_mask (*((u64[]) { DMA_BIT_MASK(32) })) |
| 296 | |
Heiko Stuebner | f2dda07 | 2013-10-08 06:42:10 +0900 | [diff] [blame] | 297 | #if defined(CONFIG_CPU_S3C2410) || defined(CONFIG_CPU_S3C2412) || \ |
| 298 | defined(CONFIG_CPU_S3C2440) || defined(CONFIG_CPU_S3C2442) |
| 299 | static struct resource s3c2410_dma_resource[] = { |
| 300 | [0] = DEFINE_RES_MEM(S3C24XX_PA_DMA, S3C24XX_SZ_DMA), |
| 301 | [1] = DEFINE_RES_IRQ(IRQ_DMA0), |
| 302 | [2] = DEFINE_RES_IRQ(IRQ_DMA1), |
| 303 | [3] = DEFINE_RES_IRQ(IRQ_DMA2), |
| 304 | [4] = DEFINE_RES_IRQ(IRQ_DMA3), |
| 305 | }; |
| 306 | #endif |
| 307 | |
Heiko Stuebner | 1fecf89 | 2013-10-21 05:32:48 +0900 | [diff] [blame] | 308 | #if defined(CONFIG_CPU_S3C2410) || defined(CONFIG_CPU_S3C2442) |
| 309 | static struct s3c24xx_dma_channel s3c2410_dma_channels[DMACH_MAX] = { |
| 310 | [DMACH_XD0] = { S3C24XX_DMA_AHB, true, S3C24XX_DMA_CHANREQ(0, 0), }, |
| 311 | [DMACH_XD1] = { S3C24XX_DMA_AHB, true, S3C24XX_DMA_CHANREQ(0, 1), }, |
| 312 | [DMACH_SDI] = { S3C24XX_DMA_APB, false, S3C24XX_DMA_CHANREQ(2, 0) | |
| 313 | S3C24XX_DMA_CHANREQ(2, 2) | |
| 314 | S3C24XX_DMA_CHANREQ(1, 3), |
| 315 | }, |
| 316 | [DMACH_SPI0] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(3, 1), }, |
| 317 | [DMACH_SPI1] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(2, 3), }, |
| 318 | [DMACH_UART0] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(1, 0), }, |
| 319 | [DMACH_UART1] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(1, 1), }, |
| 320 | [DMACH_UART2] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(0, 3), }, |
| 321 | [DMACH_TIMER] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(3, 0) | |
| 322 | S3C24XX_DMA_CHANREQ(3, 2) | |
| 323 | S3C24XX_DMA_CHANREQ(3, 3), |
| 324 | }, |
| 325 | [DMACH_I2S_IN] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(2, 1) | |
| 326 | S3C24XX_DMA_CHANREQ(1, 2), |
| 327 | }, |
| 328 | [DMACH_I2S_OUT] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(0, 2), }, |
| 329 | [DMACH_USB_EP1] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(4, 0), }, |
| 330 | [DMACH_USB_EP2] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(4, 1), }, |
| 331 | [DMACH_USB_EP3] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(4, 2), }, |
| 332 | [DMACH_USB_EP4] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(4, 3), }, |
| 333 | }; |
| 334 | |
Sylwester Nawrocki | 9d56d6c | 2016-11-04 10:45:53 +0100 | [diff] [blame] | 335 | static const struct dma_slave_map s3c2410_dma_slave_map[] = { |
| 336 | { "s3c2410-sdi", "rx-tx", (void *)DMACH_SDI }, |
| 337 | { "s3c2410-spi.0", "rx", (void *)DMACH_SPI0_RX }, |
| 338 | { "s3c2410-spi.0", "tx", (void *)DMACH_SPI0_TX }, |
| 339 | { "s3c2410-spi.1", "rx", (void *)DMACH_SPI1_RX }, |
| 340 | { "s3c2410-spi.1", "tx", (void *)DMACH_SPI1_TX }, |
| 341 | /* |
| 342 | * The DMA request source[1] (DMACH_UARTx_SRC2) are |
| 343 | * not used in the UART driver. |
| 344 | */ |
| 345 | { "s3c2410-uart.0", "rx", (void *)DMACH_UART0 }, |
| 346 | { "s3c2410-uart.0", "tx", (void *)DMACH_UART0 }, |
| 347 | { "s3c2410-uart.1", "rx", (void *)DMACH_UART1 }, |
| 348 | { "s3c2410-uart.1", "tx", (void *)DMACH_UART1 }, |
| 349 | { "s3c2410-uart.2", "rx", (void *)DMACH_UART2 }, |
| 350 | { "s3c2410-uart.2", "tx", (void *)DMACH_UART2 }, |
| 351 | { "s3c24xx-iis", "rx", (void *)DMACH_I2S_IN }, |
| 352 | { "s3c24xx-iis", "tx", (void *)DMACH_I2S_OUT }, |
| 353 | { "s3c-hsudc", "rx0", (void *)DMACH_USB_EP1 }, |
| 354 | { "s3c-hsudc", "tx0", (void *)DMACH_USB_EP1 }, |
| 355 | { "s3c-hsudc", "rx1", (void *)DMACH_USB_EP2 }, |
| 356 | { "s3c-hsudc", "tx1", (void *)DMACH_USB_EP2 }, |
| 357 | { "s3c-hsudc", "rx2", (void *)DMACH_USB_EP3 }, |
| 358 | { "s3c-hsudc", "tx2", (void *)DMACH_USB_EP3 }, |
| 359 | { "s3c-hsudc", "rx3", (void *)DMACH_USB_EP4 }, |
| 360 | { "s3c-hsudc", "tx3", (void *)DMACH_USB_EP4 } |
| 361 | }; |
| 362 | |
Heiko Stuebner | 1fecf89 | 2013-10-21 05:32:48 +0900 | [diff] [blame] | 363 | static struct s3c24xx_dma_platdata s3c2410_dma_platdata = { |
| 364 | .num_phy_channels = 4, |
| 365 | .channels = s3c2410_dma_channels, |
| 366 | .num_channels = DMACH_MAX, |
Sylwester Nawrocki | 9d56d6c | 2016-11-04 10:45:53 +0100 | [diff] [blame] | 367 | .slave_map = s3c2410_dma_slave_map, |
| 368 | .slavecnt = ARRAY_SIZE(s3c2410_dma_slave_map), |
Heiko Stuebner | 1fecf89 | 2013-10-21 05:32:48 +0900 | [diff] [blame] | 369 | }; |
| 370 | |
| 371 | struct platform_device s3c2410_device_dma = { |
| 372 | .name = "s3c2410-dma", |
| 373 | .id = 0, |
| 374 | .num_resources = ARRAY_SIZE(s3c2410_dma_resource), |
| 375 | .resource = s3c2410_dma_resource, |
| 376 | .dev = { |
Sylwester Nawrocki | 971466b | 2016-08-04 11:56:12 +0200 | [diff] [blame] | 377 | .dma_mask = &s3c24xx_device_dma_mask, |
| 378 | .coherent_dma_mask = DMA_BIT_MASK(32), |
| 379 | .platform_data = &s3c2410_dma_platdata, |
Heiko Stuebner | 1fecf89 | 2013-10-21 05:32:48 +0900 | [diff] [blame] | 380 | }, |
| 381 | }; |
| 382 | #endif |
| 383 | |
Heiko Stuebner | f2dda07 | 2013-10-08 06:42:10 +0900 | [diff] [blame] | 384 | #ifdef CONFIG_CPU_S3C2412 |
| 385 | static struct s3c24xx_dma_channel s3c2412_dma_channels[DMACH_MAX] = { |
| 386 | [DMACH_XD0] = { S3C24XX_DMA_AHB, true, 17 }, |
| 387 | [DMACH_XD1] = { S3C24XX_DMA_AHB, true, 18 }, |
| 388 | [DMACH_SDI] = { S3C24XX_DMA_APB, false, 10 }, |
| 389 | [DMACH_SPI0_RX] = { S3C24XX_DMA_APB, true, 1 }, |
| 390 | [DMACH_SPI0_TX] = { S3C24XX_DMA_APB, true, 0 }, |
| 391 | [DMACH_SPI1_RX] = { S3C24XX_DMA_APB, true, 3 }, |
| 392 | [DMACH_SPI1_TX] = { S3C24XX_DMA_APB, true, 2 }, |
| 393 | [DMACH_UART0] = { S3C24XX_DMA_APB, true, 19 }, |
| 394 | [DMACH_UART1] = { S3C24XX_DMA_APB, true, 21 }, |
| 395 | [DMACH_UART2] = { S3C24XX_DMA_APB, true, 23 }, |
| 396 | [DMACH_UART0_SRC2] = { S3C24XX_DMA_APB, true, 20 }, |
| 397 | [DMACH_UART1_SRC2] = { S3C24XX_DMA_APB, true, 22 }, |
| 398 | [DMACH_UART2_SRC2] = { S3C24XX_DMA_APB, true, 24 }, |
| 399 | [DMACH_TIMER] = { S3C24XX_DMA_APB, true, 9 }, |
| 400 | [DMACH_I2S_IN] = { S3C24XX_DMA_APB, true, 5 }, |
| 401 | [DMACH_I2S_OUT] = { S3C24XX_DMA_APB, true, 4 }, |
| 402 | [DMACH_USB_EP1] = { S3C24XX_DMA_APB, true, 13 }, |
| 403 | [DMACH_USB_EP2] = { S3C24XX_DMA_APB, true, 14 }, |
| 404 | [DMACH_USB_EP3] = { S3C24XX_DMA_APB, true, 15 }, |
| 405 | [DMACH_USB_EP4] = { S3C24XX_DMA_APB, true, 16 }, |
| 406 | }; |
| 407 | |
Sylwester Nawrocki | 9d56d6c | 2016-11-04 10:45:53 +0100 | [diff] [blame] | 408 | static const struct dma_slave_map s3c2412_dma_slave_map[] = { |
| 409 | { "s3c2412-sdi", "rx-tx", (void *)DMACH_SDI }, |
| 410 | { "s3c2412-spi.0", "rx", (void *)DMACH_SPI0_RX }, |
| 411 | { "s3c2412-spi.0", "tx", (void *)DMACH_SPI0_TX }, |
| 412 | { "s3c2412-spi.1", "rx", (void *)DMACH_SPI1_RX }, |
| 413 | { "s3c2412-spi.1", "tx", (void *)DMACH_SPI1_TX }, |
| 414 | { "s3c2440-uart.0", "rx", (void *)DMACH_UART0 }, |
| 415 | { "s3c2440-uart.0", "tx", (void *)DMACH_UART0 }, |
| 416 | { "s3c2440-uart.1", "rx", (void *)DMACH_UART1 }, |
| 417 | { "s3c2440-uart.1", "tx", (void *)DMACH_UART1 }, |
| 418 | { "s3c2440-uart.2", "rx", (void *)DMACH_UART2 }, |
| 419 | { "s3c2440-uart.2", "tx", (void *)DMACH_UART2 }, |
| 420 | { "s3c2412-iis", "rx", (void *)DMACH_I2S_IN }, |
| 421 | { "s3c2412-iis", "tx", (void *)DMACH_I2S_OUT }, |
| 422 | { "s3c-hsudc", "rx0", (void *)DMACH_USB_EP1 }, |
| 423 | { "s3c-hsudc", "tx0", (void *)DMACH_USB_EP1 }, |
| 424 | { "s3c-hsudc", "rx1", (void *)DMACH_USB_EP2 }, |
| 425 | { "s3c-hsudc", "tx1", (void *)DMACH_USB_EP2 }, |
| 426 | { "s3c-hsudc", "rx2", (void *)DMACH_USB_EP3 }, |
| 427 | { "s3c-hsudc", "tx2", (void *)DMACH_USB_EP3 }, |
| 428 | { "s3c-hsudc", "rx3", (void *)DMACH_USB_EP4 }, |
| 429 | { "s3c-hsudc", "tx3", (void *)DMACH_USB_EP4 } |
| 430 | }; |
| 431 | |
Heiko Stuebner | f2dda07 | 2013-10-08 06:42:10 +0900 | [diff] [blame] | 432 | static struct s3c24xx_dma_platdata s3c2412_dma_platdata = { |
| 433 | .num_phy_channels = 4, |
| 434 | .channels = s3c2412_dma_channels, |
| 435 | .num_channels = DMACH_MAX, |
Sylwester Nawrocki | 9d56d6c | 2016-11-04 10:45:53 +0100 | [diff] [blame] | 436 | .slave_map = s3c2412_dma_slave_map, |
| 437 | .slavecnt = ARRAY_SIZE(s3c2412_dma_slave_map), |
Heiko Stuebner | f2dda07 | 2013-10-08 06:42:10 +0900 | [diff] [blame] | 438 | }; |
| 439 | |
| 440 | struct platform_device s3c2412_device_dma = { |
| 441 | .name = "s3c2412-dma", |
| 442 | .id = 0, |
| 443 | .num_resources = ARRAY_SIZE(s3c2410_dma_resource), |
| 444 | .resource = s3c2410_dma_resource, |
| 445 | .dev = { |
Sylwester Nawrocki | 971466b | 2016-08-04 11:56:12 +0200 | [diff] [blame] | 446 | .dma_mask = &s3c24xx_device_dma_mask, |
| 447 | .coherent_dma_mask = DMA_BIT_MASK(32), |
| 448 | .platform_data = &s3c2412_dma_platdata, |
Heiko Stuebner | f2dda07 | 2013-10-08 06:42:10 +0900 | [diff] [blame] | 449 | }, |
| 450 | }; |
| 451 | #endif |
| 452 | |
Heiko Stuebner | 1fecf89 | 2013-10-21 05:32:48 +0900 | [diff] [blame] | 453 | #if defined(CONFIG_CPU_S3C2440) |
| 454 | static struct s3c24xx_dma_channel s3c2440_dma_channels[DMACH_MAX] = { |
| 455 | [DMACH_XD0] = { S3C24XX_DMA_AHB, true, S3C24XX_DMA_CHANREQ(0, 0), }, |
| 456 | [DMACH_XD1] = { S3C24XX_DMA_AHB, true, S3C24XX_DMA_CHANREQ(0, 1), }, |
| 457 | [DMACH_SDI] = { S3C24XX_DMA_APB, false, S3C24XX_DMA_CHANREQ(2, 0) | |
| 458 | S3C24XX_DMA_CHANREQ(6, 1) | |
| 459 | S3C24XX_DMA_CHANREQ(2, 2) | |
| 460 | S3C24XX_DMA_CHANREQ(1, 3), |
| 461 | }, |
| 462 | [DMACH_SPI0] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(3, 1), }, |
| 463 | [DMACH_SPI1] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(2, 3), }, |
| 464 | [DMACH_UART0] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(1, 0), }, |
| 465 | [DMACH_UART1] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(1, 1), }, |
| 466 | [DMACH_UART2] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(0, 3), }, |
| 467 | [DMACH_TIMER] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(3, 0) | |
| 468 | S3C24XX_DMA_CHANREQ(3, 2) | |
| 469 | S3C24XX_DMA_CHANREQ(3, 3), |
| 470 | }, |
| 471 | [DMACH_I2S_IN] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(2, 1) | |
| 472 | S3C24XX_DMA_CHANREQ(1, 2), |
| 473 | }, |
| 474 | [DMACH_I2S_OUT] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(5, 0) | |
| 475 | S3C24XX_DMA_CHANREQ(0, 2), |
| 476 | }, |
| 477 | [DMACH_PCM_IN] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(6, 0) | |
| 478 | S3C24XX_DMA_CHANREQ(5, 2), |
| 479 | }, |
| 480 | [DMACH_PCM_OUT] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(5, 1) | |
| 481 | S3C24XX_DMA_CHANREQ(6, 3), |
| 482 | }, |
| 483 | [DMACH_MIC_IN] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(6, 2) | |
| 484 | S3C24XX_DMA_CHANREQ(5, 3), |
| 485 | }, |
| 486 | [DMACH_USB_EP1] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(4, 0), }, |
| 487 | [DMACH_USB_EP2] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(4, 1), }, |
| 488 | [DMACH_USB_EP3] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(4, 2), }, |
| 489 | [DMACH_USB_EP4] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(4, 3), }, |
| 490 | }; |
| 491 | |
Sam Van Den Berge | 34681d8 | 2016-09-22 20:51:15 +0200 | [diff] [blame] | 492 | static const struct dma_slave_map s3c2440_dma_slave_map[] = { |
| 493 | /* TODO: DMACH_XD0 */ |
| 494 | /* TODO: DMACH_XD1 */ |
| 495 | { "s3c2440-sdi", "rx-tx", (void *)DMACH_SDI }, |
| 496 | { "s3c2410-spi.0", "rx", (void *)DMACH_SPI0 }, |
| 497 | { "s3c2410-spi.0", "tx", (void *)DMACH_SPI0 }, |
| 498 | { "s3c2410-spi.1", "rx", (void *)DMACH_SPI1 }, |
| 499 | { "s3c2410-spi.1", "tx", (void *)DMACH_SPI1 }, |
| 500 | { "s3c2440-uart.0", "rx", (void *)DMACH_UART0 }, |
| 501 | { "s3c2440-uart.0", "tx", (void *)DMACH_UART0 }, |
| 502 | { "s3c2440-uart.1", "rx", (void *)DMACH_UART1 }, |
| 503 | { "s3c2440-uart.1", "tx", (void *)DMACH_UART1 }, |
| 504 | { "s3c2440-uart.2", "rx", (void *)DMACH_UART2 }, |
| 505 | { "s3c2440-uart.2", "tx", (void *)DMACH_UART2 }, |
| 506 | { "s3c2440-uart.3", "rx", (void *)DMACH_UART3 }, |
| 507 | { "s3c2440-uart.3", "tx", (void *)DMACH_UART3 }, |
| 508 | /* TODO: DMACH_TIMER */ |
| 509 | { "s3c24xx-iis", "rx", (void *)DMACH_I2S_IN }, |
| 510 | { "s3c24xx-iis", "tx", (void *)DMACH_I2S_OUT }, |
| 511 | { "samsung-ac97", "rx", (void *)DMACH_PCM_IN }, |
| 512 | { "samsung-ac97", "tx", (void *)DMACH_PCM_OUT }, |
| 513 | { "samsung-ac97", "rx", (void *)DMACH_MIC_IN }, |
| 514 | { "s3c-hsudc", "rx0", (void *)DMACH_USB_EP1 }, |
| 515 | { "s3c-hsudc", "rx1", (void *)DMACH_USB_EP2 }, |
| 516 | { "s3c-hsudc", "rx2", (void *)DMACH_USB_EP3 }, |
| 517 | { "s3c-hsudc", "rx3", (void *)DMACH_USB_EP4 }, |
| 518 | { "s3c-hsudc", "tx0", (void *)DMACH_USB_EP1 }, |
| 519 | { "s3c-hsudc", "tx1", (void *)DMACH_USB_EP2 }, |
| 520 | { "s3c-hsudc", "tx2", (void *)DMACH_USB_EP3 }, |
| 521 | { "s3c-hsudc", "tx3", (void *)DMACH_USB_EP4 } |
| 522 | }; |
| 523 | |
Heiko Stuebner | 1fecf89 | 2013-10-21 05:32:48 +0900 | [diff] [blame] | 524 | static struct s3c24xx_dma_platdata s3c2440_dma_platdata = { |
| 525 | .num_phy_channels = 4, |
| 526 | .channels = s3c2440_dma_channels, |
| 527 | .num_channels = DMACH_MAX, |
Sam Van Den Berge | 34681d8 | 2016-09-22 20:51:15 +0200 | [diff] [blame] | 528 | .slave_map = s3c2440_dma_slave_map, |
| 529 | .slavecnt = ARRAY_SIZE(s3c2440_dma_slave_map), |
Heiko Stuebner | 1fecf89 | 2013-10-21 05:32:48 +0900 | [diff] [blame] | 530 | }; |
| 531 | |
| 532 | struct platform_device s3c2440_device_dma = { |
| 533 | .name = "s3c2410-dma", |
| 534 | .id = 0, |
| 535 | .num_resources = ARRAY_SIZE(s3c2410_dma_resource), |
| 536 | .resource = s3c2410_dma_resource, |
| 537 | .dev = { |
Sylwester Nawrocki | 971466b | 2016-08-04 11:56:12 +0200 | [diff] [blame] | 538 | .dma_mask = &s3c24xx_device_dma_mask, |
| 539 | .coherent_dma_mask = DMA_BIT_MASK(32), |
| 540 | .platform_data = &s3c2440_dma_platdata, |
Heiko Stuebner | 1fecf89 | 2013-10-21 05:32:48 +0900 | [diff] [blame] | 541 | }, |
| 542 | }; |
| 543 | #endif |
| 544 | |
Paul Bolle | 469641c | 2014-02-14 07:35:12 +0900 | [diff] [blame] | 545 | #if defined(CONFIG_CPU_S3C2443) || defined(CONFIG_CPU_S3C2416) |
Heiko Stuebner | f2dda07 | 2013-10-08 06:42:10 +0900 | [diff] [blame] | 546 | static struct resource s3c2443_dma_resource[] = { |
| 547 | [0] = DEFINE_RES_MEM(S3C24XX_PA_DMA, S3C24XX_SZ_DMA), |
| 548 | [1] = DEFINE_RES_IRQ(IRQ_S3C2443_DMA0), |
| 549 | [2] = DEFINE_RES_IRQ(IRQ_S3C2443_DMA1), |
| 550 | [3] = DEFINE_RES_IRQ(IRQ_S3C2443_DMA2), |
| 551 | [4] = DEFINE_RES_IRQ(IRQ_S3C2443_DMA3), |
| 552 | [5] = DEFINE_RES_IRQ(IRQ_S3C2443_DMA4), |
| 553 | [6] = DEFINE_RES_IRQ(IRQ_S3C2443_DMA5), |
| 554 | }; |
| 555 | |
| 556 | static struct s3c24xx_dma_channel s3c2443_dma_channels[DMACH_MAX] = { |
| 557 | [DMACH_XD0] = { S3C24XX_DMA_AHB, true, 17 }, |
| 558 | [DMACH_XD1] = { S3C24XX_DMA_AHB, true, 18 }, |
| 559 | [DMACH_SDI] = { S3C24XX_DMA_APB, false, 10 }, |
| 560 | [DMACH_SPI0_RX] = { S3C24XX_DMA_APB, true, 1 }, |
| 561 | [DMACH_SPI0_TX] = { S3C24XX_DMA_APB, true, 0 }, |
| 562 | [DMACH_SPI1_RX] = { S3C24XX_DMA_APB, true, 3 }, |
| 563 | [DMACH_SPI1_TX] = { S3C24XX_DMA_APB, true, 2 }, |
| 564 | [DMACH_UART0] = { S3C24XX_DMA_APB, true, 19 }, |
| 565 | [DMACH_UART1] = { S3C24XX_DMA_APB, true, 21 }, |
| 566 | [DMACH_UART2] = { S3C24XX_DMA_APB, true, 23 }, |
| 567 | [DMACH_UART3] = { S3C24XX_DMA_APB, true, 25 }, |
| 568 | [DMACH_UART0_SRC2] = { S3C24XX_DMA_APB, true, 20 }, |
| 569 | [DMACH_UART1_SRC2] = { S3C24XX_DMA_APB, true, 22 }, |
| 570 | [DMACH_UART2_SRC2] = { S3C24XX_DMA_APB, true, 24 }, |
| 571 | [DMACH_UART3_SRC2] = { S3C24XX_DMA_APB, true, 26 }, |
| 572 | [DMACH_TIMER] = { S3C24XX_DMA_APB, true, 9 }, |
| 573 | [DMACH_I2S_IN] = { S3C24XX_DMA_APB, true, 5 }, |
| 574 | [DMACH_I2S_OUT] = { S3C24XX_DMA_APB, true, 4 }, |
| 575 | [DMACH_PCM_IN] = { S3C24XX_DMA_APB, true, 28 }, |
| 576 | [DMACH_PCM_OUT] = { S3C24XX_DMA_APB, true, 27 }, |
| 577 | [DMACH_MIC_IN] = { S3C24XX_DMA_APB, true, 29 }, |
| 578 | }; |
| 579 | |
Sylwester Nawrocki | 9d56d6c | 2016-11-04 10:45:53 +0100 | [diff] [blame] | 580 | static const struct dma_slave_map s3c2443_dma_slave_map[] = { |
| 581 | { "s3c2440-sdi", "rx-tx", (void *)DMACH_SDI }, |
| 582 | { "s3c2443-spi.0", "rx", (void *)DMACH_SPI0_RX }, |
| 583 | { "s3c2443-spi.0", "tx", (void *)DMACH_SPI0_TX }, |
| 584 | { "s3c2443-spi.1", "rx", (void *)DMACH_SPI1_RX }, |
| 585 | { "s3c2443-spi.1", "tx", (void *)DMACH_SPI1_TX }, |
| 586 | { "s3c2440-uart.0", "rx", (void *)DMACH_UART0 }, |
| 587 | { "s3c2440-uart.0", "tx", (void *)DMACH_UART0 }, |
| 588 | { "s3c2440-uart.1", "rx", (void *)DMACH_UART1 }, |
| 589 | { "s3c2440-uart.1", "tx", (void *)DMACH_UART1 }, |
| 590 | { "s3c2440-uart.2", "rx", (void *)DMACH_UART2 }, |
| 591 | { "s3c2440-uart.2", "tx", (void *)DMACH_UART2 }, |
| 592 | { "s3c2440-uart.3", "rx", (void *)DMACH_UART3 }, |
| 593 | { "s3c2440-uart.3", "tx", (void *)DMACH_UART3 }, |
| 594 | { "s3c24xx-iis", "rx", (void *)DMACH_I2S_IN }, |
| 595 | { "s3c24xx-iis", "tx", (void *)DMACH_I2S_OUT }, |
| 596 | }; |
| 597 | |
Heiko Stuebner | f2dda07 | 2013-10-08 06:42:10 +0900 | [diff] [blame] | 598 | static struct s3c24xx_dma_platdata s3c2443_dma_platdata = { |
| 599 | .num_phy_channels = 6, |
| 600 | .channels = s3c2443_dma_channels, |
| 601 | .num_channels = DMACH_MAX, |
Sylwester Nawrocki | 9d56d6c | 2016-11-04 10:45:53 +0100 | [diff] [blame] | 602 | .slave_map = s3c2443_dma_slave_map, |
| 603 | .slavecnt = ARRAY_SIZE(s3c2443_dma_slave_map), |
Heiko Stuebner | f2dda07 | 2013-10-08 06:42:10 +0900 | [diff] [blame] | 604 | }; |
| 605 | |
| 606 | struct platform_device s3c2443_device_dma = { |
| 607 | .name = "s3c2443-dma", |
| 608 | .id = 0, |
| 609 | .num_resources = ARRAY_SIZE(s3c2443_dma_resource), |
| 610 | .resource = s3c2443_dma_resource, |
| 611 | .dev = { |
Sylwester Nawrocki | 971466b | 2016-08-04 11:56:12 +0200 | [diff] [blame] | 612 | .dma_mask = &s3c24xx_device_dma_mask, |
| 613 | .coherent_dma_mask = DMA_BIT_MASK(32), |
| 614 | .platform_data = &s3c2443_dma_platdata, |
Heiko Stuebner | f2dda07 | 2013-10-08 06:42:10 +0900 | [diff] [blame] | 615 | }, |
| 616 | }; |
| 617 | #endif |
Heiko Stuebner | dfc0f50 | 2014-02-19 09:26:21 +0900 | [diff] [blame] | 618 | |
Heiko Stuebner | 4659c53 | 2014-05-09 05:49:14 +0900 | [diff] [blame] | 619 | #if defined(CONFIG_COMMON_CLK) && defined(CONFIG_CPU_S3C2410) |
| 620 | void __init s3c2410_init_clocks(int xtal) |
| 621 | { |
| 622 | s3c2410_common_clk_init(NULL, xtal, 0, S3C24XX_VA_CLKPWR); |
Heiko Stuebner | 4659c53 | 2014-05-09 05:49:14 +0900 | [diff] [blame] | 623 | } |
| 624 | #endif |
| 625 | |
Heiko Stuebner | 3c27f31 | 2014-02-25 09:50:44 +0900 | [diff] [blame] | 626 | #ifdef CONFIG_CPU_S3C2412 |
| 627 | void __init s3c2412_init_clocks(int xtal) |
| 628 | { |
| 629 | s3c2412_common_clk_init(NULL, xtal, 0, S3C24XX_VA_CLKPWR); |
| 630 | } |
| 631 | #endif |
| 632 | |
Heiko Stuebner | dfc0f50 | 2014-02-19 09:26:21 +0900 | [diff] [blame] | 633 | #ifdef CONFIG_CPU_S3C2416 |
| 634 | void __init s3c2416_init_clocks(int xtal) |
| 635 | { |
| 636 | s3c2443_common_clk_init(NULL, xtal, 0, S3C24XX_VA_CLKPWR); |
| 637 | } |
| 638 | #endif |
| 639 | |
Heiko Stuebner | 4659c53 | 2014-05-09 05:49:14 +0900 | [diff] [blame] | 640 | #if defined(CONFIG_COMMON_CLK) && defined(CONFIG_CPU_S3C2440) |
| 641 | void __init s3c2440_init_clocks(int xtal) |
| 642 | { |
| 643 | s3c2410_common_clk_init(NULL, xtal, 1, S3C24XX_VA_CLKPWR); |
Heiko Stuebner | 4659c53 | 2014-05-09 05:49:14 +0900 | [diff] [blame] | 644 | } |
| 645 | #endif |
| 646 | |
| 647 | #if defined(CONFIG_COMMON_CLK) && defined(CONFIG_CPU_S3C2442) |
| 648 | void __init s3c2442_init_clocks(int xtal) |
| 649 | { |
| 650 | s3c2410_common_clk_init(NULL, xtal, 2, S3C24XX_VA_CLKPWR); |
Heiko Stuebner | 4659c53 | 2014-05-09 05:49:14 +0900 | [diff] [blame] | 651 | } |
| 652 | #endif |
| 653 | |
Heiko Stuebner | dfc0f50 | 2014-02-19 09:26:21 +0900 | [diff] [blame] | 654 | #ifdef CONFIG_CPU_S3C2443 |
| 655 | void __init s3c2443_init_clocks(int xtal) |
| 656 | { |
| 657 | s3c2443_common_clk_init(NULL, xtal, 1, S3C24XX_VA_CLKPWR); |
| 658 | } |
| 659 | #endif |
Heiko Stuebner | 51cb128 | 2014-05-09 05:48:57 +0900 | [diff] [blame] | 660 | |
| 661 | #if defined(CONFIG_CPU_S3C2410) || defined(CONFIG_CPU_S3C2440) || \ |
| 662 | defined(CONFIG_CPU_S3C2442) |
| 663 | static struct resource s3c2410_dclk_resource[] = { |
| 664 | [0] = DEFINE_RES_MEM(0x56000084, 0x4), |
| 665 | }; |
| 666 | |
Krzysztof Kozlowski | b84e23f | 2020-08-06 20:20:23 +0200 | [diff] [blame] | 667 | static struct s3c2410_clk_platform_data s3c_clk_platform_data = { |
| 668 | .modify_misccr = s3c2410_modify_misccr, |
| 669 | }; |
| 670 | |
Heiko Stuebner | 51cb128 | 2014-05-09 05:48:57 +0900 | [diff] [blame] | 671 | struct platform_device s3c2410_device_dclk = { |
| 672 | .name = "s3c2410-dclk", |
| 673 | .id = 0, |
| 674 | .num_resources = ARRAY_SIZE(s3c2410_dclk_resource), |
| 675 | .resource = s3c2410_dclk_resource, |
Arnd Bergmann | 346f183 | 2020-08-06 20:20:22 +0200 | [diff] [blame] | 676 | .dev = { |
Krzysztof Kozlowski | b84e23f | 2020-08-06 20:20:23 +0200 | [diff] [blame] | 677 | .platform_data = &s3c_clk_platform_data, |
Arnd Bergmann | 346f183 | 2020-08-06 20:20:22 +0200 | [diff] [blame] | 678 | }, |
Heiko Stuebner | 51cb128 | 2014-05-09 05:48:57 +0900 | [diff] [blame] | 679 | }; |
| 680 | #endif |