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Jamie Ilesc9353ae2011-01-24 12:19:12 +00001/*
2 * Copyright 2010-2011 Picochip Ltd., Jamie Iles
3 * http://www.picochip.com
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version
8 * 2 of the License, or (at your option) any later version.
9 *
10 * This file implements a driver for the Synopsys DesignWare watchdog device
Baruch Siach58a251f2013-12-30 14:25:54 +020011 * in the many subsystems. The watchdog has 16 different timeout periods
Jamie Ilesc9353ae2011-01-24 12:19:12 +000012 * and these are a function of the input clock frequency.
13 *
14 * The DesignWare watchdog cannot be stopped once it has been started so we
Guenter Roeckf29a72c2016-02-28 13:12:19 -080015 * do not implement a stop function. The watchdog core will continue to send
16 * heartbeat requests after the watchdog device has been closed.
Jamie Ilesc9353ae2011-01-24 12:19:12 +000017 */
Joe Perches27c766a2012-02-15 15:06:19 -080018
19#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
Jamie Ilesc9353ae2011-01-24 12:19:12 +000020
21#include <linux/bitops.h>
22#include <linux/clk.h>
Jisheng Zhang31228f42014-09-23 15:42:12 +080023#include <linux/delay.h>
Jamie Ilesc9353ae2011-01-24 12:19:12 +000024#include <linux/err.h>
Jamie Ilesc9353ae2011-01-24 12:19:12 +000025#include <linux/io.h>
26#include <linux/kernel.h>
Jamie Ilesc9353ae2011-01-24 12:19:12 +000027#include <linux/module.h>
28#include <linux/moduleparam.h>
Dinh Nguyen58e56372013-10-22 11:59:12 -050029#include <linux/of.h>
Jamie Ilesc9353ae2011-01-24 12:19:12 +000030#include <linux/pm.h>
31#include <linux/platform_device.h>
Jamie Ilesc9353ae2011-01-24 12:19:12 +000032#include <linux/watchdog.h>
33
34#define WDOG_CONTROL_REG_OFFSET 0x00
35#define WDOG_CONTROL_REG_WDT_EN_MASK 0x01
36#define WDOG_TIMEOUT_RANGE_REG_OFFSET 0x04
Jisheng Zhangdfa07142014-09-23 15:42:11 +080037#define WDOG_TIMEOUT_RANGE_TOPINIT_SHIFT 4
Jamie Ilesc9353ae2011-01-24 12:19:12 +000038#define WDOG_CURRENT_COUNT_REG_OFFSET 0x08
39#define WDOG_COUNTER_RESTART_REG_OFFSET 0x0c
40#define WDOG_COUNTER_RESTART_KICK_VALUE 0x76
41
42/* The maximum TOP (timeout period) value that can be set in the watchdog. */
43#define DW_WDT_MAX_TOP 15
44
Doug Andersonb5ade9b2015-01-27 14:25:17 -080045#define DW_WDT_DEFAULT_SECONDS 30
46
Wim Van Sebroeck86a1e182012-03-05 16:51:11 +010047static bool nowayout = WATCHDOG_NOWAYOUT;
48module_param(nowayout, bool, 0);
Jamie Ilesc9353ae2011-01-24 12:19:12 +000049MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started "
50 "(default=" __MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
51
Guenter Roeckf29a72c2016-02-28 13:12:19 -080052struct dw_wdt {
Jamie Ilesc9353ae2011-01-24 12:19:12 +000053 void __iomem *regs;
54 struct clk *clk;
Guenter Roeckc97344f2016-08-09 22:35:58 -070055 unsigned long rate;
Guenter Roeckf29a72c2016-02-28 13:12:19 -080056 struct watchdog_device wdd;
57};
Jamie Ilesc9353ae2011-01-24 12:19:12 +000058
Guenter Roeckf29a72c2016-02-28 13:12:19 -080059#define to_dw_wdt(wdd) container_of(wdd, struct dw_wdt, wdd)
60
61static inline int dw_wdt_is_enabled(struct dw_wdt *dw_wdt)
Jamie Ilesc9353ae2011-01-24 12:19:12 +000062{
Guenter Roeckf29a72c2016-02-28 13:12:19 -080063 return readl(dw_wdt->regs + WDOG_CONTROL_REG_OFFSET) &
Jamie Ilesc9353ae2011-01-24 12:19:12 +000064 WDOG_CONTROL_REG_WDT_EN_MASK;
65}
66
Guenter Roeckf29a72c2016-02-28 13:12:19 -080067static inline int dw_wdt_top_in_seconds(struct dw_wdt *dw_wdt, unsigned top)
Jamie Ilesc9353ae2011-01-24 12:19:12 +000068{
69 /*
70 * There are 16 possible timeout values in 0..15 where the number of
71 * cycles is 2 ^ (16 + i) and the watchdog counts down.
72 */
Guenter Roeckc97344f2016-08-09 22:35:58 -070073 return (1U << (16 + top)) / dw_wdt->rate;
Jamie Ilesc9353ae2011-01-24 12:19:12 +000074}
75
Guenter Roeckf29a72c2016-02-28 13:12:19 -080076static int dw_wdt_get_top(struct dw_wdt *dw_wdt)
Jamie Ilesc9353ae2011-01-24 12:19:12 +000077{
Guenter Roeckf29a72c2016-02-28 13:12:19 -080078 int top = readl(dw_wdt->regs + WDOG_TIMEOUT_RANGE_REG_OFFSET) & 0xF;
Jamie Ilesc9353ae2011-01-24 12:19:12 +000079
Guenter Roeckf29a72c2016-02-28 13:12:19 -080080 return dw_wdt_top_in_seconds(dw_wdt, top);
Jamie Ilesc9353ae2011-01-24 12:19:12 +000081}
82
Guenter Roeckf29a72c2016-02-28 13:12:19 -080083static int dw_wdt_ping(struct watchdog_device *wdd)
Jamie Ilesc9353ae2011-01-24 12:19:12 +000084{
Guenter Roeckf29a72c2016-02-28 13:12:19 -080085 struct dw_wdt *dw_wdt = to_dw_wdt(wdd);
Jamie Ilesc9353ae2011-01-24 12:19:12 +000086
Guenter Roeckf29a72c2016-02-28 13:12:19 -080087 writel(WDOG_COUNTER_RESTART_KICK_VALUE, dw_wdt->regs +
Doug Andersona0085012015-01-27 14:25:16 -080088 WDOG_COUNTER_RESTART_REG_OFFSET);
Guenter Roeckf29a72c2016-02-28 13:12:19 -080089
90 return 0;
Doug Andersona0085012015-01-27 14:25:16 -080091}
92
Guenter Roeckf29a72c2016-02-28 13:12:19 -080093static int dw_wdt_set_timeout(struct watchdog_device *wdd, unsigned int top_s)
Jamie Ilesc9353ae2011-01-24 12:19:12 +000094{
Guenter Roeckf29a72c2016-02-28 13:12:19 -080095 struct dw_wdt *dw_wdt = to_dw_wdt(wdd);
Jamie Ilesc9353ae2011-01-24 12:19:12 +000096 int i, top_val = DW_WDT_MAX_TOP;
97
98 /*
99 * Iterate over the timeout values until we find the closest match. We
100 * always look for >=.
101 */
102 for (i = 0; i <= DW_WDT_MAX_TOP; ++i)
Guenter Roeckf29a72c2016-02-28 13:12:19 -0800103 if (dw_wdt_top_in_seconds(dw_wdt, i) >= top_s) {
Jamie Ilesc9353ae2011-01-24 12:19:12 +0000104 top_val = i;
105 break;
106 }
107
Doug Andersona0085012015-01-27 14:25:16 -0800108 /*
109 * Set the new value in the watchdog. Some versions of dw_wdt
110 * have have TOPINIT in the TIMEOUT_RANGE register (as per
111 * CP_WDT_DUAL_TOP in WDT_COMP_PARAMS_1). On those we
112 * effectively get a pat of the watchdog right here.
113 */
Jisheng Zhangdfa07142014-09-23 15:42:11 +0800114 writel(top_val | top_val << WDOG_TIMEOUT_RANGE_TOPINIT_SHIFT,
Guenter Roeckf29a72c2016-02-28 13:12:19 -0800115 dw_wdt->regs + WDOG_TIMEOUT_RANGE_REG_OFFSET);
Jamie Ilesc9353ae2011-01-24 12:19:12 +0000116
Guenter Roeckf29a72c2016-02-28 13:12:19 -0800117 wdd->timeout = dw_wdt_top_in_seconds(dw_wdt, top_val);
Doug Andersona0085012015-01-27 14:25:16 -0800118
Guenter Roeckf29a72c2016-02-28 13:12:19 -0800119 return 0;
120}
Jamie Ilesc9353ae2011-01-24 12:19:12 +0000121
Guenter Roeckf29a72c2016-02-28 13:12:19 -0800122static int dw_wdt_start(struct watchdog_device *wdd)
123{
124 struct dw_wdt *dw_wdt = to_dw_wdt(wdd);
125
126 dw_wdt_set_timeout(wdd, wdd->timeout);
127
128 set_bit(WDOG_HW_RUNNING, &wdd->status);
129
130 writel(WDOG_CONTROL_REG_WDT_EN_MASK,
131 dw_wdt->regs + WDOG_CONTROL_REG_OFFSET);
132
133 return 0;
Jamie Ilesc9353ae2011-01-24 12:19:12 +0000134}
135
Guenter Roecka70dcc02017-01-04 12:27:21 -0800136static int dw_wdt_restart(struct watchdog_device *wdd,
137 unsigned long action, void *data)
Jisheng Zhang31228f42014-09-23 15:42:12 +0800138{
Guenter Roecka70dcc02017-01-04 12:27:21 -0800139 struct dw_wdt *dw_wdt = to_dw_wdt(wdd);
Jisheng Zhang31228f42014-09-23 15:42:12 +0800140 u32 val;
141
Guenter Roeckf29a72c2016-02-28 13:12:19 -0800142 writel(0, dw_wdt->regs + WDOG_TIMEOUT_RANGE_REG_OFFSET);
143 val = readl(dw_wdt->regs + WDOG_CONTROL_REG_OFFSET);
Jisheng Zhang31228f42014-09-23 15:42:12 +0800144 if (val & WDOG_CONTROL_REG_WDT_EN_MASK)
Guenter Roeckf29a72c2016-02-28 13:12:19 -0800145 writel(WDOG_COUNTER_RESTART_KICK_VALUE,
146 dw_wdt->regs + WDOG_COUNTER_RESTART_REG_OFFSET);
Jisheng Zhang31228f42014-09-23 15:42:12 +0800147 else
148 writel(WDOG_CONTROL_REG_WDT_EN_MASK,
Guenter Roeckf29a72c2016-02-28 13:12:19 -0800149 dw_wdt->regs + WDOG_CONTROL_REG_OFFSET);
Jisheng Zhang31228f42014-09-23 15:42:12 +0800150
151 /* wait for reset to assert... */
152 mdelay(500);
153
Guenter Roecka70dcc02017-01-04 12:27:21 -0800154 return 0;
Jisheng Zhang31228f42014-09-23 15:42:12 +0800155}
156
Guenter Roeckf29a72c2016-02-28 13:12:19 -0800157static unsigned int dw_wdt_get_timeleft(struct watchdog_device *wdd)
Jamie Ilesc9353ae2011-01-24 12:19:12 +0000158{
Guenter Roeckf29a72c2016-02-28 13:12:19 -0800159 struct dw_wdt *dw_wdt = to_dw_wdt(wdd);
Jamie Ilesc9353ae2011-01-24 12:19:12 +0000160
Guenter Roeckf29a72c2016-02-28 13:12:19 -0800161 return readl(dw_wdt->regs + WDOG_CURRENT_COUNT_REG_OFFSET) /
Guenter Roeckc97344f2016-08-09 22:35:58 -0700162 dw_wdt->rate;
Jamie Ilesc9353ae2011-01-24 12:19:12 +0000163}
164
165static const struct watchdog_info dw_wdt_ident = {
166 .options = WDIOF_KEEPALIVEPING | WDIOF_SETTIMEOUT |
167 WDIOF_MAGICCLOSE,
168 .identity = "Synopsys DesignWare Watchdog",
169};
170
Guenter Roeckf29a72c2016-02-28 13:12:19 -0800171static const struct watchdog_ops dw_wdt_ops = {
172 .owner = THIS_MODULE,
173 .start = dw_wdt_start,
174 .ping = dw_wdt_ping,
175 .set_timeout = dw_wdt_set_timeout,
176 .get_timeleft = dw_wdt_get_timeleft,
Guenter Roecka70dcc02017-01-04 12:27:21 -0800177 .restart = dw_wdt_restart,
Guenter Roeckf29a72c2016-02-28 13:12:19 -0800178};
Jamie Ilesc9353ae2011-01-24 12:19:12 +0000179
Heiko Stübnerad83c6c2013-06-26 20:03:52 +0200180#ifdef CONFIG_PM_SLEEP
Jamie Ilesc9353ae2011-01-24 12:19:12 +0000181static int dw_wdt_suspend(struct device *dev)
182{
Guenter Roeckf29a72c2016-02-28 13:12:19 -0800183 struct dw_wdt *dw_wdt = dev_get_drvdata(dev);
184
185 clk_disable_unprepare(dw_wdt->clk);
Jamie Ilesc9353ae2011-01-24 12:19:12 +0000186
187 return 0;
188}
189
190static int dw_wdt_resume(struct device *dev)
191{
Guenter Roeckf29a72c2016-02-28 13:12:19 -0800192 struct dw_wdt *dw_wdt = dev_get_drvdata(dev);
193 int err = clk_prepare_enable(dw_wdt->clk);
Jamie Ilesc9353ae2011-01-24 12:19:12 +0000194
195 if (err)
196 return err;
197
Guenter Roeckf29a72c2016-02-28 13:12:19 -0800198 dw_wdt_ping(&dw_wdt->wdd);
Jamie Ilesc9353ae2011-01-24 12:19:12 +0000199
200 return 0;
201}
Heiko Stübnerad83c6c2013-06-26 20:03:52 +0200202#endif /* CONFIG_PM_SLEEP */
Jamie Ilesc9353ae2011-01-24 12:19:12 +0000203
Heiko Stübnerad83c6c2013-06-26 20:03:52 +0200204static SIMPLE_DEV_PM_OPS(dw_wdt_pm_ops, dw_wdt_suspend, dw_wdt_resume);
Jamie Ilesc9353ae2011-01-24 12:19:12 +0000205
Bill Pemberton2d991a12012-11-19 13:21:41 -0500206static int dw_wdt_drv_probe(struct platform_device *pdev)
Jamie Ilesc9353ae2011-01-24 12:19:12 +0000207{
Guenter Roeckf29a72c2016-02-28 13:12:19 -0800208 struct device *dev = &pdev->dev;
209 struct watchdog_device *wdd;
210 struct dw_wdt *dw_wdt;
211 struct resource *mem;
Jamie Ilesc9353ae2011-01-24 12:19:12 +0000212 int ret;
Jamie Ilesc9353ae2011-01-24 12:19:12 +0000213
Guenter Roeckf29a72c2016-02-28 13:12:19 -0800214 dw_wdt = devm_kzalloc(dev, sizeof(*dw_wdt), GFP_KERNEL);
215 if (!dw_wdt)
216 return -ENOMEM;
Jamie Ilesc9353ae2011-01-24 12:19:12 +0000217
Guenter Roeckf29a72c2016-02-28 13:12:19 -0800218 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
219 dw_wdt->regs = devm_ioremap_resource(dev, mem);
220 if (IS_ERR(dw_wdt->regs))
221 return PTR_ERR(dw_wdt->regs);
Jamie Ilesc9353ae2011-01-24 12:19:12 +0000222
Guenter Roeckf29a72c2016-02-28 13:12:19 -0800223 dw_wdt->clk = devm_clk_get(dev, NULL);
224 if (IS_ERR(dw_wdt->clk))
225 return PTR_ERR(dw_wdt->clk);
226
227 ret = clk_prepare_enable(dw_wdt->clk);
Jamie Ilesc9353ae2011-01-24 12:19:12 +0000228 if (ret)
Jingoo Hancf3cc8c2013-04-29 18:15:26 +0900229 return ret;
Jamie Ilesc9353ae2011-01-24 12:19:12 +0000230
Guenter Roeckc97344f2016-08-09 22:35:58 -0700231 dw_wdt->rate = clk_get_rate(dw_wdt->clk);
232 if (dw_wdt->rate == 0) {
233 ret = -EINVAL;
234 goto out_disable_clk;
235 }
236
Guenter Roeckf29a72c2016-02-28 13:12:19 -0800237 wdd = &dw_wdt->wdd;
238 wdd->info = &dw_wdt_ident;
239 wdd->ops = &dw_wdt_ops;
240 wdd->min_timeout = 1;
241 wdd->max_hw_heartbeat_ms =
242 dw_wdt_top_in_seconds(dw_wdt, DW_WDT_MAX_TOP) * 1000;
243 wdd->parent = dev;
244
245 watchdog_set_drvdata(wdd, dw_wdt);
246 watchdog_set_nowayout(wdd, nowayout);
247 watchdog_init_timeout(wdd, 0, dev);
248
249 /*
250 * If the watchdog is already running, use its already configured
251 * timeout. Otherwise use the default or the value provided through
252 * devicetree.
253 */
254 if (dw_wdt_is_enabled(dw_wdt)) {
255 wdd->timeout = dw_wdt_get_top(dw_wdt);
256 set_bit(WDOG_HW_RUNNING, &wdd->status);
257 } else {
258 wdd->timeout = DW_WDT_DEFAULT_SECONDS;
259 watchdog_init_timeout(wdd, 0, dev);
260 }
261
262 platform_set_drvdata(pdev, dw_wdt);
263
Guenter Roecka70dcc02017-01-04 12:27:21 -0800264 watchdog_set_restart_priority(wdd, 128);
265
Guenter Roeckf29a72c2016-02-28 13:12:19 -0800266 ret = watchdog_register_device(wdd);
Jamie Ilesc9353ae2011-01-24 12:19:12 +0000267 if (ret)
268 goto out_disable_clk;
269
Jamie Ilesc9353ae2011-01-24 12:19:12 +0000270 return 0;
271
272out_disable_clk:
Guenter Roeckf29a72c2016-02-28 13:12:19 -0800273 clk_disable_unprepare(dw_wdt->clk);
Jamie Ilesc9353ae2011-01-24 12:19:12 +0000274 return ret;
275}
276
Bill Pemberton4b12b892012-11-19 13:26:24 -0500277static int dw_wdt_drv_remove(struct platform_device *pdev)
Jamie Ilesc9353ae2011-01-24 12:19:12 +0000278{
Guenter Roeckf29a72c2016-02-28 13:12:19 -0800279 struct dw_wdt *dw_wdt = platform_get_drvdata(pdev);
Jisheng Zhang31228f42014-09-23 15:42:12 +0800280
Guenter Roeckf29a72c2016-02-28 13:12:19 -0800281 watchdog_unregister_device(&dw_wdt->wdd);
282 clk_disable_unprepare(dw_wdt->clk);
Jamie Ilesc9353ae2011-01-24 12:19:12 +0000283
284 return 0;
285}
286
Dinh Nguyen58e56372013-10-22 11:59:12 -0500287#ifdef CONFIG_OF
288static const struct of_device_id dw_wdt_of_match[] = {
289 { .compatible = "snps,dw-wdt", },
290 { /* sentinel */ }
291};
292MODULE_DEVICE_TABLE(of, dw_wdt_of_match);
293#endif
294
Jamie Ilesc9353ae2011-01-24 12:19:12 +0000295static struct platform_driver dw_wdt_driver = {
296 .probe = dw_wdt_drv_probe,
Bill Pemberton82268712012-11-19 13:21:12 -0500297 .remove = dw_wdt_drv_remove,
Jamie Ilesc9353ae2011-01-24 12:19:12 +0000298 .driver = {
299 .name = "dw_wdt",
Dinh Nguyen58e56372013-10-22 11:59:12 -0500300 .of_match_table = of_match_ptr(dw_wdt_of_match),
Jamie Ilesc9353ae2011-01-24 12:19:12 +0000301 .pm = &dw_wdt_pm_ops,
Jamie Ilesc9353ae2011-01-24 12:19:12 +0000302 },
303};
304
Axel Linb8ec6112011-11-29 13:56:27 +0800305module_platform_driver(dw_wdt_driver);
Jamie Ilesc9353ae2011-01-24 12:19:12 +0000306
307MODULE_AUTHOR("Jamie Iles");
308MODULE_DESCRIPTION("Synopsys DesignWare Watchdog Driver");
309MODULE_LICENSE("GPL");