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review.shift-gmbh.com / SHIFTPHONES / mainline / linux / ea1be1e59b19017e61aa357d524b743ba5602d3c / . / arch / arm64 / boot / dts / freescale / fsl-ls2080a.dtsi
blob: f9c1d30cf4a7df64d7e877d6be18fa156d16faa6 [file] [log] [blame]
Li Yang7a2aeb92018-06-12 13:28:42 -0500[diff] [blame]1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
Bhupesh Sharma747c84d02015-01-25 02:42:52 +0530[diff] [blame]2/*
Bhupesh Sharmaf43a4b82015-10-24 01:01:51 +0530[diff] [blame]3 * Device Tree Include file for Freescale Layerscape-2080A family SoC.
Bhupesh Sharma747c84d02015-01-25 02:42:52 +0530[diff] [blame]4 *
Li Yang8637f582017-04-27 11:47:58 -0500[diff] [blame]5 * Copyright 2014-2016 Freescale Semiconductor, Inc.
Bhupesh Sharma747c84d02015-01-25 02:42:52 +0530[diff] [blame]6 *
Abhimanyu Sainic2f6a472017-02-01 11:58:35 +0530[diff] [blame]7 * Abhimanyu Saini <abhimanyu.saini@nxp.com>
Bhupesh Sharma747c84d02015-01-25 02:42:52 +0530[diff] [blame]8 * Bhupesh Sharma <bhupesh.sharma@freescale.com>
9 *
Bhupesh Sharma747c84d02015-01-25 02:42:52 +0530[diff] [blame]10 */
11
Abhimanyu Sainic2f6a472017-02-01 11:58:35 +0530[diff] [blame]12#include "fsl-ls208xa.dtsi"
Hongtao Jia236f7942016-10-09 14:47:06 +0800[diff] [blame]13
Abhimanyu Sainic2f6a472017-02-01 11:58:35 +0530[diff] [blame]14&cpu {
15 cpu0: cpu@0 {
16 device_type = "cpu";
17 compatible = "arm,cortex-a57";
18 reg = <0x0>;
19 clocks = <&clockgen 1 0>;
Yuantian Tang39a71db2017-08-07 09:54:39 +0800[diff] [blame]20 cpu-idle-states = <&CPU_PW20>;
Abhimanyu Sainic2f6a472017-02-01 11:58:35 +0530[diff] [blame]21 next-level-cache = <&cluster0_l2>;
22 #cooling-cells = <2>;
Bhupesh Sharma747c84d02015-01-25 02:42:52 +0530[diff] [blame]23 };
24
Abhimanyu Sainic2f6a472017-02-01 11:58:35 +0530[diff] [blame]25 cpu1: cpu@1 {
26 device_type = "cpu";
27 compatible = "arm,cortex-a57";
28 reg = <0x1>;
29 clocks = <&clockgen 1 0>;
Yuantian Tang39a71db2017-08-07 09:54:39 +0800[diff] [blame]30 cpu-idle-states = <&CPU_PW20>;
Abhimanyu Sainic2f6a472017-02-01 11:58:35 +0530[diff] [blame]31 next-level-cache = <&cluster0_l2>;
Viresh Kumar346f5972018-05-25 11:10:02 +0530[diff] [blame]32 #cooling-cells = <2>;
Bhupesh Sharma747c84d02015-01-25 02:42:52 +0530[diff] [blame]33 };
34
Abhimanyu Sainic2f6a472017-02-01 11:58:35 +0530[diff] [blame]35 cpu2: cpu@100 {
36 device_type = "cpu";
37 compatible = "arm,cortex-a57";
38 reg = <0x100>;
39 clocks = <&clockgen 1 1>;
Yuantian Tang39a71db2017-08-07 09:54:39 +0800[diff] [blame]40 cpu-idle-states = <&CPU_PW20>;
Abhimanyu Sainic2f6a472017-02-01 11:58:35 +0530[diff] [blame]41 next-level-cache = <&cluster1_l2>;
42 #cooling-cells = <2>;
Bhupesh Sharma54615972015-10-24 01:01:57 +0530[diff] [blame]43 };
44
Abhimanyu Sainic2f6a472017-02-01 11:58:35 +0530[diff] [blame]45 cpu3: cpu@101 {
46 device_type = "cpu";
47 compatible = "arm,cortex-a57";
48 reg = <0x101>;
49 clocks = <&clockgen 1 1>;
Yuantian Tang39a71db2017-08-07 09:54:39 +0800[diff] [blame]50 cpu-idle-states = <&CPU_PW20>;
Abhimanyu Sainic2f6a472017-02-01 11:58:35 +0530[diff] [blame]51 next-level-cache = <&cluster1_l2>;
Viresh Kumar346f5972018-05-25 11:10:02 +0530[diff] [blame]52 #cooling-cells = <2>;
Bhupesh Sharma747c84d02015-01-25 02:42:52 +0530[diff] [blame]53 };
54
Abhimanyu Sainic2f6a472017-02-01 11:58:35 +0530[diff] [blame]55 cpu4: cpu@200 {
56 device_type = "cpu";
57 compatible = "arm,cortex-a57";
58 reg = <0x200>;
59 clocks = <&clockgen 1 2>;
Yuantian Tang39a71db2017-08-07 09:54:39 +0800[diff] [blame]60 cpu-idle-states = <&CPU_PW20>;
Abhimanyu Sainic2f6a472017-02-01 11:58:35 +0530[diff] [blame]61 next-level-cache = <&cluster2_l2>;
62 #cooling-cells = <2>;
J. German Riverac7a56752015-12-04 16:56:04 -0600[diff] [blame]63 };
64
Abhimanyu Sainic2f6a472017-02-01 11:58:35 +0530[diff] [blame]65 cpu5: cpu@201 {
66 device_type = "cpu";
67 compatible = "arm,cortex-a57";
68 reg = <0x201>;
69 clocks = <&clockgen 1 2>;
Yuantian Tang39a71db2017-08-07 09:54:39 +0800[diff] [blame]70 cpu-idle-states = <&CPU_PW20>;
Abhimanyu Sainic2f6a472017-02-01 11:58:35 +0530[diff] [blame]71 next-level-cache = <&cluster2_l2>;
Viresh Kumar346f5972018-05-25 11:10:02 +0530[diff] [blame]72 #cooling-cells = <2>;
J. German Riverac7a56752015-12-04 16:56:04 -0600[diff] [blame]73 };
74
Abhimanyu Sainic2f6a472017-02-01 11:58:35 +0530[diff] [blame]75 cpu6: cpu@300 {
76 device_type = "cpu";
77 compatible = "arm,cortex-a57";
78 reg = <0x300>;
79 clocks = <&clockgen 1 3>;
80 next-level-cache = <&cluster3_l2>;
Yuantian Tang39a71db2017-08-07 09:54:39 +0800[diff] [blame]81 cpu-idle-states = <&CPU_PW20>;
Abhimanyu Sainic2f6a472017-02-01 11:58:35 +0530[diff] [blame]82 #cooling-cells = <2>;
Bhupesh Sharma747c84d02015-01-25 02:42:52 +0530[diff] [blame]83 };
84
Abhimanyu Sainic2f6a472017-02-01 11:58:35 +0530[diff] [blame]85 cpu7: cpu@301 {
86 device_type = "cpu";
87 compatible = "arm,cortex-a57";
88 reg = <0x301>;
89 clocks = <&clockgen 1 3>;
Yuantian Tang39a71db2017-08-07 09:54:39 +0800[diff] [blame]90 cpu-idle-states = <&CPU_PW20>;
Abhimanyu Sainic2f6a472017-02-01 11:58:35 +0530[diff] [blame]91 next-level-cache = <&cluster3_l2>;
Viresh Kumar346f5972018-05-25 11:10:02 +0530[diff] [blame]92 #cooling-cells = <2>;
Bhupesh Sharma747c84d02015-01-25 02:42:52 +0530[diff] [blame]93 };
94
Abhimanyu Sainic2f6a472017-02-01 11:58:35 +0530[diff] [blame]95 cluster0_l2: l2-cache0 {
96 compatible = "cache";
Bhupesh Sharma747c84d02015-01-25 02:42:52 +0530[diff] [blame]97 };
York Sun30062fb2016-08-09 14:59:39 -0700[diff] [blame]98
Abhimanyu Sainic2f6a472017-02-01 11:58:35 +0530[diff] [blame]99 cluster1_l2: l2-cache1 {
100 compatible = "cache";
York Sun30062fb2016-08-09 14:59:39 -0700[diff] [blame]101 };
102
Abhimanyu Sainic2f6a472017-02-01 11:58:35 +0530[diff] [blame]103 cluster2_l2: l2-cache2 {
104 compatible = "cache";
York Sun30062fb2016-08-09 14:59:39 -0700[diff] [blame]105 };
Abhimanyu Sainic2f6a472017-02-01 11:58:35 +0530[diff] [blame]106
107 cluster3_l2: l2-cache3 {
108 compatible = "cache";
109 };
Yuantian Tang39a71db2017-08-07 09:54:39 +0800[diff] [blame]110
111 CPU_PW20: cpu-pw20 {
112 compatible = "arm,idle-state";
113 idle-state-name = "PW20";
114 arm,psci-suspend-param = <0x00010000>;
115 entry-latency-us = <2000>;
116 exit-latency-us = <2000>;
117 min-residency-us = <6000>;
118 };
Abhimanyu Sainic2f6a472017-02-01 11:58:35 +0530[diff] [blame]119};
120
121&pcie1 {
122 reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */
123 0x10 0x00000000 0x0 0x00002000>; /* configuration space */
124
125 ranges = <0x81000000 0x0 0x00000000 0x10 0x00010000 0x0 0x00010000 /* downstream I/O */
126 0x82000000 0x0 0x40000000 0x10 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
127};
128
129&pcie2 {
130 reg = <0x00 0x03500000 0x0 0x00100000 /* controller registers */
131 0x12 0x00000000 0x0 0x00002000>; /* configuration space */
132
133 ranges = <0x81000000 0x0 0x00000000 0x12 0x00010000 0x0 0x00010000 /* downstream I/O */
134 0x82000000 0x0 0x40000000 0x12 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
135};
136
137&pcie3 {
138 reg = <0x00 0x03600000 0x0 0x00100000 /* controller registers */
139 0x14 0x00000000 0x0 0x00002000>; /* configuration space */
140
141 ranges = <0x81000000 0x0 0x00000000 0x14 0x00010000 0x0 0x00010000 /* downstream I/O */
142 0x82000000 0x0 0x40000000 0x14 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
143};
144
145&pcie4 {
146 reg = <0x00 0x03700000 0x0 0x00100000 /* controller registers */
147 0x16 0x00000000 0x0 0x00002000>; /* configuration space */
148
149 ranges = <0x81000000 0x0 0x00000000 0x16 0x00010000 0x0 0x00010000 /* downstream I/O */
150 0x82000000 0x0 0x40000000 0x16 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
Bhupesh Sharma747c84d02015-01-25 02:42:52 +0530[diff] [blame]151};