blob: d92156ceb3ac57283c1d20f3c7a5934cca74b064 [file] [log] [blame]
Thomas Gleixner97fb5e82019-05-29 07:17:58 -07001/* SPDX-License-Identifier: GPL-2.0-only */
Elliot Berman5443cc52020-01-07 13:04:11 -08002/* Copyright (c) 2010-2015,2019 The Linux Foundation. All rights reserved.
Kumar Galab6a1dfb2015-03-11 16:28:10 -05003 */
4#ifndef __QCOM_SCM_INT_H
5#define __QCOM_SCM_INT_H
Elliot Berman9a434cee2020-01-07 13:04:26 -08006
7enum qcom_scm_convention {
8 SMC_CONVENTION_UNKNOWN,
9 SMC_CONVENTION_LEGACY,
10 SMC_CONVENTION_ARM_32,
11 SMC_CONVENTION_ARM_64,
12};
13
14extern enum qcom_scm_convention qcom_scm_convention;
15
Elliot Berman57d3b812020-01-07 13:04:25 -080016#define MAX_QCOM_SCM_ARGS 10
17#define MAX_QCOM_SCM_RETS 3
18
19enum qcom_scm_arg_types {
20 QCOM_SCM_VAL,
21 QCOM_SCM_RO,
22 QCOM_SCM_RW,
23 QCOM_SCM_BUFVAL,
24};
25
26#define QCOM_SCM_ARGS_IMPL(num, a, b, c, d, e, f, g, h, i, j, ...) (\
27 (((a) & 0x3) << 4) | \
28 (((b) & 0x3) << 6) | \
29 (((c) & 0x3) << 8) | \
30 (((d) & 0x3) << 10) | \
31 (((e) & 0x3) << 12) | \
32 (((f) & 0x3) << 14) | \
33 (((g) & 0x3) << 16) | \
34 (((h) & 0x3) << 18) | \
35 (((i) & 0x3) << 20) | \
36 (((j) & 0x3) << 22) | \
37 ((num) & 0xf))
38
39#define QCOM_SCM_ARGS(...) QCOM_SCM_ARGS_IMPL(__VA_ARGS__, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0)
40
41
42/**
43 * struct qcom_scm_desc
44 * @arginfo: Metadata describing the arguments in args[]
45 * @args: The array of arguments for the secure syscall
46 */
47struct qcom_scm_desc {
48 u32 svc;
49 u32 cmd;
50 u32 arginfo;
51 u64 args[MAX_QCOM_SCM_ARGS];
52 u32 owner;
53};
54
55/**
56 * struct qcom_scm_res
57 * @result: The values returned by the secure syscall
58 */
59struct qcom_scm_res {
60 u64 result[MAX_QCOM_SCM_RETS];
61};
62
Elliot Berman9a434cee2020-01-07 13:04:26 -080063#define SCM_SMC_FNID(s, c) ((((s) & 0xFF) << 8) | ((c) & 0xFF))
Stephen Boydf6ea5682021-02-23 13:45:35 -080064extern int __scm_smc_call(struct device *dev, const struct qcom_scm_desc *desc,
65 enum qcom_scm_convention qcom_convention,
66 struct qcom_scm_res *res, bool atomic);
67#define scm_smc_call(dev, desc, res, atomic) \
68 __scm_smc_call((dev), (desc), qcom_scm_convention, (res), (atomic))
Elliot Berman9a434cee2020-01-07 13:04:26 -080069
70#define SCM_LEGACY_FNID(s, c) (((s) << 10) | ((c) & 0x3ff))
71extern int scm_legacy_call_atomic(struct device *dev,
72 const struct qcom_scm_desc *desc,
73 struct qcom_scm_res *res);
74extern int scm_legacy_call(struct device *dev, const struct qcom_scm_desc *desc,
75 struct qcom_scm_res *res);
Kumar Galab6a1dfb2015-03-11 16:28:10 -050076
Elliot Berman65f0c902020-01-07 13:04:24 -080077#define QCOM_SCM_SVC_BOOT 0x01
78#define QCOM_SCM_BOOT_SET_ADDR 0x01
79#define QCOM_SCM_BOOT_TERMINATE_PC 0x02
80#define QCOM_SCM_BOOT_SET_DLOAD_MODE 0x10
81#define QCOM_SCM_BOOT_SET_REMOTE_STATE 0x0a
Elliot Berman65f0c902020-01-07 13:04:24 -080082#define QCOM_SCM_FLUSH_FLAG_MASK 0x3
Kumar Galab6a1dfb2015-03-11 16:28:10 -050083
Elliot Berman65f0c902020-01-07 13:04:24 -080084#define QCOM_SCM_SVC_PIL 0x02
85#define QCOM_SCM_PIL_PAS_INIT_IMAGE 0x01
86#define QCOM_SCM_PIL_PAS_MEM_SETUP 0x02
87#define QCOM_SCM_PIL_PAS_AUTH_AND_RESET 0x05
88#define QCOM_SCM_PIL_PAS_SHUTDOWN 0x06
89#define QCOM_SCM_PIL_PAS_IS_SUPPORTED 0x07
90#define QCOM_SCM_PIL_PAS_MSS_RESET 0x0a
Bjorn Anderssonf01e90f2015-09-23 12:56:12 -070091
Elliot Berman65f0c902020-01-07 13:04:24 -080092#define QCOM_SCM_SVC_IO 0x05
93#define QCOM_SCM_IO_READ 0x01
94#define QCOM_SCM_IO_WRITE 0x02
Elliot Berman65f0c902020-01-07 13:04:24 -080095
96#define QCOM_SCM_SVC_INFO 0x06
97#define QCOM_SCM_INFO_IS_CALL_AVAIL 0x01
Elliot Berman65f0c902020-01-07 13:04:24 -080098
99#define QCOM_SCM_SVC_MP 0x0c
100#define QCOM_SCM_MP_RESTORE_SEC_CFG 0x02
101#define QCOM_SCM_MP_IOMMU_SECURE_PTBL_SIZE 0x03
102#define QCOM_SCM_MP_IOMMU_SECURE_PTBL_INIT 0x04
Stanimir Varbanov6d885332020-08-17 10:27:22 +0200103#define QCOM_SCM_MP_VIDEO_VAR 0x08
Elliot Berman65f0c902020-01-07 13:04:24 -0800104#define QCOM_SCM_MP_ASSIGN 0x16
Elliot Berman65f0c902020-01-07 13:04:24 -0800105
106#define QCOM_SCM_SVC_OCMEM 0x0f
107#define QCOM_SCM_OCMEM_LOCK_CMD 0x01
108#define QCOM_SCM_OCMEM_UNLOCK_CMD 0x02
Elliot Berman65f0c902020-01-07 13:04:24 -0800109
Eric Biggers0f2065142020-07-10 00:20:08 -0700110#define QCOM_SCM_SVC_ES 0x10 /* Enterprise Security */
111#define QCOM_SCM_ES_INVALIDATE_ICE_KEY 0x03
112#define QCOM_SCM_ES_CONFIG_SET_ICE_KEY 0x04
113
Elliot Berman65f0c902020-01-07 13:04:24 -0800114#define QCOM_SCM_SVC_HDCP 0x11
115#define QCOM_SCM_HDCP_INVOKE 0x01
Elliot Berman65f0c902020-01-07 13:04:24 -0800116
Thara Gopinathde3438c2021-08-09 15:15:59 -0400117#define QCOM_SCM_SVC_LMH 0x13
118#define QCOM_SCM_LMH_LIMIT_PROFILE_CHANGE 0x01
119#define QCOM_SCM_LMH_LIMIT_DCVSH 0x10
120
Elliot Berman65f0c902020-01-07 13:04:24 -0800121#define QCOM_SCM_SVC_SMMU_PROGRAM 0x15
122#define QCOM_SCM_SMMU_CONFIG_ERRATA1 0x03
123#define QCOM_SCM_SMMU_CONFIG_ERRATA1_CLIENT_ALL 0x02
Elliot Berman65f0c902020-01-07 13:04:24 -0800124
125extern void __qcom_scm_init(void);
126
Kumar Galab6a1dfb2015-03-11 16:28:10 -0500127/* common error codes */
Kumar Gala6b1751a2016-06-03 18:25:26 -0500128#define QCOM_SCM_V2_EBUSY -12
Kumar Galab6a1dfb2015-03-11 16:28:10 -0500129#define QCOM_SCM_ENOMEM -5
130#define QCOM_SCM_EOPNOTSUPP -4
131#define QCOM_SCM_EINVAL_ADDR -3
132#define QCOM_SCM_EINVAL_ARG -2
133#define QCOM_SCM_ERROR -1
134#define QCOM_SCM_INTERRUPTED 1
135
Andy Gross11bdcee2016-06-03 18:25:24 -0500136static inline int qcom_scm_remap_error(int err)
137{
138 switch (err) {
139 case QCOM_SCM_ERROR:
140 return -EIO;
141 case QCOM_SCM_EINVAL_ADDR:
142 case QCOM_SCM_EINVAL_ARG:
143 return -EINVAL;
144 case QCOM_SCM_EOPNOTSUPP:
145 return -EOPNOTSUPP;
146 case QCOM_SCM_ENOMEM:
147 return -ENOMEM;
Kumar Gala6b1751a2016-06-03 18:25:26 -0500148 case QCOM_SCM_V2_EBUSY:
149 return -EBUSY;
Andy Gross11bdcee2016-06-03 18:25:24 -0500150 }
151 return -EINVAL;
152}
153
Kumar Galab6a1dfb2015-03-11 16:28:10 -0500154#endif