Dan Williams | 8fdcb17 | 2021-06-15 16:18:17 -0700 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0-only |
| 2 | /* Copyright(c) 2021 Intel Corporation. All rights reserved. */ |
| 3 | #include <linux/libnvdimm.h> |
Dan Williams | 60b8f17 | 2021-09-09 15:08:15 -0700 | [diff] [blame] | 4 | #include <asm/unaligned.h> |
Dan Williams | 8fdcb17 | 2021-06-15 16:18:17 -0700 | [diff] [blame] | 5 | #include <linux/device.h> |
| 6 | #include <linux/module.h> |
Dan Williams | 21083f5 | 2021-06-15 16:36:31 -0700 | [diff] [blame] | 7 | #include <linux/ndctl.h> |
| 8 | #include <linux/async.h> |
Dan Williams | 8fdcb17 | 2021-06-15 16:18:17 -0700 | [diff] [blame] | 9 | #include <linux/slab.h> |
Ben Widawsky | 5161a55 | 2021-08-02 10:29:38 -0700 | [diff] [blame] | 10 | #include "cxlmem.h" |
Dan Williams | 8fdcb17 | 2021-06-15 16:18:17 -0700 | [diff] [blame] | 11 | #include "cxl.h" |
| 12 | |
| 13 | /* |
| 14 | * Ordered workqueue for cxl nvdimm device arrival and departure |
| 15 | * to coordinate bus rescans when a bridge arrives and trigger remove |
| 16 | * operations when the bridge is removed. |
| 17 | */ |
| 18 | static struct workqueue_struct *cxl_pmem_wq; |
| 19 | |
Dan Williams | 12f3856 | 2021-09-14 12:03:04 -0700 | [diff] [blame] | 20 | static __read_mostly DECLARE_BITMAP(exclusive_cmds, CXL_MEM_COMMAND_ID_MAX); |
| 21 | |
Ira Weiny | 5e2411a | 2021-11-02 13:29:01 -0700 | [diff] [blame] | 22 | static void clear_exclusive(void *cxlds) |
Dan Williams | 12f3856 | 2021-09-14 12:03:04 -0700 | [diff] [blame] | 23 | { |
Ira Weiny | 5e2411a | 2021-11-02 13:29:01 -0700 | [diff] [blame] | 24 | clear_exclusive_cxl_commands(cxlds, exclusive_cmds); |
Dan Williams | 12f3856 | 2021-09-14 12:03:04 -0700 | [diff] [blame] | 25 | } |
| 26 | |
Dan Williams | 21083f5 | 2021-06-15 16:36:31 -0700 | [diff] [blame] | 27 | static void unregister_nvdimm(void *nvdimm) |
| 28 | { |
| 29 | nvdimm_delete(nvdimm); |
| 30 | } |
| 31 | |
Dan Williams | 21083f5 | 2021-06-15 16:36:31 -0700 | [diff] [blame] | 32 | static int cxl_nvdimm_probe(struct device *dev) |
| 33 | { |
| 34 | struct cxl_nvdimm *cxl_nvd = to_cxl_nvdimm(dev); |
Dan Williams | 12f3856 | 2021-09-14 12:03:04 -0700 | [diff] [blame] | 35 | struct cxl_memdev *cxlmd = cxl_nvd->cxlmd; |
Dan Williams | 60b8f17 | 2021-09-09 15:08:15 -0700 | [diff] [blame] | 36 | unsigned long flags = 0, cmd_mask = 0; |
Ira Weiny | 5e2411a | 2021-11-02 13:29:01 -0700 | [diff] [blame] | 37 | struct cxl_dev_state *cxlds = cxlmd->cxlds; |
Dan Williams | 21083f5 | 2021-06-15 16:36:31 -0700 | [diff] [blame] | 38 | struct cxl_nvdimm_bridge *cxl_nvb; |
Dan Williams | 21083f5 | 2021-06-15 16:36:31 -0700 | [diff] [blame] | 39 | struct nvdimm *nvdimm; |
Dan Williams | 12f3856 | 2021-09-14 12:03:04 -0700 | [diff] [blame] | 40 | int rc; |
Dan Williams | 21083f5 | 2021-06-15 16:36:31 -0700 | [diff] [blame] | 41 | |
Dan Williams | 7d3eb23 | 2021-09-08 22:13:21 -0700 | [diff] [blame] | 42 | cxl_nvb = cxl_find_nvdimm_bridge(cxl_nvd); |
Dan Williams | 21083f5 | 2021-06-15 16:36:31 -0700 | [diff] [blame] | 43 | if (!cxl_nvb) |
| 44 | return -ENXIO; |
| 45 | |
| 46 | device_lock(&cxl_nvb->dev); |
Dan Williams | 12f3856 | 2021-09-14 12:03:04 -0700 | [diff] [blame] | 47 | if (!cxl_nvb->nvdimm_bus) { |
| 48 | rc = -ENXIO; |
| 49 | goto out; |
| 50 | } |
| 51 | |
Ira Weiny | 5e2411a | 2021-11-02 13:29:01 -0700 | [diff] [blame] | 52 | set_exclusive_cxl_commands(cxlds, exclusive_cmds); |
| 53 | rc = devm_add_action_or_reset(dev, clear_exclusive, cxlds); |
Dan Williams | 12f3856 | 2021-09-14 12:03:04 -0700 | [diff] [blame] | 54 | if (rc) |
Dan Williams | 21083f5 | 2021-06-15 16:36:31 -0700 | [diff] [blame] | 55 | goto out; |
| 56 | |
| 57 | set_bit(NDD_LABELING, &flags); |
Dan Williams | 60b8f17 | 2021-09-09 15:08:15 -0700 | [diff] [blame] | 58 | set_bit(ND_CMD_GET_CONFIG_SIZE, &cmd_mask); |
| 59 | set_bit(ND_CMD_GET_CONFIG_DATA, &cmd_mask); |
| 60 | set_bit(ND_CMD_SET_CONFIG_DATA, &cmd_mask); |
| 61 | nvdimm = nvdimm_create(cxl_nvb->nvdimm_bus, cxl_nvd, NULL, flags, |
| 62 | cmd_mask, 0, NULL); |
Dan Williams | 12f3856 | 2021-09-14 12:03:04 -0700 | [diff] [blame] | 63 | if (!nvdimm) { |
| 64 | rc = -ENOMEM; |
Dan Williams | 21083f5 | 2021-06-15 16:36:31 -0700 | [diff] [blame] | 65 | goto out; |
Dan Williams | 12f3856 | 2021-09-14 12:03:04 -0700 | [diff] [blame] | 66 | } |
Dan Williams | 21083f5 | 2021-06-15 16:36:31 -0700 | [diff] [blame] | 67 | |
Dan Williams | 12f3856 | 2021-09-14 12:03:04 -0700 | [diff] [blame] | 68 | dev_set_drvdata(dev, nvdimm); |
Dan Williams | 21083f5 | 2021-06-15 16:36:31 -0700 | [diff] [blame] | 69 | rc = devm_add_action_or_reset(dev, unregister_nvdimm, nvdimm); |
| 70 | out: |
| 71 | device_unlock(&cxl_nvb->dev); |
| 72 | put_device(&cxl_nvb->dev); |
| 73 | |
| 74 | return rc; |
| 75 | } |
| 76 | |
| 77 | static struct cxl_driver cxl_nvdimm_driver = { |
| 78 | .name = "cxl_nvdimm", |
| 79 | .probe = cxl_nvdimm_probe, |
| 80 | .id = CXL_DEVICE_NVDIMM, |
| 81 | }; |
| 82 | |
Ira Weiny | 5e2411a | 2021-11-02 13:29:01 -0700 | [diff] [blame] | 83 | static int cxl_pmem_get_config_size(struct cxl_dev_state *cxlds, |
Dan Williams | 60b8f17 | 2021-09-09 15:08:15 -0700 | [diff] [blame] | 84 | struct nd_cmd_get_config_size *cmd, |
| 85 | unsigned int buf_len) |
| 86 | { |
| 87 | if (sizeof(*cmd) > buf_len) |
| 88 | return -EINVAL; |
| 89 | |
| 90 | *cmd = (struct nd_cmd_get_config_size) { |
Ira Weiny | 5e2411a | 2021-11-02 13:29:01 -0700 | [diff] [blame] | 91 | .config_size = cxlds->lsa_size, |
| 92 | .max_xfer = cxlds->payload_size, |
Dan Williams | 60b8f17 | 2021-09-09 15:08:15 -0700 | [diff] [blame] | 93 | }; |
| 94 | |
| 95 | return 0; |
| 96 | } |
| 97 | |
Ira Weiny | 5e2411a | 2021-11-02 13:29:01 -0700 | [diff] [blame] | 98 | static int cxl_pmem_get_config_data(struct cxl_dev_state *cxlds, |
Dan Williams | 60b8f17 | 2021-09-09 15:08:15 -0700 | [diff] [blame] | 99 | struct nd_cmd_get_config_data_hdr *cmd, |
| 100 | unsigned int buf_len) |
| 101 | { |
Dan Williams | 49be6dd | 2021-09-08 22:13:15 -0700 | [diff] [blame] | 102 | struct cxl_mbox_get_lsa get_lsa; |
Dan Williams | 60b8f17 | 2021-09-09 15:08:15 -0700 | [diff] [blame] | 103 | int rc; |
| 104 | |
| 105 | if (sizeof(*cmd) > buf_len) |
| 106 | return -EINVAL; |
| 107 | if (struct_size(cmd, out_buf, cmd->in_length) > buf_len) |
| 108 | return -EINVAL; |
| 109 | |
| 110 | get_lsa = (struct cxl_mbox_get_lsa) { |
| 111 | .offset = cmd->in_offset, |
| 112 | .length = cmd->in_length, |
| 113 | }; |
| 114 | |
Ira Weiny | 5e2411a | 2021-11-02 13:29:01 -0700 | [diff] [blame] | 115 | rc = cxl_mbox_send_cmd(cxlds, CXL_MBOX_OP_GET_LSA, &get_lsa, |
| 116 | sizeof(get_lsa), cmd->out_buf, cmd->in_length); |
Dan Williams | 60b8f17 | 2021-09-09 15:08:15 -0700 | [diff] [blame] | 117 | cmd->status = 0; |
| 118 | |
| 119 | return rc; |
| 120 | } |
| 121 | |
Ira Weiny | 5e2411a | 2021-11-02 13:29:01 -0700 | [diff] [blame] | 122 | static int cxl_pmem_set_config_data(struct cxl_dev_state *cxlds, |
Dan Williams | 60b8f17 | 2021-09-09 15:08:15 -0700 | [diff] [blame] | 123 | struct nd_cmd_set_config_hdr *cmd, |
| 124 | unsigned int buf_len) |
| 125 | { |
Dan Williams | 49be6dd | 2021-09-08 22:13:15 -0700 | [diff] [blame] | 126 | struct cxl_mbox_set_lsa *set_lsa; |
Dan Williams | 60b8f17 | 2021-09-09 15:08:15 -0700 | [diff] [blame] | 127 | int rc; |
| 128 | |
| 129 | if (sizeof(*cmd) > buf_len) |
| 130 | return -EINVAL; |
| 131 | |
| 132 | /* 4-byte status follows the input data in the payload */ |
| 133 | if (struct_size(cmd, in_buf, cmd->in_length) + 4 > buf_len) |
| 134 | return -EINVAL; |
| 135 | |
| 136 | set_lsa = |
| 137 | kvzalloc(struct_size(set_lsa, data, cmd->in_length), GFP_KERNEL); |
| 138 | if (!set_lsa) |
| 139 | return -ENOMEM; |
| 140 | |
| 141 | *set_lsa = (struct cxl_mbox_set_lsa) { |
| 142 | .offset = cmd->in_offset, |
| 143 | }; |
| 144 | memcpy(set_lsa->data, cmd->in_buf, cmd->in_length); |
| 145 | |
Ira Weiny | 5e2411a | 2021-11-02 13:29:01 -0700 | [diff] [blame] | 146 | rc = cxl_mbox_send_cmd(cxlds, CXL_MBOX_OP_SET_LSA, set_lsa, |
| 147 | struct_size(set_lsa, data, cmd->in_length), |
| 148 | NULL, 0); |
Dan Williams | 60b8f17 | 2021-09-09 15:08:15 -0700 | [diff] [blame] | 149 | |
| 150 | /* |
| 151 | * Set "firmware" status (4-packed bytes at the end of the input |
| 152 | * payload. |
| 153 | */ |
| 154 | put_unaligned(0, (u32 *) &cmd->in_buf[cmd->in_length]); |
| 155 | kvfree(set_lsa); |
| 156 | |
| 157 | return rc; |
| 158 | } |
| 159 | |
| 160 | static int cxl_pmem_nvdimm_ctl(struct nvdimm *nvdimm, unsigned int cmd, |
| 161 | void *buf, unsigned int buf_len) |
| 162 | { |
| 163 | struct cxl_nvdimm *cxl_nvd = nvdimm_provider_data(nvdimm); |
| 164 | unsigned long cmd_mask = nvdimm_cmd_mask(nvdimm); |
| 165 | struct cxl_memdev *cxlmd = cxl_nvd->cxlmd; |
Ira Weiny | 5e2411a | 2021-11-02 13:29:01 -0700 | [diff] [blame] | 166 | struct cxl_dev_state *cxlds = cxlmd->cxlds; |
Dan Williams | 60b8f17 | 2021-09-09 15:08:15 -0700 | [diff] [blame] | 167 | |
| 168 | if (!test_bit(cmd, &cmd_mask)) |
| 169 | return -ENOTTY; |
| 170 | |
| 171 | switch (cmd) { |
| 172 | case ND_CMD_GET_CONFIG_SIZE: |
Ira Weiny | 5e2411a | 2021-11-02 13:29:01 -0700 | [diff] [blame] | 173 | return cxl_pmem_get_config_size(cxlds, buf, buf_len); |
Dan Williams | 60b8f17 | 2021-09-09 15:08:15 -0700 | [diff] [blame] | 174 | case ND_CMD_GET_CONFIG_DATA: |
Ira Weiny | 5e2411a | 2021-11-02 13:29:01 -0700 | [diff] [blame] | 175 | return cxl_pmem_get_config_data(cxlds, buf, buf_len); |
Dan Williams | 60b8f17 | 2021-09-09 15:08:15 -0700 | [diff] [blame] | 176 | case ND_CMD_SET_CONFIG_DATA: |
Ira Weiny | 5e2411a | 2021-11-02 13:29:01 -0700 | [diff] [blame] | 177 | return cxl_pmem_set_config_data(cxlds, buf, buf_len); |
Dan Williams | 60b8f17 | 2021-09-09 15:08:15 -0700 | [diff] [blame] | 178 | default: |
| 179 | return -ENOTTY; |
| 180 | } |
| 181 | } |
| 182 | |
Dan Williams | 8fdcb17 | 2021-06-15 16:18:17 -0700 | [diff] [blame] | 183 | static int cxl_pmem_ctl(struct nvdimm_bus_descriptor *nd_desc, |
| 184 | struct nvdimm *nvdimm, unsigned int cmd, void *buf, |
| 185 | unsigned int buf_len, int *cmd_rc) |
| 186 | { |
Dan Williams | 60b8f17 | 2021-09-09 15:08:15 -0700 | [diff] [blame] | 187 | /* |
| 188 | * No firmware response to translate, let the transport error |
| 189 | * code take precedence. |
| 190 | */ |
| 191 | *cmd_rc = 0; |
| 192 | |
| 193 | if (!nvdimm) |
| 194 | return -ENOTTY; |
| 195 | return cxl_pmem_nvdimm_ctl(nvdimm, cmd, buf, buf_len); |
Dan Williams | 8fdcb17 | 2021-06-15 16:18:17 -0700 | [diff] [blame] | 196 | } |
| 197 | |
| 198 | static bool online_nvdimm_bus(struct cxl_nvdimm_bridge *cxl_nvb) |
| 199 | { |
| 200 | if (cxl_nvb->nvdimm_bus) |
| 201 | return true; |
| 202 | cxl_nvb->nvdimm_bus = |
| 203 | nvdimm_bus_register(&cxl_nvb->dev, &cxl_nvb->nd_desc); |
| 204 | return cxl_nvb->nvdimm_bus != NULL; |
| 205 | } |
| 206 | |
Dan Williams | 21083f5 | 2021-06-15 16:36:31 -0700 | [diff] [blame] | 207 | static int cxl_nvdimm_release_driver(struct device *dev, void *data) |
Dan Williams | 8fdcb17 | 2021-06-15 16:18:17 -0700 | [diff] [blame] | 208 | { |
Dan Williams | 21083f5 | 2021-06-15 16:36:31 -0700 | [diff] [blame] | 209 | if (!is_cxl_nvdimm(dev)) |
| 210 | return 0; |
| 211 | device_release_driver(dev); |
| 212 | return 0; |
| 213 | } |
| 214 | |
| 215 | static void offline_nvdimm_bus(struct nvdimm_bus *nvdimm_bus) |
| 216 | { |
| 217 | if (!nvdimm_bus) |
Dan Williams | 8fdcb17 | 2021-06-15 16:18:17 -0700 | [diff] [blame] | 218 | return; |
Dan Williams | 21083f5 | 2021-06-15 16:36:31 -0700 | [diff] [blame] | 219 | |
| 220 | /* |
| 221 | * Set the state of cxl_nvdimm devices to unbound / idle before |
| 222 | * nvdimm_bus_unregister() rips the nvdimm objects out from |
| 223 | * underneath them. |
| 224 | */ |
| 225 | bus_for_each_dev(&cxl_bus_type, NULL, NULL, cxl_nvdimm_release_driver); |
| 226 | nvdimm_bus_unregister(nvdimm_bus); |
Dan Williams | 8fdcb17 | 2021-06-15 16:18:17 -0700 | [diff] [blame] | 227 | } |
| 228 | |
| 229 | static void cxl_nvb_update_state(struct work_struct *work) |
| 230 | { |
| 231 | struct cxl_nvdimm_bridge *cxl_nvb = |
| 232 | container_of(work, typeof(*cxl_nvb), state_work); |
Dan Williams | 21083f5 | 2021-06-15 16:36:31 -0700 | [diff] [blame] | 233 | struct nvdimm_bus *victim_bus = NULL; |
| 234 | bool release = false, rescan = false; |
Dan Williams | 8fdcb17 | 2021-06-15 16:18:17 -0700 | [diff] [blame] | 235 | |
| 236 | device_lock(&cxl_nvb->dev); |
| 237 | switch (cxl_nvb->state) { |
| 238 | case CXL_NVB_ONLINE: |
| 239 | if (!online_nvdimm_bus(cxl_nvb)) { |
| 240 | dev_err(&cxl_nvb->dev, |
| 241 | "failed to establish nvdimm bus\n"); |
| 242 | release = true; |
Dan Williams | 21083f5 | 2021-06-15 16:36:31 -0700 | [diff] [blame] | 243 | } else |
| 244 | rescan = true; |
Dan Williams | 8fdcb17 | 2021-06-15 16:18:17 -0700 | [diff] [blame] | 245 | break; |
| 246 | case CXL_NVB_OFFLINE: |
| 247 | case CXL_NVB_DEAD: |
Dan Williams | 21083f5 | 2021-06-15 16:36:31 -0700 | [diff] [blame] | 248 | victim_bus = cxl_nvb->nvdimm_bus; |
| 249 | cxl_nvb->nvdimm_bus = NULL; |
Dan Williams | 8fdcb17 | 2021-06-15 16:18:17 -0700 | [diff] [blame] | 250 | break; |
| 251 | default: |
| 252 | break; |
| 253 | } |
| 254 | device_unlock(&cxl_nvb->dev); |
| 255 | |
| 256 | if (release) |
| 257 | device_release_driver(&cxl_nvb->dev); |
Dan Williams | 21083f5 | 2021-06-15 16:36:31 -0700 | [diff] [blame] | 258 | if (rescan) { |
| 259 | int rc = bus_rescan_devices(&cxl_bus_type); |
| 260 | |
| 261 | dev_dbg(&cxl_nvb->dev, "rescan: %d\n", rc); |
| 262 | } |
| 263 | offline_nvdimm_bus(victim_bus); |
Dan Williams | 8fdcb17 | 2021-06-15 16:18:17 -0700 | [diff] [blame] | 264 | |
| 265 | put_device(&cxl_nvb->dev); |
| 266 | } |
| 267 | |
Dan Williams | 08b9e0a | 2021-10-29 12:55:47 -0700 | [diff] [blame] | 268 | static void cxl_nvdimm_bridge_state_work(struct cxl_nvdimm_bridge *cxl_nvb) |
| 269 | { |
| 270 | /* |
| 271 | * Take a reference that the workqueue will drop if new work |
| 272 | * gets queued. |
| 273 | */ |
| 274 | get_device(&cxl_nvb->dev); |
| 275 | if (!queue_work(cxl_pmem_wq, &cxl_nvb->state_work)) |
| 276 | put_device(&cxl_nvb->dev); |
| 277 | } |
| 278 | |
Dan Williams | 8fdcb17 | 2021-06-15 16:18:17 -0700 | [diff] [blame] | 279 | static void cxl_nvdimm_bridge_remove(struct device *dev) |
| 280 | { |
| 281 | struct cxl_nvdimm_bridge *cxl_nvb = to_cxl_nvdimm_bridge(dev); |
| 282 | |
| 283 | if (cxl_nvb->state == CXL_NVB_ONLINE) |
| 284 | cxl_nvb->state = CXL_NVB_OFFLINE; |
Dan Williams | 08b9e0a | 2021-10-29 12:55:47 -0700 | [diff] [blame] | 285 | cxl_nvdimm_bridge_state_work(cxl_nvb); |
Dan Williams | 8fdcb17 | 2021-06-15 16:18:17 -0700 | [diff] [blame] | 286 | } |
| 287 | |
| 288 | static int cxl_nvdimm_bridge_probe(struct device *dev) |
| 289 | { |
| 290 | struct cxl_nvdimm_bridge *cxl_nvb = to_cxl_nvdimm_bridge(dev); |
| 291 | |
| 292 | if (cxl_nvb->state == CXL_NVB_DEAD) |
| 293 | return -ENXIO; |
| 294 | |
| 295 | if (cxl_nvb->state == CXL_NVB_NEW) { |
| 296 | cxl_nvb->nd_desc = (struct nvdimm_bus_descriptor) { |
| 297 | .provider_name = "CXL", |
| 298 | .module = THIS_MODULE, |
| 299 | .ndctl = cxl_pmem_ctl, |
| 300 | }; |
| 301 | |
| 302 | INIT_WORK(&cxl_nvb->state_work, cxl_nvb_update_state); |
| 303 | } |
| 304 | |
| 305 | cxl_nvb->state = CXL_NVB_ONLINE; |
Dan Williams | 08b9e0a | 2021-10-29 12:55:47 -0700 | [diff] [blame] | 306 | cxl_nvdimm_bridge_state_work(cxl_nvb); |
Dan Williams | 8fdcb17 | 2021-06-15 16:18:17 -0700 | [diff] [blame] | 307 | |
| 308 | return 0; |
| 309 | } |
| 310 | |
| 311 | static struct cxl_driver cxl_nvdimm_bridge_driver = { |
| 312 | .name = "cxl_nvdimm_bridge", |
| 313 | .probe = cxl_nvdimm_bridge_probe, |
| 314 | .remove = cxl_nvdimm_bridge_remove, |
| 315 | .id = CXL_DEVICE_NVDIMM_BRIDGE, |
| 316 | }; |
| 317 | |
Dan Williams | 53989fa | 2021-11-11 10:19:05 -0800 | [diff] [blame] | 318 | /* |
| 319 | * Return all bridges to the CXL_NVB_NEW state to invalidate any |
| 320 | * ->state_work referring to the now destroyed cxl_pmem_wq. |
| 321 | */ |
| 322 | static int cxl_nvdimm_bridge_reset(struct device *dev, void *data) |
| 323 | { |
| 324 | struct cxl_nvdimm_bridge *cxl_nvb; |
| 325 | |
| 326 | if (!is_cxl_nvdimm_bridge(dev)) |
| 327 | return 0; |
| 328 | |
| 329 | cxl_nvb = to_cxl_nvdimm_bridge(dev); |
| 330 | device_lock(dev); |
| 331 | cxl_nvb->state = CXL_NVB_NEW; |
| 332 | device_unlock(dev); |
| 333 | |
| 334 | return 0; |
| 335 | } |
| 336 | |
| 337 | static void destroy_cxl_pmem_wq(void) |
| 338 | { |
| 339 | destroy_workqueue(cxl_pmem_wq); |
| 340 | bus_for_each_dev(&cxl_bus_type, NULL, NULL, cxl_nvdimm_bridge_reset); |
| 341 | } |
| 342 | |
Dan Williams | 8fdcb17 | 2021-06-15 16:18:17 -0700 | [diff] [blame] | 343 | static __init int cxl_pmem_init(void) |
| 344 | { |
| 345 | int rc; |
| 346 | |
Dan Williams | 12f3856 | 2021-09-14 12:03:04 -0700 | [diff] [blame] | 347 | set_bit(CXL_MEM_COMMAND_ID_SET_PARTITION_INFO, exclusive_cmds); |
| 348 | set_bit(CXL_MEM_COMMAND_ID_SET_SHUTDOWN_STATE, exclusive_cmds); |
| 349 | set_bit(CXL_MEM_COMMAND_ID_SET_LSA, exclusive_cmds); |
| 350 | |
Dan Williams | 8fdcb17 | 2021-06-15 16:18:17 -0700 | [diff] [blame] | 351 | cxl_pmem_wq = alloc_ordered_workqueue("cxl_pmem", 0); |
| 352 | if (!cxl_pmem_wq) |
| 353 | return -ENXIO; |
| 354 | |
| 355 | rc = cxl_driver_register(&cxl_nvdimm_bridge_driver); |
| 356 | if (rc) |
Dan Williams | 21083f5 | 2021-06-15 16:36:31 -0700 | [diff] [blame] | 357 | goto err_bridge; |
| 358 | |
| 359 | rc = cxl_driver_register(&cxl_nvdimm_driver); |
| 360 | if (rc) |
| 361 | goto err_nvdimm; |
Dan Williams | 8fdcb17 | 2021-06-15 16:18:17 -0700 | [diff] [blame] | 362 | |
| 363 | return 0; |
| 364 | |
Dan Williams | 21083f5 | 2021-06-15 16:36:31 -0700 | [diff] [blame] | 365 | err_nvdimm: |
| 366 | cxl_driver_unregister(&cxl_nvdimm_bridge_driver); |
| 367 | err_bridge: |
Dan Williams | 53989fa | 2021-11-11 10:19:05 -0800 | [diff] [blame] | 368 | destroy_cxl_pmem_wq(); |
Dan Williams | 8fdcb17 | 2021-06-15 16:18:17 -0700 | [diff] [blame] | 369 | return rc; |
| 370 | } |
| 371 | |
| 372 | static __exit void cxl_pmem_exit(void) |
| 373 | { |
Dan Williams | 21083f5 | 2021-06-15 16:36:31 -0700 | [diff] [blame] | 374 | cxl_driver_unregister(&cxl_nvdimm_driver); |
Dan Williams | 8fdcb17 | 2021-06-15 16:18:17 -0700 | [diff] [blame] | 375 | cxl_driver_unregister(&cxl_nvdimm_bridge_driver); |
Dan Williams | 53989fa | 2021-11-11 10:19:05 -0800 | [diff] [blame] | 376 | destroy_cxl_pmem_wq(); |
Dan Williams | 8fdcb17 | 2021-06-15 16:18:17 -0700 | [diff] [blame] | 377 | } |
| 378 | |
| 379 | MODULE_LICENSE("GPL v2"); |
| 380 | module_init(cxl_pmem_init); |
| 381 | module_exit(cxl_pmem_exit); |
| 382 | MODULE_IMPORT_NS(CXL); |
| 383 | MODULE_ALIAS_CXL(CXL_DEVICE_NVDIMM_BRIDGE); |
Dan Williams | 21083f5 | 2021-06-15 16:36:31 -0700 | [diff] [blame] | 384 | MODULE_ALIAS_CXL(CXL_DEVICE_NVDIMM); |