| Mauro Carvalho Chehab | 4d2e26a | 2019-04-10 08:32:42 -0300 | [diff] [blame] | 1 | ========================== |
| Michael Ellerman | ec2adcd | 2018-11-05 20:01:01 +1100 | [diff] [blame] | 2 | CPU to ISA Version Mapping |
| 3 | ========================== |
| 4 | |
| 5 | Mapping of some CPU versions to relevant ISA versions. |
| 6 | |
| Mauro Carvalho Chehab | 4d2e26a | 2019-04-10 08:32:42 -0300 | [diff] [blame] | 7 | ========= ==================================================================== |
| Michael Ellerman | ec2adcd | 2018-11-05 20:01:01 +1100 | [diff] [blame] | 8 | CPU Architecture version |
| Mauro Carvalho Chehab | 4d2e26a | 2019-04-10 08:32:42 -0300 | [diff] [blame] | 9 | ========= ==================================================================== |
| Jordan Niethe | 51a1588 | 2020-08-27 14:05:56 +1000 | [diff] [blame] | 10 | Power10 Power ISA v3.1 |
| Michael Ellerman | ec2adcd | 2018-11-05 20:01:01 +1100 | [diff] [blame] | 11 | Power9 Power ISA v3.0B |
| 12 | Power8 Power ISA v2.07 |
| 13 | Power7 Power ISA v2.06 |
| 14 | Power6 Power ISA v2.05 |
| 15 | PA6T Power ISA v2.04 |
| 16 | Cell PPU - Power ISA v2.02 with some minor exceptions |
| 17 | - Plus Altivec/VMX ~= 2.03 |
| 18 | Power5++ Power ISA v2.04 (no VMX) |
| 19 | Power5+ Power ISA v2.03 |
| 20 | Power5 - PowerPC User Instruction Set Architecture Book I v2.02 |
| 21 | - PowerPC Virtual Environment Architecture Book II v2.02 |
| 22 | - PowerPC Operating Environment Architecture Book III v2.02 |
| 23 | PPC970 - PowerPC User Instruction Set Architecture Book I v2.01 |
| 24 | - PowerPC Virtual Environment Architecture Book II v2.01 |
| 25 | - PowerPC Operating Environment Architecture Book III v2.01 |
| 26 | - Plus Altivec/VMX ~= 2.03 |
| Mauro Carvalho Chehab | 4d2e26a | 2019-04-10 08:32:42 -0300 | [diff] [blame] | 27 | ========= ==================================================================== |
| Michael Ellerman | ec2adcd | 2018-11-05 20:01:01 +1100 | [diff] [blame] | 28 | |
| 29 | |
| 30 | Key Features |
| 31 | ------------ |
| 32 | |
| 33 | ========== ================== |
| 34 | CPU VMX (aka. Altivec) |
| 35 | ========== ================== |
| Jordan Niethe | 51a1588 | 2020-08-27 14:05:56 +1000 | [diff] [blame] | 36 | Power10 Yes |
| Michael Ellerman | ec2adcd | 2018-11-05 20:01:01 +1100 | [diff] [blame] | 37 | Power9 Yes |
| 38 | Power8 Yes |
| 39 | Power7 Yes |
| 40 | Power6 Yes |
| 41 | PA6T Yes |
| 42 | Cell PPU Yes |
| 43 | Power5++ No |
| 44 | Power5+ No |
| 45 | Power5 No |
| 46 | PPC970 Yes |
| 47 | ========== ================== |
| 48 | |
| 49 | ========== ==== |
| 50 | CPU VSX |
| 51 | ========== ==== |
| Jordan Niethe | 51a1588 | 2020-08-27 14:05:56 +1000 | [diff] [blame] | 52 | Power10 Yes |
| Michael Ellerman | ec2adcd | 2018-11-05 20:01:01 +1100 | [diff] [blame] | 53 | Power9 Yes |
| 54 | Power8 Yes |
| 55 | Power7 Yes |
| 56 | Power6 No |
| 57 | PA6T No |
| 58 | Cell PPU No |
| 59 | Power5++ No |
| 60 | Power5+ No |
| 61 | Power5 No |
| 62 | PPC970 No |
| 63 | ========== ==== |
| 64 | |
| Mauro Carvalho Chehab | 4d2e26a | 2019-04-10 08:32:42 -0300 | [diff] [blame] | 65 | ========== ==================================== |
| Michael Ellerman | ec2adcd | 2018-11-05 20:01:01 +1100 | [diff] [blame] | 66 | CPU Transactional Memory |
| Mauro Carvalho Chehab | 4d2e26a | 2019-04-10 08:32:42 -0300 | [diff] [blame] | 67 | ========== ==================================== |
| Jordan Niethe | 51a1588 | 2020-08-27 14:05:56 +1000 | [diff] [blame] | 68 | Power10 No (* see Power ISA v3.1, "Appendix A. Notes on the Removal of Transactional Memory from the Architecture") |
| Michael Ellerman | ec2adcd | 2018-11-05 20:01:01 +1100 | [diff] [blame] | 69 | Power9 Yes (* see transactional_memory.txt) |
| 70 | Power8 Yes |
| 71 | Power7 No |
| 72 | Power6 No |
| 73 | PA6T No |
| 74 | Cell PPU No |
| 75 | Power5++ No |
| 76 | Power5+ No |
| 77 | Power5 No |
| 78 | PPC970 No |
| Mauro Carvalho Chehab | 4d2e26a | 2019-04-10 08:32:42 -0300 | [diff] [blame] | 79 | ========== ==================================== |