blob: 284aae351ff234df64928b28d36a882a31bb2876 [file] [log] [blame]
Greg Kroah-Hartmanb2441312017-11-01 15:07:57 +01001// SPDX-License-Identifier: GPL-2.0
Grant Likely8e267f32011-07-19 17:26:54 -06002/dts-v1/;
3
Laxman Dewangan6bccbd52013-12-02 18:39:57 +05304#include <dt-bindings/input/input.h>
Stephen Warren1bd0bd42012-10-17 16:38:21 -06005#include "tegra20.dtsi"
Grant Likely8e267f32011-07-19 17:26:54 -06006
7/ {
8 model = "NVIDIA Seaboard";
9 compatible = "nvidia,seaboard", "nvidia,tegra20";
10
Stephen Warren553c0a22013-12-09 14:43:59 -070011 aliases {
12 rtc0 = "/i2c@7000d000/tps6586x@34";
13 rtc1 = "/rtc@7000e000";
Olof Johanssonc4574aa2014-11-11 12:49:30 -080014 serial0 = &uartd;
Stephen Warren553c0a22013-12-09 14:43:59 -070015 };
16
Jon Hunterf5bbb322016-02-09 13:51:59 +000017 chosen {
18 stdout-path = "serial0:115200n8";
19 };
20
Grant Likely8e267f32011-07-19 17:26:54 -060021 memory {
Stephen Warren95decf82012-05-11 16:11:38 -060022 reg = <0x00000000 0x40000000>;
Grant Likely8e267f32011-07-19 17:26:54 -060023 };
24
Stephen Warren58ecb232013-11-25 17:53:16 -070025 host1x@50000000 {
Stephen Warren9615d652014-01-07 16:16:32 -070026 dc@54200000 {
27 rgb {
28 status = "okay";
29
30 nvidia,panel = <&panel>;
31 };
32 };
33
Stephen Warren58ecb232013-11-25 17:53:16 -070034 hdmi@54280000 {
Stephen Warrena75191e2013-01-02 14:53:20 -070035 status = "okay";
36
37 vdd-supply = <&hdmi_vdd_reg>;
38 pll-supply = <&hdmi_pll_reg>;
Thierry Reding5264d272015-04-24 11:57:06 +020039 hdmi-supply = <&vdd_hdmi>;
Stephen Warrena75191e2013-01-02 14:53:20 -070040
41 nvidia,ddc-i2c-bus = <&hdmi_ddc>;
Stephen Warren3325f1b2013-02-12 17:25:15 -070042 nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7)
43 GPIO_ACTIVE_HIGH>;
Stephen Warrena75191e2013-01-02 14:53:20 -070044 };
45 };
46
Stephen Warren58ecb232013-11-25 17:53:16 -070047 pinmux@70000014 {
Stephen Warrenecc295b2012-03-15 16:27:36 -060048 pinctrl-names = "default";
49 pinctrl-0 = <&state_default>;
50
51 state_default: pinmux {
52 ata {
53 nvidia,pins = "ata";
54 nvidia,function = "ide";
55 };
56 atb {
57 nvidia,pins = "atb", "gma", "gme";
58 nvidia,function = "sdio4";
59 };
60 atc {
61 nvidia,pins = "atc";
62 nvidia,function = "nand";
63 };
64 atd {
65 nvidia,pins = "atd", "ate", "gmb", "spia",
66 "spib", "spic";
67 nvidia,function = "gmi";
68 };
69 cdev1 {
70 nvidia,pins = "cdev1";
71 nvidia,function = "plla_out";
72 };
73 cdev2 {
74 nvidia,pins = "cdev2";
75 nvidia,function = "pllp_out4";
76 };
77 crtp {
78 nvidia,pins = "crtp", "lm1";
79 nvidia,function = "crt";
80 };
81 csus {
82 nvidia,pins = "csus";
83 nvidia,function = "vi_sensor_clk";
84 };
85 dap1 {
86 nvidia,pins = "dap1";
87 nvidia,function = "dap1";
88 };
89 dap2 {
90 nvidia,pins = "dap2";
91 nvidia,function = "dap2";
92 };
93 dap3 {
94 nvidia,pins = "dap3";
95 nvidia,function = "dap3";
96 };
97 dap4 {
98 nvidia,pins = "dap4";
99 nvidia,function = "dap4";
100 };
Stephen Warrenecc295b2012-03-15 16:27:36 -0600101 dta {
102 nvidia,pins = "dta", "dtb", "dtc", "dtd", "dte";
103 nvidia,function = "vi";
104 };
105 dtf {
106 nvidia,pins = "dtf";
107 nvidia,function = "i2c3";
108 };
109 gmc {
110 nvidia,pins = "gmc";
111 nvidia,function = "uartd";
112 };
113 gmd {
114 nvidia,pins = "gmd";
115 nvidia,function = "sflash";
116 };
117 gpu {
118 nvidia,pins = "gpu";
119 nvidia,function = "pwm";
120 };
121 gpu7 {
122 nvidia,pins = "gpu7";
123 nvidia,function = "rtck";
124 };
125 gpv {
126 nvidia,pins = "gpv", "slxa", "slxk";
127 nvidia,function = "pcie";
128 };
129 hdint {
130 nvidia,pins = "hdint", "lpw0", "lpw2", "lsc1",
Stephen Warren802a8492012-04-26 11:21:54 -0600131 "lsck", "lsda";
Stephen Warrenecc295b2012-03-15 16:27:36 -0600132 nvidia,function = "hdmi";
133 };
134 i2cp {
135 nvidia,pins = "i2cp";
136 nvidia,function = "i2cp";
137 };
138 irrx {
139 nvidia,pins = "irrx", "irtx";
140 nvidia,function = "uartb";
141 };
142 kbca {
143 nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd",
144 "kbce", "kbcf";
145 nvidia,function = "kbc";
146 };
147 lcsn {
148 nvidia,pins = "lcsn", "ldc", "lm0", "lpw1",
149 "lsdi", "lvp0";
150 nvidia,function = "rsvd4";
151 };
152 ld0 {
153 nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4",
154 "ld5", "ld6", "ld7", "ld8", "ld9",
155 "ld10", "ld11", "ld12", "ld13", "ld14",
156 "ld15", "ld16", "ld17", "ldi", "lhp0",
157 "lhp1", "lhp2", "lhs", "lpp", "lsc0",
158 "lspi", "lvp1", "lvs";
159 nvidia,function = "displaya";
160 };
Stephen Warrena18cf6d2012-04-16 17:41:17 -0600161 owc {
162 nvidia,pins = "owc", "spdi", "spdo", "uac";
163 nvidia,function = "rsvd2";
164 };
Stephen Warrenecc295b2012-03-15 16:27:36 -0600165 pmc {
166 nvidia,pins = "pmc";
167 nvidia,function = "pwr_on";
168 };
169 rm {
170 nvidia,pins = "rm";
171 nvidia,function = "i2c1";
172 };
173 sdb {
174 nvidia,pins = "sdb", "sdc", "sdd";
175 nvidia,function = "sdio3";
176 };
177 sdio1 {
178 nvidia,pins = "sdio1";
179 nvidia,function = "sdio1";
180 };
181 slxc {
182 nvidia,pins = "slxc", "slxd";
183 nvidia,function = "spdif";
184 };
185 spid {
186 nvidia,pins = "spid", "spie", "spif";
187 nvidia,function = "spi1";
188 };
189 spig {
190 nvidia,pins = "spig", "spih";
191 nvidia,function = "spi2_alt";
192 };
193 uaa {
194 nvidia,pins = "uaa", "uab", "uda";
195 nvidia,function = "ulpi";
196 };
197 uad {
198 nvidia,pins = "uad";
199 nvidia,function = "irda";
200 };
201 uca {
202 nvidia,pins = "uca", "ucb";
203 nvidia,function = "uartc";
204 };
205 conf_ata {
206 nvidia,pins = "ata", "atb", "atc", "atd",
207 "cdev1", "cdev2", "dap1", "dap2",
Stephen Warrena18cf6d2012-04-16 17:41:17 -0600208 "dap4", "ddc", "dtf", "gma", "gmc", "gmd",
Stephen Warrenecc295b2012-03-15 16:27:36 -0600209 "gme", "gpu", "gpu7", "i2cp", "irrx",
210 "irtx", "pta", "rm", "sdc", "sdd",
211 "slxd", "slxk", "spdi", "spdo", "uac",
212 "uad", "uca", "ucb", "uda";
Laxman Dewanganba4104e2013-12-05 16:14:08 +0530213 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
214 nvidia,tristate = <TEGRA_PIN_DISABLE>;
Stephen Warrenecc295b2012-03-15 16:27:36 -0600215 };
216 conf_ate {
Stephen Warrena18cf6d2012-04-16 17:41:17 -0600217 nvidia,pins = "ate", "csus", "dap3",
Stephen Warrenecc295b2012-03-15 16:27:36 -0600218 "gpv", "owc", "slxc", "spib", "spid",
219 "spie";
Laxman Dewanganba4104e2013-12-05 16:14:08 +0530220 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
221 nvidia,tristate = <TEGRA_PIN_ENABLE>;
Stephen Warrenecc295b2012-03-15 16:27:36 -0600222 };
223 conf_ck32 {
224 nvidia,pins = "ck32", "ddrc", "pmca", "pmcb",
225 "pmcc", "pmcd", "pmce", "xm2c", "xm2d";
Laxman Dewanganba4104e2013-12-05 16:14:08 +0530226 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
Stephen Warrenecc295b2012-03-15 16:27:36 -0600227 };
228 conf_crtp {
229 nvidia,pins = "crtp", "gmb", "slxa", "spia",
230 "spig", "spih";
Laxman Dewanganba4104e2013-12-05 16:14:08 +0530231 nvidia,pull = <TEGRA_PIN_PULL_UP>;
232 nvidia,tristate = <TEGRA_PIN_ENABLE>;
Stephen Warrenecc295b2012-03-15 16:27:36 -0600233 };
234 conf_dta {
235 nvidia,pins = "dta", "dtb", "dtc", "dtd";
Laxman Dewanganba4104e2013-12-05 16:14:08 +0530236 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
237 nvidia,tristate = <TEGRA_PIN_DISABLE>;
Stephen Warrenecc295b2012-03-15 16:27:36 -0600238 };
239 conf_dte {
240 nvidia,pins = "dte", "spif";
Laxman Dewanganba4104e2013-12-05 16:14:08 +0530241 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
242 nvidia,tristate = <TEGRA_PIN_ENABLE>;
Stephen Warrenecc295b2012-03-15 16:27:36 -0600243 };
244 conf_hdint {
245 nvidia,pins = "hdint", "lcsn", "ldc", "lm1",
246 "lpw1", "lsc1", "lsck", "lsda", "lsdi",
247 "lvp0";
Laxman Dewanganba4104e2013-12-05 16:14:08 +0530248 nvidia,tristate = <TEGRA_PIN_ENABLE>;
Stephen Warrenecc295b2012-03-15 16:27:36 -0600249 };
250 conf_kbca {
251 nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd",
252 "kbce", "kbcf", "sdio1", "spic", "uaa",
253 "uab";
Laxman Dewanganba4104e2013-12-05 16:14:08 +0530254 nvidia,pull = <TEGRA_PIN_PULL_UP>;
255 nvidia,tristate = <TEGRA_PIN_DISABLE>;
Stephen Warrenecc295b2012-03-15 16:27:36 -0600256 };
257 conf_lc {
258 nvidia,pins = "lc", "ls";
Laxman Dewanganba4104e2013-12-05 16:14:08 +0530259 nvidia,pull = <TEGRA_PIN_PULL_UP>;
Stephen Warrenecc295b2012-03-15 16:27:36 -0600260 };
261 conf_ld0 {
262 nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4",
263 "ld5", "ld6", "ld7", "ld8", "ld9",
264 "ld10", "ld11", "ld12", "ld13", "ld14",
265 "ld15", "ld16", "ld17", "ldi", "lhp0",
266 "lhp1", "lhp2", "lhs", "lm0", "lpp",
267 "lpw0", "lpw2", "lsc0", "lspi", "lvp1",
268 "lvs", "pmc", "sdb";
Laxman Dewanganba4104e2013-12-05 16:14:08 +0530269 nvidia,tristate = <TEGRA_PIN_DISABLE>;
Stephen Warrenecc295b2012-03-15 16:27:36 -0600270 };
271 conf_ld17_0 {
272 nvidia,pins = "ld17_0", "ld19_18", "ld21_20",
273 "ld23_22";
Laxman Dewanganba4104e2013-12-05 16:14:08 +0530274 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
Stephen Warrenecc295b2012-03-15 16:27:36 -0600275 };
276 drive_sdio1 {
277 nvidia,pins = "drive_sdio1";
Laxman Dewanganba4104e2013-12-05 16:14:08 +0530278 nvidia,high-speed-mode = <TEGRA_PIN_DISABLE>;
279 nvidia,schmitt = <TEGRA_PIN_DISABLE>;
280 nvidia,low-power-mode = <TEGRA_PIN_LP_DRIVE_DIV_1>;
Stephen Warrenecc295b2012-03-15 16:27:36 -0600281 nvidia,pull-down-strength = <31>;
282 nvidia,pull-up-strength = <31>;
Laxman Dewanganba4104e2013-12-05 16:14:08 +0530283 nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_SLOWEST>;
284 nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_SLOWEST>;
Stephen Warrenecc295b2012-03-15 16:27:36 -0600285 };
286 };
Stephen Warrena18cf6d2012-04-16 17:41:17 -0600287
288 state_i2cmux_ddc: pinmux_i2cmux_ddc {
289 ddc {
290 nvidia,pins = "ddc";
291 nvidia,function = "i2c2";
292 };
293 pta {
294 nvidia,pins = "pta";
295 nvidia,function = "rsvd4";
296 };
297 };
298
299 state_i2cmux_pta: pinmux_i2cmux_pta {
300 ddc {
301 nvidia,pins = "ddc";
302 nvidia,function = "rsvd4";
303 };
304 pta {
305 nvidia,pins = "pta";
306 nvidia,function = "i2c2";
307 };
308 };
309
310 state_i2cmux_idle: pinmux_i2cmux_idle {
311 ddc {
312 nvidia,pins = "ddc";
313 nvidia,function = "rsvd4";
314 };
315 pta {
316 nvidia,pins = "pta";
317 nvidia,function = "rsvd4";
318 };
319 };
Stephen Warrenecc295b2012-03-15 16:27:36 -0600320 };
321
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600322 i2s@70002800 {
323 status = "okay";
Stephen Warrenc04abb32012-05-11 17:03:26 -0600324 };
325
326 serial@70006300 {
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600327 status = "okay";
Stephen Warrenc04abb32012-05-11 17:03:26 -0600328 };
329
Stephen Warren9615d652014-01-07 16:16:32 -0700330 pwm: pwm@7000a000 {
331 status = "okay";
332 };
333
Stephen Warren88950f3b2011-11-21 14:44:09 -0700334 i2c@7000c000 {
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600335 status = "okay";
Stephen Warren88950f3b2011-11-21 14:44:09 -0700336 clock-frequency = <400000>;
Stephen Warren797acf72012-01-11 16:09:57 -0700337
338 wm8903: wm8903@1a {
339 compatible = "wlf,wm8903";
340 reg = <0x1a>;
341 interrupt-parent = <&gpio>;
Stephen Warren6cecf912013-02-13 12:51:51 -0700342 interrupts = <TEGRA_GPIO(X, 3) IRQ_TYPE_LEVEL_HIGH>;
Stephen Warren797acf72012-01-11 16:09:57 -0700343
344 gpio-controller;
345 #gpio-cells = <2>;
346
347 micdet-cfg = <0>;
348 micdet-delay = <100>;
Stephen Warren95decf82012-05-11 16:11:38 -0600349 gpio-cfg = <0xffffffff 0xffffffff 0 0xffffffff 0xffffffff>;
Stephen Warren797acf72012-01-11 16:09:57 -0700350 };
Laxman Dewanganb46b0b52012-04-23 17:41:36 +0530351
352 /* ALS and proximity sensor */
353 isl29018@44 {
354 compatible = "isil,isl29018";
355 reg = <0x44>;
356 interrupt-parent = <&gpio>;
Stephen Warren6cecf912013-02-13 12:51:51 -0700357 interrupts = <TEGRA_GPIO(Z, 2) IRQ_TYPE_LEVEL_HIGH>;
Laxman Dewanganb46b0b52012-04-23 17:41:36 +0530358 };
Olof Johansson45dbe9d2011-12-22 16:33:13 +0000359
360 gyrometer@68 {
361 compatible = "invn,mpu3050";
362 reg = <0x68>;
363 interrupt-parent = <&gpio>;
Stephen Warren6cecf912013-02-13 12:51:51 -0700364 interrupts = <TEGRA_GPIO(Z, 4) IRQ_TYPE_LEVEL_HIGH>;
Olof Johansson45dbe9d2011-12-22 16:33:13 +0000365 };
Stephen Warren88950f3b2011-11-21 14:44:09 -0700366 };
367
368 i2c@7000c400 {
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600369 status = "okay";
Stephen Warren22bd1f72012-04-26 11:19:03 -0600370 clock-frequency = <100000>;
Stephen Warren88950f3b2011-11-21 14:44:09 -0700371 };
372
Stephen Warrena18cf6d2012-04-16 17:41:17 -0600373 i2cmux {
374 compatible = "i2c-mux-pinctrl";
375 #address-cells = <1>;
376 #size-cells = <0>;
377
378 i2c-parent = <&{/i2c@7000c400}>;
379
380 pinctrl-names = "ddc", "pta", "idle";
381 pinctrl-0 = <&state_i2cmux_ddc>;
382 pinctrl-1 = <&state_i2cmux_pta>;
383 pinctrl-2 = <&state_i2cmux_idle>;
384
Stephen Warrena75191e2013-01-02 14:53:20 -0700385 hdmi_ddc: i2c@0 {
Stephen Warrena18cf6d2012-04-16 17:41:17 -0600386 reg = <0>;
387 #address-cells = <1>;
388 #size-cells = <0>;
389 };
390
Stephen Warren9615d652014-01-07 16:16:32 -0700391 lvds_ddc: i2c@1 {
Stephen Warrena18cf6d2012-04-16 17:41:17 -0600392 reg = <1>;
393 #address-cells = <1>;
394 #size-cells = <0>;
Stephen Warren0879c5f2012-04-25 16:57:28 -0600395
396 smart-battery@b {
397 compatible = "ti,bq20z75", "smart-battery-1.1";
398 reg = <0xb>;
399 ti,i2c-retry-count = <2>;
400 ti,poll-retry-count = <10>;
401 };
Stephen Warrena18cf6d2012-04-16 17:41:17 -0600402 };
403 };
404
Stephen Warren88950f3b2011-11-21 14:44:09 -0700405 i2c@7000c500 {
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600406 status = "okay";
Stephen Warren88950f3b2011-11-21 14:44:09 -0700407 clock-frequency = <400000>;
408 };
409
410 i2c@7000d000 {
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600411 status = "okay";
Stephen Warren88950f3b2011-11-21 14:44:09 -0700412 clock-frequency = <400000>;
Stephen Warren401c9a52011-12-17 23:29:32 -0700413
Stephen Warren57899052013-11-26 14:43:45 -0700414 magnetometer@c {
Kuninori Morimoto7c7a9b32014-12-25 03:55:52 +0000415 compatible = "asahi-kasei,ak8975";
Stephen Warren57899052013-11-26 14:43:45 -0700416 reg = <0xc>;
417 interrupt-parent = <&gpio>;
418 interrupts = <TEGRA_GPIO(N, 5) IRQ_TYPE_LEVEL_HIGH>;
419 };
420
Stephen Warren6529e632012-06-20 15:58:34 -0600421 pmic: tps6586x@34 {
422 compatible = "ti,tps6586x";
423 reg = <0x34>;
Stephen Warren6cecf912013-02-13 12:51:51 -0700424 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
Stephen Warren6529e632012-06-20 15:58:34 -0600425
Stephen Warren44b12ef2012-09-11 11:42:26 -0600426 ti,system-power-controller;
427
Stephen Warren6529e632012-06-20 15:58:34 -0600428 #gpio-cells = <2>;
429 gpio-controller;
430
431 sys-supply = <&vdd_5v0_reg>;
432 vin-sm0-supply = <&sys_reg>;
433 vin-sm1-supply = <&sys_reg>;
434 vin-sm2-supply = <&sys_reg>;
435 vinldo01-supply = <&sm2_reg>;
436 vinldo23-supply = <&sm2_reg>;
437 vinldo4-supply = <&sm2_reg>;
438 vinldo678-supply = <&sm2_reg>;
439 vinldo9-supply = <&sm2_reg>;
440
441 regulators {
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600442 sys_reg: sys {
Stephen Warren6529e632012-06-20 15:58:34 -0600443 regulator-name = "vdd_sys";
444 regulator-always-on;
445 };
446
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600447 sm0 {
Stephen Warren6529e632012-06-20 15:58:34 -0600448 regulator-name = "vdd_sm0,vdd_core";
449 regulator-min-microvolt = <1300000>;
450 regulator-max-microvolt = <1300000>;
451 regulator-always-on;
452 };
453
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600454 sm1 {
Stephen Warren6529e632012-06-20 15:58:34 -0600455 regulator-name = "vdd_sm1,vdd_cpu";
456 regulator-min-microvolt = <1125000>;
457 regulator-max-microvolt = <1125000>;
458 regulator-always-on;
459 };
460
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600461 sm2_reg: sm2 {
Stephen Warren6529e632012-06-20 15:58:34 -0600462 regulator-name = "vdd_sm2,vin_ldo*";
463 regulator-min-microvolt = <3700000>;
464 regulator-max-microvolt = <3700000>;
465 regulator-always-on;
466 };
467
468 /* LDO0 is not connected to anything */
469
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600470 ldo1 {
Stephen Warren6529e632012-06-20 15:58:34 -0600471 regulator-name = "vdd_ldo1,avdd_pll*";
472 regulator-min-microvolt = <1100000>;
473 regulator-max-microvolt = <1100000>;
474 regulator-always-on;
475 };
476
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600477 ldo2 {
Stephen Warren6529e632012-06-20 15:58:34 -0600478 regulator-name = "vdd_ldo2,vdd_rtc";
479 regulator-min-microvolt = <1200000>;
480 regulator-max-microvolt = <1200000>;
481 };
482
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600483 ldo3 {
Stephen Warren6529e632012-06-20 15:58:34 -0600484 regulator-name = "vdd_ldo3,avdd_usb*";
485 regulator-min-microvolt = <3300000>;
486 regulator-max-microvolt = <3300000>;
487 regulator-always-on;
488 };
489
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600490 ldo4 {
Stephen Warren6529e632012-06-20 15:58:34 -0600491 regulator-name = "vdd_ldo4,avdd_osc,vddio_sys";
492 regulator-min-microvolt = <1800000>;
493 regulator-max-microvolt = <1800000>;
494 regulator-always-on;
495 };
496
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600497 ldo5 {
Stephen Warren6529e632012-06-20 15:58:34 -0600498 regulator-name = "vdd_ldo5,vcore_mmc";
499 regulator-min-microvolt = <2850000>;
500 regulator-max-microvolt = <2850000>;
501 regulator-always-on;
502 };
503
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600504 ldo6 {
Stephen Warren6529e632012-06-20 15:58:34 -0600505 regulator-name = "vdd_ldo6,avdd_vdac,vddio_vi,vddio_cam";
506 regulator-min-microvolt = <1800000>;
507 regulator-max-microvolt = <1800000>;
508 };
509
Stephen Warrena75191e2013-01-02 14:53:20 -0700510 hdmi_vdd_reg: ldo7 {
Stephen Warren6529e632012-06-20 15:58:34 -0600511 regulator-name = "vdd_ldo7,avdd_hdmi,vdd_fuse";
512 regulator-min-microvolt = <3300000>;
513 regulator-max-microvolt = <3300000>;
514 };
515
Stephen Warrena75191e2013-01-02 14:53:20 -0700516 hdmi_pll_reg: ldo8 {
Stephen Warren6529e632012-06-20 15:58:34 -0600517 regulator-name = "vdd_ldo8,avdd_hdmi_pll";
518 regulator-min-microvolt = <1800000>;
519 regulator-max-microvolt = <1800000>;
520 };
521
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600522 ldo9 {
Stephen Warren6529e632012-06-20 15:58:34 -0600523 regulator-name = "vdd_ldo9,avdd_2v85,vdd_ddr_rx";
524 regulator-min-microvolt = <2850000>;
525 regulator-max-microvolt = <2850000>;
526 regulator-always-on;
527 };
528
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600529 ldo_rtc {
Stephen Warren6529e632012-06-20 15:58:34 -0600530 regulator-name = "vdd_rtc_out,vdd_cell";
531 regulator-min-microvolt = <3300000>;
532 regulator-max-microvolt = <3300000>;
533 regulator-always-on;
534 };
535 };
536 };
537
Olof Johansson45dbe9d2011-12-22 16:33:13 +0000538 temperature-sensor@4c {
Stephen Warren98462102012-11-19 15:34:44 -0700539 compatible = "onnn,nct1008";
Stephen Warren401c9a52011-12-17 23:29:32 -0700540 reg = <0x4c>;
541 };
Stephen Warrenc04abb32012-05-11 17:03:26 -0600542 };
543
Stephen Warren58ecb232013-11-25 17:53:16 -0700544 kbc@7000e200 {
Laxman Dewanganbeb0e322013-01-15 12:54:49 +0530545 status = "okay";
546 nvidia,debounce-delay-ms = <32>;
547 nvidia,repeat-delay-ms = <160>;
548 nvidia,ghost-filter;
549 nvidia,kbc-row-pins = <0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15>;
550 nvidia,kbc-col-pins = <16 17 18 19 20 21 22 23>;
Laxman Dewangan6bccbd52013-12-02 18:39:57 +0530551 linux,keymap = <MATRIX_KEY(0x00, 0x02, KEY_W)
552 MATRIX_KEY(0x00, 0x03, KEY_S)
553 MATRIX_KEY(0x00, 0x04, KEY_A)
554 MATRIX_KEY(0x00, 0x05, KEY_Z)
555 MATRIX_KEY(0x00, 0x07, KEY_FN)
Laxman Dewanganbeb0e322013-01-15 12:54:49 +0530556
Laxman Dewangan6bccbd52013-12-02 18:39:57 +0530557 MATRIX_KEY(0x01, 0x07, KEY_LEFTMETA)
558 MATRIX_KEY(0x02, 0x06, KEY_RIGHTALT)
559 MATRIX_KEY(0x02, 0x07, KEY_LEFTALT)
Laxman Dewanganbeb0e322013-01-15 12:54:49 +0530560
Laxman Dewangan6bccbd52013-12-02 18:39:57 +0530561 MATRIX_KEY(0x03, 0x00, KEY_5)
562 MATRIX_KEY(0x03, 0x01, KEY_4)
563 MATRIX_KEY(0x03, 0x02, KEY_R)
564 MATRIX_KEY(0x03, 0x03, KEY_E)
565 MATRIX_KEY(0x03, 0x04, KEY_F)
566 MATRIX_KEY(0x03, 0x05, KEY_D)
567 MATRIX_KEY(0x03, 0x06, KEY_X)
Laxman Dewanganbeb0e322013-01-15 12:54:49 +0530568
Laxman Dewangan6bccbd52013-12-02 18:39:57 +0530569 MATRIX_KEY(0x04, 0x00, KEY_7)
570 MATRIX_KEY(0x04, 0x01, KEY_6)
571 MATRIX_KEY(0x04, 0x02, KEY_T)
572 MATRIX_KEY(0x04, 0x03, KEY_H)
573 MATRIX_KEY(0x04, 0x04, KEY_G)
574 MATRIX_KEY(0x04, 0x05, KEY_V)
575 MATRIX_KEY(0x04, 0x06, KEY_C)
576 MATRIX_KEY(0x04, 0x07, KEY_SPACE)
Laxman Dewanganbeb0e322013-01-15 12:54:49 +0530577
Laxman Dewangan6bccbd52013-12-02 18:39:57 +0530578 MATRIX_KEY(0x05, 0x00, KEY_9)
579 MATRIX_KEY(0x05, 0x01, KEY_8)
580 MATRIX_KEY(0x05, 0x02, KEY_U)
581 MATRIX_KEY(0x05, 0x03, KEY_Y)
582 MATRIX_KEY(0x05, 0x04, KEY_J)
583 MATRIX_KEY(0x05, 0x05, KEY_N)
584 MATRIX_KEY(0x05, 0x06, KEY_B)
585 MATRIX_KEY(0x05, 0x07, KEY_BACKSLASH)
Laxman Dewanganbeb0e322013-01-15 12:54:49 +0530586
Laxman Dewangan6bccbd52013-12-02 18:39:57 +0530587 MATRIX_KEY(0x06, 0x00, KEY_MINUS)
588 MATRIX_KEY(0x06, 0x01, KEY_0)
589 MATRIX_KEY(0x06, 0x02, KEY_O)
590 MATRIX_KEY(0x06, 0x03, KEY_I)
591 MATRIX_KEY(0x06, 0x04, KEY_L)
592 MATRIX_KEY(0x06, 0x05, KEY_K)
593 MATRIX_KEY(0x06, 0x06, KEY_COMMA)
594 MATRIX_KEY(0x06, 0x07, KEY_M)
Laxman Dewanganbeb0e322013-01-15 12:54:49 +0530595
Laxman Dewangan6bccbd52013-12-02 18:39:57 +0530596 MATRIX_KEY(0x07, 0x01, KEY_EQUAL)
597 MATRIX_KEY(0x07, 0x02, KEY_RIGHTBRACE)
598 MATRIX_KEY(0x07, 0x03, KEY_ENTER)
599 MATRIX_KEY(0x07, 0x07, KEY_MENU)
Laxman Dewanganbeb0e322013-01-15 12:54:49 +0530600
Laxman Dewangan6bccbd52013-12-02 18:39:57 +0530601 MATRIX_KEY(0x08, 0x04, KEY_RIGHTSHIFT)
602 MATRIX_KEY(0x08, 0x05, KEY_LEFTSHIFT)
Laxman Dewanganbeb0e322013-01-15 12:54:49 +0530603
Laxman Dewangan6bccbd52013-12-02 18:39:57 +0530604 MATRIX_KEY(0x09, 0x05, KEY_RIGHTCTRL)
605 MATRIX_KEY(0x09, 0x07, KEY_LEFTCTRL)
Laxman Dewanganbeb0e322013-01-15 12:54:49 +0530606
Laxman Dewangan6bccbd52013-12-02 18:39:57 +0530607 MATRIX_KEY(0x0B, 0x00, KEY_LEFTBRACE)
608 MATRIX_KEY(0x0B, 0x01, KEY_P)
609 MATRIX_KEY(0x0B, 0x02, KEY_APOSTROPHE)
610 MATRIX_KEY(0x0B, 0x03, KEY_SEMICOLON)
611 MATRIX_KEY(0x0B, 0x04, KEY_SLASH)
612 MATRIX_KEY(0x0B, 0x05, KEY_DOT)
Laxman Dewanganbeb0e322013-01-15 12:54:49 +0530613
Laxman Dewangan6bccbd52013-12-02 18:39:57 +0530614 MATRIX_KEY(0x0C, 0x00, KEY_F10)
615 MATRIX_KEY(0x0C, 0x01, KEY_F9)
616 MATRIX_KEY(0x0C, 0x02, KEY_BACKSPACE)
617 MATRIX_KEY(0x0C, 0x03, KEY_3)
618 MATRIX_KEY(0x0C, 0x04, KEY_2)
619 MATRIX_KEY(0x0C, 0x05, KEY_UP)
620 MATRIX_KEY(0x0C, 0x06, KEY_PRINT)
621 MATRIX_KEY(0x0C, 0x07, KEY_PAUSE)
Laxman Dewanganbeb0e322013-01-15 12:54:49 +0530622
Laxman Dewangan6bccbd52013-12-02 18:39:57 +0530623 MATRIX_KEY(0x0D, 0x00, KEY_INSERT)
624 MATRIX_KEY(0x0D, 0x01, KEY_DELETE)
625 MATRIX_KEY(0x0D, 0x03, KEY_PAGEUP )
626 MATRIX_KEY(0x0D, 0x04, KEY_PAGEDOWN)
627 MATRIX_KEY(0x0D, 0x05, KEY_RIGHT)
628 MATRIX_KEY(0x0D, 0x06, KEY_DOWN)
629 MATRIX_KEY(0x0D, 0x07, KEY_LEFT)
Laxman Dewanganbeb0e322013-01-15 12:54:49 +0530630
Laxman Dewangan6bccbd52013-12-02 18:39:57 +0530631 MATRIX_KEY(0x0E, 0x00, KEY_F11)
632 MATRIX_KEY(0x0E, 0x01, KEY_F12)
633 MATRIX_KEY(0x0E, 0x02, KEY_F8)
634 MATRIX_KEY(0x0E, 0x03, KEY_Q)
635 MATRIX_KEY(0x0E, 0x04, KEY_F4)
636 MATRIX_KEY(0x0E, 0x05, KEY_F3)
637 MATRIX_KEY(0x0E, 0x06, KEY_1)
638 MATRIX_KEY(0x0E, 0x07, KEY_F7)
Laxman Dewanganbeb0e322013-01-15 12:54:49 +0530639
Laxman Dewangan6bccbd52013-12-02 18:39:57 +0530640 MATRIX_KEY(0x0F, 0x00, KEY_ESC)
641 MATRIX_KEY(0x0F, 0x01, KEY_GRAVE)
642 MATRIX_KEY(0x0F, 0x02, KEY_F5)
643 MATRIX_KEY(0x0F, 0x03, KEY_TAB)
644 MATRIX_KEY(0x0F, 0x04, KEY_F1)
645 MATRIX_KEY(0x0F, 0x05, KEY_F2)
646 MATRIX_KEY(0x0F, 0x06, KEY_CAPSLOCK)
647 MATRIX_KEY(0x0F, 0x07, KEY_F6)
Laxman Dewanganbeb0e322013-01-15 12:54:49 +0530648
649 /* Software Handled Function Keys */
Laxman Dewangan6bccbd52013-12-02 18:39:57 +0530650 MATRIX_KEY(0x14, 0x00, KEY_KP7)
Laxman Dewanganbeb0e322013-01-15 12:54:49 +0530651
Laxman Dewangan6bccbd52013-12-02 18:39:57 +0530652 MATRIX_KEY(0x15, 0x00, KEY_KP9)
653 MATRIX_KEY(0x15, 0x01, KEY_KP8)
654 MATRIX_KEY(0x15, 0x02, KEY_KP4)
655 MATRIX_KEY(0x15, 0x04, KEY_KP1)
Laxman Dewanganbeb0e322013-01-15 12:54:49 +0530656
Laxman Dewangan6bccbd52013-12-02 18:39:57 +0530657 MATRIX_KEY(0x16, 0x01, KEY_KPSLASH)
658 MATRIX_KEY(0x16, 0x02, KEY_KP6)
659 MATRIX_KEY(0x16, 0x03, KEY_KP5)
660 MATRIX_KEY(0x16, 0x04, KEY_KP3)
661 MATRIX_KEY(0x16, 0x05, KEY_KP2)
662 MATRIX_KEY(0x16, 0x07, KEY_KP0)
Laxman Dewanganbeb0e322013-01-15 12:54:49 +0530663
Laxman Dewangan6bccbd52013-12-02 18:39:57 +0530664 MATRIX_KEY(0x1B, 0x01, KEY_KPASTERISK)
665 MATRIX_KEY(0x1B, 0x03, KEY_KPMINUS)
666 MATRIX_KEY(0x1B, 0x04, KEY_KPPLUS)
667 MATRIX_KEY(0x1B, 0x05, KEY_KPDOT)
Laxman Dewanganbeb0e322013-01-15 12:54:49 +0530668
Laxman Dewangan6bccbd52013-12-02 18:39:57 +0530669 MATRIX_KEY(0x1C, 0x05, KEY_VOLUMEUP)
Laxman Dewanganbeb0e322013-01-15 12:54:49 +0530670
Laxman Dewangan6bccbd52013-12-02 18:39:57 +0530671 MATRIX_KEY(0x1D, 0x03, KEY_HOME)
672 MATRIX_KEY(0x1D, 0x04, KEY_END)
673 MATRIX_KEY(0x1D, 0x05, KEY_BRIGHTNESSDOWN)
674 MATRIX_KEY(0x1D, 0x06, KEY_VOLUMEDOWN)
675 MATRIX_KEY(0x1D, 0x07, KEY_BRIGHTNESSUP)
Laxman Dewanganbeb0e322013-01-15 12:54:49 +0530676
Laxman Dewangan6bccbd52013-12-02 18:39:57 +0530677 MATRIX_KEY(0x1E, 0x00, KEY_NUMLOCK)
678 MATRIX_KEY(0x1E, 0x01, KEY_SCROLLLOCK)
679 MATRIX_KEY(0x1E, 0x02, KEY_MUTE)
Laxman Dewanganbeb0e322013-01-15 12:54:49 +0530680
Laxman Dewangan6bccbd52013-12-02 18:39:57 +0530681 MATRIX_KEY(0x1F, 0x04, KEY_HELP)>;
Laxman Dewanganbeb0e322013-01-15 12:54:49 +0530682 };
Stephen Warren57899052013-11-26 14:43:45 -0700683
684 pmc@7000e400 {
685 nvidia,invert-interrupt;
686 nvidia,suspend-mode = <1>;
687 nvidia,cpu-pwr-good-time = <5000>;
688 nvidia,cpu-pwr-off-time = <5000>;
689 nvidia,core-pwr-good-time = <3845 3845>;
690 nvidia,core-pwr-off-time = <3875>;
691 nvidia,sys-clock-req-active-high;
692 };
693
694 memory-controller@7000f400 {
695 emc-table@190000 {
696 reg = <190000>;
697 compatible = "nvidia,tegra20-emc-table";
698 clock-frequency = <190000>;
699 nvidia,emc-registers = <0x0000000c 0x00000026
700 0x00000009 0x00000003 0x00000004 0x00000004
701 0x00000002 0x0000000c 0x00000003 0x00000003
702 0x00000002 0x00000001 0x00000004 0x00000005
703 0x00000004 0x00000009 0x0000000d 0x0000059f
704 0x00000000 0x00000003 0x00000003 0x00000003
705 0x00000003 0x00000001 0x0000000b 0x000000c8
706 0x00000003 0x00000007 0x00000004 0x0000000f
707 0x00000002 0x00000000 0x00000000 0x00000002
708 0x00000000 0x00000000 0x00000083 0xa06204ae
709 0x007dc010 0x00000000 0x00000000 0x00000000
710 0x00000000 0x00000000 0x00000000 0x00000000>;
711 };
712
713 emc-table@380000 {
714 reg = <380000>;
715 compatible = "nvidia,tegra20-emc-table";
716 clock-frequency = <380000>;
717 nvidia,emc-registers = <0x00000017 0x0000004b
718 0x00000012 0x00000006 0x00000004 0x00000005
719 0x00000003 0x0000000c 0x00000006 0x00000006
720 0x00000003 0x00000001 0x00000004 0x00000005
721 0x00000004 0x00000009 0x0000000d 0x00000b5f
722 0x00000000 0x00000003 0x00000003 0x00000006
723 0x00000006 0x00000001 0x00000011 0x000000c8
724 0x00000003 0x0000000e 0x00000007 0x0000000f
725 0x00000002 0x00000000 0x00000000 0x00000002
726 0x00000000 0x00000000 0x00000083 0xe044048b
727 0x007d8010 0x00000000 0x00000000 0x00000000
728 0x00000000 0x00000000 0x00000000 0x00000000>;
729 };
730 };
731
732 usb@c5000000 {
733 status = "okay";
734 dr_mode = "otg";
735 };
736
737 usb-phy@c5000000 {
738 status = "okay";
739 vbus-supply = <&vbus_reg>;
740 dr_mode = "otg";
741 };
742
743 usb@c5004000 {
744 status = "okay";
745 nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1)
746 GPIO_ACTIVE_LOW>;
747 };
748
749 usb-phy@c5004000 {
750 status = "okay";
751 nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1)
752 GPIO_ACTIVE_LOW>;
753 };
754
755 usb@c5008000 {
756 status = "okay";
757 };
758
759 usb-phy@c5008000 {
760 status = "okay";
761 };
762
763 sdhci@c8000000 {
764 status = "okay";
765 power-gpios = <&gpio TEGRA_GPIO(K, 6) GPIO_ACTIVE_HIGH>;
766 bus-width = <4>;
767 keep-power-in-suspend;
768 };
769
770 sdhci@c8000400 {
771 status = "okay";
772 cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>;
773 wp-gpios = <&gpio TEGRA_GPIO(H, 1) GPIO_ACTIVE_HIGH>;
774 power-gpios = <&gpio TEGRA_GPIO(I, 6) GPIO_ACTIVE_HIGH>;
775 bus-width = <4>;
776 };
777
778 sdhci@c8000600 {
779 status = "okay";
780 bus-width = <8>;
781 non-removable;
782 };
783
Stephen Warren9615d652014-01-07 16:16:32 -0700784 backlight: backlight {
785 compatible = "pwm-backlight";
786
787 enable-gpios = <&gpio TEGRA_GPIO(D, 4) GPIO_ACTIVE_HIGH>;
788 power-supply = <&vdd_bl_reg>;
789 pwms = <&pwm 2 5000000>;
790
791 brightness-levels = <0 4 8 16 32 64 128 255>;
792 default-brightness-level = <6>;
793 };
794
Stephen Warren57899052013-11-26 14:43:45 -0700795 clocks {
796 compatible = "simple-bus";
797 #address-cells = <1>;
798 #size-cells = <0>;
799
800 clk32k_in: clock@0 {
801 compatible = "fixed-clock";
Thierry Reding4ec2e602016-06-10 18:55:24 +0200802 reg = <0>;
Stephen Warren57899052013-11-26 14:43:45 -0700803 #clock-cells = <0>;
804 clock-frequency = <32768>;
805 };
806 };
807
808 gpio-keys {
809 compatible = "gpio-keys";
810
811 power {
812 label = "Power";
813 gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>;
Laxman Dewangan6bccbd52013-12-02 18:39:57 +0530814 linux,code = <KEY_POWER>;
Sudeep Hollad1c04d32016-02-08 21:55:43 +0000815 wakeup-source;
Stephen Warren57899052013-11-26 14:43:45 -0700816 };
817
818 lid {
819 label = "Lid";
820 gpios = <&gpio TEGRA_GPIO(C, 7) GPIO_ACTIVE_HIGH>;
821 linux,input-type = <5>; /* EV_SW */
822 linux,code = <0>; /* SW_LID */
823 debounce-interval = <1>;
Sudeep Hollad1c04d32016-02-08 21:55:43 +0000824 wakeup-source;
Stephen Warren57899052013-11-26 14:43:45 -0700825 };
826 };
827
Stephen Warren9615d652014-01-07 16:16:32 -0700828 panel: panel {
829 compatible = "chunghwa,claa101wa01a", "simple-panel";
830
831 power-supply = <&vdd_pnl_reg>;
832 enable-gpios = <&gpio TEGRA_GPIO(B, 2) GPIO_ACTIVE_HIGH>;
833
834 backlight = <&backlight>;
835 ddc-i2c-bus = <&lvds_ddc>;
836 };
837
Stephen Warren6529e632012-06-20 15:58:34 -0600838 regulators {
839 compatible = "simple-bus";
840 #address-cells = <1>;
841 #size-cells = <0>;
842
843 vdd_5v0_reg: regulator@0 {
844 compatible = "regulator-fixed";
845 reg = <0>;
846 regulator-name = "vdd_5v0";
847 regulator-min-microvolt = <5000000>;
848 regulator-max-microvolt = <5000000>;
849 regulator-always-on;
850 };
851
852 regulator@1 {
853 compatible = "regulator-fixed";
854 reg = <1>;
855 regulator-name = "vdd_1v5";
856 regulator-min-microvolt = <1500000>;
857 regulator-max-microvolt = <1500000>;
Stephen Warren3325f1b2013-02-12 17:25:15 -0700858 gpio = <&pmic 0 GPIO_ACTIVE_HIGH>;
Stephen Warren6529e632012-06-20 15:58:34 -0600859 };
860
861 regulator@2 {
862 compatible = "regulator-fixed";
863 reg = <2>;
864 regulator-name = "vdd_1v2";
865 regulator-min-microvolt = <1200000>;
866 regulator-max-microvolt = <1200000>;
Stephen Warren3325f1b2013-02-12 17:25:15 -0700867 gpio = <&pmic 1 GPIO_ACTIVE_HIGH>;
Stephen Warren6529e632012-06-20 15:58:34 -0600868 enable-active-high;
869 };
Venu Byravarasu4c94c8b2013-05-16 19:42:57 +0530870
871 vbus_reg: regulator@3 {
872 compatible = "regulator-fixed";
873 reg = <3>;
874 regulator-name = "vdd_vbus_wup1";
875 regulator-min-microvolt = <5000000>;
876 regulator-max-microvolt = <5000000>;
Stephen Warren9f310de2013-07-01 15:07:05 -0600877 enable-active-high;
Stephen Warren23f95ef2013-08-01 12:26:01 -0600878 gpio = <&gpio TEGRA_GPIO(D, 0) 0>;
Stephen Warren30ca2222013-08-20 14:00:13 -0600879 regulator-always-on;
880 regulator-boot-on;
Venu Byravarasu4c94c8b2013-05-16 19:42:57 +0530881 };
Stephen Warren9615d652014-01-07 16:16:32 -0700882
883 vdd_pnl_reg: regulator@4 {
884 compatible = "regulator-fixed";
885 reg = <4>;
886 regulator-name = "vdd_pnl";
887 regulator-min-microvolt = <2800000>;
888 regulator-max-microvolt = <2800000>;
889 gpio = <&gpio TEGRA_GPIO(C, 6) GPIO_ACTIVE_HIGH>;
890 enable-active-high;
891 };
892
893 vdd_bl_reg: regulator@5 {
894 compatible = "regulator-fixed";
895 reg = <5>;
896 regulator-name = "vdd_bl";
897 regulator-min-microvolt = <2800000>;
898 regulator-max-microvolt = <2800000>;
899 gpio = <&gpio TEGRA_GPIO(W, 0) GPIO_ACTIVE_HIGH>;
900 enable-active-high;
901 };
Thierry Reding5264d272015-04-24 11:57:06 +0200902
903 vdd_hdmi: regulator@6 {
904 compatible = "regulator-fixed";
905 reg = <6>;
906 regulator-name = "VDDIO_HDMI";
907 regulator-min-microvolt = <5000000>;
908 regulator-max-microvolt = <5000000>;
909 gpio = <&gpio TEGRA_GPIO(V, 5) GPIO_ACTIVE_HIGH>;
910 enable-active-high;
911 vin-supply = <&vdd_5v0_reg>;
912 };
Stephen Warren6529e632012-06-20 15:58:34 -0600913 };
914
Stephen Warrenc04abb32012-05-11 17:03:26 -0600915 sound {
916 compatible = "nvidia,tegra-audio-wm8903-seaboard",
917 "nvidia,tegra-audio-wm8903";
918 nvidia,model = "NVIDIA Tegra Seaboard";
919
920 nvidia,audio-routing =
921 "Headphone Jack", "HPOUTR",
922 "Headphone Jack", "HPOUTL",
923 "Int Spk", "ROP",
924 "Int Spk", "RON",
925 "Int Spk", "LOP",
926 "Int Spk", "LON",
927 "Mic Jack", "MICBIAS",
928 "IN1R", "Mic Jack";
929
930 nvidia,i2s-controller = <&tegra_i2s1>;
931 nvidia,audio-codec = <&wm8903>;
932
Stephen Warren3325f1b2013-02-12 17:25:15 -0700933 nvidia,spkr-en-gpios = <&wm8903 2 GPIO_ACTIVE_HIGH>;
934 nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(X, 1) GPIO_ACTIVE_HIGH>;
Stephen Warrenf9cd2b32013-03-26 16:45:52 -0600935
Hiroshi Doyu885a8cf2013-05-22 19:45:32 +0300936 clocks = <&tegra_car TEGRA20_CLK_PLL_A>,
937 <&tegra_car TEGRA20_CLK_PLL_A_OUT0>,
938 <&tegra_car TEGRA20_CLK_CDEV1>;
Stephen Warrenf9cd2b32013-03-26 16:45:52 -0600939 clock-names = "pll_a", "pll_a_out0", "mclk";
Stephen Warrenc04abb32012-05-11 17:03:26 -0600940 };
Grant Likely8e267f32011-07-19 17:26:54 -0600941};