Blame - arch/powerpc/include/asm/cputable.h - SHIFTPHONES/mainline/linux

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Kumar Gala	10b35d9	2005-09-23 14:08:58 -0500	[diff] [blame]	1	#ifndef __ASM_POWERPC_CPUTABLE_H
				2	#define __ASM_POWERPC_CPUTABLE_H
				3
Adrian Bunk	d1cdcf2	2008-06-24 03:48:21 +1000	[diff] [blame]	4
				5	#include <asm/asm-compat.h>
Michael Ellerman	c5157e5	2008-06-24 11:32:39 +1000	[diff] [blame]	6	#include <asm/feature-fixups.h>
David Howells	c3617f7	2012-10-09 09:47:26 +0100	[diff] [blame]	7	#include <uapi/asm/cputable.h>
Adrian Bunk	d1cdcf2	2008-06-24 03:48:21 +1000	[diff] [blame]	8
Kumar Gala	10b35d9	2005-09-23 14:08:58 -0500	[diff] [blame]	9	#ifndef __ASSEMBLY__
				10
				11	/* This structure can grow, it's real size is used by head.S code
				12	* via the mkdefs mechanism.
				13	*/
				14	struct cpu_spec;
Kumar Gala	10b35d9	2005-09-23 14:08:58 -0500	[diff] [blame]	15
Kumar Gala	10b35d9	2005-09-23 14:08:58 -0500	[diff] [blame]	16	typedef void (cpu_setup_t)(unsigned long offset, struct cpu_spec spec);
Olof Johansson	f39b7a5	2006-08-11 00:07:08 -0500	[diff] [blame]	17	typedef void (*cpu_restore_t)(void);
Kumar Gala	10b35d9	2005-09-23 14:08:58 -0500	[diff] [blame]	18
Anton Blanchard	32a3399	2006-01-09 15:41:31 +1100	[diff] [blame]	19	enum powerpc_oprofile_type {
Andy Whitcroft	7a45fb1	2006-01-13 12:35:49 +0000	[diff] [blame]	20	PPC_OPROFILE_INVALID = 0,
				21	PPC_OPROFILE_RS64 = 1,
				22	PPC_OPROFILE_POWER4 = 2,
				23	PPC_OPROFILE_G4 = 3,
Andy Fleming	39aef68	2008-02-04 18:27:55 -0600	[diff] [blame]	24	PPC_OPROFILE_FSL_EMB = 4,
Maynard Johnson	18f2190	2006-11-20 18:45:16 +0100	[diff] [blame]	25	PPC_OPROFILE_CELL = 5,
Olof Johansson	25fc530	2007-04-18 16:38:21 +1000	[diff] [blame]	26	PPC_OPROFILE_PA6T = 6,
Anton Blanchard	32a3399	2006-01-09 15:41:31 +1100	[diff] [blame]	27	};
				28
Olof Johansson	1bd2e5a	2007-01-28 21:23:54 -0600	[diff] [blame]	29	enum powerpc_pmc_type {
				30	PPC_PMC_DEFAULT = 0,
				31	PPC_PMC_IBM = 1,
				32	PPC_PMC_PA6T = 2,
Benjamin Herrenschmidt	b950bdd	2008-08-18 14:23:51 +1000	[diff] [blame]	33	PPC_PMC_G4 = 3,
Olof Johansson	1bd2e5a	2007-01-28 21:23:54 -0600	[diff] [blame]	34	};
				35
Benjamin Herrenschmidt	47c0bd1	2007-12-21 15:39:21 +1100	[diff] [blame]	36	struct pt_regs;
				37
				38	extern int machine_check_generic(struct pt_regs *regs);
				39	extern int machine_check_4xx(struct pt_regs *regs);
				40	extern int machine_check_440A(struct pt_regs *regs);
Scott Wood	fe04b11	2010-04-08 00:38:22 -0500	[diff] [blame]	41	extern int machine_check_e500mc(struct pt_regs *regs);
Benjamin Herrenschmidt	47c0bd1	2007-12-21 15:39:21 +1100	[diff] [blame]	42	extern int machine_check_e500(struct pt_regs *regs);
				43	extern int machine_check_e200(struct pt_regs *regs);
Dave Kleikamp	fc5e709	2010-03-05 03:43:18 +0000	[diff] [blame]	44	extern int machine_check_47x(struct pt_regs *regs);
Benjamin Herrenschmidt	47c0bd1	2007-12-21 15:39:21 +1100	[diff] [blame]	45
chenhui zhao	e7affb1	2015-11-20 17:13:58 +0800	[diff] [blame^]	46	extern void cpu_down_flush_e500v2(void);
				47	extern void cpu_down_flush_e500mc(void);
				48	extern void cpu_down_flush_e5500(void);
				49	extern void cpu_down_flush_e6500(void);
				50
Paul Mackerras	87a72f9	2007-10-04 14:18:01 +1000	[diff] [blame]	51	/* NOTE WELL: Update identify_cpu() if fields are added or removed! */
Kumar Gala	10b35d9	2005-09-23 14:08:58 -0500	[diff] [blame]	52	struct cpu_spec {
				53	/* CPU is matched via (PVR & pvr_mask) == pvr_value */
				54	unsigned int pvr_mask;
				55	unsigned int pvr_value;
				56
				57	char *cpu_name;
				58	unsigned long cpu_features; /* Kernel features */
				59	unsigned int cpu_user_features; /* Userland features */
Michael Neuling	2171364	2013-04-17 17:33:11 +0000	[diff] [blame]	60	unsigned int cpu_user_features2; /* Userland features v2 */
Benjamin Herrenschmidt	7c03d65	2008-12-18 19:13:32 +0000	[diff] [blame]	61	unsigned int mmu_features; /* MMU features */
Kumar Gala	10b35d9	2005-09-23 14:08:58 -0500	[diff] [blame]	62
				63	/* cache line sizes */
				64	unsigned int icache_bsize;
				65	unsigned int dcache_bsize;
				66
chenhui zhao	e7affb1	2015-11-20 17:13:58 +0800	[diff] [blame^]	67	/* flush caches inside the current cpu */
				68	void (*cpu_down_flush)(void);
				69
Kumar Gala	10b35d9	2005-09-23 14:08:58 -0500	[diff] [blame]	70	/* number of performance monitor counters */
				71	unsigned int num_pmcs;
Olof Johansson	1bd2e5a	2007-01-28 21:23:54 -0600	[diff] [blame]	72	enum powerpc_pmc_type pmc_type;
Kumar Gala	10b35d9	2005-09-23 14:08:58 -0500	[diff] [blame]	73
				74	/* this is called to initialize various CPU bits like L1 cache,
				75	* BHT, SPD, etc... from head.S before branching to identify_machine
				76	*/
				77	cpu_setup_t cpu_setup;
Olof Johansson	f39b7a5	2006-08-11 00:07:08 -0500	[diff] [blame]	78	/* Used to restore cpu setup on secondary processors and at resume */
				79	cpu_restore_t cpu_restore;
Kumar Gala	10b35d9	2005-09-23 14:08:58 -0500	[diff] [blame]	80
				81	/* Used by oprofile userspace to select the right counters */
				82	char *oprofile_cpu_type;
				83
				84	/* Processor specific oprofile operations */
Anton Blanchard	32a3399	2006-01-09 15:41:31 +1100	[diff] [blame]	85	enum powerpc_oprofile_type oprofile_type;
Paul Mackerras	80f15dc	2006-01-14 10:11:39 +1100	[diff] [blame]	86
Michael Neuling	e78dbc8	2006-06-08 14:42:34 +1000	[diff] [blame]	87	/* Bit locations inside the mmcra change */
				88	unsigned long oprofile_mmcra_sihv;
				89	unsigned long oprofile_mmcra_sipr;
				90
				91	/* Bits to clear during an oprofile exception */
				92	unsigned long oprofile_mmcra_clear;
				93
Paul Mackerras	80f15dc	2006-01-14 10:11:39 +1100	[diff] [blame]	94	/* Name of processor class, for the ELF AT_PLATFORM entry */
				95	char *platform;
Benjamin Herrenschmidt	47c0bd1	2007-12-21 15:39:21 +1100	[diff] [blame]	96
				97	/* Processor specific machine check handling. Return negative
				98	* if the error is fatal, 1 if it was fully recovered and 0 to
				99	* pass up (not CPU originated) */
				100	int (machine_check)(struct pt_regs regs);
Mahesh Salgaonkar	4c70341	2013-10-30 20:04:40 +0530	[diff] [blame]	101
				102	/*
				103	* Processor specific early machine check handler which is
				104	* called in real mode to handle SLB and TLB errors.
				105	*/
				106	long (machine_check_early)(struct pt_regs regs);
				107
Mahesh Salgaonkar	0440705	2013-10-30 20:04:56 +0530	[diff] [blame]	108	/*
				109	* Processor specific routine to flush tlbs.
				110	*/
Mahesh Salgaonkar	45706bb	2014-12-19 08:41:05 +0530	[diff] [blame]	111	void (*flush_tlb)(unsigned int action);
Mahesh Salgaonkar	0440705	2013-10-30 20:04:56 +0530	[diff] [blame]	112
Kumar Gala	10b35d9	2005-09-23 14:08:58 -0500	[diff] [blame]	113	};
				114
Kumar Gala	10b35d9	2005-09-23 14:08:58 -0500	[diff] [blame]	115	extern struct cpu_spec *cur_cpu_spec;
Kumar Gala	10b35d9	2005-09-23 14:08:58 -0500	[diff] [blame]	116
Benjamin Herrenschmidt	42c4aaa	2006-10-24 16:42:40 +1000	[diff] [blame]	117	extern unsigned int __start___ftr_fixup, __stop___ftr_fixup;
				118
Paul Mackerras	974a76f	2006-11-10 20:38:53 +1100	[diff] [blame]	119	extern struct cpu_spec *identify_cpu(unsigned long offset, unsigned int pvr);
Benjamin Herrenschmidt	0909c8c	2006-10-20 11:47:18 +1000	[diff] [blame]	120	extern void do_feature_fixups(unsigned long value, void *fixup_start,
				121	void *fixup_end);
Paul Mackerras	9b6b563	2005-10-06 12:06:20 +1000	[diff] [blame]	122
Nathan Lynch	9115d13	2008-07-16 09:58:51 +1000	[diff] [blame]	123	extern const char *powerpc_base_platform;
				124
Mahesh Salgaonkar	45706bb	2014-12-19 08:41:05 +0530	[diff] [blame]	125	/* TLB flush actions. Used as argument to cpu_spec.flush_tlb() hook */
				126	enum {
				127	TLB_INVAL_SCOPE_GLOBAL = 0, /* invalidate all TLBs */
				128	TLB_INVAL_SCOPE_LPID = 1, /* invalidate TLBs for current LPID */
				129	};
				130
Kumar Gala	10b35d9	2005-09-23 14:08:58 -0500	[diff] [blame]	131	#endif /* __ASSEMBLY__ */
				132
				133	/* CPU kernel features */
				134
				135	/* Retain the 32b definitions all use bottom half of word */
Michael Neuling	cde4d49	2012-12-20 14:06:39 +0000	[diff] [blame]	136	#define CPU_FTR_COHERENT_ICACHE ASM_CONST(0x00000001)
				137	#define CPU_FTR_L2CR ASM_CONST(0x00000002)
				138	#define CPU_FTR_SPEC7450 ASM_CONST(0x00000004)
				139	#define CPU_FTR_ALTIVEC ASM_CONST(0x00000008)
				140	#define CPU_FTR_TAU ASM_CONST(0x00000010)
				141	#define CPU_FTR_CAN_DOZE ASM_CONST(0x00000020)
				142	#define CPU_FTR_USE_TB ASM_CONST(0x00000040)
				143	#define CPU_FTR_L2CSR ASM_CONST(0x00000080)
				144	#define CPU_FTR_601 ASM_CONST(0x00000100)
				145	#define CPU_FTR_DBELL ASM_CONST(0x00000200)
				146	#define CPU_FTR_CAN_NAP ASM_CONST(0x00000400)
				147	#define CPU_FTR_L3CR ASM_CONST(0x00000800)
				148	#define CPU_FTR_L3_DISABLE_NAP ASM_CONST(0x00001000)
				149	#define CPU_FTR_NAP_DISABLE_L2_PR ASM_CONST(0x00002000)
				150	#define CPU_FTR_DUAL_PLL_750FX ASM_CONST(0x00004000)
				151	#define CPU_FTR_NO_DPM ASM_CONST(0x00008000)
				152	#define CPU_FTR_476_DD2 ASM_CONST(0x00010000)
				153	#define CPU_FTR_NEED_COHERENT ASM_CONST(0x00020000)
				154	#define CPU_FTR_NO_BTIC ASM_CONST(0x00040000)
				155	#define CPU_FTR_DEBUG_LVL_EXC ASM_CONST(0x00080000)
				156	#define CPU_FTR_NODSISRALIGN ASM_CONST(0x00100000)
				157	#define CPU_FTR_PPC_LE ASM_CONST(0x00200000)
				158	#define CPU_FTR_REAL_LE ASM_CONST(0x00400000)
				159	#define CPU_FTR_FPU_UNAVAILABLE ASM_CONST(0x00800000)
				160	#define CPU_FTR_UNIFIED_ID_CACHE ASM_CONST(0x01000000)
				161	#define CPU_FTR_SPE ASM_CONST(0x02000000)
				162	#define CPU_FTR_NEED_PAIRED_STWCX ASM_CONST(0x04000000)
				163	#define CPU_FTR_LWSYNC ASM_CONST(0x08000000)
				164	#define CPU_FTR_NOEXECUTE ASM_CONST(0x10000000)
				165	#define CPU_FTR_INDEXED_DCR ASM_CONST(0x20000000)
				166	#define CPU_FTR_EMB_HV ASM_CONST(0x40000000)
Kumar Gala	10b35d9	2005-09-23 14:08:58 -0500	[diff] [blame]	167
Paul Mackerras	3965f8c	2006-06-28 13:50:39 +1000	[diff] [blame]	168	/*
				169	* Add the 64-bit processor unique features in the top half of the word;
				170	* on 32-bit, make the names available but defined to be 0.
				171	*/
Kumar Gala	10b35d9	2005-09-23 14:08:58 -0500	[diff] [blame]	172	#ifdef __powerpc64__
Paul Mackerras	3965f8c	2006-06-28 13:50:39 +1000	[diff] [blame]	173	#define LONG_ASM_CONST(x) ASM_CONST(x)
Kumar Gala	10b35d9	2005-09-23 14:08:58 -0500	[diff] [blame]	174	#else
Paul Mackerras	3965f8c	2006-06-28 13:50:39 +1000	[diff] [blame]	175	#define LONG_ASM_CONST(x) 0
Kumar Gala	10b35d9	2005-09-23 14:08:58 -0500	[diff] [blame]	176	#endif
				177
Michael Neuling	1580b3b	2012-12-20 14:06:40 +0000	[diff] [blame]	178	#define CPU_FTR_HVMODE LONG_ASM_CONST(0x0000000100000000)
				179	#define CPU_FTR_ARCH_201 LONG_ASM_CONST(0x0000000200000000)
				180	#define CPU_FTR_ARCH_206 LONG_ASM_CONST(0x0000000400000000)
Michael Ellerman	1de2bd4	2013-04-30 20:17:02 +0000	[diff] [blame]	181	#define CPU_FTR_ARCH_207S LONG_ASM_CONST(0x0000000800000000)
Michael Neuling	c3ab300	2016-02-19 11:16:24 +1100	[diff] [blame]	182	#define CPU_FTR_ARCH_300 LONG_ASM_CONST(0x0000001000000000)
Michael Neuling	1580b3b	2012-12-20 14:06:40 +0000	[diff] [blame]	183	#define CPU_FTR_MMCRA LONG_ASM_CONST(0x0000002000000000)
				184	#define CPU_FTR_CTRL LONG_ASM_CONST(0x0000004000000000)
				185	#define CPU_FTR_SMT LONG_ASM_CONST(0x0000008000000000)
				186	#define CPU_FTR_PAUSE_ZERO LONG_ASM_CONST(0x0000010000000000)
				187	#define CPU_FTR_PURR LONG_ASM_CONST(0x0000020000000000)
				188	#define CPU_FTR_CELL_TB_BUG LONG_ASM_CONST(0x0000040000000000)
				189	#define CPU_FTR_SPURR LONG_ASM_CONST(0x0000080000000000)
				190	#define CPU_FTR_DSCR LONG_ASM_CONST(0x0000100000000000)
				191	#define CPU_FTR_VSX LONG_ASM_CONST(0x0000200000000000)
				192	#define CPU_FTR_SAO LONG_ASM_CONST(0x0000400000000000)
				193	#define CPU_FTR_CP_USE_DCBTZ LONG_ASM_CONST(0x0000800000000000)
				194	#define CPU_FTR_UNALIGNED_LD_STD LONG_ASM_CONST(0x0001000000000000)
				195	#define CPU_FTR_ASYM_SMT LONG_ASM_CONST(0x0002000000000000)
				196	#define CPU_FTR_STCX_CHECKS_ADDRESS LONG_ASM_CONST(0x0004000000000000)
				197	#define CPU_FTR_POPCNTB LONG_ASM_CONST(0x0008000000000000)
				198	#define CPU_FTR_POPCNTD LONG_ASM_CONST(0x0010000000000000)
				199	#define CPU_FTR_ICSWX LONG_ASM_CONST(0x0020000000000000)
				200	#define CPU_FTR_VMX_COPY LONG_ASM_CONST(0x0040000000000000)
				201	#define CPU_FTR_TM LONG_ASM_CONST(0x0080000000000000)
Michael Ellerman	1de2bd4	2013-04-30 20:17:02 +0000	[diff] [blame]	202	#define CPU_FTR_CFAR LONG_ASM_CONST(0x0100000000000000)
Michael Neuling	1580b3b	2012-12-20 14:06:40 +0000	[diff] [blame]	203	#define CPU_FTR_HAS_PPR LONG_ASM_CONST(0x0200000000000000)
Michael Neuling	79879c1	2012-12-20 14:06:42 +0000	[diff] [blame]	204	#define CPU_FTR_DAWR LONG_ASM_CONST(0x0400000000000000)
Michael Neuling	82a9f16	2013-05-16 20:27:31 +0000	[diff] [blame]	205	#define CPU_FTR_DABRX LONG_ASM_CONST(0x0800000000000000)
Michael Ellerman	68f2f0d	2014-03-14 16:00:28 +1100	[diff] [blame]	206	#define CPU_FTR_PMAO_BUG LONG_ASM_CONST(0x1000000000000000)
Michael Neuling	ce5732a	2016-02-19 11:16:22 +1100	[diff] [blame]	207	#define CPU_FTR_SUBCORE LONG_ASM_CONST(0x2000000000000000)
Paul Mackerras	3965f8c	2006-06-28 13:50:39 +1000	[diff] [blame]	208
Kumar Gala	10b35d9	2005-09-23 14:08:58 -0500	[diff] [blame]	209	#ifndef __ASSEMBLY__
				210
Matt Evans	44ae3ab	2011-04-06 19:48:50 +0000	[diff] [blame]	211	#define CPU_FTR_PPCAS_ARCH_V2 (CPU_FTR_NOEXECUTE \| CPU_FTR_NODSISRALIGN)
				212
Michael Ellerman	13b3d13	2014-07-10 12:29:20 +1000	[diff] [blame]	213	#define MMU_FTR_PPCAS_ARCH_V2 (MMU_FTR_TLBIEL \| MMU_FTR_16M_PAGE)
Kumar Gala	10b35d9	2005-09-23 14:08:58 -0500	[diff] [blame]	214
				215	/* We only set the altivec features if the kernel was compiled with altivec
				216	* support
				217	*/
				218	#ifdef CONFIG_ALTIVEC
				219	#define CPU_FTR_ALTIVEC_COMP CPU_FTR_ALTIVEC
				220	#define PPC_FEATURE_HAS_ALTIVEC_COMP PPC_FEATURE_HAS_ALTIVEC
				221	#else
				222	#define CPU_FTR_ALTIVEC_COMP 0
				223	#define PPC_FEATURE_HAS_ALTIVEC_COMP 0
				224	#endif
				225
Michael Neuling	b962ce9	2008-06-25 14:07:18 +1000	[diff] [blame]	226	/* We only set the VSX features if the kernel was compiled with VSX
				227	* support
				228	*/
				229	#ifdef CONFIG_VSX
				230	#define CPU_FTR_VSX_COMP CPU_FTR_VSX
				231	#define PPC_FEATURE_HAS_VSX_COMP PPC_FEATURE_HAS_VSX
				232	#else
				233	#define CPU_FTR_VSX_COMP 0
				234	#define PPC_FEATURE_HAS_VSX_COMP 0
				235	#endif
				236
Kumar Gala	5e14d21	2007-09-13 01:44:20 -0500	[diff] [blame]	237	/* We only set the spe features if the kernel was compiled with spe
				238	* support
				239	*/
				240	#ifdef CONFIG_SPE
				241	#define CPU_FTR_SPE_COMP CPU_FTR_SPE
				242	#define PPC_FEATURE_HAS_SPE_COMP PPC_FEATURE_HAS_SPE
				243	#define PPC_FEATURE_HAS_EFP_SINGLE_COMP PPC_FEATURE_HAS_EFP_SINGLE
				244	#define PPC_FEATURE_HAS_EFP_DOUBLE_COMP PPC_FEATURE_HAS_EFP_DOUBLE
				245	#else
				246	#define CPU_FTR_SPE_COMP 0
				247	#define PPC_FEATURE_HAS_SPE_COMP 0
				248	#define PPC_FEATURE_HAS_EFP_SINGLE_COMP 0
				249	#define PPC_FEATURE_HAS_EFP_DOUBLE_COMP 0
				250	#endif
				251
Michael Neuling	6a6d541	2013-02-13 16:21:29 +0000	[diff] [blame]	252	/* We only set the TM feature if the kernel was compiled with TM supprt */
				253	#ifdef CONFIG_PPC_TRANSACTIONAL_MEM
Sam bobroff	b4b56f9	2015-06-12 11:06:32 +1000	[diff] [blame]	254	#define CPU_FTR_TM_COMP CPU_FTR_TM
				255	#define PPC_FEATURE2_HTM_COMP PPC_FEATURE2_HTM
				256	#define PPC_FEATURE2_HTM_NOSC_COMP PPC_FEATURE2_HTM_NOSC
Michael Neuling	6a6d541	2013-02-13 16:21:29 +0000	[diff] [blame]	257	#else
Sam bobroff	b4b56f9	2015-06-12 11:06:32 +1000	[diff] [blame]	258	#define CPU_FTR_TM_COMP 0
				259	#define PPC_FEATURE2_HTM_COMP 0
				260	#define PPC_FEATURE2_HTM_NOSC_COMP 0
Michael Neuling	6a6d541	2013-02-13 16:21:29 +0000	[diff] [blame]	261	#endif
				262
Scott Wood	11af119	2007-09-14 15:32:14 -0500	[diff] [blame]	263	/* We need to mark all pages as being coherent if we're SMP or we have a
				264	* 74[45]x and an MPC107 host bridge. Also 83xx and PowerQUICC II
				265	* require it for PCI "streaming/prefetch" to work properly.
Piotr Ziecik	c931092	2009-03-17 09:17:50 -0600	[diff] [blame]	266	* This is also required by 52xx family.
Kumar Gala	10b35d9	2005-09-23 14:08:58 -0500	[diff] [blame]	267	*/
Kumar Gala	1775dbb	2006-02-22 09:46:02 -0600	[diff] [blame]	268	#if defined(CONFIG_SMP) \|\| defined(CONFIG_MPC10X_BRIDGE) \
Piotr Ziecik	c931092	2009-03-17 09:17:50 -0600	[diff] [blame]	269	\|\| defined(CONFIG_PPC_83xx) \|\| defined(CONFIG_8260) \
				270	\|\| defined(CONFIG_PPC_MPC52xx)
Kumar Gala	10b35d9	2005-09-23 14:08:58 -0500	[diff] [blame]	271	#define CPU_FTR_COMMON CPU_FTR_NEED_COHERENT
				272	#else
				273	#define CPU_FTR_COMMON 0
				274	#endif
				275
				276	/* The powersave features NAP & DOZE seems to confuse BDI when
				277	debugging. So if a BDI is used, disable theses
				278	*/
				279	#ifndef CONFIG_BDI_SWITCH
				280	#define CPU_FTR_MAYBE_CAN_DOZE CPU_FTR_CAN_DOZE
				281	#define CPU_FTR_MAYBE_CAN_NAP CPU_FTR_CAN_NAP
				282	#else
				283	#define CPU_FTR_MAYBE_CAN_DOZE 0
				284	#define CPU_FTR_MAYBE_CAN_NAP 0
				285	#endif
				286
Benjamin Herrenschmidt	7c03d65	2008-12-18 19:13:32 +0000	[diff] [blame]	287	#define CPU_FTRS_PPC601 (CPU_FTR_COMMON \| CPU_FTR_601 \| \
David Gibson	4508dc2	2007-06-13 14:52:57 +1000	[diff] [blame]	288	CPU_FTR_COHERENT_ICACHE \| CPU_FTR_UNIFIED_ID_CACHE)
				289	#define CPU_FTRS_603 (CPU_FTR_COMMON \| \
Stephen Rothwell	7c92943	2006-03-23 17:36:59 +1100	[diff] [blame]	290	CPU_FTR_MAYBE_CAN_DOZE \| CPU_FTR_USE_TB \| \
Paul Mackerras	fab5db9	2006-06-07 16:14:40 +1000	[diff] [blame]	291	CPU_FTR_MAYBE_CAN_NAP \| CPU_FTR_PPC_LE)
David Gibson	4508dc2	2007-06-13 14:52:57 +1000	[diff] [blame]	292	#define CPU_FTRS_604 (CPU_FTR_COMMON \| \
Benjamin Herrenschmidt	7c03d65	2008-12-18 19:13:32 +0000	[diff] [blame]	293	CPU_FTR_USE_TB \| CPU_FTR_PPC_LE)
David Gibson	4508dc2	2007-06-13 14:52:57 +1000	[diff] [blame]	294	#define CPU_FTRS_740_NOTAU (CPU_FTR_COMMON \| \
Stephen Rothwell	7c92943	2006-03-23 17:36:59 +1100	[diff] [blame]	295	CPU_FTR_MAYBE_CAN_DOZE \| CPU_FTR_USE_TB \| CPU_FTR_L2CR \| \
Benjamin Herrenschmidt	7c03d65	2008-12-18 19:13:32 +0000	[diff] [blame]	296	CPU_FTR_MAYBE_CAN_NAP \| CPU_FTR_PPC_LE)
David Gibson	4508dc2	2007-06-13 14:52:57 +1000	[diff] [blame]	297	#define CPU_FTRS_740 (CPU_FTR_COMMON \| \
Stephen Rothwell	7c92943	2006-03-23 17:36:59 +1100	[diff] [blame]	298	CPU_FTR_MAYBE_CAN_DOZE \| CPU_FTR_USE_TB \| CPU_FTR_L2CR \| \
Benjamin Herrenschmidt	7c03d65	2008-12-18 19:13:32 +0000	[diff] [blame]	299	CPU_FTR_TAU \| CPU_FTR_MAYBE_CAN_NAP \| \
Paul Mackerras	fab5db9	2006-06-07 16:14:40 +1000	[diff] [blame]	300	CPU_FTR_PPC_LE)
David Gibson	4508dc2	2007-06-13 14:52:57 +1000	[diff] [blame]	301	#define CPU_FTRS_750 (CPU_FTR_COMMON \| \
Stephen Rothwell	7c92943	2006-03-23 17:36:59 +1100	[diff] [blame]	302	CPU_FTR_MAYBE_CAN_DOZE \| CPU_FTR_USE_TB \| CPU_FTR_L2CR \| \
Benjamin Herrenschmidt	7c03d65	2008-12-18 19:13:32 +0000	[diff] [blame]	303	CPU_FTR_TAU \| CPU_FTR_MAYBE_CAN_NAP \| \
Paul Mackerras	fab5db9	2006-06-07 16:14:40 +1000	[diff] [blame]	304	CPU_FTR_PPC_LE)
Benjamin Herrenschmidt	7c03d65	2008-12-18 19:13:32 +0000	[diff] [blame]	305	#define CPU_FTRS_750CL (CPU_FTRS_750)
Josh Boyer	b6f41cc	2007-07-03 02:06:53 +1000	[diff] [blame]	306	#define CPU_FTRS_750FX1 (CPU_FTRS_750 \| CPU_FTR_DUAL_PLL_750FX \| CPU_FTR_NO_DPM)
				307	#define CPU_FTRS_750FX2 (CPU_FTRS_750 \| CPU_FTR_NO_DPM)
Benjamin Herrenschmidt	7c03d65	2008-12-18 19:13:32 +0000	[diff] [blame]	308	#define CPU_FTRS_750FX (CPU_FTRS_750 \| CPU_FTR_DUAL_PLL_750FX)
Josh Boyer	b6f41cc	2007-07-03 02:06:53 +1000	[diff] [blame]	309	#define CPU_FTRS_750GX (CPU_FTRS_750FX)
David Gibson	4508dc2	2007-06-13 14:52:57 +1000	[diff] [blame]	310	#define CPU_FTRS_7400_NOTAU (CPU_FTR_COMMON \| \
Stephen Rothwell	7c92943	2006-03-23 17:36:59 +1100	[diff] [blame]	311	CPU_FTR_MAYBE_CAN_DOZE \| CPU_FTR_USE_TB \| CPU_FTR_L2CR \| \
Benjamin Herrenschmidt	7c03d65	2008-12-18 19:13:32 +0000	[diff] [blame]	312	CPU_FTR_ALTIVEC_COMP \| \
Paul Mackerras	fab5db9	2006-06-07 16:14:40 +1000	[diff] [blame]	313	CPU_FTR_MAYBE_CAN_NAP \| CPU_FTR_PPC_LE)
David Gibson	4508dc2	2007-06-13 14:52:57 +1000	[diff] [blame]	314	#define CPU_FTRS_7400 (CPU_FTR_COMMON \| \
Stephen Rothwell	7c92943	2006-03-23 17:36:59 +1100	[diff] [blame]	315	CPU_FTR_MAYBE_CAN_DOZE \| CPU_FTR_USE_TB \| CPU_FTR_L2CR \| \
Benjamin Herrenschmidt	7c03d65	2008-12-18 19:13:32 +0000	[diff] [blame]	316	CPU_FTR_TAU \| CPU_FTR_ALTIVEC_COMP \| \
Paul Mackerras	fab5db9	2006-06-07 16:14:40 +1000	[diff] [blame]	317	CPU_FTR_MAYBE_CAN_NAP \| CPU_FTR_PPC_LE)
David Gibson	4508dc2	2007-06-13 14:52:57 +1000	[diff] [blame]	318	#define CPU_FTRS_7450_20 (CPU_FTR_COMMON \| \
Stephen Rothwell	7c92943	2006-03-23 17:36:59 +1100	[diff] [blame]	319	CPU_FTR_USE_TB \| CPU_FTR_L2CR \| CPU_FTR_ALTIVEC_COMP \| \
Benjamin Herrenschmidt	7c03d65	2008-12-18 19:13:32 +0000	[diff] [blame]	320	CPU_FTR_L3CR \| CPU_FTR_SPEC7450 \| \
Becky Bruce	b64f87c	2007-11-10 09:17:49 +1100	[diff] [blame]	321	CPU_FTR_NEED_COHERENT \| CPU_FTR_PPC_LE \| CPU_FTR_NEED_PAIRED_STWCX)
David Gibson	4508dc2	2007-06-13 14:52:57 +1000	[diff] [blame]	322	#define CPU_FTRS_7450_21 (CPU_FTR_COMMON \| \
Stephen Rothwell	7c92943	2006-03-23 17:36:59 +1100	[diff] [blame]	323	CPU_FTR_USE_TB \| \
				324	CPU_FTR_MAYBE_CAN_NAP \| CPU_FTR_L2CR \| CPU_FTR_ALTIVEC_COMP \| \
Benjamin Herrenschmidt	7c03d65	2008-12-18 19:13:32 +0000	[diff] [blame]	325	CPU_FTR_L3CR \| CPU_FTR_SPEC7450 \| \
Stephen Rothwell	7c92943	2006-03-23 17:36:59 +1100	[diff] [blame]	326	CPU_FTR_NAP_DISABLE_L2_PR \| CPU_FTR_L3_DISABLE_NAP \| \
Becky Bruce	b64f87c	2007-11-10 09:17:49 +1100	[diff] [blame]	327	CPU_FTR_NEED_COHERENT \| CPU_FTR_PPC_LE \| CPU_FTR_NEED_PAIRED_STWCX)
David Gibson	4508dc2	2007-06-13 14:52:57 +1000	[diff] [blame]	328	#define CPU_FTRS_7450_23 (CPU_FTR_COMMON \| \
Becky Bruce	b64f87c	2007-11-10 09:17:49 +1100	[diff] [blame]	329	CPU_FTR_USE_TB \| CPU_FTR_NEED_PAIRED_STWCX \| \
Stephen Rothwell	7c92943	2006-03-23 17:36:59 +1100	[diff] [blame]	330	CPU_FTR_MAYBE_CAN_NAP \| CPU_FTR_L2CR \| CPU_FTR_ALTIVEC_COMP \| \
Benjamin Herrenschmidt	7c03d65	2008-12-18 19:13:32 +0000	[diff] [blame]	331	CPU_FTR_L3CR \| CPU_FTR_SPEC7450 \| \
Paul Mackerras	fab5db9	2006-06-07 16:14:40 +1000	[diff] [blame]	332	CPU_FTR_NAP_DISABLE_L2_PR \| CPU_FTR_NEED_COHERENT \| CPU_FTR_PPC_LE)
David Gibson	4508dc2	2007-06-13 14:52:57 +1000	[diff] [blame]	333	#define CPU_FTRS_7455_1 (CPU_FTR_COMMON \| \
Becky Bruce	b64f87c	2007-11-10 09:17:49 +1100	[diff] [blame]	334	CPU_FTR_USE_TB \| CPU_FTR_NEED_PAIRED_STWCX \| \
Stephen Rothwell	7c92943	2006-03-23 17:36:59 +1100	[diff] [blame]	335	CPU_FTR_L2CR \| CPU_FTR_ALTIVEC_COMP \| CPU_FTR_L3CR \| \
Benjamin Herrenschmidt	7c03d65	2008-12-18 19:13:32 +0000	[diff] [blame]	336	CPU_FTR_SPEC7450 \| CPU_FTR_NEED_COHERENT \| CPU_FTR_PPC_LE)
David Gibson	4508dc2	2007-06-13 14:52:57 +1000	[diff] [blame]	337	#define CPU_FTRS_7455_20 (CPU_FTR_COMMON \| \
Becky Bruce	b64f87c	2007-11-10 09:17:49 +1100	[diff] [blame]	338	CPU_FTR_USE_TB \| CPU_FTR_NEED_PAIRED_STWCX \| \
Stephen Rothwell	7c92943	2006-03-23 17:36:59 +1100	[diff] [blame]	339	CPU_FTR_MAYBE_CAN_NAP \| CPU_FTR_L2CR \| CPU_FTR_ALTIVEC_COMP \| \
Benjamin Herrenschmidt	7c03d65	2008-12-18 19:13:32 +0000	[diff] [blame]	340	CPU_FTR_L3CR \| CPU_FTR_SPEC7450 \| \
Stephen Rothwell	7c92943	2006-03-23 17:36:59 +1100	[diff] [blame]	341	CPU_FTR_NAP_DISABLE_L2_PR \| CPU_FTR_L3_DISABLE_NAP \| \
Benjamin Herrenschmidt	7c03d65	2008-12-18 19:13:32 +0000	[diff] [blame]	342	CPU_FTR_NEED_COHERENT \| CPU_FTR_PPC_LE)
David Gibson	4508dc2	2007-06-13 14:52:57 +1000	[diff] [blame]	343	#define CPU_FTRS_7455 (CPU_FTR_COMMON \| \
Stephen Rothwell	7c92943	2006-03-23 17:36:59 +1100	[diff] [blame]	344	CPU_FTR_USE_TB \| \
				345	CPU_FTR_MAYBE_CAN_NAP \| CPU_FTR_L2CR \| CPU_FTR_ALTIVEC_COMP \| \
Benjamin Herrenschmidt	7c03d65	2008-12-18 19:13:32 +0000	[diff] [blame]	346	CPU_FTR_L3CR \| CPU_FTR_SPEC7450 \| CPU_FTR_NAP_DISABLE_L2_PR \| \
Becky Bruce	b64f87c	2007-11-10 09:17:49 +1100	[diff] [blame]	347	CPU_FTR_NEED_COHERENT \| CPU_FTR_PPC_LE \| CPU_FTR_NEED_PAIRED_STWCX)
David Gibson	4508dc2	2007-06-13 14:52:57 +1000	[diff] [blame]	348	#define CPU_FTRS_7447_10 (CPU_FTR_COMMON \| \
Stephen Rothwell	7c92943	2006-03-23 17:36:59 +1100	[diff] [blame]	349	CPU_FTR_USE_TB \| \
				350	CPU_FTR_MAYBE_CAN_NAP \| CPU_FTR_L2CR \| CPU_FTR_ALTIVEC_COMP \| \
Benjamin Herrenschmidt	7c03d65	2008-12-18 19:13:32 +0000	[diff] [blame]	351	CPU_FTR_L3CR \| CPU_FTR_SPEC7450 \| CPU_FTR_NAP_DISABLE_L2_PR \| \
Becky Bruce	b64f87c	2007-11-10 09:17:49 +1100	[diff] [blame]	352	CPU_FTR_NEED_COHERENT \| CPU_FTR_NO_BTIC \| CPU_FTR_PPC_LE \| \
				353	CPU_FTR_NEED_PAIRED_STWCX)
David Gibson	4508dc2	2007-06-13 14:52:57 +1000	[diff] [blame]	354	#define CPU_FTRS_7447 (CPU_FTR_COMMON \| \
Stephen Rothwell	7c92943	2006-03-23 17:36:59 +1100	[diff] [blame]	355	CPU_FTR_USE_TB \| \
				356	CPU_FTR_MAYBE_CAN_NAP \| CPU_FTR_L2CR \| CPU_FTR_ALTIVEC_COMP \| \
Benjamin Herrenschmidt	7c03d65	2008-12-18 19:13:32 +0000	[diff] [blame]	357	CPU_FTR_L3CR \| CPU_FTR_SPEC7450 \| CPU_FTR_NAP_DISABLE_L2_PR \| \
Becky Bruce	b64f87c	2007-11-10 09:17:49 +1100	[diff] [blame]	358	CPU_FTR_NEED_COHERENT \| CPU_FTR_PPC_LE \| CPU_FTR_NEED_PAIRED_STWCX)
David Gibson	4508dc2	2007-06-13 14:52:57 +1000	[diff] [blame]	359	#define CPU_FTRS_7447A (CPU_FTR_COMMON \| \
Stephen Rothwell	7c92943	2006-03-23 17:36:59 +1100	[diff] [blame]	360	CPU_FTR_USE_TB \| \
				361	CPU_FTR_MAYBE_CAN_NAP \| CPU_FTR_L2CR \| CPU_FTR_ALTIVEC_COMP \| \
Benjamin Herrenschmidt	7c03d65	2008-12-18 19:13:32 +0000	[diff] [blame]	362	CPU_FTR_SPEC7450 \| CPU_FTR_NAP_DISABLE_L2_PR \| \
Becky Bruce	b64f87c	2007-11-10 09:17:49 +1100	[diff] [blame]	363	CPU_FTR_NEED_COHERENT \| CPU_FTR_PPC_LE \| CPU_FTR_NEED_PAIRED_STWCX)
David Gibson	4508dc2	2007-06-13 14:52:57 +1000	[diff] [blame]	364	#define CPU_FTRS_7448 (CPU_FTR_COMMON \| \
James.Yang	3d37254	2007-05-02 16:34:43 -0500	[diff] [blame]	365	CPU_FTR_USE_TB \| \
				366	CPU_FTR_MAYBE_CAN_NAP \| CPU_FTR_L2CR \| CPU_FTR_ALTIVEC_COMP \| \
Benjamin Herrenschmidt	7c03d65	2008-12-18 19:13:32 +0000	[diff] [blame]	367	CPU_FTR_SPEC7450 \| CPU_FTR_NAP_DISABLE_L2_PR \| \
Becky Bruce	b64f87c	2007-11-10 09:17:49 +1100	[diff] [blame]	368	CPU_FTR_PPC_LE \| CPU_FTR_NEED_PAIRED_STWCX)
David Gibson	4508dc2	2007-06-13 14:52:57 +1000	[diff] [blame]	369	#define CPU_FTRS_82XX (CPU_FTR_COMMON \| \
Stephen Rothwell	7c92943	2006-03-23 17:36:59 +1100	[diff] [blame]	370	CPU_FTR_MAYBE_CAN_DOZE \| CPU_FTR_USE_TB)
Scott Wood	11af119	2007-09-14 15:32:14 -0500	[diff] [blame]	371	#define CPU_FTRS_G2_LE (CPU_FTR_COMMON \| CPU_FTR_MAYBE_CAN_DOZE \| \
Benjamin Herrenschmidt	7c03d65	2008-12-18 19:13:32 +0000	[diff] [blame]	372	CPU_FTR_USE_TB \| CPU_FTR_MAYBE_CAN_NAP)
David Gibson	4508dc2	2007-06-13 14:52:57 +1000	[diff] [blame]	373	#define CPU_FTRS_E300 (CPU_FTR_MAYBE_CAN_DOZE \| \
Benjamin Herrenschmidt	7c03d65	2008-12-18 19:13:32 +0000	[diff] [blame]	374	CPU_FTR_USE_TB \| CPU_FTR_MAYBE_CAN_NAP \| \
Stephen Rothwell	7c92943	2006-03-23 17:36:59 +1100	[diff] [blame]	375	CPU_FTR_COMMON)
David Gibson	4508dc2	2007-06-13 14:52:57 +1000	[diff] [blame]	376	#define CPU_FTRS_E300C2 (CPU_FTR_MAYBE_CAN_DOZE \| \
Benjamin Herrenschmidt	7c03d65	2008-12-18 19:13:32 +0000	[diff] [blame]	377	CPU_FTR_USE_TB \| CPU_FTR_MAYBE_CAN_NAP \| \
Kim Phillips	aa42c69	2006-12-08 02:43:30 -0600	[diff] [blame]	378	CPU_FTR_COMMON \| CPU_FTR_FPU_UNAVAILABLE)
Benjamin Herrenschmidt	7c03d65	2008-12-18 19:13:32 +0000	[diff] [blame]	379	#define CPU_FTRS_CLASSIC32 (CPU_FTR_COMMON \| CPU_FTR_USE_TB)
LEROY Christophe	5b2753f	2015-04-22 12:06:45 +0200	[diff] [blame]	380	#define CPU_FTRS_8XX (CPU_FTR_USE_TB \| CPU_FTR_NOEXECUTE)
Benjamin Herrenschmidt	8309ce72	2008-12-12 17:33:25 +1100	[diff] [blame]	381	#define CPU_FTRS_40X (CPU_FTR_USE_TB \| CPU_FTR_NODSISRALIGN \| CPU_FTR_NOEXECUTE)
				382	#define CPU_FTRS_44X (CPU_FTR_USE_TB \| CPU_FTR_NODSISRALIGN \| CPU_FTR_NOEXECUTE)
Benjamin Herrenschmidt	6d2170b	2008-12-18 19:13:22 +0000	[diff] [blame]	383	#define CPU_FTRS_440x6 (CPU_FTR_USE_TB \| CPU_FTR_NODSISRALIGN \| CPU_FTR_NOEXECUTE \| \
				384	CPU_FTR_INDEXED_DCR)
Dave Kleikamp	e7f75ad	2010-03-05 10:43:12 +0000	[diff] [blame]	385	#define CPU_FTRS_47X (CPU_FTRS_440x6)
Kumar Gala	5e14d21	2007-09-13 01:44:20 -0500	[diff] [blame]	386	#define CPU_FTRS_E200 (CPU_FTR_USE_TB \| CPU_FTR_SPE_COMP \| \
				387	CPU_FTR_NODSISRALIGN \| CPU_FTR_COHERENT_ICACHE \| \
Scott Wood	52b066f	2011-12-20 15:34:12 +0000	[diff] [blame]	388	CPU_FTR_UNIFIED_ID_CACHE \| CPU_FTR_NOEXECUTE \| \
				389	CPU_FTR_DEBUG_LVL_EXC)
Kumar Gala	fc4033b	2008-06-18 16:26:52 -0500	[diff] [blame]	390	#define CPU_FTRS_E500 (CPU_FTR_MAYBE_CAN_DOZE \| CPU_FTR_USE_TB \| \
Benjamin Herrenschmidt	8309ce72	2008-12-12 17:33:25 +1100	[diff] [blame]	391	CPU_FTR_SPE_COMP \| CPU_FTR_MAYBE_CAN_NAP \| CPU_FTR_NODSISRALIGN \| \
				392	CPU_FTR_NOEXECUTE)
Kumar Gala	fc4033b	2008-06-18 16:26:52 -0500	[diff] [blame]	393	#define CPU_FTRS_E500_2 (CPU_FTR_MAYBE_CAN_DOZE \| CPU_FTR_USE_TB \| \
Benjamin Herrenschmidt	7c03d65	2008-12-18 19:13:32 +0000	[diff] [blame]	394	CPU_FTR_SPE_COMP \| CPU_FTR_MAYBE_CAN_NAP \| \
Benjamin Herrenschmidt	8309ce72	2008-12-12 17:33:25 +1100	[diff] [blame]	395	CPU_FTR_NODSISRALIGN \| CPU_FTR_NOEXECUTE)
Scott Wood	d51ad91	2010-05-27 17:35:12 -0500	[diff] [blame]	396	#define CPU_FTRS_E500MC (CPU_FTR_USE_TB \| CPU_FTR_NODSISRALIGN \| \
Kumar Gala	620165f	2009-02-12 13:54:53 +0000	[diff] [blame]	397	CPU_FTR_L2CSR \| CPU_FTR_LWSYNC \| CPU_FTR_NOEXECUTE \| \
Scott Wood	73196cd3	2011-12-20 15:34:47 +0000	[diff] [blame]	398	CPU_FTR_DBELL \| CPU_FTR_DEBUG_LVL_EXC \| CPU_FTR_EMB_HV)
Scott Wood	d52459c	2013-07-23 20:21:11 -0500	[diff] [blame]	399	/*
				400	* e5500/e6500 erratum A-006958 is a timebase bug that can use the
				401	* same workaround as CPU_FTR_CELL_TB_BUG.
				402	*/
Kumar Gala	11ed0db	2011-04-06 00:11:06 -0500	[diff] [blame]	403	#define CPU_FTRS_E5500 (CPU_FTR_USE_TB \| CPU_FTR_NODSISRALIGN \| \
				404	CPU_FTR_L2CSR \| CPU_FTR_LWSYNC \| CPU_FTR_NOEXECUTE \| \
Kumar Gala	d36b4c4	2011-04-06 00:18:48 -0500	[diff] [blame]	405	CPU_FTR_DBELL \| CPU_FTR_POPCNTB \| CPU_FTR_POPCNTD \| \
Scott Wood	d52459c	2013-07-23 20:21:11 -0500	[diff] [blame]	406	CPU_FTR_DEBUG_LVL_EXC \| CPU_FTR_EMB_HV \| CPU_FTR_CELL_TB_BUG)
Kumar Gala	1024184	2011-11-06 11:51:07 -0600	[diff] [blame]	407	#define CPU_FTRS_E6500 (CPU_FTR_USE_TB \| CPU_FTR_NODSISRALIGN \| \
				408	CPU_FTR_L2CSR \| CPU_FTR_LWSYNC \| CPU_FTR_NOEXECUTE \| \
				409	CPU_FTR_DBELL \| CPU_FTR_POPCNTB \| CPU_FTR_POPCNTD \| \
Scott Wood	d52459c	2013-07-23 20:21:11 -0500	[diff] [blame]	410	CPU_FTR_DEBUG_LVL_EXC \| CPU_FTR_EMB_HV \| CPU_FTR_ALTIVEC_COMP \| \
Andy Fleming	e16c876	2011-12-08 01:20:27 -0600	[diff] [blame]	411	CPU_FTR_CELL_TB_BUG \| CPU_FTR_SMT)
Stephen Rothwell	7c92943	2006-03-23 17:36:59 +1100	[diff] [blame]	412	#define CPU_FTRS_GENERIC_32 (CPU_FTR_COMMON \| CPU_FTR_NODSISRALIGN)
Michael Ellerman	0b8e2e1	2006-11-23 00:46:46 +0100	[diff] [blame]	413
				414	/* 64-bit CPUs */
Kumar Gala	2d1b202	2008-07-02 01:16:40 +1000	[diff] [blame]	415	#define CPU_FTRS_POWER4 (CPU_FTR_USE_TB \| CPU_FTR_LWSYNC \| \
Benjamin Herrenschmidt	7c03d65	2008-12-18 19:13:32 +0000	[diff] [blame]	416	CPU_FTR_PPCAS_ARCH_V2 \| CPU_FTR_CTRL \| \
Anton Blanchard	f89451f	2010-08-11 01:40:27 +0000	[diff] [blame]	417	CPU_FTR_MMCRA \| CPU_FTR_CP_USE_DCBTZ \| \
				418	CPU_FTR_STCX_CHECKS_ADDRESS)
Kumar Gala	2d1b202	2008-07-02 01:16:40 +1000	[diff] [blame]	419	#define CPU_FTRS_PPC970 (CPU_FTR_USE_TB \| CPU_FTR_LWSYNC \| \
Paul Mackerras	969391c	2011-06-29 00:26:11 +0000	[diff] [blame]	420	CPU_FTR_PPCAS_ARCH_V2 \| CPU_FTR_CTRL \| CPU_FTR_ARCH_201 \| \
Mark Nelson	2a92943	2008-08-22 14:36:19 +1000	[diff] [blame]	421	CPU_FTR_ALTIVEC_COMP \| CPU_FTR_CAN_NAP \| CPU_FTR_MMCRA \| \
Paul Mackerras	969391c	2011-06-29 00:26:11 +0000	[diff] [blame]	422	CPU_FTR_CP_USE_DCBTZ \| CPU_FTR_STCX_CHECKS_ADDRESS \| \
Michael Neuling	82a9f16	2013-05-16 20:27:31 +0000	[diff] [blame]	423	CPU_FTR_HVMODE \| CPU_FTR_DABRX)
Kumar Gala	2d1b202	2008-07-02 01:16:40 +1000	[diff] [blame]	424	#define CPU_FTRS_POWER5 (CPU_FTR_USE_TB \| CPU_FTR_LWSYNC \| \
Benjamin Herrenschmidt	7c03d65	2008-12-18 19:13:32 +0000	[diff] [blame]	425	CPU_FTR_PPCAS_ARCH_V2 \| CPU_FTR_CTRL \| \
Stephen Rothwell	7c92943	2006-03-23 17:36:59 +1100	[diff] [blame]	426	CPU_FTR_MMCRA \| CPU_FTR_SMT \| \
Matt Evans	44ae3ab	2011-04-06 19:48:50 +0000	[diff] [blame]	427	CPU_FTR_COHERENT_ICACHE \| CPU_FTR_PURR \| \
Michael Neuling	82a9f16	2013-05-16 20:27:31 +0000	[diff] [blame]	428	CPU_FTR_STCX_CHECKS_ADDRESS \| CPU_FTR_POPCNTB \| CPU_FTR_DABRX)
Kumar Gala	2d1b202	2008-07-02 01:16:40 +1000	[diff] [blame]	429	#define CPU_FTRS_POWER6 (CPU_FTR_USE_TB \| CPU_FTR_LWSYNC \| \
Benjamin Herrenschmidt	7c03d65	2008-12-18 19:13:32 +0000	[diff] [blame]	430	CPU_FTR_PPCAS_ARCH_V2 \| CPU_FTR_CTRL \| \
Anton Blanchard	03054d5	2006-04-29 09:51:06 +1000	[diff] [blame]	431	CPU_FTR_MMCRA \| CPU_FTR_SMT \| \
Matt Evans	44ae3ab	2011-04-06 19:48:50 +0000	[diff] [blame]	432	CPU_FTR_COHERENT_ICACHE \| \
Anton Blanchard	4c198557	2006-12-08 17:46:58 +1100	[diff] [blame]	433	CPU_FTR_PURR \| CPU_FTR_SPURR \| CPU_FTR_REAL_LE \| \
Anton Blanchard	f89451f	2010-08-11 01:40:27 +0000	[diff] [blame]	434	CPU_FTR_DSCR \| CPU_FTR_UNALIGNED_LD_STD \| \
Michael Neuling	82a9f16	2013-05-16 20:27:31 +0000	[diff] [blame]	435	CPU_FTR_STCX_CHECKS_ADDRESS \| CPU_FTR_POPCNTB \| CPU_FTR_CFAR \| \
				436	CPU_FTR_DABRX)
Kumar Gala	2d1b202	2008-07-02 01:16:40 +1000	[diff] [blame]	437	#define CPU_FTRS_POWER7 (CPU_FTR_USE_TB \| CPU_FTR_LWSYNC \| \
Paul Mackerras	969391c	2011-06-29 00:26:11 +0000	[diff] [blame]	438	CPU_FTR_PPCAS_ARCH_V2 \| CPU_FTR_CTRL \| CPU_FTR_ARCH_206 \|\
Michael Neuling	e952e6c	2008-06-18 10:47:26 +1000	[diff] [blame]	439	CPU_FTR_MMCRA \| CPU_FTR_SMT \| \
Matt Evans	44ae3ab	2011-04-06 19:48:50 +0000	[diff] [blame]	440	CPU_FTR_COHERENT_ICACHE \| \
Michael Neuling	e952e6c	2008-06-18 10:47:26 +1000	[diff] [blame]	441	CPU_FTR_PURR \| CPU_FTR_SPURR \| CPU_FTR_REAL_LE \| \
Anton Blanchard	f89451f	2010-08-11 01:40:27 +0000	[diff] [blame]	442	CPU_FTR_DSCR \| CPU_FTR_SAO \| CPU_FTR_ASYM_SMT \| \
Tseng-Hui (Frank) Lin	851d2e2	2011-05-02 20:43:04 +0000	[diff] [blame]	443	CPU_FTR_STCX_CHECKS_ADDRESS \| CPU_FTR_POPCNTB \| CPU_FTR_POPCNTD \| \
Haren Myneni	d2613868	2012-12-06 21:47:42 +0000	[diff] [blame]	444	CPU_FTR_ICSWX \| CPU_FTR_CFAR \| CPU_FTR_HVMODE \| \
Michael Neuling	82a9f16	2013-05-16 20:27:31 +0000	[diff] [blame]	445	CPU_FTR_VMX_COPY \| CPU_FTR_HAS_PPR \| CPU_FTR_DABRX)
Michael Neuling	71e1849	2012-10-30 19:34:15 +0000	[diff] [blame]	446	#define CPU_FTRS_POWER8 (CPU_FTR_USE_TB \| CPU_FTR_LWSYNC \| \
				447	CPU_FTR_PPCAS_ARCH_V2 \| CPU_FTR_CTRL \| CPU_FTR_ARCH_206 \|\
				448	CPU_FTR_MMCRA \| CPU_FTR_SMT \| \
				449	CPU_FTR_COHERENT_ICACHE \| \
				450	CPU_FTR_PURR \| CPU_FTR_SPURR \| CPU_FTR_REAL_LE \| \
				451	CPU_FTR_DSCR \| CPU_FTR_SAO \| \
				452	CPU_FTR_STCX_CHECKS_ADDRESS \| CPU_FTR_POPCNTB \| CPU_FTR_POPCNTD \| \
Ian Munsie	e5e84f0	2012-11-14 18:49:50 +0000	[diff] [blame]	453	CPU_FTR_ICSWX \| CPU_FTR_CFAR \| CPU_FTR_HVMODE \| CPU_FTR_VMX_COPY \| \
Michael Ellerman	1de2bd4	2013-04-30 20:17:02 +0000	[diff] [blame]	454	CPU_FTR_DBELL \| CPU_FTR_HAS_PPR \| CPU_FTR_DAWR \| \
Michael Neuling	ce5732a	2016-02-19 11:16:22 +1100	[diff] [blame]	455	CPU_FTR_ARCH_207S \| CPU_FTR_TM_COMP \| CPU_FTR_SUBCORE)
Michael Ellerman	68f2f0d	2014-03-14 16:00:28 +1100	[diff] [blame]	456	#define CPU_FTRS_POWER8E (CPU_FTRS_POWER8 \| CPU_FTR_PMAO_BUG)
Joel Stanley	bd6ba35	2014-07-18 11:41:37 +0930	[diff] [blame]	457	#define CPU_FTRS_POWER8_DD1 (CPU_FTRS_POWER8 & ~CPU_FTR_DBELL)
Michael Neuling	c3ab300	2016-02-19 11:16:24 +1100	[diff] [blame]	458	#define CPU_FTRS_POWER9 (CPU_FTR_USE_TB \| CPU_FTR_LWSYNC \| \
				459	CPU_FTR_PPCAS_ARCH_V2 \| CPU_FTR_CTRL \| CPU_FTR_ARCH_206 \|\
				460	CPU_FTR_MMCRA \| CPU_FTR_SMT \| \
				461	CPU_FTR_COHERENT_ICACHE \| \
				462	CPU_FTR_PURR \| CPU_FTR_SPURR \| CPU_FTR_REAL_LE \| \
				463	CPU_FTR_DSCR \| CPU_FTR_SAO \| \
				464	CPU_FTR_STCX_CHECKS_ADDRESS \| CPU_FTR_POPCNTB \| CPU_FTR_POPCNTD \| \
				465	CPU_FTR_ICSWX \| CPU_FTR_CFAR \| CPU_FTR_HVMODE \| CPU_FTR_VMX_COPY \| \
				466	CPU_FTR_DBELL \| CPU_FTR_HAS_PPR \| CPU_FTR_DAWR \| \
				467	CPU_FTR_ARCH_207S \| CPU_FTR_TM_COMP \| CPU_FTR_ARCH_300)
Kumar Gala	2d1b202	2008-07-02 01:16:40 +1000	[diff] [blame]	468	#define CPU_FTRS_CELL (CPU_FTR_USE_TB \| CPU_FTR_LWSYNC \| \
Benjamin Herrenschmidt	7c03d65	2008-12-18 19:13:32 +0000	[diff] [blame]	469	CPU_FTR_PPCAS_ARCH_V2 \| CPU_FTR_CTRL \| \
Stephen Rothwell	7c92943	2006-03-23 17:36:59 +1100	[diff] [blame]	470	CPU_FTR_ALTIVEC_COMP \| CPU_FTR_MMCRA \| CPU_FTR_SMT \| \
Matt Evans	44ae3ab	2011-04-06 19:48:50 +0000	[diff] [blame]	471	CPU_FTR_PAUSE_ZERO \| CPU_FTR_CELL_TB_BUG \| CPU_FTR_CP_USE_DCBTZ \| \
Michael Neuling	82a9f16	2013-05-16 20:27:31 +0000	[diff] [blame]	472	CPU_FTR_UNALIGNED_LD_STD \| CPU_FTR_DABRX)
Kumar Gala	2d1b202	2008-07-02 01:16:40 +1000	[diff] [blame]	473	#define CPU_FTRS_PA6T (CPU_FTR_USE_TB \| CPU_FTR_LWSYNC \| \
Matt Evans	44ae3ab	2011-04-06 19:48:50 +0000	[diff] [blame]	474	CPU_FTR_PPCAS_ARCH_V2 \| CPU_FTR_ALTIVEC_COMP \| \
Michael Neuling	82a9f16	2013-05-16 20:27:31 +0000	[diff] [blame]	475	CPU_FTR_PURR \| CPU_FTR_REAL_LE \| CPU_FTR_DABRX)
Benjamin Herrenschmidt	7c03d65	2008-12-18 19:13:32 +0000	[diff] [blame]	476	#define CPU_FTRS_COMPATIBLE (CPU_FTR_USE_TB \| CPU_FTR_PPCAS_ARCH_V2)
Kumar Gala	10b35d9	2005-09-23 14:08:58 -0500	[diff] [blame]	477
Anton Blanchard	2406f60	2005-12-13 07:45:33 +1100	[diff] [blame]	478	#ifdef __powerpc64__
Kumar Gala	11ed0db	2011-04-06 00:11:06 -0500	[diff] [blame]	479	#ifdef CONFIG_PPC_BOOK3E
Michael Ellerman	9002964	2014-08-06 18:26:28 +1000	[diff] [blame]	480	#define CPU_FTRS_POSSIBLE (CPU_FTRS_E6500 \| CPU_FTRS_E5500)
Kumar Gala	11ed0db	2011-04-06 00:11:06 -0500	[diff] [blame]	481	#else
Stephen Rothwell	7c92943	2006-03-23 17:36:59 +1100	[diff] [blame]	482	#define CPU_FTRS_POSSIBLE \
Michael Ellerman	468a330	2014-07-10 12:29:18 +1000	[diff] [blame]	483	(CPU_FTRS_POWER4 \| CPU_FTRS_PPC970 \| CPU_FTRS_POWER5 \| \
				484	CPU_FTRS_POWER6 \| CPU_FTRS_POWER7 \| CPU_FTRS_POWER8E \| \
Michael Ellerman	3609e09	2014-08-06 15:42:17 +1000	[diff] [blame]	485	CPU_FTRS_POWER8 \| CPU_FTRS_POWER8_DD1 \| CPU_FTRS_CELL \| \
Michael Neuling	c3ab300	2016-02-19 11:16:24 +1100	[diff] [blame]	486	CPU_FTRS_PA6T \| CPU_FTR_VSX \| CPU_FTRS_POWER9)
Kumar Gala	11ed0db	2011-04-06 00:11:06 -0500	[diff] [blame]	487	#endif
Anton Blanchard	2406f60	2005-12-13 07:45:33 +1100	[diff] [blame]	488	#else
Stephen Rothwell	7c92943	2006-03-23 17:36:59 +1100	[diff] [blame]	489	enum {
				490	CPU_FTRS_POSSIBLE =
Michael Ellerman	1e07a0a	2014-07-10 12:29:26 +1000	[diff] [blame]	491	#ifdef CONFIG_PPC_BOOK3S_32
Kumar Gala	10b35d9	2005-09-23 14:08:58 -0500	[diff] [blame]	492	CPU_FTRS_PPC601 \| CPU_FTRS_603 \| CPU_FTRS_604 \| CPU_FTRS_740_NOTAU \|
				493	CPU_FTRS_740 \| CPU_FTRS_750 \| CPU_FTRS_750FX1 \|
				494	CPU_FTRS_750FX2 \| CPU_FTRS_750FX \| CPU_FTRS_750GX \|
				495	CPU_FTRS_7400_NOTAU \| CPU_FTRS_7400 \| CPU_FTRS_7450_20 \|
				496	CPU_FTRS_7450_21 \| CPU_FTRS_7450_23 \| CPU_FTRS_7455_1 \|
				497	CPU_FTRS_7455_20 \| CPU_FTRS_7455 \| CPU_FTRS_7447_10 \|
				498	CPU_FTRS_7447 \| CPU_FTRS_7447A \| CPU_FTRS_82XX \|
Kim Phillips	aa42c69	2006-12-08 02:43:30 -0600	[diff] [blame]	499	CPU_FTRS_G2_LE \| CPU_FTRS_E300 \| CPU_FTRS_E300C2 \|
				500	CPU_FTRS_CLASSIC32 \|
Kumar Gala	10b35d9	2005-09-23 14:08:58 -0500	[diff] [blame]	501	#else
				502	CPU_FTRS_GENERIC_32 \|
				503	#endif
Kumar Gala	10b35d9	2005-09-23 14:08:58 -0500	[diff] [blame]	504	#ifdef CONFIG_8xx
				505	CPU_FTRS_8XX \|
				506	#endif
				507	#ifdef CONFIG_40x
				508	CPU_FTRS_40X \|
				509	#endif
				510	#ifdef CONFIG_44x
Benjamin Herrenschmidt	6d2170b	2008-12-18 19:13:22 +0000	[diff] [blame]	511	CPU_FTRS_44X \| CPU_FTRS_440x6 \|
Kumar Gala	10b35d9	2005-09-23 14:08:58 -0500	[diff] [blame]	512	#endif
Dave Kleikamp	e7f75ad	2010-03-05 10:43:12 +0000	[diff] [blame]	513	#ifdef CONFIG_PPC_47x
Dave Kleikamp	c48d0db	2011-01-26 06:17:58 +0000	[diff] [blame]	514	CPU_FTRS_47X \| CPU_FTR_476_DD2 \|
Dave Kleikamp	e7f75ad	2010-03-05 10:43:12 +0000	[diff] [blame]	515	#endif
Kumar Gala	10b35d9	2005-09-23 14:08:58 -0500	[diff] [blame]	516	#ifdef CONFIG_E200
				517	CPU_FTRS_E200 \|
				518	#endif
				519	#ifdef CONFIG_E500
Scott Wood	06aae86	2011-12-20 15:34:14 +0000	[diff] [blame]	520	CPU_FTRS_E500 \| CPU_FTRS_E500_2 \|
				521	#endif
				522	#ifdef CONFIG_PPC_E500MC
				523	CPU_FTRS_E500MC \| CPU_FTRS_E5500 \| CPU_FTRS_E6500 \|
Kumar Gala	10b35d9	2005-09-23 14:08:58 -0500	[diff] [blame]	524	#endif
Kumar Gala	10b35d9	2005-09-23 14:08:58 -0500	[diff] [blame]	525	0,
Stephen Rothwell	7c92943	2006-03-23 17:36:59 +1100	[diff] [blame]	526	};
				527	#endif /* __powerpc64__ */
Kumar Gala	10b35d9	2005-09-23 14:08:58 -0500	[diff] [blame]	528
Anton Blanchard	2406f60	2005-12-13 07:45:33 +1100	[diff] [blame]	529	#ifdef __powerpc64__
Kumar Gala	11ed0db	2011-04-06 00:11:06 -0500	[diff] [blame]	530	#ifdef CONFIG_PPC_BOOK3E
Michael Ellerman	9002964	2014-08-06 18:26:28 +1000	[diff] [blame]	531	#define CPU_FTRS_ALWAYS (CPU_FTRS_E6500 & CPU_FTRS_E5500)
Kumar Gala	11ed0db	2011-04-06 00:11:06 -0500	[diff] [blame]	532	#else
Stephen Rothwell	7c92943	2006-03-23 17:36:59 +1100	[diff] [blame]	533	#define CPU_FTRS_ALWAYS \
Michael Ellerman	468a330	2014-07-10 12:29:18 +1000	[diff] [blame]	534	(CPU_FTRS_POWER4 & CPU_FTRS_PPC970 & CPU_FTRS_POWER5 & \
				535	CPU_FTRS_POWER6 & CPU_FTRS_POWER7 & CPU_FTRS_CELL & \
Michael Ellerman	3609e09	2014-08-06 15:42:17 +1000	[diff] [blame]	536	CPU_FTRS_PA6T & CPU_FTRS_POWER8 & CPU_FTRS_POWER8E & \
Michael Neuling	c3ab300	2016-02-19 11:16:24 +1100	[diff] [blame]	537	CPU_FTRS_POWER8_DD1 & ~CPU_FTR_HVMODE & CPU_FTRS_POSSIBLE & \
				538	CPU_FTRS_POWER9)
Kumar Gala	11ed0db	2011-04-06 00:11:06 -0500	[diff] [blame]	539	#endif
Anton Blanchard	2406f60	2005-12-13 07:45:33 +1100	[diff] [blame]	540	#else
Stephen Rothwell	7c92943	2006-03-23 17:36:59 +1100	[diff] [blame]	541	enum {
				542	CPU_FTRS_ALWAYS =
Michael Ellerman	1e07a0a	2014-07-10 12:29:26 +1000	[diff] [blame]	543	#ifdef CONFIG_PPC_BOOK3S_32
Kumar Gala	10b35d9	2005-09-23 14:08:58 -0500	[diff] [blame]	544	CPU_FTRS_PPC601 & CPU_FTRS_603 & CPU_FTRS_604 & CPU_FTRS_740_NOTAU &
				545	CPU_FTRS_740 & CPU_FTRS_750 & CPU_FTRS_750FX1 &
				546	CPU_FTRS_750FX2 & CPU_FTRS_750FX & CPU_FTRS_750GX &
				547	CPU_FTRS_7400_NOTAU & CPU_FTRS_7400 & CPU_FTRS_7450_20 &
				548	CPU_FTRS_7450_21 & CPU_FTRS_7450_23 & CPU_FTRS_7455_1 &
				549	CPU_FTRS_7455_20 & CPU_FTRS_7455 & CPU_FTRS_7447_10 &
				550	CPU_FTRS_7447 & CPU_FTRS_7447A & CPU_FTRS_82XX &
Kim Phillips	aa42c69	2006-12-08 02:43:30 -0600	[diff] [blame]	551	CPU_FTRS_G2_LE & CPU_FTRS_E300 & CPU_FTRS_E300C2 &
				552	CPU_FTRS_CLASSIC32 &
Kumar Gala	10b35d9	2005-09-23 14:08:58 -0500	[diff] [blame]	553	#else
				554	CPU_FTRS_GENERIC_32 &
				555	#endif
Kumar Gala	10b35d9	2005-09-23 14:08:58 -0500	[diff] [blame]	556	#ifdef CONFIG_8xx
				557	CPU_FTRS_8XX &
				558	#endif
				559	#ifdef CONFIG_40x
				560	CPU_FTRS_40X &
				561	#endif
				562	#ifdef CONFIG_44x
Benjamin Herrenschmidt	6d2170b	2008-12-18 19:13:22 +0000	[diff] [blame]	563	CPU_FTRS_44X & CPU_FTRS_440x6 &
Kumar Gala	10b35d9	2005-09-23 14:08:58 -0500	[diff] [blame]	564	#endif
				565	#ifdef CONFIG_E200
				566	CPU_FTRS_E200 &
				567	#endif
				568	#ifdef CONFIG_E500
Scott Wood	06aae86	2011-12-20 15:34:14 +0000	[diff] [blame]	569	CPU_FTRS_E500 & CPU_FTRS_E500_2 &
				570	#endif
				571	#ifdef CONFIG_PPC_E500MC
				572	CPU_FTRS_E500MC & CPU_FTRS_E5500 & CPU_FTRS_E6500 &
Kumar Gala	10b35d9	2005-09-23 14:08:58 -0500	[diff] [blame]	573	#endif
Scott Wood	73196cd3	2011-12-20 15:34:47 +0000	[diff] [blame]	574	~CPU_FTR_EMB_HV & /* can be removed at runtime */
Kumar Gala	10b35d9	2005-09-23 14:08:58 -0500	[diff] [blame]	575	CPU_FTRS_POSSIBLE,
				576	};
Stephen Rothwell	7c92943	2006-03-23 17:36:59 +1100	[diff] [blame]	577	#endif /* __powerpc64__ */
Kumar Gala	10b35d9	2005-09-23 14:08:58 -0500	[diff] [blame]	578
				579	static inline int cpu_has_feature(unsigned long feature)
				580	{
				581	return (CPU_FTRS_ALWAYS & feature) \|\|
				582	(CPU_FTRS_POSSIBLE
Kumar Gala	10b35d9	2005-09-23 14:08:58 -0500	[diff] [blame]	583	& cur_cpu_spec->cpu_features
Kumar Gala	10b35d9	2005-09-23 14:08:58 -0500	[diff] [blame]	584	& feature);
				585	}
				586
K.Prasad	5aae8a5	2010-06-15 11:35:19 +0530	[diff] [blame]	587	#define HBP_NUM 1
K.Prasad	5aae8a5	2010-06-15 11:35:19 +0530	[diff] [blame]	588
Kumar Gala	10b35d9	2005-09-23 14:08:58 -0500	[diff] [blame]	589	#endif /* !__ASSEMBLY__ */
				590
Kumar Gala	10b35d9	2005-09-23 14:08:58 -0500	[diff] [blame]	591	#endif /* __ASM_POWERPC_CPUTABLE_H */