Michael Turquette | 2cc9e7e | 2016-06-09 16:20:47 -0700 | [diff] [blame] | 1 | * Amlogic GXBB Clock and Reset Unit |
| 2 | |
| 3 | The Amlogic GXBB clock controller generates and supplies clock to various |
| 4 | controllers within the SoC. |
| 5 | |
| 6 | Required Properties: |
| 7 | |
Yixun Lan | f8d0dfe | 2017-12-11 22:13:44 +0800 | [diff] [blame] | 8 | - compatible: should be: |
| 9 | "amlogic,gxbb-clkc" for GXBB SoC, |
| 10 | "amlogic,gxl-clkc" for GXL and GXM SoC, |
| 11 | "amlogic,axg-clkc" for AXG SoC. |
Jian Hu | 25db146 | 2019-02-01 15:53:43 +0100 | [diff] [blame] | 12 | "amlogic,g12a-clkc" for G12A SoC. |
Neil Armstrong | 7391d7f | 2019-05-28 10:07:56 +0200 | [diff] [blame] | 13 | "amlogic,g12b-clkc" for G12B SoC. |
Neil Armstrong | cda4569 | 2019-08-26 09:25:35 +0200 | [diff] [blame] | 14 | "amlogic,sm1-clkc" for SM1 SoC. |
Jerome Brunet | b1d02a8 | 2018-12-03 18:16:39 +0100 | [diff] [blame] | 15 | - clocks : list of clock phandle, one for each entry clock-names. |
| 16 | - clock-names : should contain the following: |
| 17 | * "xtal": the platform xtal |
Yixun Lan | f8d0dfe | 2017-12-11 22:13:44 +0800 | [diff] [blame] | 18 | |
Michael Turquette | 2cc9e7e | 2016-06-09 16:20:47 -0700 | [diff] [blame] | 19 | - #clock-cells: should be 1. |
| 20 | |
| 21 | Each clock is assigned an identifier and client nodes can use this identifier |
| 22 | to specify the clock which they consume. All available clocks are defined as |
| 23 | preprocessor macros in the dt-bindings/clock/gxbb-clkc.h header and can be |
| 24 | used in device tree sources. |
| 25 | |
Jerome Brunet | d474056 | 2018-03-15 12:55:42 +0100 | [diff] [blame] | 26 | Parent node should have the following properties : |
| 27 | - compatible: "syscon", "simple-mfd, and "amlogic,meson-gx-hhi-sysctrl" or |
| 28 | "amlogic,meson-axg-hhi-sysctrl" |
| 29 | - reg: base address and size of the HHI system control register space. |
| 30 | |
Michael Turquette | 2cc9e7e | 2016-06-09 16:20:47 -0700 | [diff] [blame] | 31 | Example: Clock controller node: |
| 32 | |
Jerome Brunet | d474056 | 2018-03-15 12:55:42 +0100 | [diff] [blame] | 33 | sysctrl: system-controller@0 { |
| 34 | compatible = "amlogic,meson-gx-hhi-sysctrl", "syscon", "simple-mfd"; |
| 35 | reg = <0 0 0 0x400>; |
| 36 | |
| 37 | clkc: clock-controller { |
Michael Turquette | 2cc9e7e | 2016-06-09 16:20:47 -0700 | [diff] [blame] | 38 | #clock-cells = <1>; |
| 39 | compatible = "amlogic,gxbb-clkc"; |
Jerome Brunet | b1d02a8 | 2018-12-03 18:16:39 +0100 | [diff] [blame] | 40 | clocks = <&xtal>; |
| 41 | clock-names = "xtal"; |
Michael Turquette | 2cc9e7e | 2016-06-09 16:20:47 -0700 | [diff] [blame] | 42 | }; |
Jerome Brunet | d474056 | 2018-03-15 12:55:42 +0100 | [diff] [blame] | 43 | }; |
Michael Turquette | 2cc9e7e | 2016-06-09 16:20:47 -0700 | [diff] [blame] | 44 | |
| 45 | Example: UART controller node that consumes the clock generated by the clock |
| 46 | controller: |
| 47 | |
| 48 | uart_AO: serial@c81004c0 { |
| 49 | compatible = "amlogic,meson-uart"; |
| 50 | reg = <0xc81004c0 0x14>; |
| 51 | interrupts = <0 90 1>; |
| 52 | clocks = <&clkc CLKID_CLK81>; |
Michael Turquette | 2cc9e7e | 2016-06-09 16:20:47 -0700 | [diff] [blame] | 53 | }; |