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review.shift-gmbh.com / SHIFTPHONES / mainline / linux / e5a594643a3444d39c1467040e638bf08a4e0db8 / . / drivers / infiniband / hw / i40iw / i40iw_verbs.h
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Faisal Latifd3749842016-01-20 13:40:09 -0600[diff] [blame]1/*******************************************************************************
2*
3* Copyright (c) 2015-2016 Intel Corporation. All rights reserved.
4*
5* This software is available to you under a choice of one of two
6* licenses. You may choose to be licensed under the terms of the GNU
7* General Public License (GPL) Version 2, available from the file
8* COPYING in the main directory of this source tree, or the
9* OpenFabrics.org BSD license below:
10*
11* Redistribution and use in source and binary forms, with or
12* without modification, are permitted provided that the following
13* conditions are met:
14*
15* - Redistributions of source code must retain the above
16* copyright notice, this list of conditions and the following
17* disclaimer.
18*
19* - Redistributions in binary form must reproduce the above
20* copyright notice, this list of conditions and the following
21* disclaimer in the documentation and/or other materials
22* provided with the distribution.
23*
24* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
25* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
26* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
27* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
28* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
29* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
30* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
31* SOFTWARE.
32*
33*******************************************************************************/
34
35#ifndef I40IW_VERBS_H
36#define I40IW_VERBS_H
37
38struct i40iw_ucontext {
39 struct ib_ucontext ibucontext;
40 struct i40iw_device *iwdev;
41 struct list_head cq_reg_mem_list;
42 spinlock_t cq_reg_mem_list_lock; /* memory list for cq's */
43 struct list_head qp_reg_mem_list;
44 spinlock_t qp_reg_mem_list_lock; /* memory list for qp's */
Chien Tin Tung61f51b72016-12-21 08:53:46 -0600[diff] [blame]45 int abi_ver;
Faisal Latifd3749842016-01-20 13:40:09 -0600[diff] [blame]46};
47
48struct i40iw_pd {
49 struct ib_pd ibpd;
50 struct i40iw_sc_pd sc_pd;
51 atomic_t usecount;
52};
53
54struct i40iw_hmc_pble {
55 union {
56 u32 idx;
57 dma_addr_t addr;
58 };
59};
60
61struct i40iw_cq_mr {
62 struct i40iw_hmc_pble cq_pbl;
63 dma_addr_t shadow;
64};
65
66struct i40iw_qp_mr {
67 struct i40iw_hmc_pble sq_pbl;
68 struct i40iw_hmc_pble rq_pbl;
69 dma_addr_t shadow;
70 struct page *sq_page;
71};
72
73struct i40iw_pbl {
74 struct list_head list;
75 union {
76 struct i40iw_qp_mr qp_mr;
77 struct i40iw_cq_mr cq_mr;
78 };
79
80 bool pbl_allocated;
Andrew Boyera75895b2018-05-07 13:23:36 -0400[diff] [blame]81 bool on_list;
Faisal Latifd3749842016-01-20 13:40:09 -0600[diff] [blame]82 u64 user_base;
83 struct i40iw_pble_alloc pble_alloc;
84 struct i40iw_mr *iwmr;
85};
86
87#define MAX_SAVE_PAGE_ADDRS 4
88struct i40iw_mr {
89 union {
90 struct ib_mr ibmr;
91 struct ib_mw ibmw;
92 struct ib_fmr ibfmr;
93 };
94 struct ib_umem *region;
95 u16 type;
96 u32 page_cnt;
Henry Oroscof26c7c82016-11-30 14:57:40 -0600[diff] [blame]97 u32 page_size;
98 u64 page_msk;
Ismail, Mustafab7aee852016-04-18 10:33:06 -0500[diff] [blame]99 u32 npages;
Faisal Latifd3749842016-01-20 13:40:09 -0600[diff] [blame]100 u32 stag;
101 u64 length;
102 u64 pgaddrmem[MAX_SAVE_PAGE_ADDRS];
103 struct i40iw_pbl iwpbl;
104};
105
106struct i40iw_cq {
107 struct ib_cq ibcq;
108 struct i40iw_sc_cq sc_cq;
109 u16 cq_head;
110 u16 cq_size;
111 u16 cq_number;
112 bool user_mode;
113 u32 polled_completions;
114 u32 cq_mem_size;
115 struct i40iw_dma_mem kmem;
116 spinlock_t lock; /* for poll cq */
117 struct i40iw_pbl *iwpbl;
118};
119
120struct disconn_work {
121 struct work_struct work;
122 struct i40iw_qp *iwqp;
123};
124
125struct iw_cm_id;
126struct ietf_mpa_frame;
127struct i40iw_ud_file;
128
129struct i40iw_qp_kmode {
130 struct i40iw_dma_mem dma_mem;
131 u64 *wrid_mem;
132};
133
134struct i40iw_qp {
135 struct ib_qp ibqp;
136 struct i40iw_sc_qp sc_qp;
137 struct i40iw_device *iwdev;
138 struct i40iw_cq *iwscq;
139 struct i40iw_cq *iwrcq;
140 struct i40iw_pd *iwpd;
141 struct i40iw_qp_host_ctx_info ctx_info;
142 struct i40iwarp_offload_info iwarp_info;
143 void *allocated_buffer;
144 atomic_t refcount;
145 struct iw_cm_id *cm_id;
146 void *cm_node;
147 struct ib_mr *lsmm_mr;
148 struct work_struct work;
149 enum ib_qp_state ibqp_state;
150 u32 iwarp_state;
151 u32 qp_mem_size;
152 u32 last_aeq;
153 atomic_t close_timer_started;
154 spinlock_t lock; /* for post work requests */
155 struct i40iw_qp_context *iwqp_context;
156 void *pbl_vbase;
157 dma_addr_t pbl_pbase;
158 struct page *page;
159 u8 active_conn:1;
160 u8 user_mode:1;
161 u8 hte_added:1;
162 u8 flush_issued:1;
163 u8 destroyed:1;
164 u8 sig_all:1;
165 u8 pau_mode:1;
166 u8 rsvd:1;
167 u16 term_sq_flush_code;
168 u16 term_rq_flush_code;
169 u8 hw_iwarp_state;
170 u8 hw_tcp_state;
171 struct i40iw_qp_kmode kqp;
172 struct i40iw_dma_mem host_ctx;
173 struct timer_list terminate_timer;
Tatyana Nikolovaaf56e532017-07-05 21:25:33 -0500[diff] [blame]174 struct i40iw_pbl iwpbl;
Faisal Latifd3749842016-01-20 13:40:09 -0600[diff] [blame]175 struct i40iw_dma_mem q2_ctx_mem;
176 struct i40iw_dma_mem ietf_mem;
Ismail, Mustafac2b75ef2016-04-18 10:33:09 -0500[diff] [blame]177 struct completion sq_drained;
178 struct completion rq_drained;
Faisal Latifd3749842016-01-20 13:40:09 -0600[diff] [blame]179};
180#endif