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Thomas Gleixnere62d9492019-05-20 19:07:58 +02001// SPDX-License-Identifier: GPL-2.0-or-later
Dan Williamsb2f46fd2009-07-14 12:20:36 -07002/*
3 * Copyright(c) 2007 Yuri Tikhonov <yur@emcraft.com>
4 * Copyright(c) 2009 Intel Corporation
Dan Williamsb2f46fd2009-07-14 12:20:36 -07005 */
6#include <linux/kernel.h>
7#include <linux/interrupt.h>
Paul Gortmaker4bb33cc2011-05-27 14:41:48 -04008#include <linux/module.h>
Dan Williamsb2f46fd2009-07-14 12:20:36 -07009#include <linux/dma-mapping.h>
10#include <linux/raid/pq.h>
11#include <linux/async_tx.h>
Tejun Heo5a0e3ad2010-03-24 17:04:11 +090012#include <linux/gfp.h>
Dan Williamsb2f46fd2009-07-14 12:20:36 -070013
14/**
Dan Williams030b0772009-10-19 18:09:32 -070015 * pq_scribble_page - space to hold throwaway P or Q buffer for
16 * synchronous gen_syndrome
Dan Williamsb2f46fd2009-07-14 12:20:36 -070017 */
Dan Williams030b0772009-10-19 18:09:32 -070018static struct page *pq_scribble_page;
Dan Williamsb2f46fd2009-07-14 12:20:36 -070019
Dan Williamsb2f46fd2009-07-14 12:20:36 -070020/* the struct page *blocks[] parameter passed to async_gen_syndrome()
21 * and async_syndrome_val() contains the 'P' destination address at
22 * blocks[disks-2] and the 'Q' destination address at blocks[disks-1]
23 *
24 * note: these are macros as they are used as lvalues
25 */
26#define P(b, d) (b[d-2])
27#define Q(b, d) (b[d-1])
28
Kyle Spiers89a7e2f2018-06-01 13:20:16 -070029#define MAX_DISKS 255
30
Dan Williamsb2f46fd2009-07-14 12:20:36 -070031/**
32 * do_async_gen_syndrome - asynchronously calculate P and/or Q
33 */
34static __async_inline struct dma_async_tx_descriptor *
Dan Williams7476bd792013-10-18 19:35:29 +020035do_async_gen_syndrome(struct dma_chan *chan,
36 const unsigned char *scfs, int disks,
37 struct dmaengine_unmap_data *unmap,
38 enum dma_ctrl_flags dma_flags,
Dan Williamsb2f46fd2009-07-14 12:20:36 -070039 struct async_submit_ctl *submit)
40{
41 struct dma_async_tx_descriptor *tx = NULL;
42 struct dma_device *dma = chan->device;
Dan Williamsb2f46fd2009-07-14 12:20:36 -070043 enum async_tx_flags flags_orig = submit->flags;
44 dma_async_tx_callback cb_fn_orig = submit->cb_fn;
45 dma_async_tx_callback cb_param_orig = submit->cb_param;
46 int src_cnt = disks - 2;
Dan Williamsb2f46fd2009-07-14 12:20:36 -070047 unsigned short pq_src_cnt;
48 dma_addr_t dma_dest[2];
49 int src_off = 0;
Dan Williamsb2f46fd2009-07-14 12:20:36 -070050
Dan Williamsb2f46fd2009-07-14 12:20:36 -070051 while (src_cnt > 0) {
52 submit->flags = flags_orig;
53 pq_src_cnt = min(src_cnt, dma_maxpq(dma, dma_flags));
54 /* if we are submitting additional pqs, leave the chain open,
55 * clear the callback parameters, and leave the destination
56 * buffers mapped
57 */
58 if (src_cnt > pq_src_cnt) {
59 submit->flags &= ~ASYNC_TX_ACK;
Dan Williams0403e382009-09-08 17:42:50 -070060 submit->flags |= ASYNC_TX_FENCE;
Dan Williamsb2f46fd2009-07-14 12:20:36 -070061 submit->cb_fn = NULL;
62 submit->cb_param = NULL;
63 } else {
Dan Williamsb2f46fd2009-07-14 12:20:36 -070064 submit->cb_fn = cb_fn_orig;
65 submit->cb_param = cb_param_orig;
66 if (cb_fn_orig)
67 dma_flags |= DMA_PREP_INTERRUPT;
68 }
Anup Patelbaae03a2017-05-15 10:34:53 +053069 if (submit->flags & ASYNC_TX_FENCE)
70 dma_flags |= DMA_PREP_FENCE;
Dan Williamsb2f46fd2009-07-14 12:20:36 -070071
Dan Williams7476bd792013-10-18 19:35:29 +020072 /* Drivers force forward progress in case they can not provide
73 * a descriptor
Dan Williamsb2f46fd2009-07-14 12:20:36 -070074 */
75 for (;;) {
Dan Williams7476bd792013-10-18 19:35:29 +020076 dma_dest[0] = unmap->addr[disks - 2];
77 dma_dest[1] = unmap->addr[disks - 1];
Dan Williamsb2f46fd2009-07-14 12:20:36 -070078 tx = dma->device_prep_dma_pq(chan, dma_dest,
Dan Williams7476bd792013-10-18 19:35:29 +020079 &unmap->addr[src_off],
Dan Williamsb2f46fd2009-07-14 12:20:36 -070080 pq_src_cnt,
Dan Williams7476bd792013-10-18 19:35:29 +020081 &scfs[src_off], unmap->len,
Dan Williamsb2f46fd2009-07-14 12:20:36 -070082 dma_flags);
83 if (likely(tx))
84 break;
85 async_tx_quiesce(&submit->depend_tx);
86 dma_async_issue_pending(chan);
87 }
88
Dan Williams7476bd792013-10-18 19:35:29 +020089 dma_set_unmap(tx, unmap);
Dan Williamsb2f46fd2009-07-14 12:20:36 -070090 async_tx_submit(chan, tx, submit);
91 submit->depend_tx = tx;
92
93 /* drop completed sources */
94 src_cnt -= pq_src_cnt;
95 src_off += pq_src_cnt;
96
97 dma_flags |= DMA_PREP_CONTINUE;
98 }
99
100 return tx;
101}
102
103/**
104 * do_sync_gen_syndrome - synchronously calculate a raid6 syndrome
105 */
106static void
Yufen Yud69454b2020-08-20 09:22:10 -0400107do_sync_gen_syndrome(struct page **blocks, unsigned int *offsets, int disks,
Dan Williamsb2f46fd2009-07-14 12:20:36 -0700108 size_t len, struct async_submit_ctl *submit)
109{
110 void **srcs;
111 int i;
Markus Stockhausen584acdd2014-12-15 12:57:05 +1100112 int start = -1, stop = disks - 3;
Dan Williamsb2f46fd2009-07-14 12:20:36 -0700113
114 if (submit->scribble)
115 srcs = submit->scribble;
116 else
117 srcs = (void **) blocks;
118
119 for (i = 0; i < disks; i++) {
NeilBrown5dd33c92009-10-16 16:40:25 +1100120 if (blocks[i] == NULL) {
Dan Williamsb2f46fd2009-07-14 12:20:36 -0700121 BUG_ON(i > disks - 3); /* P or Q can't be zero */
NeilBrown5dd33c92009-10-16 16:40:25 +1100122 srcs[i] = (void*)raid6_empty_zero_page;
Markus Stockhausen584acdd2014-12-15 12:57:05 +1100123 } else {
Yufen Yud69454b2020-08-20 09:22:10 -0400124 srcs[i] = page_address(blocks[i]) + offsets[i];
125
Markus Stockhausen584acdd2014-12-15 12:57:05 +1100126 if (i < disks - 2) {
127 stop = i;
128 if (start == -1)
129 start = i;
130 }
131 }
Dan Williamsb2f46fd2009-07-14 12:20:36 -0700132 }
Markus Stockhausen584acdd2014-12-15 12:57:05 +1100133 if (submit->flags & ASYNC_TX_PQ_XOR_DST) {
134 BUG_ON(!raid6_call.xor_syndrome);
135 if (start >= 0)
136 raid6_call.xor_syndrome(disks, start, stop, len, srcs);
137 } else
138 raid6_call.gen_syndrome(disks, len, srcs);
Dan Williamsb2f46fd2009-07-14 12:20:36 -0700139 async_tx_sync_epilog(submit);
140}
141
Yufen Yud69454b2020-08-20 09:22:10 -0400142static inline bool
143is_dma_pq_aligned_offs(struct dma_device *dev, unsigned int *offs,
144 int src_cnt, size_t len)
145{
146 int i;
147
148 for (i = 0; i < src_cnt; i++) {
149 if (!is_dma_pq_aligned(dev, offs[i], 0, len))
150 return false;
151 }
152 return true;
153}
154
Dan Williamsb2f46fd2009-07-14 12:20:36 -0700155/**
156 * async_gen_syndrome - asynchronously calculate a raid6 syndrome
157 * @blocks: source blocks from idx 0..disks-3, P @ disks-2 and Q @ disks-1
Yufen Yud69454b2020-08-20 09:22:10 -0400158 * @offsets: offset array into each block (src and dest) to start transaction
Dan Williamsb2f46fd2009-07-14 12:20:36 -0700159 * @disks: number of blocks (including missing P or Q, see below)
160 * @len: length of operation in bytes
161 * @submit: submission/completion modifiers
162 *
163 * General note: This routine assumes a field of GF(2^8) with a
164 * primitive polynomial of 0x11d and a generator of {02}.
165 *
166 * 'disks' note: callers can optionally omit either P or Q (but not
167 * both) from the calculation by setting blocks[disks-2] or
168 * blocks[disks-1] to NULL. When P or Q is omitted 'len' must be <=
169 * PAGE_SIZE as a temporary buffer of this size is used in the
170 * synchronous path. 'disks' always accounts for both destination
Dan Williams56764702009-10-19 18:09:32 -0700171 * buffers. If any source buffers (blocks[i] where i < disks - 2) are
172 * set to NULL those buffers will be replaced with the raid6_zero_page
173 * in the synchronous path and omitted in the hardware-asynchronous
174 * path.
Dan Williamsb2f46fd2009-07-14 12:20:36 -0700175 */
176struct dma_async_tx_descriptor *
Yufen Yud69454b2020-08-20 09:22:10 -0400177async_gen_syndrome(struct page **blocks, unsigned int *offsets, int disks,
Dan Williamsb2f46fd2009-07-14 12:20:36 -0700178 size_t len, struct async_submit_ctl *submit)
179{
180 int src_cnt = disks - 2;
181 struct dma_chan *chan = async_tx_find_channel(submit, DMA_PQ,
182 &P(blocks, disks), 2,
183 blocks, src_cnt, len);
184 struct dma_device *device = chan ? chan->device : NULL;
Dan Williams7476bd792013-10-18 19:35:29 +0200185 struct dmaengine_unmap_data *unmap = NULL;
Dan Williamsb2f46fd2009-07-14 12:20:36 -0700186
Kyle Spiers89a7e2f2018-06-01 13:20:16 -0700187 BUG_ON(disks > MAX_DISKS || !(P(blocks, disks) || Q(blocks, disks)));
Dan Williamsb2f46fd2009-07-14 12:20:36 -0700188
Dan Williams7476bd792013-10-18 19:35:29 +0200189 if (device)
NeilBrownb02bab62016-01-07 11:02:34 +1100190 unmap = dmaengine_get_unmap_data(device->dev, disks, GFP_NOWAIT);
Dan Williamsb2f46fd2009-07-14 12:20:36 -0700191
Markus Stockhausen584acdd2014-12-15 12:57:05 +1100192 /* XORing P/Q is only implemented in software */
193 if (unmap && !(submit->flags & ASYNC_TX_PQ_XOR_DST) &&
Dan Williamsb2f46fd2009-07-14 12:20:36 -0700194 (src_cnt <= dma_maxpq(device, 0) ||
Dan Williams83544ae2009-09-08 17:42:53 -0700195 dma_maxpq(device, DMA_PREP_CONTINUE) > 0) &&
Yufen Yud69454b2020-08-20 09:22:10 -0400196 is_dma_pq_aligned_offs(device, offsets, disks, len)) {
Dan Williams7476bd792013-10-18 19:35:29 +0200197 struct dma_async_tx_descriptor *tx;
198 enum dma_ctrl_flags dma_flags = 0;
Kyle Spiers89a7e2f2018-06-01 13:20:16 -0700199 unsigned char coefs[MAX_DISKS];
Dan Williams7476bd792013-10-18 19:35:29 +0200200 int i, j;
201
Dan Williamsb2f46fd2009-07-14 12:20:36 -0700202 /* run the p+q asynchronously */
203 pr_debug("%s: (async) disks: %d len: %zu\n",
204 __func__, disks, len);
Dan Williams7476bd792013-10-18 19:35:29 +0200205
206 /* convert source addresses being careful to collapse 'empty'
207 * sources and update the coefficients accordingly
208 */
209 unmap->len = len;
210 for (i = 0, j = 0; i < src_cnt; i++) {
211 if (blocks[i] == NULL)
212 continue;
Yufen Yud69454b2020-08-20 09:22:10 -0400213 unmap->addr[j] = dma_map_page(device->dev, blocks[i],
214 offsets[i], len, DMA_TO_DEVICE);
Dan Williams7476bd792013-10-18 19:35:29 +0200215 coefs[j] = raid6_gfexp[i];
216 unmap->to_cnt++;
217 j++;
218 }
219
220 /*
221 * DMAs use destinations as sources,
222 * so use BIDIRECTIONAL mapping
223 */
224 unmap->bidi_cnt++;
225 if (P(blocks, disks))
226 unmap->addr[j++] = dma_map_page(device->dev, P(blocks, disks),
Yufen Yud69454b2020-08-20 09:22:10 -0400227 P(offsets, disks),
228 len, DMA_BIDIRECTIONAL);
Dan Williams7476bd792013-10-18 19:35:29 +0200229 else {
230 unmap->addr[j++] = 0;
231 dma_flags |= DMA_PREP_PQ_DISABLE_P;
232 }
233
234 unmap->bidi_cnt++;
235 if (Q(blocks, disks))
236 unmap->addr[j++] = dma_map_page(device->dev, Q(blocks, disks),
Yufen Yud69454b2020-08-20 09:22:10 -0400237 Q(offsets, disks),
238 len, DMA_BIDIRECTIONAL);
Dan Williams7476bd792013-10-18 19:35:29 +0200239 else {
240 unmap->addr[j++] = 0;
241 dma_flags |= DMA_PREP_PQ_DISABLE_Q;
242 }
243
244 tx = do_async_gen_syndrome(chan, coefs, j, unmap, dma_flags, submit);
245 dmaengine_unmap_put(unmap);
246 return tx;
Dan Williamsb2f46fd2009-07-14 12:20:36 -0700247 }
248
Dan Williams7476bd792013-10-18 19:35:29 +0200249 dmaengine_unmap_put(unmap);
250
Dan Williamsb2f46fd2009-07-14 12:20:36 -0700251 /* run the pq synchronously */
252 pr_debug("%s: (sync) disks: %d len: %zu\n", __func__, disks, len);
253
254 /* wait for any prerequisite operations */
255 async_tx_quiesce(&submit->depend_tx);
256
257 if (!P(blocks, disks)) {
Dan Williams030b0772009-10-19 18:09:32 -0700258 P(blocks, disks) = pq_scribble_page;
Yufen Yud69454b2020-08-20 09:22:10 -0400259 P(offsets, disks) = 0;
Dan Williamsb2f46fd2009-07-14 12:20:36 -0700260 }
261 if (!Q(blocks, disks)) {
Dan Williams030b0772009-10-19 18:09:32 -0700262 Q(blocks, disks) = pq_scribble_page;
Yufen Yud69454b2020-08-20 09:22:10 -0400263 Q(offsets, disks) = 0;
Dan Williamsb2f46fd2009-07-14 12:20:36 -0700264 }
Yufen Yud69454b2020-08-20 09:22:10 -0400265 do_sync_gen_syndrome(blocks, offsets, disks, len, submit);
Dan Williamsb2f46fd2009-07-14 12:20:36 -0700266
267 return NULL;
268}
269EXPORT_SYMBOL_GPL(async_gen_syndrome);
270
Dan Williams7b3cc2b2009-11-19 17:10:37 -0700271static inline struct dma_chan *
272pq_val_chan(struct async_submit_ctl *submit, struct page **blocks, int disks, size_t len)
273{
274 #ifdef CONFIG_ASYNC_TX_DISABLE_PQ_VAL_DMA
275 return NULL;
276 #endif
277 return async_tx_find_channel(submit, DMA_PQ_VAL, NULL, 0, blocks,
278 disks, len);
279}
280
Dan Williamsb2f46fd2009-07-14 12:20:36 -0700281/**
282 * async_syndrome_val - asynchronously validate a raid6 syndrome
283 * @blocks: source blocks from idx 0..disks-3, P @ disks-2 and Q @ disks-1
284 * @offset: common offset into each block (src and dest) to start transaction
285 * @disks: number of blocks (including missing P or Q, see below)
286 * @len: length of operation in bytes
287 * @pqres: on val failure SUM_CHECK_P_RESULT and/or SUM_CHECK_Q_RESULT are set
288 * @spare: temporary result buffer for the synchronous case
Yufen Yud69454b2020-08-20 09:22:10 -0400289 * @s_off: spare buffer page offset
Dan Williamsb2f46fd2009-07-14 12:20:36 -0700290 * @submit: submission / completion modifiers
291 *
292 * The same notes from async_gen_syndrome apply to the 'blocks',
293 * and 'disks' parameters of this routine. The synchronous path
294 * requires a temporary result buffer and submit->scribble to be
295 * specified.
296 */
297struct dma_async_tx_descriptor *
Yufen Yud69454b2020-08-20 09:22:10 -0400298async_syndrome_val(struct page **blocks, unsigned int *offsets, int disks,
Dan Williamsb2f46fd2009-07-14 12:20:36 -0700299 size_t len, enum sum_check_flags *pqres, struct page *spare,
Yufen Yud69454b2020-08-20 09:22:10 -0400300 unsigned int s_off, struct async_submit_ctl *submit)
Dan Williamsb2f46fd2009-07-14 12:20:36 -0700301{
Dan Williams7b3cc2b2009-11-19 17:10:37 -0700302 struct dma_chan *chan = pq_val_chan(submit, blocks, disks, len);
Dan Williamsb2f46fd2009-07-14 12:20:36 -0700303 struct dma_device *device = chan ? chan->device : NULL;
304 struct dma_async_tx_descriptor *tx;
Kyle Spiers89a7e2f2018-06-01 13:20:16 -0700305 unsigned char coefs[MAX_DISKS];
Dan Williamsb2f46fd2009-07-14 12:20:36 -0700306 enum dma_ctrl_flags dma_flags = submit->cb_fn ? DMA_PREP_INTERRUPT : 0;
Dan Williams1786b942013-10-18 19:35:30 +0200307 struct dmaengine_unmap_data *unmap = NULL;
Dan Williamsb2f46fd2009-07-14 12:20:36 -0700308
Kyle Spiers89a7e2f2018-06-01 13:20:16 -0700309 BUG_ON(disks < 4 || disks > MAX_DISKS);
Dan Williamsb2f46fd2009-07-14 12:20:36 -0700310
Dan Williams1786b942013-10-18 19:35:30 +0200311 if (device)
NeilBrownb02bab62016-01-07 11:02:34 +1100312 unmap = dmaengine_get_unmap_data(device->dev, disks, GFP_NOWAIT);
Dan Williamsb2f46fd2009-07-14 12:20:36 -0700313
Dan Williams1786b942013-10-18 19:35:30 +0200314 if (unmap && disks <= dma_maxpq(device, 0) &&
Yufen Yud69454b2020-08-20 09:22:10 -0400315 is_dma_pq_aligned_offs(device, offsets, disks, len)) {
Dan Williamsb2f46fd2009-07-14 12:20:36 -0700316 struct device *dev = device->dev;
Dan Williams1786b942013-10-18 19:35:30 +0200317 dma_addr_t pq[2];
318 int i, j = 0, src_cnt = 0;
Dan Williamsb2f46fd2009-07-14 12:20:36 -0700319
320 pr_debug("%s: (async) disks: %d len: %zu\n",
321 __func__, disks, len);
Dan Williams1786b942013-10-18 19:35:30 +0200322
323 unmap->len = len;
324 for (i = 0; i < disks-2; i++)
325 if (likely(blocks[i])) {
326 unmap->addr[j] = dma_map_page(dev, blocks[i],
Yufen Yud69454b2020-08-20 09:22:10 -0400327 offsets[i], len,
Dan Williams1786b942013-10-18 19:35:30 +0200328 DMA_TO_DEVICE);
329 coefs[j] = raid6_gfexp[i];
330 unmap->to_cnt++;
331 src_cnt++;
332 j++;
333 }
334
335 if (!P(blocks, disks)) {
336 pq[0] = 0;
Dan Williamsb2f46fd2009-07-14 12:20:36 -0700337 dma_flags |= DMA_PREP_PQ_DISABLE_P;
Dan Williams1786b942013-10-18 19:35:30 +0200338 } else {
Dan Williams56764702009-10-19 18:09:32 -0700339 pq[0] = dma_map_page(dev, P(blocks, disks),
Yufen Yud69454b2020-08-20 09:22:10 -0400340 P(offsets, disks), len,
NeilBrownb2141e62009-10-16 16:40:34 +1100341 DMA_TO_DEVICE);
Dan Williams1786b942013-10-18 19:35:30 +0200342 unmap->addr[j++] = pq[0];
343 unmap->to_cnt++;
344 }
345 if (!Q(blocks, disks)) {
346 pq[1] = 0;
Dan Williamsb2f46fd2009-07-14 12:20:36 -0700347 dma_flags |= DMA_PREP_PQ_DISABLE_Q;
Dan Williams1786b942013-10-18 19:35:30 +0200348 } else {
Dan Williams56764702009-10-19 18:09:32 -0700349 pq[1] = dma_map_page(dev, Q(blocks, disks),
Yufen Yud69454b2020-08-20 09:22:10 -0400350 Q(offsets, disks), len,
NeilBrownb2141e62009-10-16 16:40:34 +1100351 DMA_TO_DEVICE);
Dan Williams1786b942013-10-18 19:35:30 +0200352 unmap->addr[j++] = pq[1];
353 unmap->to_cnt++;
354 }
NeilBrownb2141e62009-10-16 16:40:34 +1100355
Dan Williams0403e382009-09-08 17:42:50 -0700356 if (submit->flags & ASYNC_TX_FENCE)
357 dma_flags |= DMA_PREP_FENCE;
Dan Williamsb2f46fd2009-07-14 12:20:36 -0700358 for (;;) {
Dan Williams1786b942013-10-18 19:35:30 +0200359 tx = device->device_prep_dma_pq_val(chan, pq,
360 unmap->addr,
NeilBrownb2141e62009-10-16 16:40:34 +1100361 src_cnt,
362 coefs,
Dan Williamsb2f46fd2009-07-14 12:20:36 -0700363 len, pqres,
364 dma_flags);
365 if (likely(tx))
366 break;
367 async_tx_quiesce(&submit->depend_tx);
368 dma_async_issue_pending(chan);
369 }
Dan Williams1786b942013-10-18 19:35:30 +0200370
371 dma_set_unmap(tx, unmap);
Dan Williamsb2f46fd2009-07-14 12:20:36 -0700372 async_tx_submit(chan, tx, submit);
Dan Williamsb2f46fd2009-07-14 12:20:36 -0700373 } else {
374 struct page *p_src = P(blocks, disks);
Yufen Yud69454b2020-08-20 09:22:10 -0400375 unsigned int p_off = P(offsets, disks);
Dan Williamsb2f46fd2009-07-14 12:20:36 -0700376 struct page *q_src = Q(blocks, disks);
Yufen Yud69454b2020-08-20 09:22:10 -0400377 unsigned int q_off = Q(offsets, disks);
Dan Williamsb2f46fd2009-07-14 12:20:36 -0700378 enum async_tx_flags flags_orig = submit->flags;
379 dma_async_tx_callback cb_fn_orig = submit->cb_fn;
380 void *scribble = submit->scribble;
381 void *cb_param_orig = submit->cb_param;
382 void *p, *q, *s;
383
384 pr_debug("%s: (sync) disks: %d len: %zu\n",
385 __func__, disks, len);
386
387 /* caller must provide a temporary result buffer and
388 * allow the input parameters to be preserved
389 */
390 BUG_ON(!spare || !scribble);
391
392 /* wait for any prerequisite operations */
393 async_tx_quiesce(&submit->depend_tx);
394
395 /* recompute p and/or q into the temporary buffer and then
396 * check to see the result matches the current value
397 */
398 tx = NULL;
399 *pqres = 0;
400 if (p_src) {
401 init_async_submit(submit, ASYNC_TX_XOR_ZERO_DST, NULL,
402 NULL, NULL, scribble);
Yufen Yud69454b2020-08-20 09:22:10 -0400403 tx = async_xor_offs(spare, s_off,
404 blocks, offsets, disks-2, len, submit);
Dan Williamsb2f46fd2009-07-14 12:20:36 -0700405 async_tx_quiesce(&tx);
Yufen Yud69454b2020-08-20 09:22:10 -0400406 p = page_address(p_src) + p_off;
407 s = page_address(spare) + s_off;
Dan Williamsb2f46fd2009-07-14 12:20:36 -0700408 *pqres |= !!memcmp(p, s, len) << SUM_CHECK_P;
409 }
410
411 if (q_src) {
412 P(blocks, disks) = NULL;
413 Q(blocks, disks) = spare;
Yufen Yud69454b2020-08-20 09:22:10 -0400414 Q(offsets, disks) = s_off;
Dan Williamsb2f46fd2009-07-14 12:20:36 -0700415 init_async_submit(submit, 0, NULL, NULL, NULL, scribble);
Yufen Yud69454b2020-08-20 09:22:10 -0400416 tx = async_gen_syndrome(blocks, offsets, disks,
417 len, submit);
Dan Williamsb2f46fd2009-07-14 12:20:36 -0700418 async_tx_quiesce(&tx);
Yufen Yud69454b2020-08-20 09:22:10 -0400419 q = page_address(q_src) + q_off;
420 s = page_address(spare) + s_off;
Dan Williamsb2f46fd2009-07-14 12:20:36 -0700421 *pqres |= !!memcmp(q, s, len) << SUM_CHECK_Q;
422 }
423
424 /* restore P, Q and submit */
425 P(blocks, disks) = p_src;
Yufen Yud69454b2020-08-20 09:22:10 -0400426 P(offsets, disks) = p_off;
Dan Williamsb2f46fd2009-07-14 12:20:36 -0700427 Q(blocks, disks) = q_src;
Yufen Yud69454b2020-08-20 09:22:10 -0400428 Q(offsets, disks) = q_off;
Dan Williamsb2f46fd2009-07-14 12:20:36 -0700429
430 submit->cb_fn = cb_fn_orig;
431 submit->cb_param = cb_param_orig;
432 submit->flags = flags_orig;
433 async_tx_sync_epilog(submit);
Justin Maggardc8475092016-10-04 13:17:58 -0700434 tx = NULL;
Dan Williamsb2f46fd2009-07-14 12:20:36 -0700435 }
Justin Maggardc8475092016-10-04 13:17:58 -0700436 dmaengine_unmap_put(unmap);
437
438 return tx;
Dan Williamsb2f46fd2009-07-14 12:20:36 -0700439}
440EXPORT_SYMBOL_GPL(async_syndrome_val);
441
442static int __init async_pq_init(void)
443{
Dan Williams030b0772009-10-19 18:09:32 -0700444 pq_scribble_page = alloc_page(GFP_KERNEL);
Dan Williamsb2f46fd2009-07-14 12:20:36 -0700445
Dan Williams030b0772009-10-19 18:09:32 -0700446 if (pq_scribble_page)
Dan Williamsb2f46fd2009-07-14 12:20:36 -0700447 return 0;
448
449 pr_err("%s: failed to allocate required spare page\n", __func__);
450
451 return -ENOMEM;
452}
453
454static void __exit async_pq_exit(void)
455{
Joonsoo Kim95813b82016-03-17 14:19:29 -0700456 __free_page(pq_scribble_page);
Dan Williamsb2f46fd2009-07-14 12:20:36 -0700457}
458
459module_init(async_pq_init);
460module_exit(async_pq_exit);
461
462MODULE_DESCRIPTION("asynchronous raid6 syndrome generation/validation");
463MODULE_LICENSE("GPL");