Thomas Gleixner | d2912cb | 2019-06-04 10:11:33 +0200 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0-only |
Paul Walmsley | c0718df | 2011-03-10 22:17:45 -0700 | [diff] [blame] | 2 | /* |
| 3 | * OMAP3 Voltage Processor (VP) data |
| 4 | * |
| 5 | * Copyright (C) 2007, 2010 Texas Instruments, Inc. |
| 6 | * Rajendra Nayak <rnayak@ti.com> |
| 7 | * Lesly A M <x0080970@ti.com> |
| 8 | * Thara Gopinath <thara@ti.com> |
| 9 | * |
| 10 | * Copyright (C) 2008, 2011 Nokia Corporation |
| 11 | * Kalle Jokiniemi |
| 12 | * Paul Walmsley |
Paul Walmsley | c0718df | 2011-03-10 22:17:45 -0700 | [diff] [blame] | 13 | */ |
| 14 | |
| 15 | #include <linux/io.h> |
| 16 | #include <linux/err.h> |
| 17 | #include <linux/init.h> |
| 18 | |
Tony Lindgren | 4e65331 | 2011-11-10 22:45:17 +0100 | [diff] [blame] | 19 | #include "common.h" |
Paul Walmsley | c0718df | 2011-03-10 22:17:45 -0700 | [diff] [blame] | 20 | |
| 21 | #include "prm44xx.h" |
| 22 | #include "prm-regbits-44xx.h" |
| 23 | #include "voltage.h" |
| 24 | |
| 25 | #include "vp.h" |
| 26 | |
Kevin Hilman | 58aaa59 | 2011-03-28 10:52:04 -0700 | [diff] [blame] | 27 | static const struct omap_vp_ops omap4_vp_ops = { |
Tero Kristo | e9f1ddc | 2014-04-04 15:52:01 +0300 | [diff] [blame] | 28 | .check_txdone = omap_prm_vp_check_txdone, |
| 29 | .clear_txdone = omap_prm_vp_clear_txdone, |
Kevin Hilman | 58aaa59 | 2011-03-28 10:52:04 -0700 | [diff] [blame] | 30 | }; |
| 31 | |
Paul Walmsley | c0718df | 2011-03-10 22:17:45 -0700 | [diff] [blame] | 32 | /* |
| 33 | * VP data common to 44xx chips |
| 34 | * XXX This stuff presumably belongs in the vp44xx.c or vp.c file. |
| 35 | */ |
Kevin Hilman | b7ea803 | 2011-04-04 15:25:07 -0700 | [diff] [blame] | 36 | static const struct omap_vp_common omap4_vp_common = { |
Kevin Hilman | 0ec3041 | 2011-04-04 16:02:28 -0700 | [diff] [blame] | 37 | .vpconfig_erroroffset_mask = OMAP4430_ERROROFFSET_MASK, |
Paul Walmsley | c0718df | 2011-03-10 22:17:45 -0700 | [diff] [blame] | 38 | .vpconfig_errorgain_mask = OMAP4430_ERRORGAIN_MASK, |
Paul Walmsley | c0718df | 2011-03-10 22:17:45 -0700 | [diff] [blame] | 39 | .vpconfig_initvoltage_mask = OMAP4430_INITVOLTAGE_MASK, |
| 40 | .vpconfig_timeouten = OMAP4430_TIMEOUTEN_MASK, |
| 41 | .vpconfig_initvdd = OMAP4430_INITVDD_MASK, |
| 42 | .vpconfig_forceupdate = OMAP4430_FORCEUPDATE_MASK, |
| 43 | .vpconfig_vpenable = OMAP4430_VPENABLE_MASK, |
| 44 | .vstepmin_smpswaittimemin_shift = OMAP4430_SMPSWAITTIMEMIN_SHIFT, |
| 45 | .vstepmax_smpswaittimemax_shift = OMAP4430_SMPSWAITTIMEMAX_SHIFT, |
| 46 | .vstepmin_stepmin_shift = OMAP4430_VSTEPMIN_SHIFT, |
| 47 | .vstepmax_stepmax_shift = OMAP4430_VSTEPMAX_SHIFT, |
| 48 | .vlimitto_vddmin_shift = OMAP4430_VDDMIN_SHIFT, |
| 49 | .vlimitto_vddmax_shift = OMAP4430_VDDMAX_SHIFT, |
| 50 | .vlimitto_timeout_shift = OMAP4430_TIMEOUT_SHIFT, |
Todd Poynor | bea30ed | 2011-05-27 19:15:59 -0700 | [diff] [blame] | 51 | .vpvoltage_mask = OMAP4430_VPVOLTAGE_MASK, |
Kevin Hilman | 58aaa59 | 2011-03-28 10:52:04 -0700 | [diff] [blame] | 52 | .ops = &omap4_vp_ops, |
Paul Walmsley | c0718df | 2011-03-10 22:17:45 -0700 | [diff] [blame] | 53 | }; |
| 54 | |
Kevin Hilman | b7ea803 | 2011-04-04 15:25:07 -0700 | [diff] [blame] | 55 | struct omap_vp_instance omap4_vp_mpu = { |
Kevin Hilman | 58aaa59 | 2011-03-28 10:52:04 -0700 | [diff] [blame] | 56 | .id = OMAP4_VP_VDD_MPU_ID, |
Kevin Hilman | b7ea803 | 2011-04-04 15:25:07 -0700 | [diff] [blame] | 57 | .common = &omap4_vp_common, |
Paul Walmsley | c0718df | 2011-03-10 22:17:45 -0700 | [diff] [blame] | 58 | .vpconfig = OMAP4_PRM_VP_MPU_CONFIG_OFFSET, |
| 59 | .vstepmin = OMAP4_PRM_VP_MPU_VSTEPMIN_OFFSET, |
| 60 | .vstepmax = OMAP4_PRM_VP_MPU_VSTEPMAX_OFFSET, |
| 61 | .vlimitto = OMAP4_PRM_VP_MPU_VLIMITTO_OFFSET, |
| 62 | .vstatus = OMAP4_PRM_VP_MPU_STATUS_OFFSET, |
| 63 | .voltage = OMAP4_PRM_VP_MPU_VOLTAGE_OFFSET, |
Paul Walmsley | c0718df | 2011-03-10 22:17:45 -0700 | [diff] [blame] | 64 | }; |
| 65 | |
Kevin Hilman | b7ea803 | 2011-04-04 15:25:07 -0700 | [diff] [blame] | 66 | struct omap_vp_instance omap4_vp_iva = { |
Kevin Hilman | 58aaa59 | 2011-03-28 10:52:04 -0700 | [diff] [blame] | 67 | .id = OMAP4_VP_VDD_IVA_ID, |
Kevin Hilman | b7ea803 | 2011-04-04 15:25:07 -0700 | [diff] [blame] | 68 | .common = &omap4_vp_common, |
Paul Walmsley | c0718df | 2011-03-10 22:17:45 -0700 | [diff] [blame] | 69 | .vpconfig = OMAP4_PRM_VP_IVA_CONFIG_OFFSET, |
| 70 | .vstepmin = OMAP4_PRM_VP_IVA_VSTEPMIN_OFFSET, |
| 71 | .vstepmax = OMAP4_PRM_VP_IVA_VSTEPMAX_OFFSET, |
| 72 | .vlimitto = OMAP4_PRM_VP_IVA_VLIMITTO_OFFSET, |
| 73 | .vstatus = OMAP4_PRM_VP_IVA_STATUS_OFFSET, |
| 74 | .voltage = OMAP4_PRM_VP_IVA_VOLTAGE_OFFSET, |
Paul Walmsley | c0718df | 2011-03-10 22:17:45 -0700 | [diff] [blame] | 75 | }; |
| 76 | |
Kevin Hilman | b7ea803 | 2011-04-04 15:25:07 -0700 | [diff] [blame] | 77 | struct omap_vp_instance omap4_vp_core = { |
Kevin Hilman | 58aaa59 | 2011-03-28 10:52:04 -0700 | [diff] [blame] | 78 | .id = OMAP4_VP_VDD_CORE_ID, |
Kevin Hilman | b7ea803 | 2011-04-04 15:25:07 -0700 | [diff] [blame] | 79 | .common = &omap4_vp_common, |
Paul Walmsley | c0718df | 2011-03-10 22:17:45 -0700 | [diff] [blame] | 80 | .vpconfig = OMAP4_PRM_VP_CORE_CONFIG_OFFSET, |
| 81 | .vstepmin = OMAP4_PRM_VP_CORE_VSTEPMIN_OFFSET, |
| 82 | .vstepmax = OMAP4_PRM_VP_CORE_VSTEPMAX_OFFSET, |
| 83 | .vlimitto = OMAP4_PRM_VP_CORE_VLIMITTO_OFFSET, |
| 84 | .vstatus = OMAP4_PRM_VP_CORE_STATUS_OFFSET, |
| 85 | .voltage = OMAP4_PRM_VP_CORE_VOLTAGE_OFFSET, |
Paul Walmsley | c0718df | 2011-03-10 22:17:45 -0700 | [diff] [blame] | 86 | }; |
Tero Kristo | 8b5d8c0 | 2012-09-25 19:33:35 +0300 | [diff] [blame] | 87 | |
| 88 | struct omap_vp_param omap4_mpu_vp_data = { |
| 89 | .vddmin = OMAP4_VP_MPU_VLIMITTO_VDDMIN, |
| 90 | .vddmax = OMAP4_VP_MPU_VLIMITTO_VDDMAX, |
| 91 | }; |
| 92 | |
| 93 | struct omap_vp_param omap4_iva_vp_data = { |
| 94 | .vddmin = OMAP4_VP_IVA_VLIMITTO_VDDMIN, |
| 95 | .vddmax = OMAP4_VP_IVA_VLIMITTO_VDDMAX, |
| 96 | }; |
| 97 | |
| 98 | struct omap_vp_param omap4_core_vp_data = { |
| 99 | .vddmin = OMAP4_VP_CORE_VLIMITTO_VDDMIN, |
| 100 | .vddmax = OMAP4_VP_CORE_VLIMITTO_VDDMAX, |
| 101 | }; |