Benjamin Herrenschmidt | 243e251 | 2017-04-05 17:54:50 +1000 | [diff] [blame] | 1 | /* |
| 2 | * Copyright 2016,2017 IBM Corporation. |
| 3 | * |
| 4 | * This program is free software; you can redistribute it and/or |
| 5 | * modify it under the terms of the GNU General Public License |
| 6 | * as published by the Free Software Foundation; either version |
| 7 | * 2 of the License, or (at your option) any later version. |
| 8 | */ |
| 9 | #ifndef _ASM_POWERPC_XIVE_REGS_H |
| 10 | #define _ASM_POWERPC_XIVE_REGS_H |
| 11 | |
| 12 | /* |
| 13 | * Thread Management (aka "TM") registers |
| 14 | */ |
| 15 | |
| 16 | /* TM register offsets */ |
| 17 | #define TM_QW0_USER 0x000 /* All rings */ |
| 18 | #define TM_QW1_OS 0x010 /* Ring 0..2 */ |
| 19 | #define TM_QW2_HV_POOL 0x020 /* Ring 0..1 */ |
| 20 | #define TM_QW3_HV_PHYS 0x030 /* Ring 0..1 */ |
| 21 | |
| 22 | /* Byte offsets inside a QW QW0 QW1 QW2 QW3 */ |
| 23 | #define TM_NSR 0x0 /* + + - + */ |
| 24 | #define TM_CPPR 0x1 /* - + - + */ |
| 25 | #define TM_IPB 0x2 /* - + + + */ |
| 26 | #define TM_LSMFB 0x3 /* - + + + */ |
| 27 | #define TM_ACK_CNT 0x4 /* - + - - */ |
| 28 | #define TM_INC 0x5 /* - + - + */ |
| 29 | #define TM_AGE 0x6 /* - + - + */ |
| 30 | #define TM_PIPR 0x7 /* - + - + */ |
| 31 | |
| 32 | #define TM_WORD0 0x0 |
| 33 | #define TM_WORD1 0x4 |
| 34 | |
| 35 | /* |
| 36 | * QW word 2 contains the valid bit at the top and other fields |
| 37 | * depending on the QW. |
| 38 | */ |
| 39 | #define TM_WORD2 0x8 |
| 40 | #define TM_QW0W2_VU PPC_BIT32(0) |
| 41 | #define TM_QW0W2_LOGIC_SERV PPC_BITMASK32(1,31) // XX 2,31 ? |
| 42 | #define TM_QW1W2_VO PPC_BIT32(0) |
| 43 | #define TM_QW1W2_OS_CAM PPC_BITMASK32(8,31) |
| 44 | #define TM_QW2W2_VP PPC_BIT32(0) |
| 45 | #define TM_QW2W2_POOL_CAM PPC_BITMASK32(8,31) |
| 46 | #define TM_QW3W2_VT PPC_BIT32(0) |
| 47 | #define TM_QW3W2_LP PPC_BIT32(6) |
| 48 | #define TM_QW3W2_LE PPC_BIT32(7) |
| 49 | #define TM_QW3W2_T PPC_BIT32(31) |
| 50 | |
| 51 | /* |
| 52 | * In addition to normal loads to "peek" and writes (only when invalid) |
| 53 | * using 4 and 8 bytes accesses, the above registers support these |
| 54 | * "special" byte operations: |
| 55 | * |
| 56 | * - Byte load from QW0[NSR] - User level NSR (EBB) |
| 57 | * - Byte store to QW0[NSR] - User level NSR (EBB) |
| 58 | * - Byte load/store to QW1[CPPR] and QW3[CPPR] - CPPR access |
| 59 | * - Byte load from QW3[TM_WORD2] - Read VT||00000||LP||LE on thrd 0 |
| 60 | * otherwise VT||0000000 |
| 61 | * - Byte store to QW3[TM_WORD2] - Set VT bit (and LP/LE if present) |
| 62 | * |
| 63 | * Then we have all these "special" CI ops at these offset that trigger |
| 64 | * all sorts of side effects: |
| 65 | */ |
| 66 | #define TM_SPC_ACK_EBB 0x800 /* Load8 ack EBB to reg*/ |
| 67 | #define TM_SPC_ACK_OS_REG 0x810 /* Load16 ack OS irq to reg */ |
| 68 | #define TM_SPC_PUSH_USR_CTX 0x808 /* Store32 Push/Validate user context */ |
| 69 | #define TM_SPC_PULL_USR_CTX 0x808 /* Load32 Pull/Invalidate user context */ |
| 70 | #define TM_SPC_SET_OS_PENDING 0x812 /* Store8 Set OS irq pending bit */ |
| 71 | #define TM_SPC_PULL_OS_CTX 0x818 /* Load32/Load64 Pull/Invalidate OS context to reg */ |
| 72 | #define TM_SPC_PULL_POOL_CTX 0x828 /* Load32/Load64 Pull/Invalidate Pool context to reg*/ |
| 73 | #define TM_SPC_ACK_HV_REG 0x830 /* Load16 ack HV irq to reg */ |
| 74 | #define TM_SPC_PULL_USR_CTX_OL 0xc08 /* Store8 Pull/Inval usr ctx to odd line */ |
| 75 | #define TM_SPC_ACK_OS_EL 0xc10 /* Store8 ack OS irq to even line */ |
| 76 | #define TM_SPC_ACK_HV_POOL_EL 0xc20 /* Store8 ack HV evt pool to even line */ |
| 77 | #define TM_SPC_ACK_HV_EL 0xc30 /* Store8 ack HV irq to even line */ |
| 78 | /* XXX more... */ |
| 79 | |
| 80 | /* NSR fields for the various QW ack types */ |
| 81 | #define TM_QW0_NSR_EB PPC_BIT8(0) |
| 82 | #define TM_QW1_NSR_EO PPC_BIT8(0) |
| 83 | #define TM_QW3_NSR_HE PPC_BITMASK8(0,1) |
| 84 | #define TM_QW3_NSR_HE_NONE 0 |
| 85 | #define TM_QW3_NSR_HE_POOL 1 |
| 86 | #define TM_QW3_NSR_HE_PHYS 2 |
| 87 | #define TM_QW3_NSR_HE_LSI 3 |
| 88 | #define TM_QW3_NSR_I PPC_BIT8(2) |
| 89 | #define TM_QW3_NSR_GRP_LVL PPC_BIT8(3,7) |
| 90 | |
| 91 | /* Utilities to manipulate these (originaly from OPAL) */ |
| 92 | #define MASK_TO_LSH(m) (__builtin_ffsl(m) - 1) |
| 93 | #define GETFIELD(m, v) (((v) & (m)) >> MASK_TO_LSH(m)) |
| 94 | #define SETFIELD(m, v, val) \ |
| 95 | (((v) & ~(m)) | ((((typeof(v))(val)) << MASK_TO_LSH(m)) & (m))) |
| 96 | |
| 97 | #endif /* _ASM_POWERPC_XIVE_REGS_H */ |