| Mahesh Salgaonkar | e22a227 | 2013-10-30 20:05:11 +0530 | [diff] [blame^] | 1 | /* |
| 2 | * Machine check exception header file. |
| 3 | * |
| 4 | * This program is free software; you can redistribute it and/or modify |
| 5 | * it under the terms of the GNU General Public License as published by |
| 6 | * the Free Software Foundation; either version 2 of the License, or |
| 7 | * (at your option) any later version. |
| 8 | * |
| 9 | * This program is distributed in the hope that it will be useful, |
| 10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 12 | * GNU General Public License for more details. |
| 13 | * |
| 14 | * You should have received a copy of the GNU General Public License |
| 15 | * along with this program; if not, write to the Free Software |
| 16 | * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. |
| 17 | * |
| 18 | * Copyright 2013 IBM Corporation |
| 19 | * Author: Mahesh Salgaonkar <mahesh@linux.vnet.ibm.com> |
| 20 | */ |
| 21 | |
| 22 | #ifndef __ASM_PPC64_MCE_H__ |
| 23 | #define __ASM_PPC64_MCE_H__ |
| 24 | |
| 25 | #include <linux/bitops.h> |
| 26 | |
| 27 | /* |
| 28 | * Machine Check bits on power7 and power8 |
| 29 | */ |
| 30 | #define P7_SRR1_MC_LOADSTORE(srr1) ((srr1) & PPC_BIT(42)) /* P8 too */ |
| 31 | |
| 32 | /* SRR1 bits for machine check (On Power7 and Power8) */ |
| 33 | #define P7_SRR1_MC_IFETCH(srr1) ((srr1) & PPC_BITMASK(43, 45)) /* P8 too */ |
| 34 | |
| 35 | #define P7_SRR1_MC_IFETCH_UE (0x1 << PPC_BITLSHIFT(45)) /* P8 too */ |
| 36 | #define P7_SRR1_MC_IFETCH_SLB_PARITY (0x2 << PPC_BITLSHIFT(45)) /* P8 too */ |
| 37 | #define P7_SRR1_MC_IFETCH_SLB_MULTIHIT (0x3 << PPC_BITLSHIFT(45)) /* P8 too */ |
| 38 | #define P7_SRR1_MC_IFETCH_SLB_BOTH (0x4 << PPC_BITLSHIFT(45)) |
| 39 | #define P7_SRR1_MC_IFETCH_TLB_MULTIHIT (0x5 << PPC_BITLSHIFT(45)) /* P8 too */ |
| 40 | #define P7_SRR1_MC_IFETCH_UE_TLB_RELOAD (0x6 << PPC_BITLSHIFT(45)) /* P8 too */ |
| 41 | #define P7_SRR1_MC_IFETCH_UE_IFU_INTERNAL (0x7 << PPC_BITLSHIFT(45)) |
| 42 | |
| 43 | /* SRR1 bits for machine check (On Power8) */ |
| 44 | #define P8_SRR1_MC_IFETCH_ERAT_MULTIHIT (0x4 << PPC_BITLSHIFT(45)) |
| 45 | |
| 46 | /* DSISR bits for machine check (On Power7 and Power8) */ |
| 47 | #define P7_DSISR_MC_UE (PPC_BIT(48)) /* P8 too */ |
| 48 | #define P7_DSISR_MC_UE_TABLEWALK (PPC_BIT(49)) /* P8 too */ |
| 49 | #define P7_DSISR_MC_ERAT_MULTIHIT (PPC_BIT(52)) /* P8 too */ |
| 50 | #define P7_DSISR_MC_TLB_MULTIHIT_MFTLB (PPC_BIT(53)) /* P8 too */ |
| 51 | #define P7_DSISR_MC_SLB_PARITY_MFSLB (PPC_BIT(55)) /* P8 too */ |
| 52 | #define P7_DSISR_MC_SLB_MULTIHIT (PPC_BIT(56)) /* P8 too */ |
| 53 | #define P7_DSISR_MC_SLB_MULTIHIT_PARITY (PPC_BIT(57)) /* P8 too */ |
| 54 | |
| 55 | /* |
| 56 | * DSISR bits for machine check (Power8) in addition to above. |
| 57 | * Secondary DERAT Multihit |
| 58 | */ |
| 59 | #define P8_DSISR_MC_ERAT_MULTIHIT_SEC (PPC_BIT(54)) |
| 60 | |
| 61 | /* SLB error bits */ |
| 62 | #define P7_DSISR_MC_SLB_ERRORS (P7_DSISR_MC_ERAT_MULTIHIT | \ |
| 63 | P7_DSISR_MC_SLB_PARITY_MFSLB | \ |
| 64 | P7_DSISR_MC_SLB_MULTIHIT | \ |
| 65 | P7_DSISR_MC_SLB_MULTIHIT_PARITY) |
| 66 | |
| 67 | #endif /* __ASM_PPC64_MCE_H__ */ |