blob: 7ff11d6bf0f2be0d98a481376a702721617142ba [file] [log] [blame]
Tony Lindgrenf711c572018-09-24 16:20:37 -07001&l4_wkup { /* 0x44c00000 */
2 compatible = "ti,am33xx-l4-wkup", "simple-bus";
3 reg = <0x44c00000 0x800>,
4 <0x44c00800 0x800>,
5 <0x44c01000 0x400>,
6 <0x44c01400 0x400>;
7 reg-names = "ap", "la", "ia0", "ia1";
8 #address-cells = <1>;
9 #size-cells = <1>;
10 ranges = <0x00000000 0x44c00000 0x100000>, /* segment 0 */
11 <0x00100000 0x44d00000 0x100000>, /* segment 1 */
12 <0x00200000 0x44e00000 0x100000>; /* segment 2 */
13
14 segment@0 { /* 0x44c00000 */
15 compatible = "simple-bus";
16 #address-cells = <1>;
17 #size-cells = <1>;
18 ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */
19 <0x00000800 0x00000800 0x000800>, /* ap 1 */
20 <0x00001000 0x00001000 0x000400>, /* ap 2 */
21 <0x00001400 0x00001400 0x000400>; /* ap 3 */
22 };
23
24 segment@100000 { /* 0x44d00000 */
25 compatible = "simple-bus";
26 #address-cells = <1>;
27 #size-cells = <1>;
28 ranges = <0x00000000 0x00100000 0x004000>, /* ap 4 */
29 <0x00004000 0x00104000 0x001000>, /* ap 5 */
30 <0x00080000 0x00180000 0x002000>, /* ap 6 */
31 <0x00082000 0x00182000 0x001000>; /* ap 7 */
32
33 target-module@0 { /* 0x44d00000, ap 4 28.0 */
Tony Lindgren87fc89c2018-09-24 16:20:54 -070034 compatible = "ti,sysc-omap4", "ti,sysc";
35 reg = <0x0 0x4>;
36 reg-names = "rev";
Tony Lindgrenf711c572018-09-24 16:20:37 -070037 #address-cells = <1>;
38 #size-cells = <1>;
39 ranges = <0x0 0x0 0x4000>;
Tony Lindgren87fc89c2018-09-24 16:20:54 -070040 status = "disabled";
Tony Lindgrenf711c572018-09-24 16:20:37 -070041 };
42
43 target-module@80000 { /* 0x44d80000, ap 6 10.0 */
44 compatible = "ti,sysc";
45 status = "disabled";
46 #address-cells = <1>;
47 #size-cells = <1>;
48 ranges = <0x0 0x80000 0x2000>;
49 };
50 };
51
52 segment@200000 { /* 0x44e00000 */
53 compatible = "simple-bus";
54 #address-cells = <1>;
55 #size-cells = <1>;
56 ranges = <0x00000000 0x00200000 0x002000>, /* ap 8 */
57 <0x00002000 0x00202000 0x001000>, /* ap 9 */
58 <0x00003000 0x00203000 0x001000>, /* ap 10 */
59 <0x00004000 0x00204000 0x001000>, /* ap 11 */
60 <0x00005000 0x00205000 0x001000>, /* ap 12 */
61 <0x00006000 0x00206000 0x001000>, /* ap 13 */
62 <0x00007000 0x00207000 0x001000>, /* ap 14 */
63 <0x00008000 0x00208000 0x001000>, /* ap 15 */
64 <0x00009000 0x00209000 0x001000>, /* ap 16 */
65 <0x0000a000 0x0020a000 0x001000>, /* ap 17 */
66 <0x0000b000 0x0020b000 0x001000>, /* ap 18 */
67 <0x0000c000 0x0020c000 0x001000>, /* ap 19 */
68 <0x0000d000 0x0020d000 0x001000>, /* ap 20 */
69 <0x0000f000 0x0020f000 0x001000>, /* ap 21 */
70 <0x00010000 0x00210000 0x010000>, /* ap 22 */
71 <0x00020000 0x00220000 0x010000>, /* ap 23 */
72 <0x00030000 0x00230000 0x001000>, /* ap 24 */
73 <0x00031000 0x00231000 0x001000>, /* ap 25 */
74 <0x00032000 0x00232000 0x001000>, /* ap 26 */
75 <0x00033000 0x00233000 0x001000>, /* ap 27 */
76 <0x00034000 0x00234000 0x001000>, /* ap 28 */
77 <0x00035000 0x00235000 0x001000>, /* ap 29 */
78 <0x00036000 0x00236000 0x001000>, /* ap 30 */
79 <0x00037000 0x00237000 0x001000>, /* ap 31 */
80 <0x00038000 0x00238000 0x001000>, /* ap 32 */
81 <0x00039000 0x00239000 0x001000>, /* ap 33 */
82 <0x0003a000 0x0023a000 0x001000>, /* ap 34 */
83 <0x0003e000 0x0023e000 0x001000>, /* ap 35 */
84 <0x0003f000 0x0023f000 0x001000>, /* ap 36 */
85 <0x0000e000 0x0020e000 0x001000>, /* ap 37 */
86 <0x00040000 0x00240000 0x040000>, /* ap 38 */
87 <0x00080000 0x00280000 0x001000>; /* ap 39 */
88
89 target-module@0 { /* 0x44e00000, ap 8 58.0 */
Tony Lindgren87fc89c2018-09-24 16:20:54 -070090 compatible = "ti,sysc-omap4", "ti,sysc";
91 reg = <0 0x4>;
92 reg-names = "rev";
Tony Lindgrenf711c572018-09-24 16:20:37 -070093 #address-cells = <1>;
94 #size-cells = <1>;
95 ranges = <0x0 0x0 0x2000>;
Tony Lindgren87fc89c2018-09-24 16:20:54 -070096
97 prcm: prcm@0 {
98 compatible = "ti,am3-prcm", "simple-bus";
99 reg = <0 0x2000>;
100 #address-cells = <1>;
101 #size-cells = <1>;
102 ranges = <0 0 0x2000>;
103
104 prcm_clocks: clocks {
105 #address-cells = <1>;
106 #size-cells = <0>;
107 };
108
109 prcm_clockdomains: clockdomains {
110 };
111 };
Tony Lindgrenf711c572018-09-24 16:20:37 -0700112 };
113
114 target-module@3000 { /* 0x44e03000, ap 10 0a.0 */
115 compatible = "ti,sysc";
116 status = "disabled";
117 #address-cells = <1>;
118 #size-cells = <1>;
119 ranges = <0x0 0x3000 0x1000>;
120 };
121
122 target-module@5000 { /* 0x44e05000, ap 12 30.0 */
123 compatible = "ti,sysc";
124 status = "disabled";
125 #address-cells = <1>;
126 #size-cells = <1>;
127 ranges = <0x0 0x5000 0x1000>;
128 };
129
Tony Lindgren4ef5d762019-09-24 09:24:28 -0700130 gpio0_target: target-module@7000 { /* 0x44e07000, ap 14 20.0 */
Tony Lindgrenf711c572018-09-24 16:20:37 -0700131 compatible = "ti,sysc-omap2", "ti,sysc";
Tony Lindgrenf711c572018-09-24 16:20:37 -0700132 reg = <0x7000 0x4>,
133 <0x7010 0x4>,
134 <0x7114 0x4>;
135 reg-names = "rev", "sysc", "syss";
136 ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
137 SYSC_OMAP2_SOFTRESET |
138 SYSC_OMAP2_AUTOIDLE)>;
139 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
140 <SYSC_IDLE_NO>,
141 <SYSC_IDLE_SMART>,
142 <SYSC_IDLE_SMART_WKUP>;
143 ti,syss-mask = <1>;
144 /* Domains (P, C): wkup_pwrdm, l4_wkup_clkdm */
145 clocks = <&l4_wkup_clkctrl AM3_L4_WKUP_GPIO1_CLKCTRL 0>,
146 <&l4_wkup_clkctrl AM3_L4_WKUP_GPIO1_CLKCTRL 18>;
147 clock-names = "fck", "dbclk";
148 #address-cells = <1>;
149 #size-cells = <1>;
150 ranges = <0x0 0x7000 0x1000>;
Tony Lindgren87fc89c2018-09-24 16:20:54 -0700151
152 gpio0: gpio@0 {
153 compatible = "ti,omap4-gpio";
154 gpio-controller;
155 #gpio-cells = <2>;
156 interrupt-controller;
157 #interrupt-cells = <2>;
158 reg = <0x0 0x1000>;
159 interrupts = <96>;
160 };
Tony Lindgrenf711c572018-09-24 16:20:37 -0700161 };
162
163 target-module@9000 { /* 0x44e09000, ap 16 04.0 */
164 compatible = "ti,sysc-omap2", "ti,sysc";
Tony Lindgrenf711c572018-09-24 16:20:37 -0700165 reg = <0x9050 0x4>,
166 <0x9054 0x4>,
167 <0x9058 0x4>;
168 reg-names = "rev", "sysc", "syss";
169 ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
170 SYSC_OMAP2_SOFTRESET |
171 SYSC_OMAP2_AUTOIDLE)>;
172 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
173 <SYSC_IDLE_NO>,
174 <SYSC_IDLE_SMART>,
175 <SYSC_IDLE_SMART_WKUP>;
176 /* Domains (P, C): wkup_pwrdm, l4_wkup_clkdm */
177 clocks = <&l4_wkup_clkctrl AM3_L4_WKUP_UART1_CLKCTRL 0>;
178 clock-names = "fck";
179 #address-cells = <1>;
180 #size-cells = <1>;
181 ranges = <0x0 0x9000 0x1000>;
Tony Lindgren87fc89c2018-09-24 16:20:54 -0700182
183 uart0: serial@0 {
184 compatible = "ti,am3352-uart", "ti,omap3-uart";
185 clock-frequency = <48000000>;
Emmanuel Vadot8613e2c2019-07-24 14:23:29 +0200186 reg = <0x0 0x1000>;
Tony Lindgren87fc89c2018-09-24 16:20:54 -0700187 interrupts = <72>;
188 status = "disabled";
189 dmas = <&edma 26 0>, <&edma 27 0>;
190 dma-names = "tx", "rx";
191 };
Tony Lindgrenf711c572018-09-24 16:20:37 -0700192 };
193
194 target-module@b000 { /* 0x44e0b000, ap 18 48.0 */
195 compatible = "ti,sysc-omap2", "ti,sysc";
Tony Lindgrenf711c572018-09-24 16:20:37 -0700196 reg = <0xb000 0x8>,
197 <0xb010 0x8>,
198 <0xb090 0x8>;
199 reg-names = "rev", "sysc", "syss";
200 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
201 SYSC_OMAP2_ENAWAKEUP |
202 SYSC_OMAP2_SOFTRESET |
203 SYSC_OMAP2_AUTOIDLE)>;
204 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
205 <SYSC_IDLE_NO>,
206 <SYSC_IDLE_SMART>,
207 <SYSC_IDLE_SMART_WKUP>;
208 ti,syss-mask = <1>;
209 /* Domains (P, C): wkup_pwrdm, l4_wkup_clkdm */
210 clocks = <&l4_wkup_clkctrl AM3_L4_WKUP_I2C1_CLKCTRL 0>;
211 clock-names = "fck";
212 #address-cells = <1>;
213 #size-cells = <1>;
214 ranges = <0x0 0xb000 0x1000>;
Tony Lindgren87fc89c2018-09-24 16:20:54 -0700215
216 i2c0: i2c@0 {
217 compatible = "ti,omap4-i2c";
218 #address-cells = <1>;
219 #size-cells = <0>;
220 reg = <0x0 0x1000>;
221 interrupts = <70>;
222 status = "disabled";
223 };
Tony Lindgrenf711c572018-09-24 16:20:37 -0700224 };
225
226 target-module@d000 { /* 0x44e0d000, ap 20 38.0 */
227 compatible = "ti,sysc-omap4", "ti,sysc";
Tony Lindgrenf711c572018-09-24 16:20:37 -0700228 reg = <0xd000 0x4>,
229 <0xd010 0x4>;
230 reg-names = "rev", "sysc";
231 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
232 <SYSC_IDLE_NO>,
233 <SYSC_IDLE_SMART>,
234 <SYSC_IDLE_SMART_WKUP>;
235 /* Domains (P, C): wkup_pwrdm, l4_wkup_clkdm */
236 clocks = <&l4_wkup_clkctrl AM3_L4_WKUP_ADC_TSC_CLKCTRL 0>;
237 clock-names = "fck";
238 #address-cells = <1>;
239 #size-cells = <1>;
240 ranges = <0x00000000 0x0000d000 0x00001000>,
241 <0x00001000 0x0000e000 0x00001000>;
Tony Lindgren87fc89c2018-09-24 16:20:54 -0700242
243 tscadc: tscadc@0 {
244 compatible = "ti,am3359-tscadc";
245 reg = <0x0 0x1000>;
246 interrupts = <16>;
247 status = "disabled";
248 dmas = <&edma 53 0>, <&edma 57 0>;
249 dma-names = "fifo0", "fifo1";
250
251 tsc {
252 compatible = "ti,am3359-tsc";
253 };
254 am335x_adc: adc {
255 #io-channel-cells = <1>;
256 compatible = "ti,am3359-adc";
257 };
258 };
Tony Lindgrenf711c572018-09-24 16:20:37 -0700259 };
260
261 target-module@10000 { /* 0x44e10000, ap 22 0c.0 */
Tony Lindgren87fc89c2018-09-24 16:20:54 -0700262 compatible = "ti,sysc-omap4", "ti,sysc";
263 reg = <0x10000 0x4>;
264 reg-names = "rev";
Tony Lindgrenf711c572018-09-24 16:20:37 -0700265 #address-cells = <1>;
266 #size-cells = <1>;
267 ranges = <0x00000000 0x00010000 0x00010000>,
268 <0x00010000 0x00020000 0x00010000>;
Tony Lindgren87fc89c2018-09-24 16:20:54 -0700269
270 scm: scm@0 {
271 compatible = "ti,am3-scm", "simple-bus";
272 reg = <0x0 0x2000>;
273 #address-cells = <1>;
274 #size-cells = <1>;
275 #pinctrl-cells = <1>;
276 ranges = <0 0 0x2000>;
277
Tony Lindgren87fc89c2018-09-24 16:20:54 -0700278 am33xx_pinmux: pinmux@800 {
279 compatible = "pinctrl-single";
280 reg = <0x800 0x238>;
Tony Lindgren87fc89c2018-09-24 16:20:54 -0700281 #pinctrl-cells = <1>;
282 pinctrl-single,register-width = <32>;
283 pinctrl-single,function-mask = <0x7f>;
284 };
285
286 scm_conf: scm_conf@0 {
287 compatible = "syscon", "simple-bus";
288 reg = <0x0 0x800>;
289 #address-cells = <1>;
290 #size-cells = <1>;
291 ranges = <0 0 0x800>;
292
Grygorii Strashkofcfa0e82019-02-20 17:25:17 +0200293 phy_gmii_sel: phy-gmii-sel {
294 compatible = "ti,am3352-phy-gmii-sel";
295 reg = <0x650 0x4>;
296 #phy-cells = <2>;
297 };
298
Tony Lindgren87fc89c2018-09-24 16:20:54 -0700299 scm_clocks: clocks {
300 #address-cells = <1>;
301 #size-cells = <0>;
302 };
303 };
304
Tony Lindgren0782e852019-10-21 14:16:41 -0700305 usb_ctrl_mod: control@620 {
306 compatible = "ti,am335x-usb-ctrl-module";
307 reg = <0x620 0x10>,
308 <0x648 0x4>;
309 reg-names = "phy_ctrl", "wakeup";
310 };
311
Tony Lindgren87fc89c2018-09-24 16:20:54 -0700312 wkup_m3_ipc: wkup_m3_ipc@1324 {
313 compatible = "ti,am3352-wkup-m3-ipc";
314 reg = <0x1324 0x24>;
315 interrupts = <78>;
316 ti,rproc = <&wkup_m3>;
317 mboxes = <&mailbox &mbox_wkupm3>;
318 };
319
320 edma_xbar: dma-router@f90 {
321 compatible = "ti,am335x-edma-crossbar";
322 reg = <0xf90 0x40>;
323 #dma-cells = <3>;
324 dma-requests = <32>;
325 dma-masters = <&edma>;
326 };
327
328 scm_clockdomains: clockdomains {
329 };
330 };
Tony Lindgrenf711c572018-09-24 16:20:37 -0700331 };
332
Tony Lindgrene20ef232020-05-07 09:59:31 -0700333 timer1_target: target-module@31000 { /* 0x44e31000, ap 25 40.0 */
Tony Lindgrenf711c572018-09-24 16:20:37 -0700334 compatible = "ti,sysc-omap2-timer", "ti,sysc";
Tony Lindgrenf711c572018-09-24 16:20:37 -0700335 reg = <0x31000 0x4>,
336 <0x31010 0x4>,
337 <0x31014 0x4>;
338 reg-names = "rev", "sysc", "syss";
339 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
340 SYSC_OMAP2_SOFTRESET |
341 SYSC_OMAP2_AUTOIDLE)>;
342 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
343 <SYSC_IDLE_NO>,
344 <SYSC_IDLE_SMART>;
345 ti,syss-mask = <1>;
346 /* Domains (P, C): wkup_pwrdm, l4_wkup_clkdm */
347 clocks = <&l4_wkup_clkctrl AM3_L4_WKUP_TIMER1_CLKCTRL 0>;
348 clock-names = "fck";
349 #address-cells = <1>;
350 #size-cells = <1>;
351 ranges = <0x0 0x31000 0x1000>;
Tony Lindgren87fc89c2018-09-24 16:20:54 -0700352
353 timer1: timer@0 {
354 compatible = "ti,am335x-timer-1ms";
355 reg = <0x0 0x400>;
356 interrupts = <67>;
357 ti,timer-alwon;
358 clocks = <&timer1_fck>;
359 clock-names = "fck";
360 };
Tony Lindgrenf711c572018-09-24 16:20:37 -0700361 };
362
363 target-module@33000 { /* 0x44e33000, ap 27 18.0 */
364 compatible = "ti,sysc";
365 status = "disabled";
366 #address-cells = <1>;
367 #size-cells = <1>;
368 ranges = <0x0 0x33000 0x1000>;
369 };
370
371 target-module@35000 { /* 0x44e35000, ap 29 50.0 */
372 compatible = "ti,sysc-omap2", "ti,sysc";
Tony Lindgrenf711c572018-09-24 16:20:37 -0700373 reg = <0x35000 0x4>,
374 <0x35010 0x4>,
375 <0x35014 0x4>;
376 reg-names = "rev", "sysc", "syss";
377 ti,sysc-mask = <(SYSC_OMAP2_EMUFREE |
378 SYSC_OMAP2_SOFTRESET)>;
379 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
380 <SYSC_IDLE_NO>,
381 <SYSC_IDLE_SMART>,
382 <SYSC_IDLE_SMART_WKUP>;
383 ti,syss-mask = <1>;
384 /* Domains (P, C): wkup_pwrdm, l4_wkup_clkdm */
385 clocks = <&l4_wkup_clkctrl AM3_L4_WKUP_WD_TIMER2_CLKCTRL 0>;
386 clock-names = "fck";
387 #address-cells = <1>;
388 #size-cells = <1>;
389 ranges = <0x0 0x35000 0x1000>;
Tony Lindgren87fc89c2018-09-24 16:20:54 -0700390
391 wdt2: wdt@0 {
392 compatible = "ti,omap3-wdt";
393 reg = <0x0 0x1000>;
394 interrupts = <91>;
395 };
Tony Lindgrenf711c572018-09-24 16:20:37 -0700396 };
397
398 target-module@37000 { /* 0x44e37000, ap 31 08.0 */
399 compatible = "ti,sysc";
400 status = "disabled";
401 #address-cells = <1>;
402 #size-cells = <1>;
403 ranges = <0x0 0x37000 0x1000>;
404 };
405
406 target-module@39000 { /* 0x44e39000, ap 33 02.0 */
407 compatible = "ti,sysc";
408 status = "disabled";
409 #address-cells = <1>;
410 #size-cells = <1>;
411 ranges = <0x0 0x39000 0x1000>;
412 };
413
414 target-module@3e000 { /* 0x44e3e000, ap 35 60.0 */
415 compatible = "ti,sysc-omap4-simple", "ti,sysc";
416 ti,hwmods = "rtc";
417 reg = <0x3e074 0x4>,
418 <0x3e078 0x4>;
419 reg-names = "rev", "sysc";
420 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
421 <SYSC_IDLE_NO>,
422 <SYSC_IDLE_SMART>,
423 <SYSC_IDLE_SMART_WKUP>;
424 /* Domains (P, C): rtc_pwrdm, l4_rtc_clkdm */
425 clocks = <&l4_rtc_clkctrl AM3_L4_RTC_RTC_CLKCTRL 0>;
426 clock-names = "fck";
427 #address-cells = <1>;
428 #size-cells = <1>;
429 ranges = <0x0 0x3e000 0x1000>;
Tony Lindgren87fc89c2018-09-24 16:20:54 -0700430
431 rtc: rtc@0 {
432 compatible = "ti,am3352-rtc", "ti,da830-rtc";
433 reg = <0x0 0x1000>;
434 interrupts = <75
435 76>;
436 };
Tony Lindgrenf711c572018-09-24 16:20:37 -0700437 };
438
439 target-module@40000 { /* 0x44e40000, ap 38 68.0 */
440 compatible = "ti,sysc";
441 status = "disabled";
442 #address-cells = <1>;
443 #size-cells = <1>;
444 ranges = <0x0 0x40000 0x40000>;
445 };
446 };
447};
448
449&l4_fw { /* 0x47c00000 */
450 compatible = "ti,am33xx-l4-fw", "simple-bus";
451 reg = <0x47c00000 0x800>,
452 <0x47c00800 0x800>,
453 <0x47c01000 0x400>;
454 reg-names = "ap", "la", "ia0";
455 #address-cells = <1>;
456 #size-cells = <1>;
457 ranges = <0x00000000 0x47c00000 0x1000000>; /* segment 0 */
458
459 segment@0 { /* 0x47c00000 */
460 compatible = "simple-bus";
461 #address-cells = <1>;
462 #size-cells = <1>;
463 ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */
464 <0x00000800 0x00000800 0x000800>, /* ap 1 */
465 <0x00001000 0x00001000 0x000400>, /* ap 2 */
466 <0x0000c000 0x0000c000 0x001000>, /* ap 3 */
467 <0x0000d000 0x0000d000 0x001000>, /* ap 4 */
468 <0x0000e000 0x0000e000 0x001000>, /* ap 5 */
469 <0x0000f000 0x0000f000 0x001000>, /* ap 6 */
470 <0x00010000 0x00010000 0x001000>, /* ap 7 */
471 <0x00011000 0x00011000 0x001000>, /* ap 8 */
472 <0x0001a000 0x0001a000 0x001000>, /* ap 9 */
473 <0x0001b000 0x0001b000 0x001000>, /* ap 10 */
474 <0x00024000 0x00024000 0x001000>, /* ap 11 */
475 <0x00025000 0x00025000 0x001000>, /* ap 12 */
476 <0x00026000 0x00026000 0x001000>, /* ap 13 */
477 <0x00027000 0x00027000 0x001000>, /* ap 14 */
478 <0x00030000 0x00030000 0x001000>, /* ap 15 */
479 <0x00031000 0x00031000 0x001000>, /* ap 16 */
480 <0x00038000 0x00038000 0x001000>, /* ap 17 */
481 <0x00039000 0x00039000 0x001000>, /* ap 18 */
482 <0x0003a000 0x0003a000 0x001000>, /* ap 19 */
483 <0x0003b000 0x0003b000 0x001000>, /* ap 20 */
484 <0x0003e000 0x0003e000 0x001000>, /* ap 21 */
485 <0x0003f000 0x0003f000 0x001000>, /* ap 22 */
486 <0x0003c000 0x0003c000 0x001000>, /* ap 23 */
487 <0x00040000 0x00040000 0x001000>, /* ap 24 */
488 <0x00046000 0x00046000 0x001000>, /* ap 25 */
489 <0x00047000 0x00047000 0x001000>, /* ap 26 */
490 <0x00044000 0x00044000 0x001000>, /* ap 27 */
491 <0x00045000 0x00045000 0x001000>, /* ap 28 */
492 <0x00028000 0x00028000 0x001000>, /* ap 29 */
493 <0x00029000 0x00029000 0x001000>, /* ap 30 */
494 <0x00032000 0x00032000 0x001000>, /* ap 31 */
495 <0x00033000 0x00033000 0x001000>, /* ap 32 */
496 <0x0003d000 0x0003d000 0x001000>, /* ap 33 */
497 <0x00041000 0x00041000 0x001000>, /* ap 34 */
498 <0x00042000 0x00042000 0x001000>, /* ap 35 */
499 <0x00043000 0x00043000 0x001000>, /* ap 36 */
500 <0x00014000 0x00014000 0x001000>, /* ap 37 */
501 <0x00015000 0x00015000 0x001000>; /* ap 38 */
502
503 target-module@c000 { /* 0x47c0c000, ap 3 04.0 */
504 compatible = "ti,sysc";
505 status = "disabled";
506 #address-cells = <1>;
507 #size-cells = <1>;
508 ranges = <0x0 0xc000 0x1000>;
509 };
510
511 target-module@e000 { /* 0x47c0e000, ap 5 0c.0 */
512 compatible = "ti,sysc";
513 status = "disabled";
514 #address-cells = <1>;
515 #size-cells = <1>;
516 ranges = <0x0 0xe000 0x1000>;
517 };
518
519 target-module@10000 { /* 0x47c10000, ap 7 20.0 */
520 compatible = "ti,sysc";
521 status = "disabled";
522 #address-cells = <1>;
523 #size-cells = <1>;
524 ranges = <0x0 0x10000 0x1000>;
525 };
526
527 target-module@14000 { /* 0x47c14000, ap 37 3c.0 */
528 compatible = "ti,sysc";
529 status = "disabled";
530 #address-cells = <1>;
531 #size-cells = <1>;
532 ranges = <0x0 0x14000 0x1000>;
533 };
534
535 target-module@1a000 { /* 0x47c1a000, ap 9 08.0 */
536 compatible = "ti,sysc";
537 status = "disabled";
538 #address-cells = <1>;
539 #size-cells = <1>;
540 ranges = <0x0 0x1a000 0x1000>;
541 };
542
543 target-module@24000 { /* 0x47c24000, ap 11 28.0 */
544 compatible = "ti,sysc";
545 status = "disabled";
546 #address-cells = <1>;
547 #size-cells = <1>;
548 ranges = <0x0 0x24000 0x1000>;
549 };
550
551 target-module@26000 { /* 0x47c26000, ap 13 30.0 */
552 compatible = "ti,sysc";
553 status = "disabled";
554 #address-cells = <1>;
555 #size-cells = <1>;
556 ranges = <0x0 0x26000 0x1000>;
557 };
558
559 target-module@28000 { /* 0x47c28000, ap 29 40.0 */
560 compatible = "ti,sysc";
561 status = "disabled";
562 #address-cells = <1>;
563 #size-cells = <1>;
564 ranges = <0x0 0x28000 0x1000>;
565 };
566
567 target-module@30000 { /* 0x47c30000, ap 15 14.0 */
568 compatible = "ti,sysc";
569 status = "disabled";
570 #address-cells = <1>;
571 #size-cells = <1>;
572 ranges = <0x0 0x30000 0x1000>;
573 };
574
575 target-module@32000 { /* 0x47c32000, ap 31 06.0 */
576 compatible = "ti,sysc";
577 status = "disabled";
578 #address-cells = <1>;
579 #size-cells = <1>;
580 ranges = <0x0 0x32000 0x1000>;
581 };
582
583 target-module@38000 { /* 0x47c38000, ap 17 18.0 */
584 compatible = "ti,sysc";
585 status = "disabled";
586 #address-cells = <1>;
587 #size-cells = <1>;
588 ranges = <0x0 0x38000 0x1000>;
589 };
590
591 target-module@3a000 { /* 0x47c3a000, ap 19 1c.0 */
592 compatible = "ti,sysc";
593 status = "disabled";
594 #address-cells = <1>;
595 #size-cells = <1>;
596 ranges = <0x0 0x3a000 0x1000>;
597 };
598
599 target-module@3c000 { /* 0x47c3c000, ap 23 38.0 */
600 compatible = "ti,sysc";
601 status = "disabled";
602 #address-cells = <1>;
603 #size-cells = <1>;
604 ranges = <0x0 0x3c000 0x1000>;
605 };
606
607 target-module@3e000 { /* 0x47c3e000, ap 21 10.0 */
608 compatible = "ti,sysc";
609 status = "disabled";
610 #address-cells = <1>;
611 #size-cells = <1>;
612 ranges = <0x0 0x3e000 0x1000>;
613 };
614
615 target-module@40000 { /* 0x47c40000, ap 24 02.0 */
616 compatible = "ti,sysc";
617 status = "disabled";
618 #address-cells = <1>;
619 #size-cells = <1>;
620 ranges = <0x0 0x40000 0x1000>;
621 };
622
623 target-module@42000 { /* 0x47c42000, ap 35 34.0 */
624 compatible = "ti,sysc";
625 status = "disabled";
626 #address-cells = <1>;
627 #size-cells = <1>;
628 ranges = <0x0 0x42000 0x1000>;
629 };
630
631 target-module@44000 { /* 0x47c44000, ap 27 24.0 */
632 compatible = "ti,sysc";
633 status = "disabled";
634 #address-cells = <1>;
635 #size-cells = <1>;
636 ranges = <0x0 0x44000 0x1000>;
637 };
638
639 target-module@46000 { /* 0x47c46000, ap 25 2c.0 */
640 compatible = "ti,sysc";
641 status = "disabled";
642 #address-cells = <1>;
643 #size-cells = <1>;
644 ranges = <0x0 0x46000 0x1000>;
645 };
646 };
647};
648
649&l4_fast { /* 0x4a000000 */
650 compatible = "ti,am33xx-l4-fast", "simple-bus";
651 reg = <0x4a000000 0x800>,
652 <0x4a000800 0x800>,
653 <0x4a001000 0x400>;
654 reg-names = "ap", "la", "ia0";
655 #address-cells = <1>;
656 #size-cells = <1>;
657 ranges = <0x00000000 0x4a000000 0x1000000>; /* segment 0 */
658
659 segment@0 { /* 0x4a000000 */
660 compatible = "simple-bus";
661 #address-cells = <1>;
662 #size-cells = <1>;
663 ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */
664 <0x00000800 0x00000800 0x000800>, /* ap 1 */
665 <0x00001000 0x00001000 0x000400>, /* ap 2 */
666 <0x00100000 0x00100000 0x008000>, /* ap 3 */
667 <0x00108000 0x00108000 0x001000>, /* ap 4 */
668 <0x00180000 0x00180000 0x020000>, /* ap 5 */
669 <0x001a0000 0x001a0000 0x001000>, /* ap 6 */
670 <0x00200000 0x00200000 0x080000>, /* ap 7 */
671 <0x00280000 0x00280000 0x001000>, /* ap 8 */
672 <0x00300000 0x00300000 0x080000>, /* ap 9 */
673 <0x00380000 0x00380000 0x001000>; /* ap 10 */
674
675 target-module@100000 { /* 0x4a100000, ap 3 08.0 */
Tony Lindgren87fc89c2018-09-24 16:20:54 -0700676 compatible = "ti,sysc-omap4-simple", "ti,sysc";
Tony Lindgren87fc89c2018-09-24 16:20:54 -0700677 reg = <0x101200 0x4>,
678 <0x101208 0x4>,
679 <0x101204 0x4>;
680 reg-names = "rev", "sysc", "syss";
681 ti,sysc-mask = <0>;
682 ti,sysc-midle = <SYSC_IDLE_FORCE>,
683 <SYSC_IDLE_NO>;
684 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
685 <SYSC_IDLE_NO>;
686 ti,syss-mask = <1>;
687 clocks = <&cpsw_125mhz_clkctrl AM3_CPSW_125MHZ_CPGMAC0_CLKCTRL 0>;
688 clock-names = "fck";
Tony Lindgrenf711c572018-09-24 16:20:37 -0700689 #address-cells = <1>;
690 #size-cells = <1>;
691 ranges = <0x0 0x100000 0x8000>;
Tony Lindgren87fc89c2018-09-24 16:20:54 -0700692
693 mac: ethernet@0 {
694 compatible = "ti,am335x-cpsw","ti,cpsw";
695 clocks = <&cpsw_125mhz_gclk>, <&cpsw_cpts_rft_clk>;
696 clock-names = "fck", "cpts";
697 cpdma_channels = <8>;
698 ale_entries = <1024>;
699 bd_ram_size = <0x2000>;
700 mac_control = <0x20>;
701 slaves = <2>;
702 active_slave = <0>;
703 cpts_clock_mult = <0x80000000>;
704 cpts_clock_shift = <29>;
705 reg = <0x0 0x800
706 0x1200 0x100>;
707 #address-cells = <1>;
708 #size-cells = <1>;
709 /*
710 * c0_rx_thresh_pend
711 * c0_rx_pend
712 * c0_tx_pend
713 * c0_misc_pend
714 */
715 interrupts = <40 41 42 43>;
716 ranges = <0 0 0x8000>;
717 syscon = <&scm_conf>;
Tony Lindgren87fc89c2018-09-24 16:20:54 -0700718 status = "disabled";
719
720 davinci_mdio: mdio@1000 {
721 compatible = "ti,cpsw-mdio","ti,davinci_mdio";
Tony Lindgren1faa4152019-08-26 08:41:14 -0700722 clocks = <&cpsw_125mhz_clkctrl AM3_CPSW_125MHZ_CPGMAC0_CLKCTRL 0>;
723 clock-names = "fck";
Tony Lindgren87fc89c2018-09-24 16:20:54 -0700724 #address-cells = <1>;
725 #size-cells = <0>;
Tony Lindgren87fc89c2018-09-24 16:20:54 -0700726 bus_freq = <1000000>;
727 reg = <0x1000 0x100>;
728 status = "disabled";
729 };
730
731 cpsw_emac0: slave@200 {
732 /* Filled in by U-Boot */
733 mac-address = [ 00 00 00 00 00 00 ];
Grygorii Strashkofcfa0e82019-02-20 17:25:17 +0200734 phys = <&phy_gmii_sel 1 1>;
Tony Lindgren87fc89c2018-09-24 16:20:54 -0700735 };
736
737 cpsw_emac1: slave@300 {
738 /* Filled in by U-Boot */
739 mac-address = [ 00 00 00 00 00 00 ];
Grygorii Strashkofcfa0e82019-02-20 17:25:17 +0200740 phys = <&phy_gmii_sel 2 1>;
Tony Lindgren87fc89c2018-09-24 16:20:54 -0700741 };
742 };
Tony Lindgrenf711c572018-09-24 16:20:37 -0700743 };
744
745 target-module@180000 { /* 0x4a180000, ap 5 10.0 */
746 compatible = "ti,sysc";
747 status = "disabled";
748 #address-cells = <1>;
749 #size-cells = <1>;
750 ranges = <0x0 0x180000 0x20000>;
751 };
752
753 target-module@200000 { /* 0x4a200000, ap 7 02.0 */
754 compatible = "ti,sysc";
755 status = "disabled";
756 #address-cells = <1>;
757 #size-cells = <1>;
758 ranges = <0x0 0x200000 0x80000>;
759 };
760
Suman Annace5ca142020-02-27 16:28:35 -0600761 pruss_tm: target-module@300000 { /* 0x4a300000, ap 9 04.0 */
762 compatible = "ti,sysc-pruss", "ti,sysc";
763 reg = <0x326000 0x4>,
764 <0x326004 0x4>;
765 reg-names = "rev", "sysc";
766 ti,sysc-mask = <(SYSC_PRUSS_STANDBY_INIT |
767 SYSC_PRUSS_SUB_MWAIT)>;
768 ti,sysc-midle = <SYSC_IDLE_FORCE>,
769 <SYSC_IDLE_NO>,
770 <SYSC_IDLE_SMART>;
771 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
772 <SYSC_IDLE_NO>,
773 <SYSC_IDLE_SMART>;
774 clocks = <&pruss_ocp_clkctrl AM3_PRUSS_OCP_PRUSS_CLKCTRL 0>;
775 clock-names = "fck";
776 resets = <&prm_per 1>;
777 reset-names = "rstctrl";
Tony Lindgrenf711c572018-09-24 16:20:37 -0700778 #address-cells = <1>;
779 #size-cells = <1>;
780 ranges = <0x0 0x300000 0x80000>;
Suman Annace5ca142020-02-27 16:28:35 -0600781 status = "disabled";
Tony Lindgrenf711c572018-09-24 16:20:37 -0700782 };
783 };
784};
785
786&l4_mpuss { /* 0x4b140000 */
787 compatible = "ti,am33xx-l4-mpuss", "simple-bus";
788 reg = <0x4b144400 0x100>,
789 <0x4b144800 0x400>;
790 reg-names = "la", "ap";
791 #address-cells = <1>;
792 #size-cells = <1>;
793 ranges = <0x00000000 0x4b140000 0x008000>; /* segment 0 */
794
795 segment@0 { /* 0x4b140000 */
796 compatible = "simple-bus";
797 #address-cells = <1>;
798 #size-cells = <1>;
799 ranges = <0x00004800 0x00004800 0x000400>, /* ap 0 */
800 <0x00001000 0x00001000 0x001000>, /* ap 1 */
801 <0x00002000 0x00002000 0x001000>, /* ap 2 */
802 <0x00004000 0x00004000 0x000400>, /* ap 3 */
803 <0x00005000 0x00005000 0x000400>, /* ap 4 */
804 <0x00000000 0x00000000 0x001000>, /* ap 5 */
805 <0x00003000 0x00003000 0x001000>, /* ap 6 */
806 <0x00000800 0x00000800 0x000800>; /* ap 7 */
807
808 target-module@0 { /* 0x4b140000, ap 5 02.2 */
809 compatible = "ti,sysc";
810 status = "disabled";
811 #address-cells = <1>;
812 #size-cells = <1>;
813 ranges = <0x00000000 0x00000000 0x00001000>,
814 <0x00001000 0x00001000 0x00001000>,
815 <0x00002000 0x00002000 0x00001000>;
816 };
817
818 target-module@3000 { /* 0x4b143000, ap 6 04.0 */
819 compatible = "ti,sysc";
820 status = "disabled";
821 #address-cells = <1>;
822 #size-cells = <1>;
823 ranges = <0x0 0x3000 0x1000>;
824 };
825 };
826};
827
828&l4_per { /* 0x48000000 */
829 compatible = "ti,am33xx-l4-per", "simple-bus";
830 reg = <0x48000000 0x800>,
831 <0x48000800 0x800>,
832 <0x48001000 0x400>,
833 <0x48001400 0x400>,
834 <0x48001800 0x400>,
835 <0x48001c00 0x400>;
836 reg-names = "ap", "la", "ia0", "ia1", "ia2", "ia3";
837 #address-cells = <1>;
838 #size-cells = <1>;
839 ranges = <0x00000000 0x48000000 0x100000>, /* segment 0 */
840 <0x00100000 0x48100000 0x100000>, /* segment 1 */
841 <0x00200000 0x48200000 0x100000>, /* segment 2 */
Tony Lindgrenf2fb18c2018-12-05 14:08:37 -0800842 <0x00300000 0x48300000 0x100000>, /* segment 3 */
843 <0x46000000 0x46000000 0x400000>, /* l3 data port */
844 <0x46400000 0x46400000 0x400000>; /* l3 data port */
Tony Lindgrenf711c572018-09-24 16:20:37 -0700845
846 segment@0 { /* 0x48000000 */
847 compatible = "simple-bus";
848 #address-cells = <1>;
849 #size-cells = <1>;
850 ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */
851 <0x00000800 0x00000800 0x000800>, /* ap 1 */
852 <0x00001000 0x00001000 0x000400>, /* ap 2 */
853 <0x00001400 0x00001400 0x000400>, /* ap 3 */
854 <0x00001800 0x00001800 0x000400>, /* ap 4 */
855 <0x00001c00 0x00001c00 0x000400>, /* ap 5 */
856 <0x00008000 0x00008000 0x001000>, /* ap 6 */
857 <0x00009000 0x00009000 0x001000>, /* ap 7 */
858 <0x00016000 0x00016000 0x001000>, /* ap 8 */
859 <0x00017000 0x00017000 0x001000>, /* ap 9 */
860 <0x00022000 0x00022000 0x001000>, /* ap 10 */
861 <0x00023000 0x00023000 0x001000>, /* ap 11 */
862 <0x00024000 0x00024000 0x001000>, /* ap 12 */
863 <0x00025000 0x00025000 0x001000>, /* ap 13 */
864 <0x0002a000 0x0002a000 0x001000>, /* ap 14 */
865 <0x0002b000 0x0002b000 0x001000>, /* ap 15 */
866 <0x00038000 0x00038000 0x002000>, /* ap 16 */
867 <0x0003a000 0x0003a000 0x001000>, /* ap 17 */
868 <0x00014000 0x00014000 0x001000>, /* ap 18 */
869 <0x00015000 0x00015000 0x001000>, /* ap 19 */
870 <0x0003c000 0x0003c000 0x002000>, /* ap 20 */
871 <0x0003e000 0x0003e000 0x001000>, /* ap 21 */
872 <0x00040000 0x00040000 0x001000>, /* ap 22 */
873 <0x00041000 0x00041000 0x001000>, /* ap 23 */
874 <0x00042000 0x00042000 0x001000>, /* ap 24 */
875 <0x00043000 0x00043000 0x001000>, /* ap 25 */
876 <0x00044000 0x00044000 0x001000>, /* ap 26 */
877 <0x00045000 0x00045000 0x001000>, /* ap 27 */
878 <0x00046000 0x00046000 0x001000>, /* ap 28 */
879 <0x00047000 0x00047000 0x001000>, /* ap 29 */
880 <0x00048000 0x00048000 0x001000>, /* ap 30 */
881 <0x00049000 0x00049000 0x001000>, /* ap 31 */
882 <0x0004c000 0x0004c000 0x001000>, /* ap 32 */
883 <0x0004d000 0x0004d000 0x001000>, /* ap 33 */
884 <0x00050000 0x00050000 0x002000>, /* ap 34 */
885 <0x00052000 0x00052000 0x001000>, /* ap 35 */
886 <0x00060000 0x00060000 0x001000>, /* ap 36 */
887 <0x00061000 0x00061000 0x001000>, /* ap 37 */
888 <0x00080000 0x00080000 0x010000>, /* ap 38 */
889 <0x00090000 0x00090000 0x001000>, /* ap 39 */
890 <0x000a0000 0x000a0000 0x010000>, /* ap 40 */
891 <0x000b0000 0x000b0000 0x001000>, /* ap 41 */
892 <0x00030000 0x00030000 0x001000>, /* ap 77 */
893 <0x00031000 0x00031000 0x001000>, /* ap 78 */
894 <0x0004a000 0x0004a000 0x001000>, /* ap 85 */
895 <0x0004b000 0x0004b000 0x001000>, /* ap 86 */
896 <0x000c8000 0x000c8000 0x001000>, /* ap 87 */
897 <0x000c9000 0x000c9000 0x001000>, /* ap 88 */
898 <0x000cc000 0x000cc000 0x001000>, /* ap 89 */
899 <0x000cd000 0x000cd000 0x001000>, /* ap 90 */
900 <0x000ca000 0x000ca000 0x001000>, /* ap 91 */
Tony Lindgrenf2fb18c2018-12-05 14:08:37 -0800901 <0x000cb000 0x000cb000 0x001000>, /* ap 92 */
902 <0x46000000 0x46000000 0x400000>, /* l3 data port */
903 <0x46400000 0x46400000 0x400000>; /* l3 data port */
Tony Lindgrenf711c572018-09-24 16:20:37 -0700904
905 target-module@8000 { /* 0x48008000, ap 6 10.0 */
906 compatible = "ti,sysc";
907 status = "disabled";
908 #address-cells = <1>;
909 #size-cells = <1>;
910 ranges = <0x0 0x8000 0x1000>;
911 };
912
913 target-module@14000 { /* 0x48014000, ap 18 58.0 */
914 compatible = "ti,sysc";
915 status = "disabled";
916 #address-cells = <1>;
917 #size-cells = <1>;
918 ranges = <0x0 0x14000 0x1000>;
919 };
920
921 target-module@16000 { /* 0x48016000, ap 8 3c.0 */
922 compatible = "ti,sysc";
923 status = "disabled";
924 #address-cells = <1>;
925 #size-cells = <1>;
926 ranges = <0x0 0x16000 0x1000>;
927 };
928
929 target-module@22000 { /* 0x48022000, ap 10 12.0 */
930 compatible = "ti,sysc-omap2", "ti,sysc";
Tony Lindgrenf711c572018-09-24 16:20:37 -0700931 reg = <0x22050 0x4>,
932 <0x22054 0x4>,
933 <0x22058 0x4>;
934 reg-names = "rev", "sysc", "syss";
935 ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
936 SYSC_OMAP2_SOFTRESET |
937 SYSC_OMAP2_AUTOIDLE)>;
938 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
939 <SYSC_IDLE_NO>,
940 <SYSC_IDLE_SMART>,
941 <SYSC_IDLE_SMART_WKUP>;
942 /* Domains (P, C): per_pwrdm, l4ls_clkdm */
943 clocks = <&l4ls_clkctrl AM3_L4LS_UART2_CLKCTRL 0>;
944 clock-names = "fck";
945 #address-cells = <1>;
946 #size-cells = <1>;
947 ranges = <0x0 0x22000 0x1000>;
Tony Lindgren87fc89c2018-09-24 16:20:54 -0700948
949 uart1: serial@0 {
950 compatible = "ti,am3352-uart", "ti,omap3-uart";
951 clock-frequency = <48000000>;
Emmanuel Vadot8613e2c2019-07-24 14:23:29 +0200952 reg = <0x0 0x1000>;
Tony Lindgren87fc89c2018-09-24 16:20:54 -0700953 interrupts = <73>;
954 status = "disabled";
955 dmas = <&edma 28 0>, <&edma 29 0>;
956 dma-names = "tx", "rx";
957 };
Tony Lindgrenf711c572018-09-24 16:20:37 -0700958 };
959
960 target-module@24000 { /* 0x48024000, ap 12 14.0 */
961 compatible = "ti,sysc-omap2", "ti,sysc";
Tony Lindgrenf711c572018-09-24 16:20:37 -0700962 reg = <0x24050 0x4>,
963 <0x24054 0x4>,
964 <0x24058 0x4>;
965 reg-names = "rev", "sysc", "syss";
966 ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
967 SYSC_OMAP2_SOFTRESET |
968 SYSC_OMAP2_AUTOIDLE)>;
969 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
970 <SYSC_IDLE_NO>,
971 <SYSC_IDLE_SMART>,
972 <SYSC_IDLE_SMART_WKUP>;
973 /* Domains (P, C): per_pwrdm, l4ls_clkdm */
974 clocks = <&l4ls_clkctrl AM3_L4LS_UART3_CLKCTRL 0>;
975 clock-names = "fck";
976 #address-cells = <1>;
977 #size-cells = <1>;
978 ranges = <0x0 0x24000 0x1000>;
Tony Lindgren87fc89c2018-09-24 16:20:54 -0700979
980 uart2: serial@0 {
981 compatible = "ti,am3352-uart", "ti,omap3-uart";
982 clock-frequency = <48000000>;
Emmanuel Vadot8613e2c2019-07-24 14:23:29 +0200983 reg = <0x0 0x1000>;
Tony Lindgren87fc89c2018-09-24 16:20:54 -0700984 interrupts = <74>;
985 status = "disabled";
986 dmas = <&edma 30 0>, <&edma 31 0>;
987 dma-names = "tx", "rx";
988 };
Tony Lindgrenf711c572018-09-24 16:20:37 -0700989 };
990
991 target-module@2a000 { /* 0x4802a000, ap 14 2a.0 */
992 compatible = "ti,sysc-omap2", "ti,sysc";
Tony Lindgrenf711c572018-09-24 16:20:37 -0700993 reg = <0x2a000 0x8>,
994 <0x2a010 0x8>,
995 <0x2a090 0x8>;
996 reg-names = "rev", "sysc", "syss";
997 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
998 SYSC_OMAP2_ENAWAKEUP |
999 SYSC_OMAP2_SOFTRESET |
1000 SYSC_OMAP2_AUTOIDLE)>;
1001 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1002 <SYSC_IDLE_NO>,
1003 <SYSC_IDLE_SMART>,
1004 <SYSC_IDLE_SMART_WKUP>;
1005 ti,syss-mask = <1>;
1006 /* Domains (P, C): per_pwrdm, l4ls_clkdm */
1007 clocks = <&l4ls_clkctrl AM3_L4LS_I2C2_CLKCTRL 0>;
1008 clock-names = "fck";
1009 #address-cells = <1>;
1010 #size-cells = <1>;
1011 ranges = <0x0 0x2a000 0x1000>;
Tony Lindgren87fc89c2018-09-24 16:20:54 -07001012
1013 i2c1: i2c@0 {
1014 compatible = "ti,omap4-i2c";
1015 #address-cells = <1>;
1016 #size-cells = <0>;
1017 reg = <0x0 0x1000>;
1018 interrupts = <71>;
1019 status = "disabled";
1020 };
Tony Lindgrenf711c572018-09-24 16:20:37 -07001021 };
1022
1023 target-module@30000 { /* 0x48030000, ap 77 08.0 */
1024 compatible = "ti,sysc-omap2", "ti,sysc";
Tony Lindgrenf711c572018-09-24 16:20:37 -07001025 reg = <0x30000 0x4>,
1026 <0x30110 0x4>,
1027 <0x30114 0x4>;
1028 reg-names = "rev", "sysc", "syss";
1029 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
1030 SYSC_OMAP2_SOFTRESET |
1031 SYSC_OMAP2_AUTOIDLE)>;
1032 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1033 <SYSC_IDLE_NO>,
1034 <SYSC_IDLE_SMART>;
1035 ti,syss-mask = <1>;
1036 /* Domains (P, C): per_pwrdm, l4ls_clkdm */
1037 clocks = <&l4ls_clkctrl AM3_L4LS_SPI0_CLKCTRL 0>;
1038 clock-names = "fck";
1039 #address-cells = <1>;
1040 #size-cells = <1>;
1041 ranges = <0x0 0x30000 0x1000>;
Tony Lindgren87fc89c2018-09-24 16:20:54 -07001042
1043 spi0: spi@0 {
1044 compatible = "ti,omap4-mcspi";
1045 #address-cells = <1>;
1046 #size-cells = <0>;
1047 reg = <0x0 0x400>;
1048 interrupts = <65>;
1049 ti,spi-num-cs = <2>;
1050 dmas = <&edma 16 0
1051 &edma 17 0
1052 &edma 18 0
1053 &edma 19 0>;
1054 dma-names = "tx0", "rx0", "tx1", "rx1";
1055 status = "disabled";
1056 };
Tony Lindgrenf711c572018-09-24 16:20:37 -07001057 };
1058
1059 target-module@38000 { /* 0x48038000, ap 16 02.0 */
1060 compatible = "ti,sysc-omap4-simple", "ti,sysc";
Tony Lindgrenf711c572018-09-24 16:20:37 -07001061 reg = <0x38000 0x4>,
1062 <0x38004 0x4>;
1063 reg-names = "rev", "sysc";
1064 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1065 <SYSC_IDLE_NO>,
1066 <SYSC_IDLE_SMART>;
1067 /* Domains (P, C): per_pwrdm, l3s_clkdm */
1068 clocks = <&l3s_clkctrl AM3_L3S_MCASP0_CLKCTRL 0>;
1069 clock-names = "fck";
1070 #address-cells = <1>;
1071 #size-cells = <1>;
Tony Lindgrenf2fb18c2018-12-05 14:08:37 -08001072 ranges = <0x0 0x38000 0x2000>,
1073 <0x46000000 0x46000000 0x400000>;
1074
1075 mcasp0: mcasp@0 {
1076 compatible = "ti,am33xx-mcasp-audio";
1077 reg = <0x0 0x2000>,
1078 <0x46000000 0x400000>;
1079 reg-names = "mpu", "dat";
1080 interrupts = <80>, <81>;
1081 interrupt-names = "tx", "rx";
1082 status = "disabled";
1083 dmas = <&edma 8 2>,
1084 <&edma 9 2>;
1085 dma-names = "tx", "rx";
1086 };
Tony Lindgrenf711c572018-09-24 16:20:37 -07001087 };
1088
1089 target-module@3c000 { /* 0x4803c000, ap 20 32.0 */
1090 compatible = "ti,sysc-omap4-simple", "ti,sysc";
Tony Lindgrenf711c572018-09-24 16:20:37 -07001091 reg = <0x3c000 0x4>,
1092 <0x3c004 0x4>;
1093 reg-names = "rev", "sysc";
1094 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1095 <SYSC_IDLE_NO>,
1096 <SYSC_IDLE_SMART>;
1097 /* Domains (P, C): per_pwrdm, l3s_clkdm */
1098 clocks = <&l3s_clkctrl AM3_L3S_MCASP1_CLKCTRL 0>;
1099 clock-names = "fck";
1100 #address-cells = <1>;
1101 #size-cells = <1>;
Tony Lindgrenf2fb18c2018-12-05 14:08:37 -08001102 ranges = <0x0 0x3c000 0x2000>,
1103 <0x46400000 0x46400000 0x400000>;
1104
1105 mcasp1: mcasp@0 {
1106 compatible = "ti,am33xx-mcasp-audio";
1107 reg = <0x0 0x2000>,
1108 <0x46400000 0x400000>;
1109 reg-names = "mpu", "dat";
1110 interrupts = <82>, <83>;
1111 interrupt-names = "tx", "rx";
1112 status = "disabled";
1113 dmas = <&edma 10 2>,
1114 <&edma 11 2>;
1115 dma-names = "tx", "rx";
1116 };
Tony Lindgrenf711c572018-09-24 16:20:37 -07001117 };
1118
Tony Lindgrene20ef232020-05-07 09:59:31 -07001119 timer2_target: target-module@40000 { /* 0x48040000, ap 22 1e.0 */
Tony Lindgrenf711c572018-09-24 16:20:37 -07001120 compatible = "ti,sysc-omap4-timer", "ti,sysc";
Tony Lindgrenf711c572018-09-24 16:20:37 -07001121 reg = <0x40000 0x4>,
1122 <0x40010 0x4>,
1123 <0x40014 0x4>;
1124 reg-names = "rev", "sysc", "syss";
1125 ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
1126 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1127 <SYSC_IDLE_NO>,
1128 <SYSC_IDLE_SMART>,
1129 <SYSC_IDLE_SMART_WKUP>;
1130 /* Domains (P, C): per_pwrdm, l4ls_clkdm */
1131 clocks = <&l4ls_clkctrl AM3_L4LS_TIMER2_CLKCTRL 0>;
1132 clock-names = "fck";
1133 #address-cells = <1>;
1134 #size-cells = <1>;
1135 ranges = <0x0 0x40000 0x1000>;
Tony Lindgren87fc89c2018-09-24 16:20:54 -07001136
1137 timer2: timer@0 {
1138 compatible = "ti,am335x-timer";
1139 reg = <0x0 0x400>;
1140 interrupts = <68>;
1141 clocks = <&timer2_fck>;
1142 clock-names = "fck";
1143 };
Tony Lindgrenf711c572018-09-24 16:20:37 -07001144 };
1145
1146 target-module@42000 { /* 0x48042000, ap 24 1c.0 */
1147 compatible = "ti,sysc-omap4-timer", "ti,sysc";
Tony Lindgrenf711c572018-09-24 16:20:37 -07001148 reg = <0x42000 0x4>,
1149 <0x42010 0x4>,
1150 <0x42014 0x4>;
1151 reg-names = "rev", "sysc", "syss";
1152 ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
1153 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1154 <SYSC_IDLE_NO>,
1155 <SYSC_IDLE_SMART>,
1156 <SYSC_IDLE_SMART_WKUP>;
1157 /* Domains (P, C): per_pwrdm, l4ls_clkdm */
1158 clocks = <&l4ls_clkctrl AM3_L4LS_TIMER3_CLKCTRL 0>;
1159 clock-names = "fck";
1160 #address-cells = <1>;
1161 #size-cells = <1>;
1162 ranges = <0x0 0x42000 0x1000>;
Tony Lindgren87fc89c2018-09-24 16:20:54 -07001163
1164 timer3: timer@0 {
1165 compatible = "ti,am335x-timer";
1166 reg = <0x0 0x400>;
1167 interrupts = <69>;
1168 };
Tony Lindgrenf711c572018-09-24 16:20:37 -07001169 };
1170
1171 target-module@44000 { /* 0x48044000, ap 26 26.0 */
1172 compatible = "ti,sysc-omap4-timer", "ti,sysc";
Tony Lindgrenf711c572018-09-24 16:20:37 -07001173 reg = <0x44000 0x4>,
1174 <0x44010 0x4>,
1175 <0x44014 0x4>;
1176 reg-names = "rev", "sysc", "syss";
1177 ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
1178 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1179 <SYSC_IDLE_NO>,
1180 <SYSC_IDLE_SMART>,
1181 <SYSC_IDLE_SMART_WKUP>;
1182 /* Domains (P, C): per_pwrdm, l4ls_clkdm */
1183 clocks = <&l4ls_clkctrl AM3_L4LS_TIMER4_CLKCTRL 0>;
1184 clock-names = "fck";
1185 #address-cells = <1>;
1186 #size-cells = <1>;
1187 ranges = <0x0 0x44000 0x1000>;
Tony Lindgren87fc89c2018-09-24 16:20:54 -07001188
1189 timer4: timer@0 {
1190 compatible = "ti,am335x-timer";
1191 reg = <0x0 0x400>;
1192 interrupts = <92>;
1193 ti,timer-pwm;
1194 };
Tony Lindgrenf711c572018-09-24 16:20:37 -07001195 };
1196
1197 target-module@46000 { /* 0x48046000, ap 28 28.0 */
1198 compatible = "ti,sysc-omap4-timer", "ti,sysc";
Tony Lindgrenf711c572018-09-24 16:20:37 -07001199 reg = <0x46000 0x4>,
1200 <0x46010 0x4>,
1201 <0x46014 0x4>;
1202 reg-names = "rev", "sysc", "syss";
1203 ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
1204 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1205 <SYSC_IDLE_NO>,
1206 <SYSC_IDLE_SMART>,
1207 <SYSC_IDLE_SMART_WKUP>;
1208 /* Domains (P, C): per_pwrdm, l4ls_clkdm */
1209 clocks = <&l4ls_clkctrl AM3_L4LS_TIMER5_CLKCTRL 0>;
1210 clock-names = "fck";
1211 #address-cells = <1>;
1212 #size-cells = <1>;
1213 ranges = <0x0 0x46000 0x1000>;
Tony Lindgren87fc89c2018-09-24 16:20:54 -07001214
1215 timer5: timer@0 {
1216 compatible = "ti,am335x-timer";
1217 reg = <0x0 0x400>;
1218 interrupts = <93>;
1219 ti,timer-pwm;
1220 };
Tony Lindgrenf711c572018-09-24 16:20:37 -07001221 };
1222
1223 target-module@48000 { /* 0x48048000, ap 30 22.0 */
1224 compatible = "ti,sysc-omap4-timer", "ti,sysc";
Tony Lindgrenf711c572018-09-24 16:20:37 -07001225 reg = <0x48000 0x4>,
1226 <0x48010 0x4>,
1227 <0x48014 0x4>;
1228 reg-names = "rev", "sysc", "syss";
1229 ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
1230 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1231 <SYSC_IDLE_NO>,
1232 <SYSC_IDLE_SMART>,
1233 <SYSC_IDLE_SMART_WKUP>;
1234 /* Domains (P, C): per_pwrdm, l4ls_clkdm */
1235 clocks = <&l4ls_clkctrl AM3_L4LS_TIMER6_CLKCTRL 0>;
1236 clock-names = "fck";
1237 #address-cells = <1>;
1238 #size-cells = <1>;
1239 ranges = <0x0 0x48000 0x1000>;
Tony Lindgren87fc89c2018-09-24 16:20:54 -07001240
1241 timer6: timer@0 {
1242 compatible = "ti,am335x-timer";
1243 reg = <0x0 0x400>;
1244 interrupts = <94>;
1245 ti,timer-pwm;
1246 };
Tony Lindgrenf711c572018-09-24 16:20:37 -07001247 };
1248
1249 target-module@4a000 { /* 0x4804a000, ap 85 60.0 */
1250 compatible = "ti,sysc-omap4-timer", "ti,sysc";
Tony Lindgrenf711c572018-09-24 16:20:37 -07001251 reg = <0x4a000 0x4>,
1252 <0x4a010 0x4>,
1253 <0x4a014 0x4>;
1254 reg-names = "rev", "sysc", "syss";
1255 ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
1256 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1257 <SYSC_IDLE_NO>,
1258 <SYSC_IDLE_SMART>,
1259 <SYSC_IDLE_SMART_WKUP>;
1260 /* Domains (P, C): per_pwrdm, l4ls_clkdm */
1261 clocks = <&l4ls_clkctrl AM3_L4LS_TIMER7_CLKCTRL 0>;
1262 clock-names = "fck";
1263 #address-cells = <1>;
1264 #size-cells = <1>;
1265 ranges = <0x0 0x4a000 0x1000>;
Tony Lindgren87fc89c2018-09-24 16:20:54 -07001266
1267 timer7: timer@0 {
1268 compatible = "ti,am335x-timer";
1269 reg = <0x0 0x400>;
1270 interrupts = <95>;
1271 ti,timer-pwm;
1272 };
Tony Lindgrenf711c572018-09-24 16:20:37 -07001273 };
1274
1275 target-module@4c000 { /* 0x4804c000, ap 32 36.0 */
1276 compatible = "ti,sysc-omap2", "ti,sysc";
Tony Lindgrenf711c572018-09-24 16:20:37 -07001277 reg = <0x4c000 0x4>,
1278 <0x4c010 0x4>,
1279 <0x4c114 0x4>;
1280 reg-names = "rev", "sysc", "syss";
1281 ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
1282 SYSC_OMAP2_SOFTRESET |
1283 SYSC_OMAP2_AUTOIDLE)>;
1284 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1285 <SYSC_IDLE_NO>,
1286 <SYSC_IDLE_SMART>,
1287 <SYSC_IDLE_SMART_WKUP>;
1288 ti,syss-mask = <1>;
1289 /* Domains (P, C): per_pwrdm, l4ls_clkdm */
1290 clocks = <&l4ls_clkctrl AM3_L4LS_GPIO2_CLKCTRL 0>,
1291 <&l4ls_clkctrl AM3_L4LS_GPIO2_CLKCTRL 18>;
1292 clock-names = "fck", "dbclk";
1293 #address-cells = <1>;
1294 #size-cells = <1>;
1295 ranges = <0x0 0x4c000 0x1000>;
Tony Lindgren87fc89c2018-09-24 16:20:54 -07001296
1297 gpio1: gpio@0 {
1298 compatible = "ti,omap4-gpio";
1299 gpio-controller;
1300 #gpio-cells = <2>;
1301 interrupt-controller;
1302 #interrupt-cells = <2>;
1303 reg = <0x0 0x1000>;
1304 interrupts = <98>;
1305 };
Tony Lindgrenf711c572018-09-24 16:20:37 -07001306 };
1307
1308 target-module@50000 { /* 0x48050000, ap 34 2c.0 */
1309 compatible = "ti,sysc";
1310 status = "disabled";
1311 #address-cells = <1>;
1312 #size-cells = <1>;
1313 ranges = <0x0 0x50000 0x2000>;
1314 };
1315
1316 target-module@60000 { /* 0x48060000, ap 36 0c.0 */
1317 compatible = "ti,sysc-omap2", "ti,sysc";
Tony Lindgrenf711c572018-09-24 16:20:37 -07001318 reg = <0x602fc 0x4>,
1319 <0x60110 0x4>,
1320 <0x60114 0x4>;
1321 reg-names = "rev", "sysc", "syss";
1322 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
1323 SYSC_OMAP2_ENAWAKEUP |
1324 SYSC_OMAP2_SOFTRESET |
1325 SYSC_OMAP2_AUTOIDLE)>;
1326 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1327 <SYSC_IDLE_NO>,
1328 <SYSC_IDLE_SMART>;
1329 ti,syss-mask = <1>;
1330 /* Domains (P, C): per_pwrdm, l4ls_clkdm */
1331 clocks = <&l4ls_clkctrl AM3_L4LS_MMC1_CLKCTRL 0>;
1332 clock-names = "fck";
1333 #address-cells = <1>;
1334 #size-cells = <1>;
1335 ranges = <0x0 0x60000 0x1000>;
Tony Lindgren87fc89c2018-09-24 16:20:54 -07001336
1337 mmc1: mmc@0 {
1338 compatible = "ti,omap4-hsmmc";
1339 ti,dual-volt;
1340 ti,needs-special-reset;
1341 ti,needs-special-hs-handling;
1342 dmas = <&edma_xbar 24 0 0
1343 &edma_xbar 25 0 0>;
1344 dma-names = "tx", "rx";
1345 interrupts = <64>;
1346 reg = <0x0 0x1000>;
1347 status = "disabled";
1348 };
Tony Lindgrenf711c572018-09-24 16:20:37 -07001349 };
1350
1351 target-module@80000 { /* 0x48080000, ap 38 18.0 */
1352 compatible = "ti,sysc-omap2", "ti,sysc";
Tony Lindgrenf711c572018-09-24 16:20:37 -07001353 reg = <0x80000 0x4>,
1354 <0x80010 0x4>,
1355 <0x80014 0x4>;
1356 reg-names = "rev", "sysc", "syss";
1357 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
1358 SYSC_OMAP2_SOFTRESET |
1359 SYSC_OMAP2_AUTOIDLE)>;
1360 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1361 <SYSC_IDLE_NO>,
1362 <SYSC_IDLE_SMART>;
1363 ti,syss-mask = <1>;
1364 /* Domains (P, C): per_pwrdm, l4ls_clkdm */
1365 clocks = <&l4ls_clkctrl AM3_L4LS_ELM_CLKCTRL 0>;
1366 clock-names = "fck";
1367 #address-cells = <1>;
1368 #size-cells = <1>;
1369 ranges = <0x0 0x80000 0x10000>;
Tony Lindgren87fc89c2018-09-24 16:20:54 -07001370
1371 elm: elm@0 {
1372 compatible = "ti,am3352-elm";
1373 reg = <0x0 0x2000>;
1374 interrupts = <4>;
1375 status = "disabled";
1376 };
Tony Lindgrenf711c572018-09-24 16:20:37 -07001377 };
1378
1379 target-module@a0000 { /* 0x480a0000, ap 40 5e.0 */
1380 compatible = "ti,sysc";
1381 status = "disabled";
1382 #address-cells = <1>;
1383 #size-cells = <1>;
1384 ranges = <0x0 0xa0000 0x10000>;
1385 };
1386
1387 target-module@c8000 { /* 0x480c8000, ap 87 06.0 */
1388 compatible = "ti,sysc-omap4", "ti,sysc";
Tony Lindgrenf711c572018-09-24 16:20:37 -07001389 reg = <0xc8000 0x4>,
1390 <0xc8010 0x4>;
1391 reg-names = "rev", "sysc";
1392 ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
1393 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1394 <SYSC_IDLE_NO>,
1395 <SYSC_IDLE_SMART>;
1396 /* Domains (P, C): per_pwrdm, l4ls_clkdm */
1397 clocks = <&l4ls_clkctrl AM3_L4LS_MAILBOX_CLKCTRL 0>;
1398 clock-names = "fck";
1399 #address-cells = <1>;
1400 #size-cells = <1>;
1401 ranges = <0x0 0xc8000 0x1000>;
Tony Lindgren87fc89c2018-09-24 16:20:54 -07001402
1403 mailbox: mailbox@0 {
1404 compatible = "ti,omap4-mailbox";
1405 reg = <0x0 0x200>;
1406 interrupts = <77>;
1407 #mbox-cells = <1>;
1408 ti,mbox-num-users = <4>;
1409 ti,mbox-num-fifos = <8>;
1410 mbox_wkupm3: wkup_m3 {
1411 ti,mbox-send-noirq;
1412 ti,mbox-tx = <0 0 0>;
1413 ti,mbox-rx = <0 0 3>;
1414 };
1415 };
Tony Lindgrenf711c572018-09-24 16:20:37 -07001416 };
1417
1418 target-module@ca000 { /* 0x480ca000, ap 91 40.0 */
1419 compatible = "ti,sysc-omap2", "ti,sysc";
Tony Lindgrenf711c572018-09-24 16:20:37 -07001420 reg = <0xca000 0x4>,
1421 <0xca010 0x4>,
1422 <0xca014 0x4>;
1423 reg-names = "rev", "sysc", "syss";
1424 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
1425 SYSC_OMAP2_ENAWAKEUP |
1426 SYSC_OMAP2_SOFTRESET |
1427 SYSC_OMAP2_AUTOIDLE)>;
1428 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1429 <SYSC_IDLE_NO>,
1430 <SYSC_IDLE_SMART>;
1431 ti,syss-mask = <1>;
1432 /* Domains (P, C): per_pwrdm, l4ls_clkdm */
1433 clocks = <&l4ls_clkctrl AM3_L4LS_SPINLOCK_CLKCTRL 0>;
1434 clock-names = "fck";
1435 #address-cells = <1>;
1436 #size-cells = <1>;
1437 ranges = <0x0 0xca000 0x1000>;
Tony Lindgren87fc89c2018-09-24 16:20:54 -07001438
1439 hwspinlock: spinlock@0 {
1440 compatible = "ti,omap4-hwspinlock";
1441 reg = <0x0 0x1000>;
1442 #hwlock-cells = <1>;
1443 };
Tony Lindgrenf711c572018-09-24 16:20:37 -07001444 };
1445
1446 target-module@cc000 { /* 0x480cc000, ap 89 0e.0 */
1447 compatible = "ti,sysc";
1448 status = "disabled";
1449 #address-cells = <1>;
1450 #size-cells = <1>;
1451 ranges = <0x0 0xcc000 0x1000>;
1452 };
1453 };
1454
1455 segment@100000 { /* 0x48100000 */
1456 compatible = "simple-bus";
1457 #address-cells = <1>;
1458 #size-cells = <1>;
1459 ranges = <0x0008c000 0x0018c000 0x001000>, /* ap 42 */
1460 <0x0008d000 0x0018d000 0x001000>, /* ap 43 */
1461 <0x0008e000 0x0018e000 0x001000>, /* ap 44 */
1462 <0x0008f000 0x0018f000 0x001000>, /* ap 45 */
1463 <0x0009c000 0x0019c000 0x001000>, /* ap 46 */
1464 <0x0009d000 0x0019d000 0x001000>, /* ap 47 */
1465 <0x000a6000 0x001a6000 0x001000>, /* ap 48 */
1466 <0x000a7000 0x001a7000 0x001000>, /* ap 49 */
1467 <0x000a8000 0x001a8000 0x001000>, /* ap 50 */
1468 <0x000a9000 0x001a9000 0x001000>, /* ap 51 */
1469 <0x000aa000 0x001aa000 0x001000>, /* ap 52 */
1470 <0x000ab000 0x001ab000 0x001000>, /* ap 53 */
1471 <0x000ac000 0x001ac000 0x001000>, /* ap 54 */
1472 <0x000ad000 0x001ad000 0x001000>, /* ap 55 */
1473 <0x000ae000 0x001ae000 0x001000>, /* ap 56 */
1474 <0x000af000 0x001af000 0x001000>, /* ap 57 */
1475 <0x000b0000 0x001b0000 0x010000>, /* ap 58 */
1476 <0x000c0000 0x001c0000 0x001000>, /* ap 59 */
1477 <0x000cc000 0x001cc000 0x002000>, /* ap 60 */
1478 <0x000ce000 0x001ce000 0x002000>, /* ap 61 */
1479 <0x000d0000 0x001d0000 0x002000>, /* ap 62 */
1480 <0x000d2000 0x001d2000 0x002000>, /* ap 63 */
1481 <0x000d8000 0x001d8000 0x001000>, /* ap 64 */
1482 <0x000d9000 0x001d9000 0x001000>, /* ap 65 */
1483 <0x000a0000 0x001a0000 0x001000>, /* ap 79 */
1484 <0x000a1000 0x001a1000 0x001000>, /* ap 80 */
1485 <0x000a2000 0x001a2000 0x001000>, /* ap 81 */
1486 <0x000a3000 0x001a3000 0x001000>, /* ap 82 */
1487 <0x000a4000 0x001a4000 0x001000>, /* ap 83 */
1488 <0x000a5000 0x001a5000 0x001000>; /* ap 84 */
1489
1490 target-module@8c000 { /* 0x4818c000, ap 42 04.0 */
1491 compatible = "ti,sysc";
1492 status = "disabled";
1493 #address-cells = <1>;
1494 #size-cells = <1>;
1495 ranges = <0x0 0x8c000 0x1000>;
1496 };
1497
1498 target-module@8e000 { /* 0x4818e000, ap 44 0a.0 */
1499 compatible = "ti,sysc";
1500 status = "disabled";
1501 #address-cells = <1>;
1502 #size-cells = <1>;
1503 ranges = <0x0 0x8e000 0x1000>;
1504 };
1505
1506 target-module@9c000 { /* 0x4819c000, ap 46 5a.0 */
1507 compatible = "ti,sysc-omap2", "ti,sysc";
Tony Lindgrenf711c572018-09-24 16:20:37 -07001508 reg = <0x9c000 0x8>,
1509 <0x9c010 0x8>,
1510 <0x9c090 0x8>;
1511 reg-names = "rev", "sysc", "syss";
1512 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
1513 SYSC_OMAP2_ENAWAKEUP |
1514 SYSC_OMAP2_SOFTRESET |
1515 SYSC_OMAP2_AUTOIDLE)>;
1516 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1517 <SYSC_IDLE_NO>,
1518 <SYSC_IDLE_SMART>,
1519 <SYSC_IDLE_SMART_WKUP>;
1520 ti,syss-mask = <1>;
1521 /* Domains (P, C): per_pwrdm, l4ls_clkdm */
1522 clocks = <&l4ls_clkctrl AM3_L4LS_I2C3_CLKCTRL 0>;
1523 clock-names = "fck";
1524 #address-cells = <1>;
1525 #size-cells = <1>;
1526 ranges = <0x0 0x9c000 0x1000>;
Tony Lindgren87fc89c2018-09-24 16:20:54 -07001527
1528 i2c2: i2c@0 {
1529 compatible = "ti,omap4-i2c";
1530 #address-cells = <1>;
1531 #size-cells = <0>;
1532 reg = <0x0 0x1000>;
1533 interrupts = <30>;
1534 status = "disabled";
1535 };
Tony Lindgrenf711c572018-09-24 16:20:37 -07001536 };
1537
1538 target-module@a0000 { /* 0x481a0000, ap 79 24.0 */
1539 compatible = "ti,sysc-omap2", "ti,sysc";
Tony Lindgrenf711c572018-09-24 16:20:37 -07001540 reg = <0xa0000 0x4>,
1541 <0xa0110 0x4>,
1542 <0xa0114 0x4>;
1543 reg-names = "rev", "sysc", "syss";
1544 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
1545 SYSC_OMAP2_SOFTRESET |
1546 SYSC_OMAP2_AUTOIDLE)>;
1547 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1548 <SYSC_IDLE_NO>,
1549 <SYSC_IDLE_SMART>;
1550 ti,syss-mask = <1>;
1551 /* Domains (P, C): per_pwrdm, l4ls_clkdm */
1552 clocks = <&l4ls_clkctrl AM3_L4LS_SPI1_CLKCTRL 0>;
1553 clock-names = "fck";
1554 #address-cells = <1>;
1555 #size-cells = <1>;
1556 ranges = <0x0 0xa0000 0x1000>;
Tony Lindgren87fc89c2018-09-24 16:20:54 -07001557
1558 spi1: spi@0 {
1559 compatible = "ti,omap4-mcspi";
1560 #address-cells = <1>;
1561 #size-cells = <0>;
1562 reg = <0x0 0x400>;
1563 interrupts = <125>;
1564 ti,spi-num-cs = <2>;
1565 dmas = <&edma 42 0
1566 &edma 43 0
1567 &edma 44 0
1568 &edma 45 0>;
1569 dma-names = "tx0", "rx0", "tx1", "rx1";
1570 status = "disabled";
1571 };
Tony Lindgrenf711c572018-09-24 16:20:37 -07001572 };
1573
1574 target-module@a2000 { /* 0x481a2000, ap 81 2e.0 */
1575 compatible = "ti,sysc";
1576 status = "disabled";
1577 #address-cells = <1>;
1578 #size-cells = <1>;
1579 ranges = <0x0 0xa2000 0x1000>;
1580 };
1581
1582 target-module@a4000 { /* 0x481a4000, ap 83 30.0 */
1583 compatible = "ti,sysc";
1584 status = "disabled";
1585 #address-cells = <1>;
1586 #size-cells = <1>;
1587 ranges = <0x0 0xa4000 0x1000>;
1588 };
1589
1590 target-module@a6000 { /* 0x481a6000, ap 48 16.0 */
1591 compatible = "ti,sysc-omap2", "ti,sysc";
Tony Lindgrenf711c572018-09-24 16:20:37 -07001592 reg = <0xa6050 0x4>,
1593 <0xa6054 0x4>,
1594 <0xa6058 0x4>;
1595 reg-names = "rev", "sysc", "syss";
1596 ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
1597 SYSC_OMAP2_SOFTRESET |
1598 SYSC_OMAP2_AUTOIDLE)>;
1599 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1600 <SYSC_IDLE_NO>,
1601 <SYSC_IDLE_SMART>,
1602 <SYSC_IDLE_SMART_WKUP>;
1603 /* Domains (P, C): per_pwrdm, l4ls_clkdm */
1604 clocks = <&l4ls_clkctrl AM3_L4LS_UART4_CLKCTRL 0>;
1605 clock-names = "fck";
1606 #address-cells = <1>;
1607 #size-cells = <1>;
1608 ranges = <0x0 0xa6000 0x1000>;
Tony Lindgren87fc89c2018-09-24 16:20:54 -07001609
1610 uart3: serial@0 {
1611 compatible = "ti,am3352-uart", "ti,omap3-uart";
1612 clock-frequency = <48000000>;
Emmanuel Vadot8613e2c2019-07-24 14:23:29 +02001613 reg = <0x0 0x1000>;
Tony Lindgren87fc89c2018-09-24 16:20:54 -07001614 interrupts = <44>;
1615 status = "disabled";
1616 };
Tony Lindgrenf711c572018-09-24 16:20:37 -07001617 };
1618
1619 target-module@a8000 { /* 0x481a8000, ap 50 20.0 */
1620 compatible = "ti,sysc-omap2", "ti,sysc";
Tony Lindgrenf711c572018-09-24 16:20:37 -07001621 reg = <0xa8050 0x4>,
1622 <0xa8054 0x4>,
1623 <0xa8058 0x4>;
1624 reg-names = "rev", "sysc", "syss";
1625 ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
1626 SYSC_OMAP2_SOFTRESET |
1627 SYSC_OMAP2_AUTOIDLE)>;
1628 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1629 <SYSC_IDLE_NO>,
1630 <SYSC_IDLE_SMART>,
1631 <SYSC_IDLE_SMART_WKUP>;
1632 /* Domains (P, C): per_pwrdm, l4ls_clkdm */
1633 clocks = <&l4ls_clkctrl AM3_L4LS_UART5_CLKCTRL 0>;
1634 clock-names = "fck";
1635 #address-cells = <1>;
1636 #size-cells = <1>;
1637 ranges = <0x0 0xa8000 0x1000>;
Tony Lindgren87fc89c2018-09-24 16:20:54 -07001638
1639 uart4: serial@0 {
1640 compatible = "ti,am3352-uart", "ti,omap3-uart";
1641 clock-frequency = <48000000>;
Emmanuel Vadot8613e2c2019-07-24 14:23:29 +02001642 reg = <0x0 0x1000>;
Tony Lindgren87fc89c2018-09-24 16:20:54 -07001643 interrupts = <45>;
1644 status = "disabled";
1645 };
Tony Lindgrenf711c572018-09-24 16:20:37 -07001646 };
1647
1648 target-module@aa000 { /* 0x481aa000, ap 52 1a.0 */
1649 compatible = "ti,sysc-omap2", "ti,sysc";
Tony Lindgrenf711c572018-09-24 16:20:37 -07001650 reg = <0xaa050 0x4>,
1651 <0xaa054 0x4>,
1652 <0xaa058 0x4>;
1653 reg-names = "rev", "sysc", "syss";
1654 ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
1655 SYSC_OMAP2_SOFTRESET |
1656 SYSC_OMAP2_AUTOIDLE)>;
1657 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1658 <SYSC_IDLE_NO>,
1659 <SYSC_IDLE_SMART>,
1660 <SYSC_IDLE_SMART_WKUP>;
1661 /* Domains (P, C): per_pwrdm, l4ls_clkdm */
1662 clocks = <&l4ls_clkctrl AM3_L4LS_UART6_CLKCTRL 0>;
1663 clock-names = "fck";
1664 #address-cells = <1>;
1665 #size-cells = <1>;
1666 ranges = <0x0 0xaa000 0x1000>;
Tony Lindgren87fc89c2018-09-24 16:20:54 -07001667
1668 uart5: serial@0 {
1669 compatible = "ti,am3352-uart", "ti,omap3-uart";
1670 clock-frequency = <48000000>;
Emmanuel Vadot8613e2c2019-07-24 14:23:29 +02001671 reg = <0x0 0x1000>;
Tony Lindgren87fc89c2018-09-24 16:20:54 -07001672 interrupts = <46>;
1673 status = "disabled";
1674 };
Tony Lindgrenf711c572018-09-24 16:20:37 -07001675 };
1676
1677 target-module@ac000 { /* 0x481ac000, ap 54 38.0 */
1678 compatible = "ti,sysc-omap2", "ti,sysc";
Tony Lindgrenf711c572018-09-24 16:20:37 -07001679 reg = <0xac000 0x4>,
1680 <0xac010 0x4>,
1681 <0xac114 0x4>;
1682 reg-names = "rev", "sysc", "syss";
1683 ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
1684 SYSC_OMAP2_SOFTRESET |
1685 SYSC_OMAP2_AUTOIDLE)>;
1686 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1687 <SYSC_IDLE_NO>,
1688 <SYSC_IDLE_SMART>,
1689 <SYSC_IDLE_SMART_WKUP>;
1690 ti,syss-mask = <1>;
1691 /* Domains (P, C): per_pwrdm, l4ls_clkdm */
1692 clocks = <&l4ls_clkctrl AM3_L4LS_GPIO3_CLKCTRL 0>,
1693 <&l4ls_clkctrl AM3_L4LS_GPIO3_CLKCTRL 18>;
1694 clock-names = "fck", "dbclk";
1695 #address-cells = <1>;
1696 #size-cells = <1>;
1697 ranges = <0x0 0xac000 0x1000>;
Tony Lindgren87fc89c2018-09-24 16:20:54 -07001698
1699 gpio2: gpio@0 {
1700 compatible = "ti,omap4-gpio";
1701 gpio-controller;
1702 #gpio-cells = <2>;
1703 interrupt-controller;
1704 #interrupt-cells = <2>;
1705 reg = <0x0 0x1000>;
1706 interrupts = <32>;
1707 };
Tony Lindgrenf711c572018-09-24 16:20:37 -07001708 };
1709
1710 target-module@ae000 { /* 0x481ae000, ap 56 3a.0 */
1711 compatible = "ti,sysc-omap2", "ti,sysc";
Tony Lindgrenf711c572018-09-24 16:20:37 -07001712 reg = <0xae000 0x4>,
1713 <0xae010 0x4>,
1714 <0xae114 0x4>;
1715 reg-names = "rev", "sysc", "syss";
1716 ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
1717 SYSC_OMAP2_SOFTRESET |
1718 SYSC_OMAP2_AUTOIDLE)>;
1719 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1720 <SYSC_IDLE_NO>,
1721 <SYSC_IDLE_SMART>,
1722 <SYSC_IDLE_SMART_WKUP>;
1723 ti,syss-mask = <1>;
1724 /* Domains (P, C): per_pwrdm, l4ls_clkdm */
1725 clocks = <&l4ls_clkctrl AM3_L4LS_GPIO4_CLKCTRL 0>,
1726 <&l4ls_clkctrl AM3_L4LS_GPIO4_CLKCTRL 18>;
1727 clock-names = "fck", "dbclk";
1728 #address-cells = <1>;
1729 #size-cells = <1>;
1730 ranges = <0x0 0xae000 0x1000>;
Tony Lindgren87fc89c2018-09-24 16:20:54 -07001731
1732 gpio3: gpio@0 {
1733 compatible = "ti,omap4-gpio";
1734 gpio-controller;
1735 #gpio-cells = <2>;
1736 interrupt-controller;
1737 #interrupt-cells = <2>;
1738 reg = <0x0 0x1000>;
1739 interrupts = <62>;
1740 };
Tony Lindgrenf711c572018-09-24 16:20:37 -07001741 };
1742
1743 target-module@b0000 { /* 0x481b0000, ap 58 50.0 */
1744 compatible = "ti,sysc";
1745 status = "disabled";
1746 #address-cells = <1>;
1747 #size-cells = <1>;
1748 ranges = <0x0 0xb0000 0x10000>;
1749 };
1750
1751 target-module@cc000 { /* 0x481cc000, ap 60 46.0 */
Tony Lindgren87fc89c2018-09-24 16:20:54 -07001752 compatible = "ti,sysc-omap4", "ti,sysc";
Tony Lindgren89bbc6f2019-07-22 03:44:42 -07001753 reg = <0xcc020 0x4>;
1754 reg-names = "rev";
Tony Lindgren87fc89c2018-09-24 16:20:54 -07001755 /* Domains (P, C): per_pwrdm, l4ls_clkdm */
Tony Lindgren516f1112019-05-01 14:24:09 -07001756 clocks = <&l4ls_clkctrl AM3_L4LS_D_CAN0_CLKCTRL 0>,
1757 <&dcan0_fck>;
1758 clock-names = "fck", "osc";
Tony Lindgrenf711c572018-09-24 16:20:37 -07001759 #address-cells = <1>;
1760 #size-cells = <1>;
1761 ranges = <0x0 0xcc000 0x2000>;
Tony Lindgren87fc89c2018-09-24 16:20:54 -07001762
1763 dcan0: can@0 {
1764 compatible = "ti,am3352-d_can";
1765 reg = <0x0 0x2000>;
1766 clocks = <&dcan0_fck>;
1767 clock-names = "fck";
1768 syscon-raminit = <&scm_conf 0x644 0>;
1769 interrupts = <52>;
1770 status = "disabled";
1771 };
Tony Lindgrenf711c572018-09-24 16:20:37 -07001772 };
1773
1774 target-module@d0000 { /* 0x481d0000, ap 62 42.0 */
Tony Lindgren87fc89c2018-09-24 16:20:54 -07001775 compatible = "ti,sysc-omap4", "ti,sysc";
Tony Lindgren89bbc6f2019-07-22 03:44:42 -07001776 reg = <0xd0020 0x4>;
1777 reg-names = "rev";
Tony Lindgren87fc89c2018-09-24 16:20:54 -07001778 /* Domains (P, C): per_pwrdm, l4ls_clkdm */
Tony Lindgren516f1112019-05-01 14:24:09 -07001779 clocks = <&l4ls_clkctrl AM3_L4LS_D_CAN1_CLKCTRL 0>,
1780 <&dcan1_fck>;
1781 clock-names = "fck", "osc";
Tony Lindgrenf711c572018-09-24 16:20:37 -07001782 #address-cells = <1>;
1783 #size-cells = <1>;
1784 ranges = <0x0 0xd0000 0x2000>;
Tony Lindgren87fc89c2018-09-24 16:20:54 -07001785
1786 dcan1: can@0 {
1787 compatible = "ti,am3352-d_can";
1788 reg = <0x0 0x2000>;
1789 clocks = <&dcan1_fck>;
1790 clock-names = "fck";
1791 syscon-raminit = <&scm_conf 0x644 1>;
1792 interrupts = <55>;
1793 status = "disabled";
1794 };
Tony Lindgrenf711c572018-09-24 16:20:37 -07001795 };
1796
1797 target-module@d8000 { /* 0x481d8000, ap 64 66.0 */
1798 compatible = "ti,sysc-omap2", "ti,sysc";
Tony Lindgrenf711c572018-09-24 16:20:37 -07001799 reg = <0xd82fc 0x4>,
1800 <0xd8110 0x4>,
1801 <0xd8114 0x4>;
1802 reg-names = "rev", "sysc", "syss";
1803 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
1804 SYSC_OMAP2_ENAWAKEUP |
1805 SYSC_OMAP2_SOFTRESET |
1806 SYSC_OMAP2_AUTOIDLE)>;
1807 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1808 <SYSC_IDLE_NO>,
1809 <SYSC_IDLE_SMART>;
1810 ti,syss-mask = <1>;
1811 /* Domains (P, C): per_pwrdm, l4ls_clkdm */
1812 clocks = <&l4ls_clkctrl AM3_L4LS_MMC2_CLKCTRL 0>;
1813 clock-names = "fck";
1814 #address-cells = <1>;
1815 #size-cells = <1>;
1816 ranges = <0x0 0xd8000 0x1000>;
Tony Lindgren87fc89c2018-09-24 16:20:54 -07001817
1818 mmc2: mmc@0 {
1819 compatible = "ti,omap4-hsmmc";
1820 ti,needs-special-reset;
1821 dmas = <&edma 2 0
1822 &edma 3 0>;
1823 dma-names = "tx", "rx";
1824 interrupts = <28>;
1825 reg = <0x0 0x1000>;
1826 status = "disabled";
1827 };
Tony Lindgrenf711c572018-09-24 16:20:37 -07001828 };
1829 };
1830
1831 segment@200000 { /* 0x48200000 */
1832 compatible = "simple-bus";
1833 #address-cells = <1>;
1834 #size-cells = <1>;
1835 };
1836
1837 segment@300000 { /* 0x48300000 */
1838 compatible = "simple-bus";
1839 #address-cells = <1>;
1840 #size-cells = <1>;
1841 ranges = <0x00000000 0x00300000 0x001000>, /* ap 66 */
1842 <0x00001000 0x00301000 0x001000>, /* ap 67 */
1843 <0x00002000 0x00302000 0x001000>, /* ap 68 */
1844 <0x00003000 0x00303000 0x001000>, /* ap 69 */
1845 <0x00004000 0x00304000 0x001000>, /* ap 70 */
1846 <0x00005000 0x00305000 0x001000>, /* ap 71 */
1847 <0x0000e000 0x0030e000 0x001000>, /* ap 72 */
1848 <0x0000f000 0x0030f000 0x001000>, /* ap 73 */
1849 <0x00018000 0x00318000 0x004000>, /* ap 74 */
1850 <0x0001c000 0x0031c000 0x001000>, /* ap 75 */
1851 <0x00010000 0x00310000 0x002000>, /* ap 76 */
1852 <0x00012000 0x00312000 0x001000>, /* ap 93 */
1853 <0x00015000 0x00315000 0x001000>, /* ap 94 */
1854 <0x00016000 0x00316000 0x001000>, /* ap 95 */
1855 <0x00017000 0x00317000 0x001000>, /* ap 96 */
1856 <0x00013000 0x00313000 0x001000>, /* ap 97 */
1857 <0x00014000 0x00314000 0x001000>, /* ap 98 */
1858 <0x00020000 0x00320000 0x001000>, /* ap 99 */
1859 <0x00021000 0x00321000 0x001000>, /* ap 100 */
1860 <0x00022000 0x00322000 0x001000>, /* ap 101 */
1861 <0x00023000 0x00323000 0x001000>, /* ap 102 */
1862 <0x00024000 0x00324000 0x001000>, /* ap 103 */
1863 <0x00025000 0x00325000 0x001000>; /* ap 104 */
1864
1865 target-module@0 { /* 0x48300000, ap 66 48.0 */
1866 compatible = "ti,sysc-omap4", "ti,sysc";
Tony Lindgrenf711c572018-09-24 16:20:37 -07001867 reg = <0x0 0x4>,
1868 <0x4 0x4>;
1869 reg-names = "rev", "sysc";
1870 ti,sysc-midle = <SYSC_IDLE_FORCE>,
1871 <SYSC_IDLE_NO>,
1872 <SYSC_IDLE_SMART>,
1873 <SYSC_IDLE_SMART_WKUP>;
1874 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1875 <SYSC_IDLE_NO>,
1876 <SYSC_IDLE_SMART>,
1877 <SYSC_IDLE_SMART_WKUP>;
1878 /* Domains (P, C): per_pwrdm, l4ls_clkdm */
1879 clocks = <&l4ls_clkctrl AM3_L4LS_EPWMSS0_CLKCTRL 0>;
1880 clock-names = "fck";
1881 #address-cells = <1>;
1882 #size-cells = <1>;
1883 ranges = <0x0 0x0 0x1000>;
Tony Lindgren87fc89c2018-09-24 16:20:54 -07001884
1885 epwmss0: epwmss@0 {
1886 compatible = "ti,am33xx-pwmss";
1887 reg = <0x0 0x10>;
1888 #address-cells = <1>;
1889 #size-cells = <1>;
1890 status = "disabled";
Tony Lindgrenf4ef6fd2018-12-10 13:43:11 -08001891 ranges = <0 0 0x1000>;
Tony Lindgren87fc89c2018-09-24 16:20:54 -07001892
Tony Lindgrenf4ef6fd2018-12-10 13:43:11 -08001893 ecap0: ecap@100 {
Tony Lindgren87fc89c2018-09-24 16:20:54 -07001894 compatible = "ti,am3352-ecap",
1895 "ti,am33xx-ecap";
1896 #pwm-cells = <3>;
Tony Lindgrenf4ef6fd2018-12-10 13:43:11 -08001897 reg = <0x100 0x80>;
Tony Lindgren87fc89c2018-09-24 16:20:54 -07001898 clocks = <&l4ls_gclk>;
1899 clock-names = "fck";
1900 interrupts = <31>;
1901 interrupt-names = "ecap0";
1902 status = "disabled";
1903 };
1904
Tony Lindgrenf4ef6fd2018-12-10 13:43:11 -08001905 ehrpwm0: pwm@200 {
Tony Lindgren87fc89c2018-09-24 16:20:54 -07001906 compatible = "ti,am3352-ehrpwm",
1907 "ti,am33xx-ehrpwm";
1908 #pwm-cells = <3>;
Tony Lindgrenf4ef6fd2018-12-10 13:43:11 -08001909 reg = <0x200 0x80>;
Tony Lindgren87fc89c2018-09-24 16:20:54 -07001910 clocks = <&ehrpwm0_tbclk>, <&l4ls_gclk>;
1911 clock-names = "tbclk", "fck";
1912 status = "disabled";
1913 };
1914 };
Tony Lindgrenf711c572018-09-24 16:20:37 -07001915 };
1916
1917 target-module@2000 { /* 0x48302000, ap 68 52.0 */
1918 compatible = "ti,sysc-omap4", "ti,sysc";
Tony Lindgrenf711c572018-09-24 16:20:37 -07001919 reg = <0x2000 0x4>,
1920 <0x2004 0x4>;
1921 reg-names = "rev", "sysc";
1922 ti,sysc-midle = <SYSC_IDLE_FORCE>,
1923 <SYSC_IDLE_NO>,
1924 <SYSC_IDLE_SMART>,
1925 <SYSC_IDLE_SMART_WKUP>;
1926 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1927 <SYSC_IDLE_NO>,
1928 <SYSC_IDLE_SMART>,
1929 <SYSC_IDLE_SMART_WKUP>;
1930 /* Domains (P, C): per_pwrdm, l4ls_clkdm */
1931 clocks = <&l4ls_clkctrl AM3_L4LS_EPWMSS1_CLKCTRL 0>;
1932 clock-names = "fck";
1933 #address-cells = <1>;
1934 #size-cells = <1>;
1935 ranges = <0x0 0x2000 0x1000>;
Tony Lindgren87fc89c2018-09-24 16:20:54 -07001936
1937 epwmss1: epwmss@0 {
1938 compatible = "ti,am33xx-pwmss";
1939 reg = <0x0 0x10>;
1940 #address-cells = <1>;
1941 #size-cells = <1>;
1942 status = "disabled";
Tony Lindgrenf4ef6fd2018-12-10 13:43:11 -08001943 ranges = <0 0 0x1000>;
Tony Lindgren87fc89c2018-09-24 16:20:54 -07001944
Tony Lindgrenf4ef6fd2018-12-10 13:43:11 -08001945 ecap1: ecap@100 {
Tony Lindgren87fc89c2018-09-24 16:20:54 -07001946 compatible = "ti,am3352-ecap",
1947 "ti,am33xx-ecap";
1948 #pwm-cells = <3>;
Tony Lindgrenf4ef6fd2018-12-10 13:43:11 -08001949 reg = <0x100 0x80>;
Tony Lindgren87fc89c2018-09-24 16:20:54 -07001950 clocks = <&l4ls_gclk>;
1951 clock-names = "fck";
1952 interrupts = <47>;
1953 interrupt-names = "ecap1";
1954 status = "disabled";
1955 };
1956
Tony Lindgrenf4ef6fd2018-12-10 13:43:11 -08001957 ehrpwm1: pwm@200 {
Tony Lindgren87fc89c2018-09-24 16:20:54 -07001958 compatible = "ti,am3352-ehrpwm",
1959 "ti,am33xx-ehrpwm";
1960 #pwm-cells = <3>;
Tony Lindgrenf4ef6fd2018-12-10 13:43:11 -08001961 reg = <0x200 0x80>;
Tony Lindgren87fc89c2018-09-24 16:20:54 -07001962 clocks = <&ehrpwm1_tbclk>, <&l4ls_gclk>;
1963 clock-names = "tbclk", "fck";
1964 status = "disabled";
1965 };
1966 };
Tony Lindgrenf711c572018-09-24 16:20:37 -07001967 };
1968
1969 target-module@4000 { /* 0x48304000, ap 70 44.0 */
1970 compatible = "ti,sysc-omap4", "ti,sysc";
Tony Lindgrenf711c572018-09-24 16:20:37 -07001971 reg = <0x4000 0x4>,
1972 <0x4004 0x4>;
1973 reg-names = "rev", "sysc";
1974 ti,sysc-midle = <SYSC_IDLE_FORCE>,
1975 <SYSC_IDLE_NO>,
1976 <SYSC_IDLE_SMART>,
1977 <SYSC_IDLE_SMART_WKUP>;
1978 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1979 <SYSC_IDLE_NO>,
1980 <SYSC_IDLE_SMART>,
1981 <SYSC_IDLE_SMART_WKUP>;
1982 /* Domains (P, C): per_pwrdm, l4ls_clkdm */
1983 clocks = <&l4ls_clkctrl AM3_L4LS_EPWMSS2_CLKCTRL 0>;
1984 clock-names = "fck";
1985 #address-cells = <1>;
1986 #size-cells = <1>;
1987 ranges = <0x0 0x4000 0x1000>;
Tony Lindgren87fc89c2018-09-24 16:20:54 -07001988
1989 epwmss2: epwmss@0 {
1990 compatible = "ti,am33xx-pwmss";
1991 reg = <0x0 0x10>;
1992 #address-cells = <1>;
1993 #size-cells = <1>;
1994 status = "disabled";
Tony Lindgrenf4ef6fd2018-12-10 13:43:11 -08001995 ranges = <0 0 0x1000>;
Tony Lindgren87fc89c2018-09-24 16:20:54 -07001996
Tony Lindgrenf4ef6fd2018-12-10 13:43:11 -08001997 ecap2: ecap@100 {
Tony Lindgren87fc89c2018-09-24 16:20:54 -07001998 compatible = "ti,am3352-ecap",
1999 "ti,am33xx-ecap";
2000 #pwm-cells = <3>;
Tony Lindgrenf4ef6fd2018-12-10 13:43:11 -08002001 reg = <0x100 0x80>;
Tony Lindgren87fc89c2018-09-24 16:20:54 -07002002 clocks = <&l4ls_gclk>;
2003 clock-names = "fck";
2004 interrupts = <61>;
2005 interrupt-names = "ecap2";
2006 status = "disabled";
2007 };
2008
Tony Lindgrenf4ef6fd2018-12-10 13:43:11 -08002009 ehrpwm2: pwm@200 {
Tony Lindgren87fc89c2018-09-24 16:20:54 -07002010 compatible = "ti,am3352-ehrpwm",
2011 "ti,am33xx-ehrpwm";
2012 #pwm-cells = <3>;
Tony Lindgrenf4ef6fd2018-12-10 13:43:11 -08002013 reg = <0x200 0x80>;
Tony Lindgren87fc89c2018-09-24 16:20:54 -07002014 clocks = <&ehrpwm2_tbclk>, <&l4ls_gclk>;
2015 clock-names = "tbclk", "fck";
2016 status = "disabled";
2017 };
2018 };
Tony Lindgrenf711c572018-09-24 16:20:37 -07002019 };
2020
2021 target-module@e000 { /* 0x4830e000, ap 72 4a.0 */
2022 compatible = "ti,sysc-omap4", "ti,sysc";
Tony Lindgrenf711c572018-09-24 16:20:37 -07002023 reg = <0xe000 0x4>,
2024 <0xe054 0x4>;
2025 reg-names = "rev", "sysc";
Tony Lindgren17529d432019-09-24 09:25:51 -07002026 ti,sysc-midle = <SYSC_IDLE_FORCE>,
2027 <SYSC_IDLE_NO>,
2028 <SYSC_IDLE_SMART>;
Tony Lindgrenf711c572018-09-24 16:20:37 -07002029 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
2030 <SYSC_IDLE_NO>,
2031 <SYSC_IDLE_SMART>;
2032 /* Domains (P, C): per_pwrdm, lcdc_clkdm */
2033 clocks = <&lcdc_clkctrl AM3_LCDC_LCDC_CLKCTRL 0>;
2034 clock-names = "fck";
2035 #address-cells = <1>;
2036 #size-cells = <1>;
2037 ranges = <0x0 0xe000 0x1000>;
Tony Lindgren87fc89c2018-09-24 16:20:54 -07002038
2039 lcdc: lcdc@0 {
2040 compatible = "ti,am33xx-tilcdc";
2041 reg = <0x0 0x1000>;
2042 interrupts = <36>;
2043 status = "disabled";
2044 };
Tony Lindgrenf711c572018-09-24 16:20:37 -07002045 };
2046
2047 target-module@10000 { /* 0x48310000, ap 76 4e.1 */
2048 compatible = "ti,sysc-omap2", "ti,sysc";
Tony Lindgrenf711c572018-09-24 16:20:37 -07002049 reg = <0x11fe0 0x4>,
2050 <0x11fe4 0x4>;
2051 reg-names = "rev", "sysc";
2052 ti,sysc-mask = <SYSC_OMAP2_AUTOIDLE>;
2053 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
2054 <SYSC_IDLE_NO>;
2055 /* Domains (P, C): per_pwrdm, l4ls_clkdm */
2056 clocks = <&l4ls_clkctrl AM3_L4LS_RNG_CLKCTRL 0>;
2057 clock-names = "fck";
2058 #address-cells = <1>;
2059 #size-cells = <1>;
2060 ranges = <0x0 0x10000 0x2000>;
Tony Lindgren87fc89c2018-09-24 16:20:54 -07002061
2062 rng: rng@0 {
2063 compatible = "ti,omap4-rng";
2064 reg = <0x0 0x2000>;
2065 interrupts = <111>;
2066 };
Tony Lindgrenf711c572018-09-24 16:20:37 -07002067 };
2068
2069 target-module@13000 { /* 0x48313000, ap 97 62.0 */
2070 compatible = "ti,sysc";
2071 status = "disabled";
2072 #address-cells = <1>;
2073 #size-cells = <1>;
2074 ranges = <0x0 0x13000 0x1000>;
2075 };
2076
2077 target-module@15000 { /* 0x48315000, ap 94 56.0 */
2078 compatible = "ti,sysc";
2079 status = "disabled";
2080 #address-cells = <1>;
2081 #size-cells = <1>;
2082 ranges = <0x00000000 0x00015000 0x00001000>,
2083 <0x00001000 0x00016000 0x00001000>;
2084 };
2085
2086 target-module@18000 { /* 0x48318000, ap 74 4c.0 */
2087 compatible = "ti,sysc";
2088 status = "disabled";
2089 #address-cells = <1>;
2090 #size-cells = <1>;
2091 ranges = <0x0 0x18000 0x4000>;
2092 };
2093
2094 target-module@20000 { /* 0x48320000, ap 99 34.0 */
2095 compatible = "ti,sysc";
2096 status = "disabled";
2097 #address-cells = <1>;
2098 #size-cells = <1>;
2099 ranges = <0x0 0x20000 0x1000>;
2100 };
2101
2102 target-module@22000 { /* 0x48322000, ap 101 3e.0 */
2103 compatible = "ti,sysc";
2104 status = "disabled";
2105 #address-cells = <1>;
2106 #size-cells = <1>;
2107 ranges = <0x0 0x22000 0x1000>;
2108 };
2109
2110 target-module@24000 { /* 0x48324000, ap 103 68.0 */
2111 compatible = "ti,sysc";
2112 status = "disabled";
2113 #address-cells = <1>;
2114 #size-cells = <1>;
2115 ranges = <0x0 0x24000 0x1000>;
2116 };
2117 };
2118};
2119