blob: 020a71b915774158d05adfd9628323a29c83dc69 [file] [log] [blame]
Thomas Gleixnera61127c2019-05-29 16:57:49 -07001/* SPDX-License-Identifier: GPL-2.0-only */
Alan Cox5c49fd32011-11-03 18:22:04 +00002/**************************************************************************
3 * Copyright (c) 2007-2011, Intel Corporation.
4 * All Rights Reserved.
5 *
Alan Cox5c49fd32011-11-03 18:22:04 +00006 **************************************************************************/
7
8#ifndef _PSB_DRV_H_
9#define _PSB_DRV_H_
10
11#include <linux/kref.h>
Souptick Joarder0edf6812018-08-23 17:01:22 -070012#include <linux/mm_types.h>
Alan Cox5c49fd32011-11-03 18:22:04 +000013
Sam Ravnborg51474332019-05-19 21:55:23 +020014#include <drm/drm_device.h>
Sam Ravnborgd825c562019-05-19 21:55:22 +020015
Patrik Jakobsson5ea75e02013-06-30 21:39:00 +020016#include "gma_display.h"
Alan Cox5c49fd32011-11-03 18:22:04 +000017#include "gtt.h"
Sam Ravnborg0c7b1782019-05-19 21:55:26 +020018#include "intel_bios.h"
Patrik Jakobssonac1b01b2014-01-04 19:35:20 +010019#include "mmu.h"
Sam Ravnborg0c7b1782019-05-19 21:55:26 +020020#include "oaktrail.h"
21#include "opregion.h"
22#include "power.h"
23#include "psb_intel_drv.h"
24#include "psb_reg.h"
Alan Cox5c49fd32011-11-03 18:22:04 +000025
Arthur Borsboomf90cd812014-03-15 22:12:17 +010026#define DRIVER_AUTHOR "Alan Cox <alan@linux.intel.com> and others"
Arthur Borsboomf90cd812014-03-15 22:12:17 +010027
28#define DRIVER_NAME "gma500"
29#define DRIVER_DESC "DRM driver for the Intel GMA500, GMA600, GMA3600, GMA3650"
30#define DRIVER_DATE "20140314"
31
32#define DRIVER_MAJOR 1
33#define DRIVER_MINOR 0
34#define DRIVER_PATCHLEVEL 0
35
Alan Cox5c49fd32011-11-03 18:22:04 +000036/* Append new drm mode definition here, align with libdrm definition */
37#define DRM_MODE_SCALE_NO_SCALE 2
38
39enum {
40 CHIP_PSB_8108 = 0, /* Poulsbo */
41 CHIP_PSB_8109 = 1, /* Poulsbo */
42 CHIP_MRST_4100 = 2, /* Moorestown/Oaktrail */
Alan Cox5c49fd32011-11-03 18:22:04 +000043};
44
Thomas Zimmermanna2c68492020-12-01 11:35:29 +010045#define IS_PSB(drm) ((to_pci_dev((drm)->dev)->device & 0xfffe) == 0x8108)
46#define IS_MRST(drm) ((to_pci_dev((drm)->dev)->device & 0xfff0) == 0x4100)
Thomas Zimmermanna2c68492020-12-01 11:35:29 +010047#define IS_CDV(drm) ((to_pci_dev((drm)->dev)->device & 0xfff0) == 0x0be0)
Alan Cox5c49fd32011-11-03 18:22:04 +000048
Arthur Borsboom9083eb32014-03-15 22:12:18 +010049/* Hardware offsets */
Alan Cox5c49fd32011-11-03 18:22:04 +000050#define PSB_VDC_OFFSET 0x00000000
51#define PSB_VDC_SIZE 0x000080000
52#define MRST_MMIO_SIZE 0x0000C0000
Alan Cox5c49fd32011-11-03 18:22:04 +000053#define PSB_SGX_SIZE 0x8000
54#define PSB_SGX_OFFSET 0x00040000
55#define MRST_SGX_OFFSET 0x00080000
Arthur Borsboom9083eb32014-03-15 22:12:18 +010056
57/* PCI resource identifiers */
Alan Cox5c49fd32011-11-03 18:22:04 +000058#define PSB_MMIO_RESOURCE 0
Patrik Jakobsson26579292013-09-16 18:02:40 +020059#define PSB_AUX_RESOURCE 0
Alan Cox5c49fd32011-11-03 18:22:04 +000060#define PSB_GATT_RESOURCE 2
61#define PSB_GTT_RESOURCE 3
Arthur Borsboom9083eb32014-03-15 22:12:18 +010062
63/* PCI configuration */
Alan Cox5c49fd32011-11-03 18:22:04 +000064#define PSB_GMCH_CTRL 0x52
65#define PSB_BSM 0x5C
66#define _PSB_GMCH_ENABLED 0x4
67#define PSB_PGETBL_CTL 0x2020
68#define _PSB_PGETBL_ENABLED 0x00000001
69#define PSB_SGX_2D_SLAVE_PORT 0x4000
Jan Safrata5a52b1f2014-09-26 10:40:29 +020070#define PSB_LPC_GBA 0x44
Alan Cox5c49fd32011-11-03 18:22:04 +000071
Arthur Borsboom9083eb32014-03-15 22:12:18 +010072/* TODO: To get rid of */
Alan Cox5c49fd32011-11-03 18:22:04 +000073#define PSB_TT_PRIV0_LIMIT (256*1024*1024)
74#define PSB_TT_PRIV0_PLIMIT (PSB_TT_PRIV0_LIMIT >> PAGE_SHIFT)
75
Arthur Borsboom9083eb32014-03-15 22:12:18 +010076/* SGX side MMU definitions (these can probably go) */
Alan Cox5c49fd32011-11-03 18:22:04 +000077
Arthur Borsboom9083eb32014-03-15 22:12:18 +010078/* Flags for external memory type field */
Alan Cox5c49fd32011-11-03 18:22:04 +000079#define PSB_MMU_CACHED_MEMORY 0x0001 /* Bind to MMU only */
80#define PSB_MMU_RO_MEMORY 0x0002 /* MMU RO memory */
81#define PSB_MMU_WO_MEMORY 0x0004 /* MMU WO memory */
Arthur Borsboom9083eb32014-03-15 22:12:18 +010082
83/* PTE's and PDE's */
Alan Cox5c49fd32011-11-03 18:22:04 +000084#define PSB_PDE_MASK 0x003FFFFF
85#define PSB_PDE_SHIFT 22
86#define PSB_PTE_SHIFT 12
Arthur Borsboom9083eb32014-03-15 22:12:18 +010087
88/* Cache control */
Alan Cox5c49fd32011-11-03 18:22:04 +000089#define PSB_PTE_VALID 0x0001 /* PTE / PDE valid */
90#define PSB_PTE_WO 0x0002 /* Write only */
91#define PSB_PTE_RO 0x0004 /* Read only */
92#define PSB_PTE_CACHED 0x0008 /* CPU cache coherent */
93
Arthur Borsboom9083eb32014-03-15 22:12:18 +010094/* VDC registers and bits */
Alan Cox5c49fd32011-11-03 18:22:04 +000095#define PSB_MSVDX_CLOCKGATING 0x2064
96#define PSB_TOPAZ_CLOCKGATING 0x2068
97#define PSB_HWSTAM 0x2098
98#define PSB_INSTPM 0x20C0
99#define PSB_INT_IDENTITY_R 0x20A4
Alan Coxd839ede2012-05-03 15:06:18 +0100100#define _PSB_IRQ_ASLE (1<<0)
Alan Cox5c49fd32011-11-03 18:22:04 +0000101#define _MDFLD_PIPEC_EVENT_FLAG (1<<2)
102#define _MDFLD_PIPEC_VBLANK_FLAG (1<<3)
103#define _PSB_DPST_PIPEB_FLAG (1<<4)
104#define _MDFLD_PIPEB_EVENT_FLAG (1<<4)
105#define _PSB_VSYNC_PIPEB_FLAG (1<<5)
106#define _PSB_DPST_PIPEA_FLAG (1<<6)
107#define _PSB_PIPEA_EVENT_FLAG (1<<6)
108#define _PSB_VSYNC_PIPEA_FLAG (1<<7)
Alan Cox68cb6382012-04-25 14:38:20 +0100109#define _PSB_IRQ_DISP_HOTSYNC (1<<17)
Alan Cox5c49fd32011-11-03 18:22:04 +0000110#define _PSB_IRQ_SGX_FLAG (1<<18)
111#define _PSB_IRQ_MSVDX_FLAG (1<<19)
112#define _LNC_IRQ_TOPAZ_FLAG (1<<20)
113
Patrik Jakobsson700e59f2011-11-29 22:20:34 +0000114#define _PSB_PIPE_EVENT_FLAG (_PSB_VSYNC_PIPEA_FLAG | \
115 _PSB_VSYNC_PIPEB_FLAG)
116
Alan Cox5c49fd32011-11-03 18:22:04 +0000117#define PSB_INT_IDENTITY_R 0x20A4
118#define PSB_INT_MASK_R 0x20A8
119#define PSB_INT_ENABLE_R 0x20A0
120
121#define _PSB_MMU_ER_MASK 0x0001FF00
122#define _PSB_MMU_ER_HOST (1 << 16)
123#define GPIOA 0x5010
124#define GPIOB 0x5014
125#define GPIOC 0x5018
126#define GPIOD 0x501c
127#define GPIOE 0x5020
128#define GPIOF 0x5024
129#define GPIOG 0x5028
130#define GPIOH 0x502c
131#define GPIO_CLOCK_DIR_MASK (1 << 0)
132#define GPIO_CLOCK_DIR_IN (0 << 1)
133#define GPIO_CLOCK_DIR_OUT (1 << 1)
134#define GPIO_CLOCK_VAL_MASK (1 << 2)
135#define GPIO_CLOCK_VAL_OUT (1 << 3)
136#define GPIO_CLOCK_VAL_IN (1 << 4)
137#define GPIO_CLOCK_PULLUP_DISABLE (1 << 5)
138#define GPIO_DATA_DIR_MASK (1 << 8)
139#define GPIO_DATA_DIR_IN (0 << 9)
140#define GPIO_DATA_DIR_OUT (1 << 9)
141#define GPIO_DATA_VAL_MASK (1 << 10)
142#define GPIO_DATA_VAL_OUT (1 << 11)
143#define GPIO_DATA_VAL_IN (1 << 12)
144#define GPIO_DATA_PULLUP_DISABLE (1 << 13)
145
146#define VCLK_DIVISOR_VGA0 0x6000
147#define VCLK_DIVISOR_VGA1 0x6004
148#define VCLK_POST_DIV 0x6010
149
150#define PSB_COMM_2D (PSB_ENGINE_2D << 4)
151#define PSB_COMM_3D (PSB_ENGINE_3D << 4)
152#define PSB_COMM_TA (PSB_ENGINE_TA << 4)
153#define PSB_COMM_HP (PSB_ENGINE_HP << 4)
154#define PSB_COMM_USER_IRQ (1024 >> 2)
155#define PSB_COMM_USER_IRQ_LOST (PSB_COMM_USER_IRQ + 1)
156#define PSB_COMM_FW (2048 >> 2)
157
158#define PSB_UIRQ_VISTEST 1
159#define PSB_UIRQ_OOM_REPLY 2
160#define PSB_UIRQ_FIRE_TA_REPLY 3
161#define PSB_UIRQ_FIRE_RASTER_REPLY 4
162
163#define PSB_2D_SIZE (256*1024*1024)
164#define PSB_MAX_RELOC_PAGES 1024
165
166#define PSB_LOW_REG_OFFS 0x0204
167#define PSB_HIGH_REG_OFFS 0x0600
168
169#define PSB_NUM_VBLANKS 2
170
171
172#define PSB_2D_SIZE (256*1024*1024)
173#define PSB_MAX_RELOC_PAGES 1024
174
175#define PSB_LOW_REG_OFFS 0x0204
176#define PSB_HIGH_REG_OFFS 0x0600
177
178#define PSB_NUM_VBLANKS 2
Daniel Vetterbfd83032013-12-11 11:34:41 +0100179#define PSB_WATCHDOG_DELAY (HZ * 2)
180#define PSB_LID_DELAY (HZ / 10)
Alan Cox5c49fd32011-11-03 18:22:04 +0000181
Alan Cox5c49fd32011-11-03 18:22:04 +0000182#define PSB_PWR_STATE_ON 1
183#define PSB_PWR_STATE_OFF 2
184
185#define PSB_PMPOLICY_NOPM 0
186#define PSB_PMPOLICY_CLOCKGATING 1
187#define PSB_PMPOLICY_POWERDOWN 2
188
189#define PSB_PMSTATE_POWERUP 0
190#define PSB_PMSTATE_CLOCKGATED 1
191#define PSB_PMSTATE_POWERDOWN 2
192#define PSB_PCIx_MSI_ADDR_LOC 0x94
193#define PSB_PCIx_MSI_DATA_LOC 0x98
194
195/* Medfield crystal settings */
196#define KSEL_CRYSTAL_19 1
197#define KSEL_BYPASS_19 5
198#define KSEL_BYPASS_25 6
199#define KSEL_BYPASS_83_100 7
200
Thomas Zimmermann6b7ce2c2019-11-22 11:05:45 +0100201struct drm_fb_helper;
202
Alan Cox5c49fd32011-11-03 18:22:04 +0000203struct opregion_header;
204struct opregion_acpi;
205struct opregion_swsci;
206struct opregion_asle;
207
208struct psb_intel_opregion {
209 struct opregion_header *header;
210 struct opregion_acpi *acpi;
211 struct opregion_swsci *swsci;
212 struct opregion_asle *asle;
Alan Cox1fb28e92012-04-25 14:37:14 +0100213 void *vbt;
Alan Coxd839ede2012-05-03 15:06:18 +0100214 u32 __iomem *lid_state;
Patrik Jakobsson778e26d2014-03-11 18:51:20 +0100215 struct work_struct asle_work;
Alan Cox5c49fd32011-11-03 18:22:04 +0000216};
217
Patrik Jakobsson57369952011-12-19 21:41:10 +0000218struct sdvo_device_mapping {
219 u8 initialized;
220 u8 dvo_port;
221 u8 slave_addr;
222 u8 dvo_wiring;
223 u8 i2c_pin;
224 u8 i2c_speed;
225 u8 ddc_pin;
226};
227
Patrik Jakobsson5c0c1d52011-12-19 21:40:58 +0000228struct intel_gmbus {
229 struct i2c_adapter adapter;
230 struct i2c_adapter *force_bit;
231 u32 reg0;
232};
233
Arthur Borsboom9083eb32014-03-15 22:12:18 +0100234/* Register offset maps */
Alan Cox8512e072012-05-11 11:30:53 +0100235struct psb_offset {
236 u32 fp0;
237 u32 fp1;
238 u32 cntr;
239 u32 conf;
240 u32 src;
241 u32 dpll;
242 u32 dpll_md;
243 u32 htotal;
244 u32 hblank;
245 u32 hsync;
246 u32 vtotal;
247 u32 vblank;
248 u32 vsync;
249 u32 stride;
250 u32 size;
251 u32 pos;
252 u32 surf;
253 u32 addr;
254 u32 base;
255 u32 status;
256 u32 linoff;
257 u32 tileoff;
258 u32 palette;
259};
260
261/*
Alan Cox648a8e32012-03-08 16:00:31 +0000262 * Register save state. This is used to hold the context when the
263 * device is powered off. In the case of Oaktrail this can (but does not
264 * yet) include screen blank. Operations occuring during the save
265 * update the register cache instead.
266 */
Alan Cox62563042012-05-11 11:30:16 +0100267
Arthur Borsboom9083eb32014-03-15 22:12:18 +0100268/* Common status for pipes */
Alan Cox62563042012-05-11 11:30:16 +0100269struct psb_pipe {
270 u32 fp0;
271 u32 fp1;
272 u32 cntr;
273 u32 conf;
274 u32 src;
275 u32 dpll;
276 u32 dpll_md;
277 u32 htotal;
278 u32 hblank;
279 u32 hsync;
280 u32 vtotal;
281 u32 vblank;
282 u32 vsync;
283 u32 stride;
284 u32 size;
285 u32 pos;
286 u32 base;
287 u32 surf;
288 u32 addr;
289 u32 status;
290 u32 linoff;
291 u32 tileoff;
292 u32 palette[256];
293};
294
Alan Cox648a8e32012-03-08 16:00:31 +0000295struct psb_state {
Alan Cox648a8e32012-03-08 16:00:31 +0000296 uint32_t saveVCLK_DIVISOR_VGA0;
297 uint32_t saveVCLK_DIVISOR_VGA1;
298 uint32_t saveVCLK_POST_DIV;
299 uint32_t saveVGACNTRL;
300 uint32_t saveADPA;
301 uint32_t saveLVDS;
302 uint32_t saveDVOA;
303 uint32_t saveDVOB;
304 uint32_t saveDVOC;
305 uint32_t savePP_ON;
306 uint32_t savePP_OFF;
307 uint32_t savePP_CONTROL;
308 uint32_t savePP_CYCLE;
309 uint32_t savePFIT_CONTROL;
Alan Cox648a8e32012-03-08 16:00:31 +0000310 uint32_t saveCLOCKGATING;
311 uint32_t saveDSPARB;
Alan Cox648a8e32012-03-08 16:00:31 +0000312 uint32_t savePFIT_AUTO_RATIOS;
313 uint32_t savePFIT_PGM_RATIOS;
314 uint32_t savePP_ON_DELAYS;
315 uint32_t savePP_OFF_DELAYS;
316 uint32_t savePP_DIVISOR;
Alan Cox648a8e32012-03-08 16:00:31 +0000317 uint32_t saveBCLRPAT_A;
318 uint32_t saveBCLRPAT_B;
Alan Cox648a8e32012-03-08 16:00:31 +0000319 uint32_t savePERF_MODE;
320 uint32_t saveDSPFW1;
321 uint32_t saveDSPFW2;
322 uint32_t saveDSPFW3;
323 uint32_t saveDSPFW4;
324 uint32_t saveDSPFW5;
325 uint32_t saveDSPFW6;
326 uint32_t saveCHICKENBIT;
327 uint32_t saveDSPACURSOR_CTRL;
328 uint32_t saveDSPBCURSOR_CTRL;
329 uint32_t saveDSPACURSOR_BASE;
330 uint32_t saveDSPBCURSOR_BASE;
331 uint32_t saveDSPACURSOR_POS;
332 uint32_t saveDSPBCURSOR_POS;
Alan Cox648a8e32012-03-08 16:00:31 +0000333 uint32_t saveOV_OVADD;
334 uint32_t saveOV_OGAMC0;
335 uint32_t saveOV_OGAMC1;
336 uint32_t saveOV_OGAMC2;
337 uint32_t saveOV_OGAMC3;
338 uint32_t saveOV_OGAMC4;
339 uint32_t saveOV_OGAMC5;
340 uint32_t saveOVC_OVADD;
341 uint32_t saveOVC_OGAMC0;
342 uint32_t saveOVC_OGAMC1;
343 uint32_t saveOVC_OGAMC2;
344 uint32_t saveOVC_OGAMC3;
345 uint32_t saveOVC_OGAMC4;
346 uint32_t saveOVC_OGAMC5;
347
348 /* DPST register save */
349 uint32_t saveHISTOGRAM_INT_CONTROL_REG;
350 uint32_t saveHISTOGRAM_LOGIC_CONTROL_REG;
351 uint32_t savePWM_CONTROL_LOGIC;
352};
353
Alan Cox09016a12012-03-14 12:00:29 +0000354struct cdv_state {
355 uint32_t saveDSPCLK_GATE_D;
356 uint32_t saveRAMCLK_GATE_D;
357 uint32_t saveDSPARB;
358 uint32_t saveDSPFW[6];
359 uint32_t saveADPA;
360 uint32_t savePP_CONTROL;
361 uint32_t savePFIT_PGM_RATIOS;
362 uint32_t saveLVDS;
363 uint32_t savePFIT_CONTROL;
364 uint32_t savePP_ON_DELAYS;
365 uint32_t savePP_OFF_DELAYS;
366 uint32_t savePP_CYCLE;
367 uint32_t saveVGACNTRL;
368 uint32_t saveIER;
369 uint32_t saveIMR;
370 u8 saveLBB;
371};
372
Alan Coxc6265ff2012-03-08 16:02:05 +0000373struct psb_save_area {
Alan Cox62563042012-05-11 11:30:16 +0100374 struct psb_pipe pipe[3];
Alan Coxc6265ff2012-03-08 16:02:05 +0000375 uint32_t saveBSM;
376 uint32_t saveVBT;
377 union {
378 struct psb_state psb;
Alan Cox09016a12012-03-14 12:00:29 +0000379 struct cdv_state cdv;
Alan Coxc6265ff2012-03-08 16:02:05 +0000380 };
381 uint32_t saveBLC_PWM_CTL2;
382 uint32_t saveBLC_PWM_CTL;
383};
384
Alan Cox5c49fd32011-11-03 18:22:04 +0000385struct psb_ops;
386
Alan Cox04bd5642011-11-16 22:39:32 +0000387#define PSB_NUM_PIPE 3
388
Alan Cox5c49fd32011-11-03 18:22:04 +0000389struct drm_psb_private {
390 struct drm_device *dev;
Patrik Jakobsson26579292013-09-16 18:02:40 +0200391 struct pci_dev *aux_pdev; /* Currently only used by mrst */
Jan Safrata5a52b1f2014-09-26 10:40:29 +0200392 struct pci_dev *lpc_pdev; /* Currently only used by mrst */
Alan Cox5c49fd32011-11-03 18:22:04 +0000393 const struct psb_ops *ops;
Alan Cox8512e072012-05-11 11:30:53 +0100394 const struct psb_offset *regmap;
Thomas Zimmermann6b7ce2c2019-11-22 11:05:45 +0100395
Alan Cox1fb28e92012-04-25 14:37:14 +0100396 struct child_device_config *child_dev;
397 int child_dev_num;
Alan Cox5c49fd32011-11-03 18:22:04 +0000398
399 struct psb_gtt gtt;
400
401 /* GTT Memory manager */
402 struct psb_gtt_mm *gtt_mm;
403 struct page *scratch_page;
Kirill A. Shutemoveab37602012-05-03 15:07:46 +0100404 u32 __iomem *gtt_map;
Alan Cox5c49fd32011-11-03 18:22:04 +0000405 uint32_t stolen_base;
Kirill A. Shutemov37214ca2012-05-03 15:08:26 +0100406 u8 __iomem *vram_addr;
Alan Cox5c49fd32011-11-03 18:22:04 +0000407 unsigned long vram_stolen_size;
408 int gtt_initialized;
409 u16 gmch_ctrl; /* Saved GTT setup */
410 u32 pge_ctl;
411
412 struct mutex gtt_mutex;
413 struct resource *gtt_mem; /* Our PCI resource */
414
Daniel Vetter737292a2015-11-23 10:32:53 +0100415 struct mutex mmap_mutex;
416
Alan Cox5c49fd32011-11-03 18:22:04 +0000417 struct psb_mmu_driver *mmu;
418 struct psb_mmu_pd *pf_pd;
419
Arthur Borsboom9083eb32014-03-15 22:12:18 +0100420 /* Register base */
Kirill A. Shutemov846a60382012-05-03 15:08:08 +0100421 uint8_t __iomem *sgx_reg;
422 uint8_t __iomem *vdc_reg;
Patrik Jakobsson26579292013-09-16 18:02:40 +0200423 uint8_t __iomem *aux_reg; /* Auxillary vdc pipe regs */
Jan Safrata5a52b1f2014-09-26 10:40:29 +0200424 uint16_t lpc_gpio_base;
Alan Cox5c49fd32011-11-03 18:22:04 +0000425 uint32_t gatt_free_offset;
426
Arthur Borsboom9083eb32014-03-15 22:12:18 +0100427 /* Fencing / irq */
Alan Cox5c49fd32011-11-03 18:22:04 +0000428 uint32_t vdc_irq_mask;
429 uint32_t pipestat[PSB_NUM_PIPE];
430
431 spinlock_t irqmask_lock;
432
Arthur Borsboom9083eb32014-03-15 22:12:18 +0100433 /* Power */
Alan Cox5c49fd32011-11-03 18:22:04 +0000434 bool suspended;
435 bool display_power;
436 int display_count;
437
Arthur Borsboom9083eb32014-03-15 22:12:18 +0100438 /* Modesetting */
Alan Cox5c49fd32011-11-03 18:22:04 +0000439 struct psb_intel_mode_device mode_dev;
Alan Cox4ab2c7f2012-05-14 12:04:00 +0100440 bool modeset; /* true if we have done the mode_device setup */
Alan Cox5c49fd32011-11-03 18:22:04 +0000441
442 struct drm_crtc *plane_to_crtc_mapping[PSB_NUM_PIPE];
443 struct drm_crtc *pipe_to_crtc_mapping[PSB_NUM_PIPE];
444 uint32_t num_pipe;
445
Arthur Borsboom9083eb32014-03-15 22:12:18 +0100446 /* OSPM info (Power management base) (TODO: can go ?) */
Alan Cox5c49fd32011-11-03 18:22:04 +0000447 uint32_t ospm_base;
448
Arthur Borsboom9083eb32014-03-15 22:12:18 +0100449 /* Sizes info */
Alan Cox5c49fd32011-11-03 18:22:04 +0000450 u32 fuse_reg_value;
451 u32 video_device_fuse;
452
453 /* PCI revision ID for B0:D2:F0 */
454 uint8_t platform_rev_id;
455
Patrik Jakobsson5c0c1d52011-12-19 21:40:58 +0000456 /* gmbus */
457 struct intel_gmbus *gmbus;
Patrik Jakobsson26579292013-09-16 18:02:40 +0200458 uint8_t __iomem *gmbus_reg;
Patrik Jakobsson5c0c1d52011-12-19 21:40:58 +0000459
Patrik Jakobsson57369952011-12-19 21:41:10 +0000460 /* Used by SDVO */
461 int crt_ddc_pin;
462 /* FIXME: The mappings should be parsed from bios but for now we can
463 pretend there are no mappings available */
464 struct sdvo_device_mapping sdvo_mappings[2];
465 u32 hotplug_supported_mask;
466 struct drm_property *broadcast_rgb_property;
467 struct drm_property *force_audio_property;
468
Arthur Borsboom9083eb32014-03-15 22:12:18 +0100469 /* LVDS info */
Alan Cox5c49fd32011-11-03 18:22:04 +0000470 int backlight_duty_cycle; /* restore backlight to this value */
471 bool panel_wants_dither;
472 struct drm_display_mode *panel_fixed_mode;
473 struct drm_display_mode *lfp_lvds_vbt_mode;
474 struct drm_display_mode *sdvo_lvds_vbt_mode;
475
476 struct bdb_lvds_backlight *lvds_bl; /* LVDS backlight info from VBT */
Patrik Jakobssona12d6a02011-12-19 21:41:22 +0000477 struct psb_intel_i2c_chan *lvds_i2c_bus; /* FIXME: Remove this? */
Alan Cox5c49fd32011-11-03 18:22:04 +0000478
479 /* Feature bits from the VBIOS */
480 unsigned int int_tv_support:1;
481 unsigned int lvds_dither:1;
482 unsigned int lvds_vbt:1;
483 unsigned int int_crt_support:1;
484 unsigned int lvds_use_ssc:1;
485 int lvds_ssc_freq;
486 bool is_lvds_on;
487 bool is_mipi_on;
Patrik Jakobsson7c420632019-04-16 13:46:07 +0200488 bool lvds_enabled_in_vbt;
Alan Cox5c49fd32011-11-03 18:22:04 +0000489 u32 mipi_ctrl_display;
490
491 unsigned int core_freq;
492 uint32_t iLVDS_enable;
493
494 /* Runtime PM state */
495 int rpm_enabled;
496
497 /* MID specific */
Kirill A. Shutemov4086b1e2012-05-03 16:27:21 +0100498 bool has_gct;
Alan Cox5c49fd32011-11-03 18:22:04 +0000499 struct oaktrail_gct_data gct_data;
500
Alan Cox933315a2012-03-08 16:00:17 +0000501 /* Oaktrail HDMI state */
Alan Cox5c49fd32011-11-03 18:22:04 +0000502 struct oaktrail_hdmi_dev *hdmi_priv;
Thomas Zimmermann6b7ce2c2019-11-22 11:05:45 +0100503
Arthur Borsboom9083eb32014-03-15 22:12:18 +0100504 /* Register state */
Alan Coxc6265ff2012-03-08 16:02:05 +0000505 struct psb_save_area regs;
506
Alan Cox5c49fd32011-11-03 18:22:04 +0000507 /* MSI reg save */
508 uint32_t msi_addr;
509 uint32_t msi_data;
510
Arthur Borsboom9083eb32014-03-15 22:12:18 +0100511 /* Hotplug handling */
Alan Coxae0a2462012-04-25 14:38:32 +0100512 struct work_struct hotplug_work;
Alan Cox5c49fd32011-11-03 18:22:04 +0000513
Arthur Borsboom9083eb32014-03-15 22:12:18 +0100514 /* LID-Switch */
Alan Cox5c49fd32011-11-03 18:22:04 +0000515 spinlock_t lid_lock;
516 struct timer_list lid_timer;
517 struct psb_intel_opregion opregion;
Alan Cox5c49fd32011-11-03 18:22:04 +0000518 u32 lid_last_state;
519
Arthur Borsboom9083eb32014-03-15 22:12:18 +0100520 /* Watchdog */
Alan Cox5c49fd32011-11-03 18:22:04 +0000521 uint32_t apm_reg;
522 uint16_t apm_base;
523
524 /*
525 * Used for modifying backlight from
526 * xrandr -- consider removing and using HAL instead
527 */
528 struct backlight_device *backlight_device;
529 struct drm_property *backlight_property;
Zhao Yakuid112a812012-08-08 13:55:55 +0000530 bool backlight_enabled;
531 int backlight_level;
Alan Cox5c49fd32011-11-03 18:22:04 +0000532 uint32_t blc_adj1;
533 uint32_t blc_adj2;
534
Thomas Zimmermann6b7ce2c2019-11-22 11:05:45 +0100535 struct drm_fb_helper *fb_helper;
Alan Cox5c49fd32011-11-03 18:22:04 +0000536
Arthur Borsboom9083eb32014-03-15 22:12:18 +0100537 /* Panel brightness */
Kirill A. Shutemov026abc32012-03-08 16:02:20 +0000538 int brightness;
539 int brightness_adjusted;
540
541 bool dsr_enable;
542 u32 dsr_fb_update;
543 bool dpi_panel_on[3];
544 void *dsi_configs[2];
545 u32 bpp;
546 u32 bpp2;
547
548 u32 pipeconf[3];
549 u32 dspcntr[3];
550
Alan Cox642c52f2012-04-25 14:36:34 +0100551 bool dplla_96mhz; /* DPLL data from the VBT */
Zhao Yakuid112a812012-08-08 13:55:55 +0000552
553 struct {
554 int rate;
555 int lanes;
556 int preemphasis;
557 int vswing;
558
559 bool initialized;
560 bool support;
561 int bpp;
562 struct edp_power_seq pps;
563 } edp;
564 uint8_t panel_type;
Alan Cox5c49fd32011-11-03 18:22:04 +0000565};
566
567
Arthur Borsboom9083eb32014-03-15 22:12:18 +0100568/* Operations for each board type */
Alan Cox5c49fd32011-11-03 18:22:04 +0000569struct psb_ops {
570 const char *name;
Alan Cox5c49fd32011-11-03 18:22:04 +0000571 int pipes; /* Number of output pipes */
572 int crtcs; /* Number of CRTCs */
573 int sgx_offset; /* Base offset of SGX device */
Alan Coxd235e642012-04-25 14:38:07 +0100574 int hdmi_mask; /* Mask of HDMI CRTCs */
575 int lvds_mask; /* Mask of LVDS CRTCs */
Patrik Jakobssoncf8efd32013-09-16 17:54:54 +0200576 int sdvo_mask; /* Mask of SDVO CRTCs */
Patrik Jakobssonbc794822012-05-21 15:27:30 +0100577 int cursor_needs_phys; /* If cursor base reg need physical address */
Alan Cox5c49fd32011-11-03 18:22:04 +0000578
579 /* Sub functions */
580 struct drm_crtc_helper_funcs const *crtc_helper;
581 struct drm_crtc_funcs const *crtc_funcs;
Patrik Jakobsson5ea75e02013-06-30 21:39:00 +0200582 const struct gma_clock_funcs *clock_funcs;
Alan Cox5c49fd32011-11-03 18:22:04 +0000583
584 /* Setup hooks */
585 int (*chip_setup)(struct drm_device *dev);
586 void (*chip_teardown)(struct drm_device *dev);
Alan Coxd235e642012-04-25 14:38:07 +0100587 /* Optional helper caller after modeset */
588 void (*errata)(struct drm_device *dev);
Alan Cox5c49fd32011-11-03 18:22:04 +0000589
590 /* Display management hooks */
591 int (*output_init)(struct drm_device *dev);
Alan Cox68cb6382012-04-25 14:38:20 +0100592 int (*hotplug)(struct drm_device *dev);
593 void (*hotplug_enable)(struct drm_device *dev, bool on);
Alan Cox5c49fd32011-11-03 18:22:04 +0000594 /* Power management hooks */
595 void (*init_pm)(struct drm_device *dev);
596 int (*save_regs)(struct drm_device *dev);
597 int (*restore_regs)(struct drm_device *dev);
Daniel Vetterd56f57a2015-12-04 09:45:53 +0100598 void (*save_crtc)(struct drm_crtc *crtc);
599 void (*restore_crtc)(struct drm_crtc *crtc);
Alan Cox5c49fd32011-11-03 18:22:04 +0000600 int (*power_up)(struct drm_device *dev);
601 int (*power_down)(struct drm_device *dev);
Patrik Jakobsson28a81942013-08-14 19:14:17 +0200602 void (*update_wm)(struct drm_device *dev, struct drm_crtc *crtc);
Patrik Jakobsson75346fe2013-08-15 00:54:44 +0200603 void (*disable_sr)(struct drm_device *dev);
Alan Cox5c49fd32011-11-03 18:22:04 +0000604
605 void (*lvds_bl_power)(struct drm_device *dev, bool on);
606#ifdef CONFIG_BACKLIGHT_CLASS_DEVICE
607 /* Backlight */
608 int (*backlight_init)(struct drm_device *dev);
609#endif
610 int i2c_bus; /* I2C bus identifier for Moorestown */
611};
612
613
614
Alan Cox5c49fd32011-11-03 18:22:04 +0000615extern int drm_crtc_probe_output_modes(struct drm_device *dev, int, int);
616extern int drm_pick_crtcs(struct drm_device *dev);
617
618static inline struct drm_psb_private *psb_priv(struct drm_device *dev)
619{
620 return (struct drm_psb_private *) dev->dev_private;
621}
622
Arthur Borsboom9083eb32014-03-15 22:12:18 +0100623/* psb_irq.c */
Daniel Vettere9f0d762013-12-11 11:34:42 +0100624extern irqreturn_t psb_irq_handler(int irq, void *arg);
Alan Cox5c49fd32011-11-03 18:22:04 +0000625extern int psb_irq_enable_dpst(struct drm_device *dev);
626extern int psb_irq_disable_dpst(struct drm_device *dev);
627extern void psb_irq_preinstall(struct drm_device *dev);
628extern int psb_irq_postinstall(struct drm_device *dev);
629extern void psb_irq_uninstall(struct drm_device *dev);
630extern void psb_irq_turn_on_dpst(struct drm_device *dev);
631extern void psb_irq_turn_off_dpst(struct drm_device *dev);
632
633extern void psb_irq_uninstall_islands(struct drm_device *dev, int hw_islands);
634extern int psb_vblank_wait2(struct drm_device *dev, unsigned int *sequence);
635extern int psb_vblank_wait(struct drm_device *dev, unsigned int *sequence);
Thomas Zimmermann42eabbe2020-01-23 14:59:27 +0100636extern int psb_enable_vblank(struct drm_crtc *crtc);
637extern void psb_disable_vblank(struct drm_crtc *crtc);
Alan Cox5c49fd32011-11-03 18:22:04 +0000638void
639psb_enable_pipestat(struct drm_psb_private *dev_priv, int pipe, u32 mask);
640
641void
642psb_disable_pipestat(struct drm_psb_private *dev_priv, int pipe, u32 mask);
643
Thomas Zimmermann42eabbe2020-01-23 14:59:27 +0100644extern u32 psb_get_vblank_counter(struct drm_crtc *crtc);
Alan Cox5c49fd32011-11-03 18:22:04 +0000645
Arthur Borsboom9083eb32014-03-15 22:12:18 +0100646/* framebuffer.c */
Alan Cox5c49fd32011-11-03 18:22:04 +0000647extern int psbfb_probed(struct drm_device *dev);
648extern int psbfb_remove(struct drm_device *dev,
649 struct drm_framebuffer *fb);
Arthur Borsboom9083eb32014-03-15 22:12:18 +0100650/* accel_2d.c */
Alan Cox5c49fd32011-11-03 18:22:04 +0000651extern void psb_spank(struct drm_psb_private *dev_priv);
652
Arthur Borsboom9083eb32014-03-15 22:12:18 +0100653/* psb_reset.c */
Alan Cox5c49fd32011-11-03 18:22:04 +0000654extern void psb_lid_timer_init(struct drm_psb_private *dev_priv);
655extern void psb_lid_timer_takedown(struct drm_psb_private *dev_priv);
656extern void psb_print_pagefault(struct drm_psb_private *dev_priv);
657
658/* modesetting */
659extern void psb_modeset_init(struct drm_device *dev);
660extern void psb_modeset_cleanup(struct drm_device *dev);
661extern int psb_fbdev_init(struct drm_device *dev);
662
663/* backlight.c */
664int gma_backlight_init(struct drm_device *dev);
665void gma_backlight_exit(struct drm_device *dev);
Zhao Yakuid112a812012-08-08 13:55:55 +0000666void gma_backlight_disable(struct drm_device *dev);
667void gma_backlight_enable(struct drm_device *dev);
668void gma_backlight_set(struct drm_device *dev, int v);
Alan Cox5c49fd32011-11-03 18:22:04 +0000669
670/* oaktrail_crtc.c */
671extern const struct drm_crtc_helper_funcs oaktrail_helper_funcs;
672
673/* oaktrail_lvds.c */
674extern void oaktrail_lvds_init(struct drm_device *dev,
675 struct psb_intel_mode_device *mode_dev);
676
677/* psb_intel_display.c */
678extern const struct drm_crtc_helper_funcs psb_intel_helper_funcs;
679extern const struct drm_crtc_funcs psb_intel_crtc_funcs;
680
681/* psb_intel_lvds.c */
682extern const struct drm_connector_helper_funcs
683 psb_intel_lvds_connector_helper_funcs;
684extern const struct drm_connector_funcs psb_intel_lvds_connector_funcs;
685
686/* gem.c */
Alan Cox5c49fd32011-11-03 18:22:04 +0000687extern int psb_gem_dumb_create(struct drm_file *file, struct drm_device *dev,
688 struct drm_mode_create_dumb *args);
Alan Cox5c49fd32011-11-03 18:22:04 +0000689
690/* psb_device.c */
691extern const struct psb_ops psb_chip_ops;
692
693/* oaktrail_device.c */
694extern const struct psb_ops oaktrail_chip_ops;
695
Alan Cox5c49fd32011-11-03 18:22:04 +0000696/* cdv_device.c */
697extern const struct psb_ops cdv_chip_ops;
698
Arthur Borsboom9083eb32014-03-15 22:12:18 +0100699/* Debug print bits setting */
Alan Cox5c49fd32011-11-03 18:22:04 +0000700#define PSB_D_GENERAL (1 << 0)
701#define PSB_D_INIT (1 << 1)
702#define PSB_D_IRQ (1 << 2)
703#define PSB_D_ENTRY (1 << 3)
704/* debug the get H/V BP/FP count */
705#define PSB_D_HV (1 << 4)
706#define PSB_D_DBI_BF (1 << 5)
707#define PSB_D_PM (1 << 6)
708#define PSB_D_RENDER (1 << 7)
709#define PSB_D_REG (1 << 8)
710#define PSB_D_MSVDX (1 << 9)
711#define PSB_D_TOPAZ (1 << 10)
712
Alan Cox5c49fd32011-11-03 18:22:04 +0000713extern int drm_idle_check_interval;
714
Arthur Borsboom9083eb32014-03-15 22:12:18 +0100715/* Utilities */
Sinan Kayaba99d832017-12-19 00:37:44 -0500716static inline u32 MRST_MSG_READ32(int domain, uint port, uint offset)
Alan Cox5c49fd32011-11-03 18:22:04 +0000717{
718 int mcr = (0xD0<<24) | (port << 16) | (offset << 8);
719 uint32_t ret_val = 0;
Sinan Kayaba99d832017-12-19 00:37:44 -0500720 struct pci_dev *pci_root = pci_get_domain_bus_and_slot(domain, 0, 0);
Alan Cox5c49fd32011-11-03 18:22:04 +0000721 pci_write_config_dword(pci_root, 0xD0, mcr);
722 pci_read_config_dword(pci_root, 0xD4, &ret_val);
723 pci_dev_put(pci_root);
724 return ret_val;
725}
Sinan Kayaba99d832017-12-19 00:37:44 -0500726static inline void MRST_MSG_WRITE32(int domain, uint port, uint offset,
727 u32 value)
Alan Cox5c49fd32011-11-03 18:22:04 +0000728{
729 int mcr = (0xE0<<24) | (port << 16) | (offset << 8) | 0xF0;
Sinan Kayaba99d832017-12-19 00:37:44 -0500730 struct pci_dev *pci_root = pci_get_domain_bus_and_slot(domain, 0, 0);
Alan Cox5c49fd32011-11-03 18:22:04 +0000731 pci_write_config_dword(pci_root, 0xD4, value);
732 pci_write_config_dword(pci_root, 0xD0, mcr);
733 pci_dev_put(pci_root);
734}
Alan Cox5c49fd32011-11-03 18:22:04 +0000735
736static inline uint32_t REGISTER_READ(struct drm_device *dev, uint32_t reg)
737{
738 struct drm_psb_private *dev_priv = dev->dev_private;
739 return ioread32(dev_priv->vdc_reg + reg);
740}
741
Patrik Jakobsson26579292013-09-16 18:02:40 +0200742static inline uint32_t REGISTER_READ_AUX(struct drm_device *dev, uint32_t reg)
743{
744 struct drm_psb_private *dev_priv = dev->dev_private;
745 return ioread32(dev_priv->aux_reg + reg);
746}
747
Alan Cox5c49fd32011-11-03 18:22:04 +0000748#define REG_READ(reg) REGISTER_READ(dev, (reg))
Patrik Jakobsson26579292013-09-16 18:02:40 +0200749#define REG_READ_AUX(reg) REGISTER_READ_AUX(dev, (reg))
Alan Cox5c49fd32011-11-03 18:22:04 +0000750
Patrik Jakobssonb97b8282013-11-07 00:14:18 +0100751/* Useful for post reads */
752static inline uint32_t REGISTER_READ_WITH_AUX(struct drm_device *dev,
753 uint32_t reg, int aux)
754{
755 uint32_t val;
756
757 if (aux)
758 val = REG_READ_AUX(reg);
759 else
760 val = REG_READ(reg);
761
762 return val;
763}
764
765#define REG_READ_WITH_AUX(reg, aux) REGISTER_READ_WITH_AUX(dev, (reg), (aux))
766
Alan Cox5c49fd32011-11-03 18:22:04 +0000767static inline void REGISTER_WRITE(struct drm_device *dev, uint32_t reg,
Patrik Jakobsson26579292013-09-16 18:02:40 +0200768 uint32_t val)
Alan Cox5c49fd32011-11-03 18:22:04 +0000769{
770 struct drm_psb_private *dev_priv = dev->dev_private;
771 iowrite32((val), dev_priv->vdc_reg + (reg));
772}
773
Patrik Jakobsson26579292013-09-16 18:02:40 +0200774static inline void REGISTER_WRITE_AUX(struct drm_device *dev, uint32_t reg,
775 uint32_t val)
776{
777 struct drm_psb_private *dev_priv = dev->dev_private;
778 iowrite32((val), dev_priv->aux_reg + (reg));
779}
780
Alan Cox5c49fd32011-11-03 18:22:04 +0000781#define REG_WRITE(reg, val) REGISTER_WRITE(dev, (reg), (val))
Patrik Jakobsson26579292013-09-16 18:02:40 +0200782#define REG_WRITE_AUX(reg, val) REGISTER_WRITE_AUX(dev, (reg), (val))
Alan Cox5c49fd32011-11-03 18:22:04 +0000783
Patrik Jakobssonb97b8282013-11-07 00:14:18 +0100784static inline void REGISTER_WRITE_WITH_AUX(struct drm_device *dev, uint32_t reg,
785 uint32_t val, int aux)
786{
787 if (aux)
788 REG_WRITE_AUX(reg, val);
789 else
790 REG_WRITE(reg, val);
791}
792
793#define REG_WRITE_WITH_AUX(reg, val, aux) REGISTER_WRITE_WITH_AUX(dev, (reg), (val), (aux))
794
Alan Cox5c49fd32011-11-03 18:22:04 +0000795static inline void REGISTER_WRITE16(struct drm_device *dev,
796 uint32_t reg, uint32_t val)
797{
798 struct drm_psb_private *dev_priv = dev->dev_private;
799 iowrite16((val), dev_priv->vdc_reg + (reg));
800}
801
802#define REG_WRITE16(reg, val) REGISTER_WRITE16(dev, (reg), (val))
803
804static inline void REGISTER_WRITE8(struct drm_device *dev,
805 uint32_t reg, uint32_t val)
806{
807 struct drm_psb_private *dev_priv = dev->dev_private;
808 iowrite8((val), dev_priv->vdc_reg + (reg));
809}
810
811#define REG_WRITE8(reg, val) REGISTER_WRITE8(dev, (reg), (val))
812
813#define PSB_WVDC32(_val, _offs) iowrite32(_val, dev_priv->vdc_reg + (_offs))
814#define PSB_RVDC32(_offs) ioread32(dev_priv->vdc_reg + (_offs))
815
816/* #define TRAP_SGX_PM_FAULT 1 */
817#ifdef TRAP_SGX_PM_FAULT
818#define PSB_RSGX32(_offs) \
819({ \
820 if (inl(dev_priv->apm_base + PSB_APM_STS) & 0x3) { \
Joe Perches8dfe1622017-02-28 04:55:54 -0800821 pr_err("access sgx when it's off!! (READ) %s, %d\n", \
822 __FILE__, __LINE__); \
Alan Cox5c49fd32011-11-03 18:22:04 +0000823 melay(1000); \
824 } \
825 ioread32(dev_priv->sgx_reg + (_offs)); \
826})
827#else
828#define PSB_RSGX32(_offs) ioread32(dev_priv->sgx_reg + (_offs))
829#endif
830#define PSB_WSGX32(_val, _offs) iowrite32(_val, dev_priv->sgx_reg + (_offs))
831
832#define MSVDX_REG_DUMP 0
833
834#define PSB_WMSVDX32(_val, _offs) iowrite32(_val, dev_priv->msvdx_reg + (_offs))
835#define PSB_RMSVDX32(_offs) ioread32(dev_priv->msvdx_reg + (_offs))
836
837#endif