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Joel Stanleyeb323ad2017-12-11 14:55:28 +10301// SPDX-License-Identifier: GPL-2.0+
Joel Stanleybb8155a2017-11-28 22:39:25 +10302#include <dt-bindings/clock/aspeed-clock.h>
Joel Stanley02440622016-04-17 15:50:56 +09303
4/ {
5 model = "Aspeed BMC";
6 compatible = "aspeed,ast2500";
7 #address-cells = <1>;
8 #size-cells = <1>;
9 interrupt-parent = <&vic>;
10
Joel Stanleyef856372017-10-04 17:19:11 +103011 aliases {
12 i2c0 = &i2c0;
13 i2c1 = &i2c1;
14 i2c2 = &i2c2;
15 i2c3 = &i2c3;
16 i2c4 = &i2c4;
17 i2c5 = &i2c5;
18 i2c6 = &i2c6;
19 i2c7 = &i2c7;
20 i2c8 = &i2c8;
21 i2c9 = &i2c9;
22 i2c10 = &i2c10;
23 i2c11 = &i2c11;
24 i2c12 = &i2c12;
25 i2c13 = &i2c13;
Joel Stanley0bae3902017-10-04 17:19:15 +103026 serial0 = &uart1;
27 serial1 = &uart2;
28 serial2 = &uart3;
29 serial3 = &uart4;
30 serial4 = &uart5;
Joel Stanleya19331c2017-10-04 17:19:17 +103031 serial5 = &vuart;
Joel Stanleyef856372017-10-04 17:19:11 +103032 };
33
Joel Stanley02440622016-04-17 15:50:56 +093034 cpus {
35 #address-cells = <1>;
36 #size-cells = <0>;
37
38 cpu@0 {
39 compatible = "arm,arm1176jzf-s";
40 device_type = "cpu";
41 reg = <0>;
42 };
43 };
44
Joel Stanley9bdc00a2018-03-14 17:43:12 +103045 memory@80000000 {
46 device_type = "memory";
47 reg = <0x80000000 0>;
48 };
49
Stefan M Schaeckeler9b7e6242019-01-17 08:38:16 -080050 edac: sdram@1e6e0000 {
51 compatible = "aspeed,ast2500-sdram-edac";
52 reg = <0x1e6e0000 0x174>;
53 interrupts = <0>;
54 status = "disabled";
55 };
56
Joel Stanley02440622016-04-17 15:50:56 +093057 ahb {
58 compatible = "simple-bus";
59 #address-cells = <1>;
60 #size-cells = <1>;
61 ranges;
62
Cédric Le Goater74dc3cd2017-03-01 15:26:42 +010063 fmc: flash-controller@1e620000 {
64 reg = < 0x1e620000 0xc4
65 0x20000000 0x10000000 >;
66 #address-cells = <1>;
67 #size-cells = <0>;
68 compatible = "aspeed,ast2500-fmc";
Joel Stanleye1e0ec42017-11-28 22:45:30 +103069 clocks = <&syscon ASPEED_CLK_AHB>;
Cédric Le Goater74dc3cd2017-03-01 15:26:42 +010070 status = "disabled";
71 interrupts = <19>;
72 flash@0 {
73 reg = < 0 >;
74 compatible = "jedec,spi-nor";
75 status = "disabled";
76 };
77 flash@1 {
78 reg = < 1 >;
79 compatible = "jedec,spi-nor";
80 status = "disabled";
81 };
82 flash@2 {
83 reg = < 2 >;
84 compatible = "jedec,spi-nor";
85 status = "disabled";
86 };
87 };
88
89 spi1: flash-controller@1e630000 {
90 reg = < 0x1e630000 0xc4
91 0x30000000 0x08000000 >;
92 #address-cells = <1>;
93 #size-cells = <0>;
94 compatible = "aspeed,ast2500-spi";
Joel Stanleye1e0ec42017-11-28 22:45:30 +103095 clocks = <&syscon ASPEED_CLK_AHB>;
Cédric Le Goater74dc3cd2017-03-01 15:26:42 +010096 status = "disabled";
97 flash@0 {
98 reg = < 0 >;
99 compatible = "jedec,spi-nor";
100 status = "disabled";
101 };
102 flash@1 {
103 reg = < 1 >;
104 compatible = "jedec,spi-nor";
105 status = "disabled";
106 };
107 };
108
109 spi2: flash-controller@1e631000 {
110 reg = < 0x1e631000 0xc4
111 0x38000000 0x08000000 >;
112 #address-cells = <1>;
113 #size-cells = <0>;
114 compatible = "aspeed,ast2500-spi";
Joel Stanleye1e0ec42017-11-28 22:45:30 +1030115 clocks = <&syscon ASPEED_CLK_AHB>;
Cédric Le Goater74dc3cd2017-03-01 15:26:42 +0100116 status = "disabled";
117 flash@0 {
118 reg = < 0 >;
119 compatible = "jedec,spi-nor";
120 status = "disabled";
121 };
122 flash@1 {
123 reg = < 1 >;
124 compatible = "jedec,spi-nor";
125 status = "disabled";
126 };
127 };
128
Joel Stanley02440622016-04-17 15:50:56 +0930129 vic: interrupt-controller@1e6c0080 {
130 compatible = "aspeed,ast2400-vic";
131 interrupt-controller;
132 #interrupt-cells = <1>;
133 valid-sources = <0xfefff7ff 0x0807ffff>;
134 reg = <0x1e6c0080 0x80>;
135 };
136
Benjamin Herrenschmidt2450cea2018-07-24 14:24:02 +1000137 cvic: copro-interrupt-controller@1e6c2000 {
138 compatible = "aspeed,ast2500-cvic", "aspeed-cvic";
139 valid-sources = <0xffffffff>;
140 copro-sw-interrupts = <1>;
141 reg = <0x1e6c2000 0x80>;
142 };
143
Joel Stanley34ea5c92017-01-04 16:30:34 +1100144 mac0: ethernet@1e660000 {
Benjamin Herrenschmidt78d28542017-04-12 13:27:02 +1000145 compatible = "aspeed,ast2500-mac", "faraday,ftgmac100";
Joel Stanley34ea5c92017-01-04 16:30:34 +1100146 reg = <0x1e660000 0x180>;
147 interrupts = <2>;
Joel Stanleydeb95c52017-11-28 22:41:10 +1030148 clocks = <&syscon ASPEED_CLK_GATE_MAC1CLK>;
Joel Stanley34ea5c92017-01-04 16:30:34 +1100149 status = "disabled";
150 };
151
152 mac1: ethernet@1e680000 {
Benjamin Herrenschmidt78d28542017-04-12 13:27:02 +1000153 compatible = "aspeed,ast2500-mac", "faraday,ftgmac100";
Joel Stanley34ea5c92017-01-04 16:30:34 +1100154 reg = <0x1e680000 0x180>;
155 interrupts = <3>;
Joel Stanleydeb95c52017-11-28 22:41:10 +1030156 clocks = <&syscon ASPEED_CLK_GATE_MAC2CLK>;
Joel Stanley34ea5c92017-01-04 16:30:34 +1100157 status = "disabled";
158 };
159
Benjamin Herrenschmidtac6e31d2018-04-13 14:40:38 +1000160 ehci0: usb@1e6a1000 {
161 compatible = "aspeed,ast2500-ehci", "generic-ehci";
162 reg = <0x1e6a1000 0x100>;
163 interrupts = <5>;
164 clocks = <&syscon ASPEED_CLK_GATE_USBPORT1CLK>;
Benjamin Herrenschmidt112c5a62018-06-29 13:51:01 +1000165 pinctrl-names = "default";
166 pinctrl-0 = <&pinctrl_usb2ah_default>;
Benjamin Herrenschmidtac6e31d2018-04-13 14:40:38 +1000167 status = "disabled";
168 };
169
170 ehci1: usb@1e6a3000 {
171 compatible = "aspeed,ast2500-ehci", "generic-ehci";
172 reg = <0x1e6a3000 0x100>;
173 interrupts = <13>;
174 clocks = <&syscon ASPEED_CLK_GATE_USBPORT2CLK>;
Benjamin Herrenschmidt112c5a62018-06-29 13:51:01 +1000175 pinctrl-names = "default";
176 pinctrl-0 = <&pinctrl_usb2bh_default>;
Benjamin Herrenschmidtac6e31d2018-04-13 14:40:38 +1000177 status = "disabled";
178 };
179
180 uhci: usb@1e6b0000 {
181 compatible = "aspeed,ast2500-uhci", "generic-uhci";
182 reg = <0x1e6b0000 0x100>;
183 interrupts = <14>;
184 #ports = <2>;
185 clocks = <&syscon ASPEED_CLK_GATE_USBUHCICLK>;
186 status = "disabled";
Benjamin Herrenschmidt112c5a62018-06-29 13:51:01 +1000187 /*
188 * No default pinmux, it will follow EHCI, use an explicit pinmux
189 * override if you don't enable EHCI
190 */
Benjamin Herrenschmidtac6e31d2018-04-13 14:40:38 +1000191 };
192
Benjamin Herrenschmidt35578a82018-06-29 13:51:03 +1000193 vhub: usb-vhub@1e6a0000 {
194 compatible = "aspeed,ast2500-usb-vhub";
195 reg = <0x1e6a0000 0x300>;
196 interrupts = <5>;
197 clocks = <&syscon ASPEED_CLK_GATE_USBPORT1CLK>;
198 pinctrl-names = "default";
199 pinctrl-0 = <&pinctrl_usb2ad_default>;
200 status = "disabled";
201 };
202
Joel Stanley02440622016-04-17 15:50:56 +0930203 apb {
204 compatible = "simple-bus";
205 #address-cells = <1>;
206 #size-cells = <1>;
207 ranges;
208
Andrew Jefferyb590c8d2016-12-06 14:53:47 +1100209 syscon: syscon@1e6e2000 {
Joel Stanleybb8155a2017-11-28 22:39:25 +1030210 compatible = "aspeed,ast2500-scu", "syscon", "simple-mfd";
Andrew Jefferyb590c8d2016-12-06 14:53:47 +1100211 reg = <0x1e6e2000 0x1a8>;
Joel Stanley8b9102d2017-03-31 13:05:10 +1030212 #address-cells = <1>;
213 #size-cells = <0>;
Joel Stanleybb8155a2017-11-28 22:39:25 +1030214 #clock-cells = <1>;
215 #reset-cells = <1>;
Andrew Jefferyb590c8d2016-12-06 14:53:47 +1100216
217 pinctrl: pinctrl {
218 compatible = "aspeed,g5-pinctrl";
219 aspeed,external-nodes = <&gfx &lhc>;
220
Andrew Jefferyb590c8d2016-12-06 14:53:47 +1100221 };
Joel Stanley02440622016-04-17 15:50:56 +0930222 };
223
Joel Stanley927c2fc2018-05-30 15:47:40 +0930224 rng: hwrng@1e6e2078 {
Joel Stanley5daa8212018-03-22 16:07:35 +1030225 compatible = "timeriomem_rng";
Joel Stanley927c2fc2018-05-30 15:47:40 +0930226 reg = <0x1e6e2078 0x4>;
Joel Stanley5daa8212018-03-22 16:07:35 +1030227 period = <1>;
228 quality = <100>;
229 };
230
Andrew Jefferydaf04252016-12-06 14:53:45 +1100231 gfx: display@1e6e6000 {
232 compatible = "aspeed,ast2500-gfx", "syscon";
233 reg = <0x1e6e6000 0x1000>;
234 reg-io-width = <4>;
Joel Stanleye1920e72018-04-19 13:50:02 +0930235 clocks = <&syscon ASPEED_CLK_GATE_D1CLK>;
236 resets = <&syscon ASPEED_RESET_CRT1>;
237 status = "disabled";
238 interrupts = <0x19>;
Andrew Jefferydaf04252016-12-06 14:53:45 +1100239 };
240
Joel Stanley29b24642017-10-04 17:19:10 +1030241 adc: adc@1e6e9000 {
242 compatible = "aspeed,ast2500-adc";
243 reg = <0x1e6e9000 0xb0>;
Joel Stanleybb8155a2017-11-28 22:39:25 +1030244 clocks = <&syscon ASPEED_CLK_APB>;
245 resets = <&syscon ASPEED_RESET_ADC>;
Joel Stanley29b24642017-10-04 17:19:10 +1030246 #io-channel-cells = <1>;
247 status = "disabled";
248 };
249
Eddie James796b4402019-04-02 18:25:04 +0000250 video: video@1e700000 {
251 compatible = "aspeed,ast2500-video-engine";
252 reg = <0x1e700000 0x1000>;
253 clocks = <&syscon ASPEED_CLK_GATE_VCLK>,
254 <&syscon ASPEED_CLK_GATE_ECLK>;
255 clock-names = "vclk", "eclk";
256 interrupts = <7>;
257 status = "disabled";
258 };
259
Benjamin Herrenschmidt2450cea2018-07-24 14:24:02 +1000260 sram: sram@1e720000 {
Joel Stanley02440622016-04-17 15:50:56 +0930261 compatible = "mmio-sram";
262 reg = <0x1e720000 0x9000>; // 36K
263 };
264
Andrew Jeffery2039f902016-12-06 14:53:48 +1100265 gpio: gpio@1e780000 {
266 #gpio-cells = <2>;
267 gpio-controller;
268 compatible = "aspeed,ast2500-gpio";
269 reg = <0x1e780000 0x1000>;
270 interrupts = <20>;
271 gpio-ranges = <&pinctrl 0 0 220>;
Joel Stanley2528be72017-09-18 17:43:09 +0930272 clocks = <&syscon ASPEED_CLK_APB>;
Andrew Jeffery2039f902016-12-06 14:53:48 +1100273 interrupt-controller;
Mark Walton8b880292018-12-14 12:07:07 +0000274 #interrupt-cells = <2>;
Andrew Jeffery2039f902016-12-06 14:53:48 +1100275 };
276
Joel Stanley6d00c6f2018-10-03 14:35:07 +0200277 rtc: rtc@1e781000 {
278 compatible = "aspeed,ast2500-rtc";
279 reg = <0x1e781000 0x18>;
280 status = "disabled";
281 };
282
Joel Stanley02440622016-04-17 15:50:56 +0930283 timer: timer@1e782000 {
Linus Walleijf46b5632017-05-24 11:07:48 +0200284 /* This timer is a Faraday FTTMR010 derivative */
Joel Stanley02440622016-04-17 15:50:56 +0930285 compatible = "aspeed,ast2400-timer";
286 reg = <0x1e782000 0x90>;
Linus Walleijf46b5632017-05-24 11:07:48 +0200287 interrupts = <16 17 18 35 36 37 38 39>;
Joel Stanleybb8155a2017-11-28 22:39:25 +1030288 clocks = <&syscon ASPEED_CLK_APB>;
Linus Walleijf46b5632017-05-24 11:07:48 +0200289 clock-names = "PCLK";
Joel Stanley02440622016-04-17 15:50:56 +0930290 };
291
Joel Stanley02440622016-04-17 15:50:56 +0930292 uart1: serial@1e783000 {
293 compatible = "ns16550a";
Joel Stanleya19331c2017-10-04 17:19:17 +1030294 reg = <0x1e783000 0x20>;
Joel Stanley02440622016-04-17 15:50:56 +0930295 reg-shift = <2>;
296 interrupts = <9>;
Joel Stanleybb8155a2017-11-28 22:39:25 +1030297 clocks = <&syscon ASPEED_CLK_GATE_UART1CLK>;
Joel Stanleyfd2de0a2018-02-19 18:05:40 +1030298 resets = <&lpc_reset 4>;
Joel Stanley02440622016-04-17 15:50:56 +0930299 no-loopback-test;
300 status = "disabled";
301 };
302
Joel Stanleydb4d6d92017-10-04 17:19:16 +1030303 uart5: serial@1e784000 {
304 compatible = "ns16550a";
Joel Stanleya19331c2017-10-04 17:19:17 +1030305 reg = <0x1e784000 0x20>;
Joel Stanleydb4d6d92017-10-04 17:19:16 +1030306 reg-shift = <2>;
307 interrupts = <10>;
Joel Stanleybb8155a2017-11-28 22:39:25 +1030308 clocks = <&syscon ASPEED_CLK_GATE_UART5CLK>;
Joel Stanleydb4d6d92017-10-04 17:19:16 +1030309 no-loopback-test;
310 status = "disabled";
311 };
Joel Stanley02440622016-04-17 15:50:56 +0930312
Joel Stanley424bd7e2017-10-04 19:46:34 +1030313 wdt1: watchdog@1e785000 {
Joel Stanley02440622016-04-17 15:50:56 +0930314 compatible = "aspeed,ast2500-wdt";
315 reg = <0x1e785000 0x20>;
Joel Stanleya563e192017-11-28 22:43:46 +1030316 clocks = <&syscon ASPEED_CLK_APB>;
Joel Stanley02440622016-04-17 15:50:56 +0930317 };
318
Joel Stanley424bd7e2017-10-04 19:46:34 +1030319 wdt2: watchdog@1e785020 {
Joel Stanley02440622016-04-17 15:50:56 +0930320 compatible = "aspeed,ast2500-wdt";
321 reg = <0x1e785020 0x20>;
Joel Stanleya563e192017-11-28 22:43:46 +1030322 clocks = <&syscon ASPEED_CLK_APB>;
Joel Stanley02440622016-04-17 15:50:56 +0930323 };
324
Joel Stanley424bd7e2017-10-04 19:46:34 +1030325 wdt3: watchdog@1e785040 {
Joel Stanley02440622016-04-17 15:50:56 +0930326 compatible = "aspeed,ast2500-wdt";
327 reg = <0x1e785040 0x20>;
Joel Stanleya563e192017-11-28 22:43:46 +1030328 clocks = <&syscon ASPEED_CLK_APB>;
Joel Stanley02440622016-04-17 15:50:56 +0930329 status = "disabled";
330 };
331
Joel Stanley07340892017-11-29 00:17:52 +1030332 pwm_tacho: pwm-tacho-controller@1e786000 {
333 compatible = "aspeed,ast2500-pwm-tacho";
334 #address-cells = <1>;
335 #size-cells = <0>;
336 reg = <0x1e786000 0x1000>;
Lei YUa2df75a2018-05-09 17:35:59 +0800337 clocks = <&syscon ASPEED_CLK_24M>;
Joel Stanley07340892017-11-29 00:17:52 +1030338 resets = <&syscon ASPEED_RESET_PWM>;
339 status = "disabled";
340 };
341
Andrew Jefferyb6436f72017-11-07 18:00:24 +1030342 vuart: serial@1e787000 {
343 compatible = "aspeed,ast2500-vuart";
344 reg = <0x1e787000 0x40>;
345 reg-shift = <2>;
Joel Stanleybb8155a2017-11-28 22:39:25 +1030346 interrupts = <8>;
347 clocks = <&syscon ASPEED_CLK_APB>;
Andrew Jefferyb6436f72017-11-07 18:00:24 +1030348 no-loopback-test;
349 status = "disabled";
350 };
351
Andrew Jefferycec822f2016-12-06 14:53:46 +1100352 lpc: lpc@1e789000 {
353 compatible = "aspeed,ast2500-lpc", "simple-mfd";
354 reg = <0x1e789000 0x1000>;
355
356 #address-cells = <1>;
357 #size-cells = <1>;
Joel Stanley542d2f42018-02-12 18:13:22 +1030358 ranges = <0x0 0x1e789000 0x1000>;
Andrew Jefferycec822f2016-12-06 14:53:46 +1100359
360 lpc_bmc: lpc-bmc@0 {
Vijay Khemka9e9a6ad2018-12-17 12:04:03 -0800361 compatible = "aspeed,ast2500-lpc-bmc", "simple-mfd", "syscon";
Andrew Jefferycec822f2016-12-06 14:53:46 +1100362 reg = <0x0 0x80>;
Vijay Khemka9e9a6ad2018-12-17 12:04:03 -0800363 reg-io-width = <4>;
364
365 #address-cells = <1>;
366 #size-cells = <1>;
367 ranges = <0x0 0x0 0x80>;
368
369 kcs1: kcs1@0 {
370 compatible = "aspeed,ast2500-kcs-bmc";
371 interrupts = <8>;
372 kcs_chan = <1>;
373 status = "disabled";
374 };
375 kcs2: kcs2@0 {
376 compatible = "aspeed,ast2500-kcs-bmc";
377 interrupts = <8>;
378 kcs_chan = <2>;
379 status = "disabled";
380 };
381 kcs3: kcs3@0 {
382 compatible = "aspeed,ast2500-kcs-bmc";
383 interrupts = <8>;
384 kcs_chan = <3>;
385 status = "disabled";
386 };
Andrew Jefferycec822f2016-12-06 14:53:46 +1100387 };
388
389 lpc_host: lpc-host@80 {
390 compatible = "aspeed,ast2500-lpc-host", "simple-mfd", "syscon";
391 reg = <0x80 0x1e0>;
Joel Stanley542d2f42018-02-12 18:13:22 +1030392 reg-io-width = <4>;
Andrew Jefferycec822f2016-12-06 14:53:46 +1100393
394 #address-cells = <1>;
395 #size-cells = <1>;
Joel Stanley542d2f42018-02-12 18:13:22 +1030396 ranges = <0x0 0x80 0x1e0>;
Andrew Jefferycec822f2016-12-06 14:53:46 +1100397
Vijay Khemka9e9a6ad2018-12-17 12:04:03 -0800398 kcs4: kcs4@0 {
399 compatible = "aspeed,ast2500-kcs-bmc";
400 interrupts = <8>;
401 kcs_chan = <4>;
402 status = "disabled";
403 };
404
Andrew Jefferyb6436f72017-11-07 18:00:24 +1030405 lpc_ctrl: lpc-ctrl@0 {
406 compatible = "aspeed,ast2500-lpc-ctrl";
407 reg = <0x0 0x80>;
Joel Stanley7674bf92018-02-12 18:13:23 +1030408 clocks = <&syscon ASPEED_CLK_GATE_LCLK>;
Andrew Jefferyb6436f72017-11-07 18:00:24 +1030409 status = "disabled";
410 };
411
Joel Stanleyd558ce02017-12-11 13:19:20 +1030412 lpc_snoop: lpc-snoop@0 {
413 compatible = "aspeed,ast2500-lpc-snoop";
414 reg = <0x0 0x80>;
415 interrupts = <8>;
416 status = "disabled";
417 };
Andrew Jefferyb6436f72017-11-07 18:00:24 +1030418
Andrew Jefferycec822f2016-12-06 14:53:46 +1100419 lhc: lhc@20 {
420 compatible = "aspeed,ast2500-lhc";
421 reg = <0x20 0x24 0x48 0x8>;
422 };
Joel Stanley75b310b2018-02-12 18:13:20 +1030423
Joel Stanleyfd2de0a2018-02-19 18:05:40 +1030424 lpc_reset: reset-controller@18 {
425 compatible = "aspeed,ast2500-lpc-reset";
426 reg = <0x18 0x4>;
427 #reset-cells = <1>;
428 };
429
Joel Stanley75b310b2018-02-12 18:13:20 +1030430 ibt: ibt@c0 {
431 compatible = "aspeed,ast2500-ibt-bmc";
432 reg = <0xc0 0x18>;
433 interrupts = <8>;
434 status = "disabled";
435 };
Andrew Jefferycec822f2016-12-06 14:53:46 +1100436 };
437 };
438
Joel Stanley02440622016-04-17 15:50:56 +0930439 uart2: serial@1e78d000 {
440 compatible = "ns16550a";
Joel Stanleya19331c2017-10-04 17:19:17 +1030441 reg = <0x1e78d000 0x20>;
Joel Stanley02440622016-04-17 15:50:56 +0930442 reg-shift = <2>;
443 interrupts = <32>;
Joel Stanleybb8155a2017-11-28 22:39:25 +1030444 clocks = <&syscon ASPEED_CLK_GATE_UART2CLK>;
Joel Stanleyfd2de0a2018-02-19 18:05:40 +1030445 resets = <&lpc_reset 5>;
Joel Stanley02440622016-04-17 15:50:56 +0930446 no-loopback-test;
447 status = "disabled";
448 };
449
450 uart3: serial@1e78e000 {
451 compatible = "ns16550a";
Joel Stanleya19331c2017-10-04 17:19:17 +1030452 reg = <0x1e78e000 0x20>;
Joel Stanley02440622016-04-17 15:50:56 +0930453 reg-shift = <2>;
454 interrupts = <33>;
Joel Stanleybb8155a2017-11-28 22:39:25 +1030455 clocks = <&syscon ASPEED_CLK_GATE_UART3CLK>;
Joel Stanleyfd2de0a2018-02-19 18:05:40 +1030456 resets = <&lpc_reset 6>;
Joel Stanley02440622016-04-17 15:50:56 +0930457 no-loopback-test;
458 status = "disabled";
459 };
460
461 uart4: serial@1e78f000 {
462 compatible = "ns16550a";
Joel Stanleya19331c2017-10-04 17:19:17 +1030463 reg = <0x1e78f000 0x20>;
Joel Stanley02440622016-04-17 15:50:56 +0930464 reg-shift = <2>;
465 interrupts = <34>;
Joel Stanleybb8155a2017-11-28 22:39:25 +1030466 clocks = <&syscon ASPEED_CLK_GATE_UART4CLK>;
Joel Stanleyfd2de0a2018-02-19 18:05:40 +1030467 resets = <&lpc_reset 7>;
Joel Stanley02440622016-04-17 15:50:56 +0930468 no-loopback-test;
469 status = "disabled";
470 };
471
Rob Herring1426d402018-09-13 13:12:27 -0500472 i2c: bus@1e78a000 {
Joel Stanleyef856372017-10-04 17:19:11 +1030473 compatible = "simple-bus";
474 #address-cells = <1>;
475 #size-cells = <1>;
476 ranges = <0 0x1e78a000 0x1000>;
Rick Altherr78a25692017-03-29 18:08:46 -0700477 };
Joel Stanley02440622016-04-17 15:50:56 +0930478 };
479 };
480};
Andrew Jefferycd7df3f2017-10-04 17:19:09 +1030481
Joel Stanleyef856372017-10-04 17:19:11 +1030482&i2c {
483 i2c_ic: interrupt-controller@0 {
484 #interrupt-cells = <1>;
485 compatible = "aspeed,ast2500-i2c-ic";
486 reg = <0x0 0x40>;
487 interrupts = <12>;
488 interrupt-controller;
489 };
490
491 i2c0: i2c-bus@40 {
492 #address-cells = <1>;
493 #size-cells = <0>;
494 #interrupt-cells = <1>;
495
496 reg = <0x40 0x40>;
497 compatible = "aspeed,ast2500-i2c-bus";
Joel Stanleybb8155a2017-11-28 22:39:25 +1030498 clocks = <&syscon ASPEED_CLK_APB>;
499 resets = <&syscon ASPEED_RESET_I2C>;
Joel Stanleyef856372017-10-04 17:19:11 +1030500 bus-frequency = <100000>;
501 interrupts = <0>;
502 interrupt-parent = <&i2c_ic>;
503 status = "disabled";
504 /* Does not need pinctrl properties */
505 };
506
507 i2c1: i2c-bus@80 {
508 #address-cells = <1>;
509 #size-cells = <0>;
510 #interrupt-cells = <1>;
511
512 reg = <0x80 0x40>;
513 compatible = "aspeed,ast2500-i2c-bus";
Joel Stanleybb8155a2017-11-28 22:39:25 +1030514 clocks = <&syscon ASPEED_CLK_APB>;
515 resets = <&syscon ASPEED_RESET_I2C>;
Joel Stanleyef856372017-10-04 17:19:11 +1030516 bus-frequency = <100000>;
517 interrupts = <1>;
518 interrupt-parent = <&i2c_ic>;
519 status = "disabled";
520 /* Does not need pinctrl properties */
521 };
522
523 i2c2: i2c-bus@c0 {
524 #address-cells = <1>;
525 #size-cells = <0>;
526 #interrupt-cells = <1>;
527
528 reg = <0xc0 0x40>;
529 compatible = "aspeed,ast2500-i2c-bus";
Joel Stanleybb8155a2017-11-28 22:39:25 +1030530 clocks = <&syscon ASPEED_CLK_APB>;
531 resets = <&syscon ASPEED_RESET_I2C>;
Joel Stanleyef856372017-10-04 17:19:11 +1030532 bus-frequency = <100000>;
533 interrupts = <2>;
534 interrupt-parent = <&i2c_ic>;
535 pinctrl-names = "default";
536 pinctrl-0 = <&pinctrl_i2c3_default>;
537 status = "disabled";
538 };
539
540 i2c3: i2c-bus@100 {
541 #address-cells = <1>;
542 #size-cells = <0>;
543 #interrupt-cells = <1>;
544
545 reg = <0x100 0x40>;
546 compatible = "aspeed,ast2500-i2c-bus";
Joel Stanleybb8155a2017-11-28 22:39:25 +1030547 clocks = <&syscon ASPEED_CLK_APB>;
548 resets = <&syscon ASPEED_RESET_I2C>;
Joel Stanleyef856372017-10-04 17:19:11 +1030549 bus-frequency = <100000>;
550 interrupts = <3>;
551 interrupt-parent = <&i2c_ic>;
552 pinctrl-names = "default";
553 pinctrl-0 = <&pinctrl_i2c4_default>;
554 status = "disabled";
555 };
556
557 i2c4: i2c-bus@140 {
558 #address-cells = <1>;
559 #size-cells = <0>;
560 #interrupt-cells = <1>;
561
562 reg = <0x140 0x40>;
563 compatible = "aspeed,ast2500-i2c-bus";
Joel Stanleybb8155a2017-11-28 22:39:25 +1030564 clocks = <&syscon ASPEED_CLK_APB>;
565 resets = <&syscon ASPEED_RESET_I2C>;
Joel Stanleyef856372017-10-04 17:19:11 +1030566 bus-frequency = <100000>;
567 interrupts = <4>;
568 interrupt-parent = <&i2c_ic>;
569 pinctrl-names = "default";
570 pinctrl-0 = <&pinctrl_i2c5_default>;
571 status = "disabled";
572 };
573
574 i2c5: i2c-bus@180 {
575 #address-cells = <1>;
576 #size-cells = <0>;
577 #interrupt-cells = <1>;
578
579 reg = <0x180 0x40>;
580 compatible = "aspeed,ast2500-i2c-bus";
Joel Stanleybb8155a2017-11-28 22:39:25 +1030581 clocks = <&syscon ASPEED_CLK_APB>;
582 resets = <&syscon ASPEED_RESET_I2C>;
Joel Stanleyef856372017-10-04 17:19:11 +1030583 bus-frequency = <100000>;
584 interrupts = <5>;
585 interrupt-parent = <&i2c_ic>;
586 pinctrl-names = "default";
587 pinctrl-0 = <&pinctrl_i2c6_default>;
588 status = "disabled";
589 };
590
591 i2c6: i2c-bus@1c0 {
592 #address-cells = <1>;
593 #size-cells = <0>;
594 #interrupt-cells = <1>;
595
596 reg = <0x1c0 0x40>;
597 compatible = "aspeed,ast2500-i2c-bus";
Joel Stanleybb8155a2017-11-28 22:39:25 +1030598 clocks = <&syscon ASPEED_CLK_APB>;
599 resets = <&syscon ASPEED_RESET_I2C>;
Joel Stanleyef856372017-10-04 17:19:11 +1030600 bus-frequency = <100000>;
601 interrupts = <6>;
602 interrupt-parent = <&i2c_ic>;
603 pinctrl-names = "default";
604 pinctrl-0 = <&pinctrl_i2c7_default>;
605 status = "disabled";
606 };
607
608 i2c7: i2c-bus@300 {
609 #address-cells = <1>;
610 #size-cells = <0>;
611 #interrupt-cells = <1>;
612
613 reg = <0x300 0x40>;
614 compatible = "aspeed,ast2500-i2c-bus";
Joel Stanleybb8155a2017-11-28 22:39:25 +1030615 clocks = <&syscon ASPEED_CLK_APB>;
616 resets = <&syscon ASPEED_RESET_I2C>;
Joel Stanleyef856372017-10-04 17:19:11 +1030617 bus-frequency = <100000>;
618 interrupts = <7>;
619 interrupt-parent = <&i2c_ic>;
620 pinctrl-names = "default";
621 pinctrl-0 = <&pinctrl_i2c8_default>;
622 status = "disabled";
623 };
624
625 i2c8: i2c-bus@340 {
626 #address-cells = <1>;
627 #size-cells = <0>;
628 #interrupt-cells = <1>;
629
630 reg = <0x340 0x40>;
631 compatible = "aspeed,ast2500-i2c-bus";
Joel Stanleybb8155a2017-11-28 22:39:25 +1030632 clocks = <&syscon ASPEED_CLK_APB>;
633 resets = <&syscon ASPEED_RESET_I2C>;
Joel Stanleyef856372017-10-04 17:19:11 +1030634 bus-frequency = <100000>;
635 interrupts = <8>;
636 interrupt-parent = <&i2c_ic>;
637 pinctrl-names = "default";
638 pinctrl-0 = <&pinctrl_i2c9_default>;
639 status = "disabled";
640 };
641
642 i2c9: i2c-bus@380 {
643 #address-cells = <1>;
644 #size-cells = <0>;
645 #interrupt-cells = <1>;
646
647 reg = <0x380 0x40>;
648 compatible = "aspeed,ast2500-i2c-bus";
Joel Stanleybb8155a2017-11-28 22:39:25 +1030649 clocks = <&syscon ASPEED_CLK_APB>;
650 resets = <&syscon ASPEED_RESET_I2C>;
Joel Stanleyef856372017-10-04 17:19:11 +1030651 bus-frequency = <100000>;
652 interrupts = <9>;
653 interrupt-parent = <&i2c_ic>;
654 pinctrl-names = "default";
655 pinctrl-0 = <&pinctrl_i2c10_default>;
656 status = "disabled";
657 };
658
659 i2c10: i2c-bus@3c0 {
660 #address-cells = <1>;
661 #size-cells = <0>;
662 #interrupt-cells = <1>;
663
664 reg = <0x3c0 0x40>;
665 compatible = "aspeed,ast2500-i2c-bus";
Joel Stanleybb8155a2017-11-28 22:39:25 +1030666 clocks = <&syscon ASPEED_CLK_APB>;
667 resets = <&syscon ASPEED_RESET_I2C>;
Joel Stanleyef856372017-10-04 17:19:11 +1030668 bus-frequency = <100000>;
669 interrupts = <10>;
670 interrupt-parent = <&i2c_ic>;
671 pinctrl-names = "default";
672 pinctrl-0 = <&pinctrl_i2c11_default>;
673 status = "disabled";
674 };
675
676 i2c11: i2c-bus@400 {
677 #address-cells = <1>;
678 #size-cells = <0>;
679 #interrupt-cells = <1>;
680
681 reg = <0x400 0x40>;
682 compatible = "aspeed,ast2500-i2c-bus";
Joel Stanleybb8155a2017-11-28 22:39:25 +1030683 clocks = <&syscon ASPEED_CLK_APB>;
684 resets = <&syscon ASPEED_RESET_I2C>;
Joel Stanleyef856372017-10-04 17:19:11 +1030685 bus-frequency = <100000>;
686 interrupts = <11>;
687 interrupt-parent = <&i2c_ic>;
688 pinctrl-names = "default";
689 pinctrl-0 = <&pinctrl_i2c12_default>;
690 status = "disabled";
691 };
692
693 i2c12: i2c-bus@440 {
694 #address-cells = <1>;
695 #size-cells = <0>;
696 #interrupt-cells = <1>;
697
698 reg = <0x440 0x40>;
699 compatible = "aspeed,ast2500-i2c-bus";
Joel Stanleybb8155a2017-11-28 22:39:25 +1030700 clocks = <&syscon ASPEED_CLK_APB>;
701 resets = <&syscon ASPEED_RESET_I2C>;
Joel Stanleyef856372017-10-04 17:19:11 +1030702 bus-frequency = <100000>;
703 interrupts = <12>;
704 interrupt-parent = <&i2c_ic>;
705 pinctrl-names = "default";
706 pinctrl-0 = <&pinctrl_i2c13_default>;
707 status = "disabled";
708 };
709
710 i2c13: i2c-bus@480 {
711 #address-cells = <1>;
712 #size-cells = <0>;
713 #interrupt-cells = <1>;
714
715 reg = <0x480 0x40>;
716 compatible = "aspeed,ast2500-i2c-bus";
Joel Stanleybb8155a2017-11-28 22:39:25 +1030717 clocks = <&syscon ASPEED_CLK_APB>;
718 resets = <&syscon ASPEED_RESET_I2C>;
Joel Stanleyef856372017-10-04 17:19:11 +1030719 bus-frequency = <100000>;
720 interrupts = <13>;
721 interrupt-parent = <&i2c_ic>;
722 pinctrl-names = "default";
723 pinctrl-0 = <&pinctrl_i2c14_default>;
724 status = "disabled";
725 };
726};
727
Andrew Jefferycd7df3f2017-10-04 17:19:09 +1030728&pinctrl {
729 pinctrl_acpi_default: acpi_default {
730 function = "ACPI";
731 groups = "ACPI";
732 };
733
734 pinctrl_adc0_default: adc0_default {
735 function = "ADC0";
736 groups = "ADC0";
737 };
738
739 pinctrl_adc1_default: adc1_default {
740 function = "ADC1";
741 groups = "ADC1";
742 };
743
744 pinctrl_adc10_default: adc10_default {
745 function = "ADC10";
746 groups = "ADC10";
747 };
748
749 pinctrl_adc11_default: adc11_default {
750 function = "ADC11";
751 groups = "ADC11";
752 };
753
754 pinctrl_adc12_default: adc12_default {
755 function = "ADC12";
756 groups = "ADC12";
757 };
758
759 pinctrl_adc13_default: adc13_default {
760 function = "ADC13";
761 groups = "ADC13";
762 };
763
764 pinctrl_adc14_default: adc14_default {
765 function = "ADC14";
766 groups = "ADC14";
767 };
768
769 pinctrl_adc15_default: adc15_default {
770 function = "ADC15";
771 groups = "ADC15";
772 };
773
774 pinctrl_adc2_default: adc2_default {
775 function = "ADC2";
776 groups = "ADC2";
777 };
778
779 pinctrl_adc3_default: adc3_default {
780 function = "ADC3";
781 groups = "ADC3";
782 };
783
784 pinctrl_adc4_default: adc4_default {
785 function = "ADC4";
786 groups = "ADC4";
787 };
788
789 pinctrl_adc5_default: adc5_default {
790 function = "ADC5";
791 groups = "ADC5";
792 };
793
794 pinctrl_adc6_default: adc6_default {
795 function = "ADC6";
796 groups = "ADC6";
797 };
798
799 pinctrl_adc7_default: adc7_default {
800 function = "ADC7";
801 groups = "ADC7";
802 };
803
804 pinctrl_adc8_default: adc8_default {
805 function = "ADC8";
806 groups = "ADC8";
807 };
808
809 pinctrl_adc9_default: adc9_default {
810 function = "ADC9";
811 groups = "ADC9";
812 };
813
814 pinctrl_bmcint_default: bmcint_default {
815 function = "BMCINT";
816 groups = "BMCINT";
817 };
818
819 pinctrl_ddcclk_default: ddcclk_default {
820 function = "DDCCLK";
821 groups = "DDCCLK";
822 };
823
824 pinctrl_ddcdat_default: ddcdat_default {
825 function = "DDCDAT";
826 groups = "DDCDAT";
827 };
828
829 pinctrl_espi_default: espi_default {
830 function = "ESPI";
831 groups = "ESPI";
832 };
833
834 pinctrl_fwspics1_default: fwspics1_default {
835 function = "FWSPICS1";
836 groups = "FWSPICS1";
837 };
838
839 pinctrl_fwspics2_default: fwspics2_default {
840 function = "FWSPICS2";
841 groups = "FWSPICS2";
842 };
843
844 pinctrl_gpid0_default: gpid0_default {
845 function = "GPID0";
846 groups = "GPID0";
847 };
848
849 pinctrl_gpid2_default: gpid2_default {
850 function = "GPID2";
851 groups = "GPID2";
852 };
853
854 pinctrl_gpid4_default: gpid4_default {
855 function = "GPID4";
856 groups = "GPID4";
857 };
858
859 pinctrl_gpid6_default: gpid6_default {
860 function = "GPID6";
861 groups = "GPID6";
862 };
863
864 pinctrl_gpie0_default: gpie0_default {
865 function = "GPIE0";
866 groups = "GPIE0";
867 };
868
869 pinctrl_gpie2_default: gpie2_default {
870 function = "GPIE2";
871 groups = "GPIE2";
872 };
873
874 pinctrl_gpie4_default: gpie4_default {
875 function = "GPIE4";
876 groups = "GPIE4";
877 };
878
879 pinctrl_gpie6_default: gpie6_default {
880 function = "GPIE6";
881 groups = "GPIE6";
882 };
883
884 pinctrl_i2c10_default: i2c10_default {
885 function = "I2C10";
886 groups = "I2C10";
887 };
888
889 pinctrl_i2c11_default: i2c11_default {
890 function = "I2C11";
891 groups = "I2C11";
892 };
893
894 pinctrl_i2c12_default: i2c12_default {
895 function = "I2C12";
896 groups = "I2C12";
897 };
898
899 pinctrl_i2c13_default: i2c13_default {
900 function = "I2C13";
901 groups = "I2C13";
902 };
903
904 pinctrl_i2c14_default: i2c14_default {
905 function = "I2C14";
906 groups = "I2C14";
907 };
908
909 pinctrl_i2c3_default: i2c3_default {
910 function = "I2C3";
911 groups = "I2C3";
912 };
913
914 pinctrl_i2c4_default: i2c4_default {
915 function = "I2C4";
916 groups = "I2C4";
917 };
918
919 pinctrl_i2c5_default: i2c5_default {
920 function = "I2C5";
921 groups = "I2C5";
922 };
923
924 pinctrl_i2c6_default: i2c6_default {
925 function = "I2C6";
926 groups = "I2C6";
927 };
928
929 pinctrl_i2c7_default: i2c7_default {
930 function = "I2C7";
931 groups = "I2C7";
932 };
933
934 pinctrl_i2c8_default: i2c8_default {
935 function = "I2C8";
936 groups = "I2C8";
937 };
938
939 pinctrl_i2c9_default: i2c9_default {
940 function = "I2C9";
941 groups = "I2C9";
942 };
943
944 pinctrl_lad0_default: lad0_default {
945 function = "LAD0";
946 groups = "LAD0";
947 };
948
949 pinctrl_lad1_default: lad1_default {
950 function = "LAD1";
951 groups = "LAD1";
952 };
953
954 pinctrl_lad2_default: lad2_default {
955 function = "LAD2";
956 groups = "LAD2";
957 };
958
959 pinctrl_lad3_default: lad3_default {
960 function = "LAD3";
961 groups = "LAD3";
962 };
963
964 pinctrl_lclk_default: lclk_default {
965 function = "LCLK";
966 groups = "LCLK";
967 };
968
969 pinctrl_lframe_default: lframe_default {
970 function = "LFRAME";
971 groups = "LFRAME";
972 };
973
974 pinctrl_lpchc_default: lpchc_default {
975 function = "LPCHC";
976 groups = "LPCHC";
977 };
978
979 pinctrl_lpcpd_default: lpcpd_default {
980 function = "LPCPD";
981 groups = "LPCPD";
982 };
983
984 pinctrl_lpcplus_default: lpcplus_default {
985 function = "LPCPLUS";
986 groups = "LPCPLUS";
987 };
988
989 pinctrl_lpcpme_default: lpcpme_default {
990 function = "LPCPME";
991 groups = "LPCPME";
992 };
993
994 pinctrl_lpcrst_default: lpcrst_default {
995 function = "LPCRST";
996 groups = "LPCRST";
997 };
998
999 pinctrl_lpcsmi_default: lpcsmi_default {
1000 function = "LPCSMI";
1001 groups = "LPCSMI";
1002 };
1003
1004 pinctrl_lsirq_default: lsirq_default {
1005 function = "LSIRQ";
1006 groups = "LSIRQ";
1007 };
1008
1009 pinctrl_mac1link_default: mac1link_default {
1010 function = "MAC1LINK";
1011 groups = "MAC1LINK";
1012 };
1013
1014 pinctrl_mac2link_default: mac2link_default {
1015 function = "MAC2LINK";
1016 groups = "MAC2LINK";
1017 };
1018
1019 pinctrl_mdio1_default: mdio1_default {
1020 function = "MDIO1";
1021 groups = "MDIO1";
1022 };
1023
1024 pinctrl_mdio2_default: mdio2_default {
1025 function = "MDIO2";
1026 groups = "MDIO2";
1027 };
1028
1029 pinctrl_ncts1_default: ncts1_default {
1030 function = "NCTS1";
1031 groups = "NCTS1";
1032 };
1033
1034 pinctrl_ncts2_default: ncts2_default {
1035 function = "NCTS2";
1036 groups = "NCTS2";
1037 };
1038
1039 pinctrl_ncts3_default: ncts3_default {
1040 function = "NCTS3";
1041 groups = "NCTS3";
1042 };
1043
1044 pinctrl_ncts4_default: ncts4_default {
1045 function = "NCTS4";
1046 groups = "NCTS4";
1047 };
1048
1049 pinctrl_ndcd1_default: ndcd1_default {
1050 function = "NDCD1";
1051 groups = "NDCD1";
1052 };
1053
1054 pinctrl_ndcd2_default: ndcd2_default {
1055 function = "NDCD2";
1056 groups = "NDCD2";
1057 };
1058
1059 pinctrl_ndcd3_default: ndcd3_default {
1060 function = "NDCD3";
1061 groups = "NDCD3";
1062 };
1063
1064 pinctrl_ndcd4_default: ndcd4_default {
1065 function = "NDCD4";
1066 groups = "NDCD4";
1067 };
1068
1069 pinctrl_ndsr1_default: ndsr1_default {
1070 function = "NDSR1";
1071 groups = "NDSR1";
1072 };
1073
1074 pinctrl_ndsr2_default: ndsr2_default {
1075 function = "NDSR2";
1076 groups = "NDSR2";
1077 };
1078
1079 pinctrl_ndsr3_default: ndsr3_default {
1080 function = "NDSR3";
1081 groups = "NDSR3";
1082 };
1083
1084 pinctrl_ndsr4_default: ndsr4_default {
1085 function = "NDSR4";
1086 groups = "NDSR4";
1087 };
1088
1089 pinctrl_ndtr1_default: ndtr1_default {
1090 function = "NDTR1";
1091 groups = "NDTR1";
1092 };
1093
1094 pinctrl_ndtr2_default: ndtr2_default {
1095 function = "NDTR2";
1096 groups = "NDTR2";
1097 };
1098
1099 pinctrl_ndtr3_default: ndtr3_default {
1100 function = "NDTR3";
1101 groups = "NDTR3";
1102 };
1103
1104 pinctrl_ndtr4_default: ndtr4_default {
1105 function = "NDTR4";
1106 groups = "NDTR4";
1107 };
1108
1109 pinctrl_nri1_default: nri1_default {
1110 function = "NRI1";
1111 groups = "NRI1";
1112 };
1113
1114 pinctrl_nri2_default: nri2_default {
1115 function = "NRI2";
1116 groups = "NRI2";
1117 };
1118
1119 pinctrl_nri3_default: nri3_default {
1120 function = "NRI3";
1121 groups = "NRI3";
1122 };
1123
1124 pinctrl_nri4_default: nri4_default {
1125 function = "NRI4";
1126 groups = "NRI4";
1127 };
1128
1129 pinctrl_nrts1_default: nrts1_default {
1130 function = "NRTS1";
1131 groups = "NRTS1";
1132 };
1133
1134 pinctrl_nrts2_default: nrts2_default {
1135 function = "NRTS2";
1136 groups = "NRTS2";
1137 };
1138
1139 pinctrl_nrts3_default: nrts3_default {
1140 function = "NRTS3";
1141 groups = "NRTS3";
1142 };
1143
1144 pinctrl_nrts4_default: nrts4_default {
1145 function = "NRTS4";
1146 groups = "NRTS4";
1147 };
1148
1149 pinctrl_oscclk_default: oscclk_default {
1150 function = "OSCCLK";
1151 groups = "OSCCLK";
1152 };
1153
1154 pinctrl_pewake_default: pewake_default {
1155 function = "PEWAKE";
1156 groups = "PEWAKE";
1157 };
1158
1159 pinctrl_pnor_default: pnor_default {
1160 function = "PNOR";
1161 groups = "PNOR";
1162 };
1163
1164 pinctrl_pwm0_default: pwm0_default {
1165 function = "PWM0";
1166 groups = "PWM0";
1167 };
1168
1169 pinctrl_pwm1_default: pwm1_default {
1170 function = "PWM1";
1171 groups = "PWM1";
1172 };
1173
1174 pinctrl_pwm2_default: pwm2_default {
1175 function = "PWM2";
1176 groups = "PWM2";
1177 };
1178
1179 pinctrl_pwm3_default: pwm3_default {
1180 function = "PWM3";
1181 groups = "PWM3";
1182 };
1183
1184 pinctrl_pwm4_default: pwm4_default {
1185 function = "PWM4";
1186 groups = "PWM4";
1187 };
1188
1189 pinctrl_pwm5_default: pwm5_default {
1190 function = "PWM5";
1191 groups = "PWM5";
1192 };
1193
1194 pinctrl_pwm6_default: pwm6_default {
1195 function = "PWM6";
1196 groups = "PWM6";
1197 };
1198
1199 pinctrl_pwm7_default: pwm7_default {
1200 function = "PWM7";
1201 groups = "PWM7";
1202 };
1203
1204 pinctrl_rgmii1_default: rgmii1_default {
1205 function = "RGMII1";
1206 groups = "RGMII1";
1207 };
1208
1209 pinctrl_rgmii2_default: rgmii2_default {
1210 function = "RGMII2";
1211 groups = "RGMII2";
1212 };
1213
1214 pinctrl_rmii1_default: rmii1_default {
1215 function = "RMII1";
1216 groups = "RMII1";
1217 };
1218
1219 pinctrl_rmii2_default: rmii2_default {
1220 function = "RMII2";
1221 groups = "RMII2";
1222 };
1223
1224 pinctrl_rxd1_default: rxd1_default {
1225 function = "RXD1";
1226 groups = "RXD1";
1227 };
1228
1229 pinctrl_rxd2_default: rxd2_default {
1230 function = "RXD2";
1231 groups = "RXD2";
1232 };
1233
1234 pinctrl_rxd3_default: rxd3_default {
1235 function = "RXD3";
1236 groups = "RXD3";
1237 };
1238
1239 pinctrl_rxd4_default: rxd4_default {
1240 function = "RXD4";
1241 groups = "RXD4";
1242 };
1243
1244 pinctrl_salt1_default: salt1_default {
1245 function = "SALT1";
1246 groups = "SALT1";
1247 };
1248
1249 pinctrl_salt10_default: salt10_default {
1250 function = "SALT10";
1251 groups = "SALT10";
1252 };
1253
1254 pinctrl_salt11_default: salt11_default {
1255 function = "SALT11";
1256 groups = "SALT11";
1257 };
1258
1259 pinctrl_salt12_default: salt12_default {
1260 function = "SALT12";
1261 groups = "SALT12";
1262 };
1263
1264 pinctrl_salt13_default: salt13_default {
1265 function = "SALT13";
1266 groups = "SALT13";
1267 };
1268
1269 pinctrl_salt14_default: salt14_default {
1270 function = "SALT14";
1271 groups = "SALT14";
1272 };
1273
1274 pinctrl_salt2_default: salt2_default {
1275 function = "SALT2";
1276 groups = "SALT2";
1277 };
1278
1279 pinctrl_salt3_default: salt3_default {
1280 function = "SALT3";
1281 groups = "SALT3";
1282 };
1283
1284 pinctrl_salt4_default: salt4_default {
1285 function = "SALT4";
1286 groups = "SALT4";
1287 };
1288
1289 pinctrl_salt5_default: salt5_default {
1290 function = "SALT5";
1291 groups = "SALT5";
1292 };
1293
1294 pinctrl_salt6_default: salt6_default {
1295 function = "SALT6";
1296 groups = "SALT6";
1297 };
1298
1299 pinctrl_salt7_default: salt7_default {
1300 function = "SALT7";
1301 groups = "SALT7";
1302 };
1303
1304 pinctrl_salt8_default: salt8_default {
1305 function = "SALT8";
1306 groups = "SALT8";
1307 };
1308
1309 pinctrl_salt9_default: salt9_default {
1310 function = "SALT9";
1311 groups = "SALT9";
1312 };
1313
1314 pinctrl_scl1_default: scl1_default {
1315 function = "SCL1";
1316 groups = "SCL1";
1317 };
1318
1319 pinctrl_scl2_default: scl2_default {
1320 function = "SCL2";
1321 groups = "SCL2";
1322 };
1323
1324 pinctrl_sd1_default: sd1_default {
1325 function = "SD1";
1326 groups = "SD1";
1327 };
1328
1329 pinctrl_sd2_default: sd2_default {
1330 function = "SD2";
1331 groups = "SD2";
1332 };
1333
1334 pinctrl_sda1_default: sda1_default {
1335 function = "SDA1";
1336 groups = "SDA1";
1337 };
1338
1339 pinctrl_sda2_default: sda2_default {
1340 function = "SDA2";
1341 groups = "SDA2";
1342 };
1343
1344 pinctrl_sgps1_default: sgps1_default {
1345 function = "SGPS1";
1346 groups = "SGPS1";
1347 };
1348
1349 pinctrl_sgps2_default: sgps2_default {
1350 function = "SGPS2";
1351 groups = "SGPS2";
1352 };
1353
1354 pinctrl_sioonctrl_default: sioonctrl_default {
1355 function = "SIOONCTRL";
1356 groups = "SIOONCTRL";
1357 };
1358
1359 pinctrl_siopbi_default: siopbi_default {
1360 function = "SIOPBI";
1361 groups = "SIOPBI";
1362 };
1363
1364 pinctrl_siopbo_default: siopbo_default {
1365 function = "SIOPBO";
1366 groups = "SIOPBO";
1367 };
1368
1369 pinctrl_siopwreq_default: siopwreq_default {
1370 function = "SIOPWREQ";
1371 groups = "SIOPWREQ";
1372 };
1373
1374 pinctrl_siopwrgd_default: siopwrgd_default {
1375 function = "SIOPWRGD";
1376 groups = "SIOPWRGD";
1377 };
1378
1379 pinctrl_sios3_default: sios3_default {
1380 function = "SIOS3";
1381 groups = "SIOS3";
1382 };
1383
1384 pinctrl_sios5_default: sios5_default {
1385 function = "SIOS5";
1386 groups = "SIOS5";
1387 };
1388
1389 pinctrl_siosci_default: siosci_default {
1390 function = "SIOSCI";
1391 groups = "SIOSCI";
1392 };
1393
1394 pinctrl_spi1_default: spi1_default {
1395 function = "SPI1";
1396 groups = "SPI1";
1397 };
1398
1399 pinctrl_spi1cs1_default: spi1cs1_default {
1400 function = "SPI1CS1";
1401 groups = "SPI1CS1";
1402 };
1403
1404 pinctrl_spi1debug_default: spi1debug_default {
1405 function = "SPI1DEBUG";
1406 groups = "SPI1DEBUG";
1407 };
1408
1409 pinctrl_spi1passthru_default: spi1passthru_default {
1410 function = "SPI1PASSTHRU";
1411 groups = "SPI1PASSTHRU";
1412 };
1413
1414 pinctrl_spi2ck_default: spi2ck_default {
1415 function = "SPI2CK";
1416 groups = "SPI2CK";
1417 };
1418
1419 pinctrl_spi2cs0_default: spi2cs0_default {
1420 function = "SPI2CS0";
1421 groups = "SPI2CS0";
1422 };
1423
1424 pinctrl_spi2cs1_default: spi2cs1_default {
1425 function = "SPI2CS1";
1426 groups = "SPI2CS1";
1427 };
1428
1429 pinctrl_spi2miso_default: spi2miso_default {
1430 function = "SPI2MISO";
1431 groups = "SPI2MISO";
1432 };
1433
1434 pinctrl_spi2mosi_default: spi2mosi_default {
1435 function = "SPI2MOSI";
1436 groups = "SPI2MOSI";
1437 };
1438
1439 pinctrl_timer3_default: timer3_default {
1440 function = "TIMER3";
1441 groups = "TIMER3";
1442 };
1443
1444 pinctrl_timer4_default: timer4_default {
1445 function = "TIMER4";
1446 groups = "TIMER4";
1447 };
1448
1449 pinctrl_timer5_default: timer5_default {
1450 function = "TIMER5";
1451 groups = "TIMER5";
1452 };
1453
1454 pinctrl_timer6_default: timer6_default {
1455 function = "TIMER6";
1456 groups = "TIMER6";
1457 };
1458
1459 pinctrl_timer7_default: timer7_default {
1460 function = "TIMER7";
1461 groups = "TIMER7";
1462 };
1463
1464 pinctrl_timer8_default: timer8_default {
1465 function = "TIMER8";
1466 groups = "TIMER8";
1467 };
1468
1469 pinctrl_txd1_default: txd1_default {
1470 function = "TXD1";
1471 groups = "TXD1";
1472 };
1473
1474 pinctrl_txd2_default: txd2_default {
1475 function = "TXD2";
1476 groups = "TXD2";
1477 };
1478
1479 pinctrl_txd3_default: txd3_default {
1480 function = "TXD3";
1481 groups = "TXD3";
1482 };
1483
1484 pinctrl_txd4_default: txd4_default {
1485 function = "TXD4";
1486 groups = "TXD4";
1487 };
1488
1489 pinctrl_uart6_default: uart6_default {
1490 function = "UART6";
1491 groups = "UART6";
1492 };
1493
1494 pinctrl_usbcki_default: usbcki_default {
1495 function = "USBCKI";
1496 groups = "USBCKI";
1497 };
1498
Benjamin Herrenschmidtac6e31d2018-04-13 14:40:38 +10001499 pinctrl_usb2ah_default: usb2ah_default {
1500 function = "USB2AH";
1501 groups = "USB2AH";
1502 };
1503
Benjamin Herrenschmidt35578a82018-06-29 13:51:03 +10001504 pinctrl_usb2ad_default: usb2ad_default {
1505 function = "USB2AD";
1506 groups = "USB2AD";
1507 };
1508
Benjamin Herrenschmidtac6e31d2018-04-13 14:40:38 +10001509 pinctrl_usb11bhid_default: usb11bhid_default {
1510 function = "USB11BHID";
1511 groups = "USB11BHID";
1512 };
1513
1514 pinctrl_usb2bh_default: usb2bh_default {
1515 function = "USB2BH";
1516 groups = "USB2BH";
1517 };
1518
Andrew Jefferycd7df3f2017-10-04 17:19:09 +10301519 pinctrl_vgabiosrom_default: vgabiosrom_default {
1520 function = "VGABIOSROM";
1521 groups = "VGABIOSROM";
1522 };
1523
1524 pinctrl_vgahs_default: vgahs_default {
1525 function = "VGAHS";
1526 groups = "VGAHS";
1527 };
1528
1529 pinctrl_vgavs_default: vgavs_default {
1530 function = "VGAVS";
1531 groups = "VGAVS";
1532 };
1533
1534 pinctrl_vpi24_default: vpi24_default {
1535 function = "VPI24";
1536 groups = "VPI24";
1537 };
1538
1539 pinctrl_vpo_default: vpo_default {
1540 function = "VPO";
1541 groups = "VPO";
1542 };
1543
1544 pinctrl_wdtrst1_default: wdtrst1_default {
1545 function = "WDTRST1";
1546 groups = "WDTRST1";
1547 };
1548
1549 pinctrl_wdtrst2_default: wdtrst2_default {
1550 function = "WDTRST2";
1551 groups = "WDTRST2";
1552 };
1553};