Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1 | #ifndef __ASM_ARM_SYSTEM_H |
| 2 | #define __ASM_ARM_SYSTEM_H |
| 3 | |
| 4 | #ifdef __KERNEL__ |
| 5 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 6 | |
| 7 | #define CPU_ARCH_UNKNOWN 0 |
| 8 | #define CPU_ARCH_ARMv3 1 |
| 9 | #define CPU_ARCH_ARMv4 2 |
| 10 | #define CPU_ARCH_ARMv4T 3 |
| 11 | #define CPU_ARCH_ARMv5 4 |
| 12 | #define CPU_ARCH_ARMv5T 5 |
| 13 | #define CPU_ARCH_ARMv5TE 6 |
| 14 | #define CPU_ARCH_ARMv5TEJ 7 |
| 15 | #define CPU_ARCH_ARMv6 8 |
| 16 | |
| 17 | /* |
| 18 | * CR1 bits (CP#15 CR1) |
| 19 | */ |
| 20 | #define CR_M (1 << 0) /* MMU enable */ |
| 21 | #define CR_A (1 << 1) /* Alignment abort enable */ |
| 22 | #define CR_C (1 << 2) /* Dcache enable */ |
| 23 | #define CR_W (1 << 3) /* Write buffer enable */ |
| 24 | #define CR_P (1 << 4) /* 32-bit exception handler */ |
| 25 | #define CR_D (1 << 5) /* 32-bit data address range */ |
| 26 | #define CR_L (1 << 6) /* Implementation defined */ |
| 27 | #define CR_B (1 << 7) /* Big endian */ |
| 28 | #define CR_S (1 << 8) /* System MMU protection */ |
| 29 | #define CR_R (1 << 9) /* ROM MMU protection */ |
| 30 | #define CR_F (1 << 10) /* Implementation defined */ |
| 31 | #define CR_Z (1 << 11) /* Implementation defined */ |
| 32 | #define CR_I (1 << 12) /* Icache enable */ |
| 33 | #define CR_V (1 << 13) /* Vectors relocated to 0xffff0000 */ |
| 34 | #define CR_RR (1 << 14) /* Round Robin cache replacement */ |
| 35 | #define CR_L4 (1 << 15) /* LDR pc can set T bit */ |
| 36 | #define CR_DT (1 << 16) |
| 37 | #define CR_IT (1 << 18) |
| 38 | #define CR_ST (1 << 19) |
| 39 | #define CR_FI (1 << 21) /* Fast interrupt (lower latency mode) */ |
| 40 | #define CR_U (1 << 22) /* Unaligned access operation */ |
| 41 | #define CR_XP (1 << 23) /* Extended page tables */ |
| 42 | #define CR_VE (1 << 24) /* Vectored interrupts */ |
| 43 | |
| 44 | #define CPUID_ID 0 |
| 45 | #define CPUID_CACHETYPE 1 |
| 46 | #define CPUID_TCM 2 |
| 47 | #define CPUID_TLBTYPE 3 |
| 48 | |
Hyok S. Choi | f12d0d7 | 2006-09-26 17:36:37 +0900 | [diff] [blame] | 49 | #ifdef CONFIG_CPU_CP15 |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 50 | #define read_cpuid(reg) \ |
| 51 | ({ \ |
| 52 | unsigned int __val; \ |
| 53 | asm("mrc p15, 0, %0, c0, c0, " __stringify(reg) \ |
| 54 | : "=r" (__val) \ |
| 55 | : \ |
| 56 | : "cc"); \ |
| 57 | __val; \ |
| 58 | }) |
Hyok S. Choi | f12d0d7 | 2006-09-26 17:36:37 +0900 | [diff] [blame] | 59 | #else |
| 60 | #define read_cpuid(reg) (processor_id) |
| 61 | #endif |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 62 | |
| 63 | /* |
| 64 | * This is used to ensure the compiler did actually allocate the register we |
| 65 | * asked it for some inline assembly sequences. Apparently we can't trust |
| 66 | * the compiler from one version to another so a bit of paranoia won't hurt. |
| 67 | * This string is meant to be concatenated with the inline asm string and |
| 68 | * will cause compilation to stop on mismatch. |
| 69 | * (for details, see gcc PR 15089) |
| 70 | */ |
| 71 | #define __asmeq(x, y) ".ifnc " x "," y " ; .err ; .endif\n\t" |
| 72 | |
| 73 | #ifndef __ASSEMBLY__ |
| 74 | |
| 75 | #include <linux/linkage.h> |
Russell King | 255d1f8 | 2006-12-18 00:12:47 +0000 | [diff] [blame] | 76 | #include <linux/irqflags.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 77 | |
| 78 | struct thread_info; |
| 79 | struct task_struct; |
| 80 | |
| 81 | /* information about the system we're running on */ |
| 82 | extern unsigned int system_rev; |
| 83 | extern unsigned int system_serial_low; |
| 84 | extern unsigned int system_serial_high; |
| 85 | extern unsigned int mem_fclk_21285; |
| 86 | |
| 87 | struct pt_regs; |
| 88 | |
| 89 | void die(const char *msg, struct pt_regs *regs, int err) |
| 90 | __attribute__((noreturn)); |
| 91 | |
Russell King | cfb0810 | 2005-06-30 11:06:49 +0100 | [diff] [blame] | 92 | struct siginfo; |
| 93 | void notify_die(const char *str, struct pt_regs *regs, struct siginfo *info, |
| 94 | unsigned long err, unsigned long trap); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 95 | |
| 96 | void hook_fault_code(int nr, int (*fn)(unsigned long, unsigned int, |
| 97 | struct pt_regs *), |
| 98 | int sig, const char *name); |
| 99 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 100 | #define xchg(ptr,x) \ |
| 101 | ((__typeof__(*(ptr)))__xchg((unsigned long)(x),(ptr),sizeof(*(ptr)))) |
| 102 | |
| 103 | #define tas(ptr) (xchg((ptr),1)) |
| 104 | |
| 105 | extern asmlinkage void __backtrace(void); |
Russell King | 652a12e | 2005-04-17 15:50:36 +0100 | [diff] [blame] | 106 | extern asmlinkage void c_backtrace(unsigned long fp, int pmode); |
Russell King | 5470dc6 | 2005-11-16 18:36:49 +0000 | [diff] [blame] | 107 | |
| 108 | struct mm_struct; |
Russell King | 652a12e | 2005-04-17 15:50:36 +0100 | [diff] [blame] | 109 | extern void show_pte(struct mm_struct *mm, unsigned long addr); |
| 110 | extern void __show_regs(struct pt_regs *); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 111 | |
| 112 | extern int cpu_architecture(void); |
Russell King | 36c5ed2 | 2005-06-19 18:39:33 +0100 | [diff] [blame] | 113 | extern void cpu_init(void); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 114 | |
Richard Purdie | 74617fb | 2006-06-19 19:57:12 +0100 | [diff] [blame] | 115 | void arm_machine_restart(char mode); |
| 116 | extern void (*arm_pm_restart)(char str); |
| 117 | |
Lennert Buytenhek | 23bdf86 | 2006-03-28 21:00:40 +0100 | [diff] [blame] | 118 | /* |
| 119 | * Intel's XScale3 core supports some v6 features (supersections, L2) |
| 120 | * but advertises itself as v5 as it does not support the v6 ISA. For |
| 121 | * this reason, we need a way to explicitly test for this type of CPU. |
| 122 | */ |
| 123 | #ifndef CONFIG_CPU_XSC3 |
| 124 | #define cpu_is_xsc3() 0 |
| 125 | #else |
| 126 | static inline int cpu_is_xsc3(void) |
| 127 | { |
| 128 | extern unsigned int processor_id; |
| 129 | |
| 130 | if ((processor_id & 0xffffe000) == 0x69056000) |
| 131 | return 1; |
| 132 | |
| 133 | return 0; |
| 134 | } |
| 135 | #endif |
| 136 | |
Deepak Saxena | 5cedae9 | 2006-05-31 16:14:05 -0700 | [diff] [blame] | 137 | #if !defined(CONFIG_CPU_XSCALE) && !defined(CONFIG_CPU_XSC3) |
| 138 | #define cpu_is_xscale() 0 |
| 139 | #else |
| 140 | #define cpu_is_xscale() 1 |
| 141 | #endif |
| 142 | |
Russell King | 255d1f8 | 2006-12-18 00:12:47 +0000 | [diff] [blame] | 143 | extern unsigned long cr_no_alignment; /* defined in entry-armv.S */ |
| 144 | extern unsigned long cr_alignment; /* defined in entry-armv.S */ |
| 145 | |
Russell King | efe90d2 | 2006-12-08 15:22:20 +0000 | [diff] [blame] | 146 | static inline unsigned int get_cr(void) |
| 147 | { |
| 148 | unsigned int val; |
| 149 | asm("mrc p15, 0, %0, c1, c0, 0 @ get CR" : "=r" (val) : : "cc"); |
| 150 | return val; |
| 151 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 152 | |
Russell King | efe90d2 | 2006-12-08 15:22:20 +0000 | [diff] [blame] | 153 | static inline void set_cr(unsigned int val) |
| 154 | { |
| 155 | asm volatile("mcr p15, 0, %0, c1, c0, 0 @ set CR" |
| 156 | : : "r" (val) : "cc"); |
| 157 | } |
| 158 | |
Russell King | 255d1f8 | 2006-12-18 00:12:47 +0000 | [diff] [blame] | 159 | #ifndef CONFIG_SMP |
| 160 | extern void adjust_cr(unsigned long mask, unsigned long set); |
| 161 | #endif |
| 162 | |
Russell King | efe90d2 | 2006-12-08 15:22:20 +0000 | [diff] [blame] | 163 | #define CPACC_FULL(n) (3 << (n * 2)) |
| 164 | #define CPACC_SVC(n) (1 << (n * 2)) |
| 165 | #define CPACC_DISABLE(n) (0 << (n * 2)) |
| 166 | |
| 167 | static inline unsigned int get_copro_access(void) |
| 168 | { |
| 169 | unsigned int val; |
| 170 | asm("mrc p15, 0, %0, c1, c0, 2 @ get copro access" |
| 171 | : "=r" (val) : : "cc"); |
| 172 | return val; |
| 173 | } |
| 174 | |
| 175 | static inline void set_copro_access(unsigned int val) |
| 176 | { |
| 177 | asm volatile("mcr p15, 0, %0, c1, c0, 2 @ set copro access" |
| 178 | : : "r" (val) : "cc"); |
| 179 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 180 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 181 | #define UDBG_UNDEFINED (1 << 0) |
| 182 | #define UDBG_SYSCALL (1 << 1) |
| 183 | #define UDBG_BADABORT (1 << 2) |
| 184 | #define UDBG_SEGV (1 << 3) |
| 185 | #define UDBG_BUS (1 << 4) |
| 186 | |
| 187 | extern unsigned int user_debug; |
| 188 | |
| 189 | #if __LINUX_ARM_ARCH__ >= 4 |
| 190 | #define vectors_high() (cr_alignment & CR_V) |
| 191 | #else |
| 192 | #define vectors_high() (0) |
| 193 | #endif |
| 194 | |
Russell King | 6d9b37a | 2005-07-26 19:44:26 +0100 | [diff] [blame] | 195 | #if __LINUX_ARM_ARCH__ >= 6 |
Catalin Marinas | dcda7e4 | 2007-02-05 14:47:35 +0100 | [diff] [blame^] | 196 | #define isb() __asm__ __volatile__ ("mcr p15, 0, %0, c7, c5, 4" \ |
| 197 | : : "r" (0) : "memory") |
| 198 | #define dsb() __asm__ __volatile__ ("mcr p15, 0, %0, c7, c10, 4" \ |
| 199 | : : "r" (0) : "memory") |
| 200 | #define dmb() __asm__ __volatile__ ("mcr p15, 0, %0, c7, c10, 5" \ |
| 201 | : : "r" (0) : "memory") |
Russell King | 6d9b37a | 2005-07-26 19:44:26 +0100 | [diff] [blame] | 202 | #else |
Catalin Marinas | dcda7e4 | 2007-02-05 14:47:35 +0100 | [diff] [blame^] | 203 | #define isb() __asm__ __volatile__ ("" : : : "memory") |
| 204 | #define dsb() __asm__ __volatile__ ("mcr p15, 0, %0, c7, c10, 4" \ |
| 205 | : : "r" (0) : "memory") |
| 206 | #define dmb() __asm__ __volatile__ ("" : : : "memory") |
Russell King | 6d9b37a | 2005-07-26 19:44:26 +0100 | [diff] [blame] | 207 | #endif |
Catalin Marinas | dcda7e4 | 2007-02-05 14:47:35 +0100 | [diff] [blame^] | 208 | #define mb() dmb() |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 209 | #define rmb() mb() |
| 210 | #define wmb() mb() |
| 211 | #define read_barrier_depends() do { } while(0) |
| 212 | #define set_mb(var, value) do { var = value; mb(); } while (0) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 213 | #define nop() __asm__ __volatile__("mov\tr0,r0\t@ nop\n\t"); |
| 214 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 215 | /* |
Nick Piggin | 4866cde | 2005-06-25 14:57:23 -0700 | [diff] [blame] | 216 | * switch_mm() may do a full cache flush over the context switch, |
| 217 | * so enable interrupts over the context switch to avoid high |
| 218 | * latency. |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 219 | */ |
Nick Piggin | 4866cde | 2005-06-25 14:57:23 -0700 | [diff] [blame] | 220 | #define __ARCH_WANT_INTERRUPTS_ON_CTXSW |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 221 | |
| 222 | /* |
| 223 | * switch_to(prev, next) should switch from task `prev' to `next' |
| 224 | * `prev' will never be the same as `next'. schedule() itself |
| 225 | * contains the memory barrier to tell GCC not to cache `current'. |
| 226 | */ |
| 227 | extern struct task_struct *__switch_to(struct task_struct *, struct thread_info *, struct thread_info *); |
| 228 | |
| 229 | #define switch_to(prev,next,last) \ |
| 230 | do { \ |
Al Viro | e7c1b32 | 2006-01-12 01:05:56 -0800 | [diff] [blame] | 231 | last = __switch_to(prev,task_thread_info(prev), task_thread_info(next)); \ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 232 | } while (0) |
| 233 | |
| 234 | /* |
Ingo Molnar | 4dc7a0b | 2006-01-12 01:05:27 -0800 | [diff] [blame] | 235 | * On SMP systems, when the scheduler does migration-cost autodetection, |
| 236 | * it needs a way to flush as much of the CPU's caches as possible. |
| 237 | * |
| 238 | * TODO: fill this in! |
| 239 | */ |
| 240 | static inline void sched_cacheflush(void) |
| 241 | { |
| 242 | } |
| 243 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 244 | #ifdef CONFIG_SMP |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 245 | |
| 246 | #define smp_mb() mb() |
| 247 | #define smp_rmb() rmb() |
| 248 | #define smp_wmb() wmb() |
| 249 | #define smp_read_barrier_depends() read_barrier_depends() |
| 250 | |
| 251 | #else |
| 252 | |
| 253 | #define smp_mb() barrier() |
| 254 | #define smp_rmb() barrier() |
| 255 | #define smp_wmb() barrier() |
| 256 | #define smp_read_barrier_depends() do { } while(0) |
| 257 | |
Russell King | 053a7b5 | 2005-06-28 19:22:25 +0100 | [diff] [blame] | 258 | #endif /* CONFIG_SMP */ |
| 259 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 260 | #if defined(CONFIG_CPU_SA1100) || defined(CONFIG_CPU_SA110) |
| 261 | /* |
| 262 | * On the StrongARM, "swp" is terminally broken since it bypasses the |
| 263 | * cache totally. This means that the cache becomes inconsistent, and, |
| 264 | * since we use normal loads/stores as well, this is really bad. |
| 265 | * Typically, this causes oopsen in filp_close, but could have other, |
| 266 | * more disasterous effects. There are two work-arounds: |
| 267 | * 1. Disable interrupts and emulate the atomic swap |
| 268 | * 2. Clean the cache, perform atomic swap, flush the cache |
| 269 | * |
| 270 | * We choose (1) since its the "easiest" to achieve here and is not |
| 271 | * dependent on the processor type. |
Russell King | 053a7b5 | 2005-06-28 19:22:25 +0100 | [diff] [blame] | 272 | * |
| 273 | * NOTE that this solution won't work on an SMP system, so explcitly |
| 274 | * forbid it here. |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 275 | */ |
| 276 | #define swp_is_buggy |
| 277 | #endif |
| 278 | |
| 279 | static inline unsigned long __xchg(unsigned long x, volatile void *ptr, int size) |
| 280 | { |
| 281 | extern void __bad_xchg(volatile void *, int); |
| 282 | unsigned long ret; |
| 283 | #ifdef swp_is_buggy |
| 284 | unsigned long flags; |
| 285 | #endif |
Russell King | 9560782 | 2005-07-26 19:39:31 +0100 | [diff] [blame] | 286 | #if __LINUX_ARM_ARCH__ >= 6 |
| 287 | unsigned int tmp; |
| 288 | #endif |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 289 | |
| 290 | switch (size) { |
Russell King | 9560782 | 2005-07-26 19:39:31 +0100 | [diff] [blame] | 291 | #if __LINUX_ARM_ARCH__ >= 6 |
| 292 | case 1: |
| 293 | asm volatile("@ __xchg1\n" |
| 294 | "1: ldrexb %0, [%3]\n" |
| 295 | " strexb %1, %2, [%3]\n" |
| 296 | " teq %1, #0\n" |
| 297 | " bne 1b" |
| 298 | : "=&r" (ret), "=&r" (tmp) |
| 299 | : "r" (x), "r" (ptr) |
| 300 | : "memory", "cc"); |
| 301 | break; |
| 302 | case 4: |
| 303 | asm volatile("@ __xchg4\n" |
| 304 | "1: ldrex %0, [%3]\n" |
| 305 | " strex %1, %2, [%3]\n" |
| 306 | " teq %1, #0\n" |
| 307 | " bne 1b" |
| 308 | : "=&r" (ret), "=&r" (tmp) |
| 309 | : "r" (x), "r" (ptr) |
| 310 | : "memory", "cc"); |
| 311 | break; |
| 312 | #elif defined(swp_is_buggy) |
| 313 | #ifdef CONFIG_SMP |
| 314 | #error SMP is not supported on this platform |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 315 | #endif |
Russell King | 9560782 | 2005-07-26 19:39:31 +0100 | [diff] [blame] | 316 | case 1: |
Lennert Buytenhek | e7cc2c5 | 2006-09-21 03:35:20 +0100 | [diff] [blame] | 317 | raw_local_irq_save(flags); |
Russell King | 9560782 | 2005-07-26 19:39:31 +0100 | [diff] [blame] | 318 | ret = *(volatile unsigned char *)ptr; |
| 319 | *(volatile unsigned char *)ptr = x; |
Lennert Buytenhek | e7cc2c5 | 2006-09-21 03:35:20 +0100 | [diff] [blame] | 320 | raw_local_irq_restore(flags); |
Russell King | 9560782 | 2005-07-26 19:39:31 +0100 | [diff] [blame] | 321 | break; |
| 322 | |
| 323 | case 4: |
Lennert Buytenhek | e7cc2c5 | 2006-09-21 03:35:20 +0100 | [diff] [blame] | 324 | raw_local_irq_save(flags); |
Russell King | 9560782 | 2005-07-26 19:39:31 +0100 | [diff] [blame] | 325 | ret = *(volatile unsigned long *)ptr; |
| 326 | *(volatile unsigned long *)ptr = x; |
Lennert Buytenhek | e7cc2c5 | 2006-09-21 03:35:20 +0100 | [diff] [blame] | 327 | raw_local_irq_restore(flags); |
Russell King | 9560782 | 2005-07-26 19:39:31 +0100 | [diff] [blame] | 328 | break; |
| 329 | #else |
| 330 | case 1: |
| 331 | asm volatile("@ __xchg1\n" |
| 332 | " swpb %0, %1, [%2]" |
| 333 | : "=&r" (ret) |
| 334 | : "r" (x), "r" (ptr) |
| 335 | : "memory", "cc"); |
| 336 | break; |
| 337 | case 4: |
| 338 | asm volatile("@ __xchg4\n" |
| 339 | " swp %0, %1, [%2]" |
| 340 | : "=&r" (ret) |
| 341 | : "r" (x), "r" (ptr) |
| 342 | : "memory", "cc"); |
| 343 | break; |
| 344 | #endif |
| 345 | default: |
| 346 | __bad_xchg(ptr, size), ret = 0; |
| 347 | break; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 348 | } |
| 349 | |
| 350 | return ret; |
| 351 | } |
| 352 | |
Ben Dooks | dabaeff | 2006-03-15 23:17:26 +0000 | [diff] [blame] | 353 | extern void disable_hlt(void); |
| 354 | extern void enable_hlt(void); |
| 355 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 356 | #endif /* __ASSEMBLY__ */ |
| 357 | |
| 358 | #define arch_align_stack(x) (x) |
| 359 | |
| 360 | #endif /* __KERNEL__ */ |
| 361 | |
| 362 | #endif |