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R Sricharan6e58b8f2013-08-14 19:08:20 +05301/*
2 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8/dts-v1/;
9
Rajendra Nayak38b248d2014-04-29 16:35:10 +053010#include "dra74x.dtsi"
R Sricharan6e58b8f2013-08-14 19:08:20 +053011
12/ {
Rajendra Nayak38b248d2014-04-29 16:35:10 +053013 model = "TI DRA742";
14 compatible = "ti,dra7-evm", "ti,dra742", "ti,dra74", "ti,dra7";
R Sricharan6e58b8f2013-08-14 19:08:20 +053015
16 memory {
17 device_type = "memory";
18 reg = <0x80000000 0x60000000>; /* 1536 MB */
19 };
Balaji T K6cf02db2013-10-07 21:55:04 +053020
21 mmc2_3v3: fixedregulator-mmc2 {
22 compatible = "regulator-fixed";
23 regulator-name = "mmc2_3v3";
24 regulator-min-microvolt = <3300000>;
25 regulator-max-microvolt = <3300000>;
26 };
R Sricharan6e58b8f2013-08-14 19:08:20 +053027};
28
29&dra7_pmx_core {
30 i2c1_pins: pinmux_i2c1_pins {
31 pinctrl-single,pins = <
32 0x400 (PIN_INPUT | MUX_MODE0) /* i2c1_sda */
33 0x404 (PIN_INPUT | MUX_MODE0) /* i2c1_scl */
34 >;
35 };
36
37 i2c2_pins: pinmux_i2c2_pins {
38 pinctrl-single,pins = <
39 0x408 (PIN_INPUT | MUX_MODE0) /* i2c2_sda */
40 0x40c (PIN_INPUT | MUX_MODE0) /* i2c2_scl */
41 >;
42 };
43
44 i2c3_pins: pinmux_i2c3_pins {
45 pinctrl-single,pins = <
46 0x410 (PIN_INPUT | MUX_MODE0) /* i2c3_sda */
47 0x414 (PIN_INPUT | MUX_MODE0) /* i2c3_scl */
48 >;
49 };
50
51 mcspi1_pins: pinmux_mcspi1_pins {
52 pinctrl-single,pins = <
53 0x3a4 (PIN_INPUT | MUX_MODE0) /* spi2_clk */
54 0x3a8 (PIN_INPUT | MUX_MODE0) /* spi2_d1 */
55 0x3ac (PIN_INPUT | MUX_MODE0) /* spi2_d0 */
56 0x3b0 (PIN_INPUT_SLEW | MUX_MODE0) /* spi2_cs0 */
57 0x3b4 (PIN_INPUT_SLEW | MUX_MODE0) /* spi2_cs1 */
58 0x3b8 (PIN_INPUT_SLEW | MUX_MODE6) /* spi2_cs2 */
59 0x3bc (PIN_INPUT_SLEW | MUX_MODE6) /* spi2_cs3 */
60 >;
61 };
62
63 mcspi2_pins: pinmux_mcspi2_pins {
64 pinctrl-single,pins = <
65 0x3c0 (PIN_INPUT | MUX_MODE0) /* spi2_sclk */
66 0x3c4 (PIN_INPUT_SLEW | MUX_MODE0) /* spi2_d1 */
67 0x3c8 (PIN_INPUT_SLEW | MUX_MODE0) /* spi2_d1 */
68 0x3cc (PIN_INPUT_SLEW | MUX_MODE0) /* spi2_cs0 */
69 >;
70 };
71
72 uart1_pins: pinmux_uart1_pins {
73 pinctrl-single,pins = <
74 0x3e0 (PIN_INPUT_SLEW | MUX_MODE0) /* uart1_rxd */
75 0x3e4 (PIN_INPUT_SLEW | MUX_MODE0) /* uart1_txd */
76 0x3e8 (PIN_INPUT | MUX_MODE3) /* uart1_ctsn */
77 0x3ec (PIN_INPUT | MUX_MODE3) /* uart1_rtsn */
78 >;
79 };
80
81 uart2_pins: pinmux_uart2_pins {
82 pinctrl-single,pins = <
83 0x3f0 (PIN_INPUT | MUX_MODE0) /* uart2_rxd */
84 0x3f4 (PIN_INPUT | MUX_MODE0) /* uart2_txd */
85 0x3f8 (PIN_INPUT | MUX_MODE0) /* uart2_ctsn */
86 0x3fc (PIN_INPUT | MUX_MODE0) /* uart2_rtsn */
87 >;
88 };
89
90 uart3_pins: pinmux_uart3_pins {
91 pinctrl-single,pins = <
92 0x248 (PIN_INPUT_SLEW | MUX_MODE0) /* uart3_rxd */
93 0x24c (PIN_INPUT_SLEW | MUX_MODE0) /* uart3_txd */
94 >;
95 };
Sourav Poddardc2dd5b2014-05-06 16:37:24 +053096
97 qspi1_pins: pinmux_qspi1_pins {
98 pinctrl-single,pins = <
99 0x4c (PIN_INPUT | MUX_MODE1) /* gpmc_a3.qspi1_cs2 */
100 0x50 (PIN_INPUT | MUX_MODE1) /* gpmc_a4.qspi1_cs3 */
101 0x74 (PIN_INPUT | MUX_MODE1) /* gpmc_a13.qspi1_rtclk */
102 0x78 (PIN_INPUT | MUX_MODE1) /* gpmc_a14.qspi1_d3 */
103 0x7c (PIN_INPUT | MUX_MODE1) /* gpmc_a15.qspi1_d2 */
104 0x80 (PIN_INPUT | MUX_MODE1) /* gpmc_a16.qspi1_d1 */
105 0x84 (PIN_INPUT | MUX_MODE1) /* gpmc_a17.qspi1_d0 */
106 0x88 (PIN_INPUT | MUX_MODE1) /* qpmc_a18.qspi1_sclk */
107 0xb8 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs2.qspi1_cs0 */
108 0xbc (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs3.qspi1_cs1 */
109 >;
110 };
R Sricharan6e58b8f2013-08-14 19:08:20 +0530111};
112
113&i2c1 {
114 status = "okay";
115 pinctrl-names = "default";
116 pinctrl-0 = <&i2c1_pins>;
117 clock-frequency = <400000>;
Keerthyc56a8312013-08-26 11:06:51 +0530118
119 tps659038: tps659038@58 {
120 compatible = "ti,tps659038";
121 reg = <0x58>;
122
123 tps659038_pmic {
124 compatible = "ti,tps659038-pmic";
125
126 regulators {
127 smps123_reg: smps123 {
128 /* VDD_MPU */
129 regulator-name = "smps123";
130 regulator-min-microvolt = < 850000>;
131 regulator-max-microvolt = <1250000>;
132 regulator-always-on;
133 regulator-boot-on;
134 };
135
136 smps45_reg: smps45 {
137 /* VDD_DSPEVE */
138 regulator-name = "smps45";
139 regulator-min-microvolt = < 850000>;
140 regulator-max-microvolt = <1150000>;
141 regulator-boot-on;
142 };
143
144 smps6_reg: smps6 {
145 /* VDD_GPU - over VDD_SMPS6 */
146 regulator-name = "smps6";
147 regulator-min-microvolt = <850000>;
148 regulator-max-microvolt = <12500000>;
149 regulator-boot-on;
150 };
151
152 smps7_reg: smps7 {
153 /* CORE_VDD */
154 regulator-name = "smps7";
155 regulator-min-microvolt = <850000>;
156 regulator-max-microvolt = <1030000>;
157 regulator-always-on;
158 regulator-boot-on;
159 };
160
161 smps8_reg: smps8 {
162 /* VDD_IVAHD */
163 regulator-name = "smps8";
164 regulator-min-microvolt = < 850000>;
165 regulator-max-microvolt = <1250000>;
166 regulator-boot-on;
167 };
168
169 smps9_reg: smps9 {
170 /* VDDS1V8 */
171 regulator-name = "smps9";
172 regulator-min-microvolt = <1800000>;
173 regulator-max-microvolt = <1800000>;
174 regulator-always-on;
175 regulator-boot-on;
176 };
177
178 ldo1_reg: ldo1 {
179 /* LDO1_OUT --> SDIO */
180 regulator-name = "ldo1";
181 regulator-min-microvolt = <1800000>;
182 regulator-max-microvolt = <3300000>;
183 regulator-boot-on;
184 };
185
186 ldo2_reg: ldo2 {
187 /* VDD_RTCIO */
188 /* LDO2 -> VDDSHV5, LDO2 also goes to CAN_PHY_3V3 */
189 regulator-name = "ldo2";
190 regulator-min-microvolt = <3300000>;
191 regulator-max-microvolt = <3300000>;
192 regulator-boot-on;
193 };
194
195 ldo3_reg: ldo3 {
196 /* VDDA_1V8_PHY */
197 regulator-name = "ldo3";
198 regulator-min-microvolt = <1800000>;
199 regulator-max-microvolt = <1800000>;
200 regulator-boot-on;
201 };
202
203 ldo9_reg: ldo9 {
204 /* VDD_RTC */
205 regulator-name = "ldo9";
206 regulator-min-microvolt = <1050000>;
207 regulator-max-microvolt = <1050000>;
208 regulator-boot-on;
209 };
210
211 ldoln_reg: ldoln {
212 /* VDDA_1V8_PLL */
213 regulator-name = "ldoln";
214 regulator-min-microvolt = <1800000>;
215 regulator-max-microvolt = <1800000>;
216 regulator-always-on;
217 regulator-boot-on;
218 };
219
220 ldousb_reg: ldousb {
221 /* VDDA_3V_USB: VDDA_USBHS33 */
222 regulator-name = "ldousb";
223 regulator-min-microvolt = <3300000>;
224 regulator-max-microvolt = <3300000>;
225 regulator-boot-on;
226 };
227 };
228 };
229 };
R Sricharan6e58b8f2013-08-14 19:08:20 +0530230};
231
232&i2c2 {
233 status = "okay";
234 pinctrl-names = "default";
235 pinctrl-0 = <&i2c2_pins>;
236 clock-frequency = <400000>;
237};
238
239&i2c3 {
240 status = "okay";
241 pinctrl-names = "default";
242 pinctrl-0 = <&i2c3_pins>;
243 clock-frequency = <3400000>;
244};
245
246&mcspi1 {
247 status = "okay";
248 pinctrl-names = "default";
249 pinctrl-0 = <&mcspi1_pins>;
250};
251
252&mcspi2 {
253 status = "okay";
254 pinctrl-names = "default";
255 pinctrl-0 = <&mcspi2_pins>;
256};
257
258&uart1 {
259 status = "okay";
260 pinctrl-names = "default";
261 pinctrl-0 = <&uart1_pins>;
262};
263
264&uart2 {
265 status = "okay";
266 pinctrl-names = "default";
267 pinctrl-0 = <&uart2_pins>;
268};
269
270&uart3 {
271 status = "okay";
272 pinctrl-names = "default";
273 pinctrl-0 = <&uart3_pins>;
274};
Balaji T Kbf1788d2013-10-07 21:55:03 +0530275
276&mmc1 {
277 status = "okay";
278 vmmc-supply = <&ldo1_reg>;
279 bus-width = <4>;
280};
Balaji T K6cf02db2013-10-07 21:55:04 +0530281
282&mmc2 {
283 status = "okay";
284 vmmc-supply = <&mmc2_3v3>;
285 bus-width = <8>;
286};
J Keerthy22f1e7e2013-10-16 10:39:05 -0500287
288&cpu0 {
289 cpu0-supply = <&smps123_reg>;
290};
Sourav Poddardc2dd5b2014-05-06 16:37:24 +0530291
292&qspi {
293 status = "okay";
294 pinctrl-names = "default";
295 pinctrl-0 = <&qspi1_pins>;
296
297 spi-max-frequency = <48000000>;
298 m25p80@0 {
299 compatible = "s25fl256s1";
300 spi-max-frequency = <48000000>;
301 reg = <0>;
302 spi-tx-bus-width = <1>;
303 spi-rx-bus-width = <4>;
304 spi-cpol;
305 spi-cpha;
306 #address-cells = <1>;
307 #size-cells = <1>;
308
309 /* MTD partition table.
310 * The ROM checks the first four physical blocks
311 * for a valid file to boot and the flash here is
312 * 64KiB block size.
313 */
314 partition@0 {
315 label = "QSPI.SPL";
316 reg = <0x00000000 0x000010000>;
317 };
318 partition@1 {
319 label = "QSPI.SPL.backup1";
320 reg = <0x00010000 0x00010000>;
321 };
322 partition@2 {
323 label = "QSPI.SPL.backup2";
324 reg = <0x00020000 0x00010000>;
325 };
326 partition@3 {
327 label = "QSPI.SPL.backup3";
328 reg = <0x00030000 0x00010000>;
329 };
330 partition@4 {
331 label = "QSPI.u-boot";
332 reg = <0x00040000 0x00100000>;
333 };
334 partition@5 {
335 label = "QSPI.u-boot-spl-os";
336 reg = <0x00140000 0x00010000>;
337 };
338 partition@6 {
339 label = "QSPI.u-boot-env";
340 reg = <0x00150000 0x00010000>;
341 };
342 partition@7 {
343 label = "QSPI.u-boot-env.backup1";
344 reg = <0x00160000 0x0010000>;
345 };
346 partition@8 {
347 label = "QSPI.kernel";
348 reg = <0x00170000 0x0800000>;
349 };
350 partition@9 {
351 label = "QSPI.file-system";
352 reg = <0x00970000 0x01690000>;
353 };
354 };
355};