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review.shift-gmbh.com / SHIFTPHONES / mainline / linux / dbd7c191dbd2bc3b17bce2fedf87cd3606b5953d / . / arch / arm / boot / dts / dra7.dtsi
blob: bff4348f48fa10ac95ea066c59a7f0f38b267725 [file] [log] [blame]
R Sricharan6e58b8f2013-08-14 19:08:20 +0530[diff] [blame]1/*
2 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 * Based on "omap4.dtsi"
8 */
9
10#include <dt-bindings/interrupt-controller/arm-gic.h>
11#include <dt-bindings/pinctrl/dra.h>
12
13#include "skeleton.dtsi"
14
15/ {
16 #address-cells = <1>;
17 #size-cells = <1>;
18
19 compatible = "ti,dra7xx";
20 interrupt-parent = <&gic>;
21
22 aliases {
Nishanth Menon20b80942013-10-16 15:21:03 -0500[diff] [blame]23 i2c0 = &i2c1;
24 i2c1 = &i2c2;
25 i2c2 = &i2c3;
26 i2c3 = &i2c4;
27 i2c4 = &i2c5;
R Sricharan6e58b8f2013-08-14 19:08:20 +0530[diff] [blame]28 serial0 = &uart1;
29 serial1 = &uart2;
30 serial2 = &uart3;
31 serial3 = &uart4;
32 serial4 = &uart5;
33 serial5 = &uart6;
34 };
35
36 cpus {
37 #address-cells = <1>;
38 #size-cells = <0>;
39
J Keerthy22f1e7e2013-10-16 10:39:05 -0500[diff] [blame]40 cpu0: cpu@0 {
R Sricharan6e58b8f2013-08-14 19:08:20 +0530[diff] [blame]41 device_type = "cpu";
42 compatible = "arm,cortex-a15";
43 reg = <0>;
J Keerthy620c5162013-10-16 10:39:07 -0500[diff] [blame]44
45 operating-points = <
46 /* kHz uV */
47 1000000 1060000
48 1176000 1160000
49 >;
R Sricharan6e58b8f2013-08-14 19:08:20 +0530[diff] [blame]50 };
51 cpu@1 {
52 device_type = "cpu";
53 compatible = "arm,cortex-a15";
54 reg = <1>;
55 };
56 };
57
58 timer {
59 compatible = "arm,armv7-timer";
60 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
61 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
62 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
63 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
64 };
65
66 gic: interrupt-controller@48211000 {
67 compatible = "arm,cortex-a15-gic";
68 interrupt-controller;
69 #interrupt-cells = <3>;
70 reg = <0x48211000 0x1000>,
71 <0x48212000 0x1000>,
72 <0x48214000 0x2000>,
73 <0x48216000 0x2000>;
74 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
75 };
76
77 /*
78 * The soc node represents the soc top level view. It is uses for IPs
79 * that are not memory mapped in the MPU view or for the MPU itself.
80 */
81 soc {
82 compatible = "ti,omap-infra";
83 mpu {
84 compatible = "ti,omap5-mpu";
85 ti,hwmods = "mpu";
86 };
87 };
88
89 /*
90 * XXX: Use a flat representation of the SOC interconnect.
91 * The real OMAP interconnect network is quite complex.
92 * Since that will not bring real advantage to represent that in DT for
93 * the moment, just use a fake OCP bus entry to represent the whole bus
94 * hierarchy.
95 */
96 ocp {
97 compatible = "ti,omap4-l3-noc", "simple-bus";
98 #address-cells = <1>;
99 #size-cells = <1>;
100 ranges;
101 ti,hwmods = "l3_main_1", "l3_main_2";
102 reg = <0x44000000 0x2000>,
103 <0x44800000 0x3000>;
104 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
105 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
106
Tero Kristoee6c7502013-07-18 17:18:33 +0300[diff] [blame]107 prm: prm@4ae06000 {
108 compatible = "ti,dra7-prm";
109 reg = <0x4ae06000 0x3000>;
110
111 prm_clocks: clocks {
112 #address-cells = <1>;
113 #size-cells = <0>;
114 };
115
116 prm_clockdomains: clockdomains {
117 };
118 };
119
120 cm_core_aon: cm_core_aon@4a005000 {
121 compatible = "ti,dra7-cm-core-aon";
122 reg = <0x4a005000 0x2000>;
123
124 cm_core_aon_clocks: clocks {
125 #address-cells = <1>;
126 #size-cells = <0>;
127 };
128
129 cm_core_aon_clockdomains: clockdomains {
130 };
131 };
132
133 cm_core: cm_core@4a008000 {
134 compatible = "ti,dra7-cm-core";
135 reg = <0x4a008000 0x3000>;
136
137 cm_core_clocks: clocks {
138 #address-cells = <1>;
139 #size-cells = <0>;
140 };
141
142 cm_core_clockdomains: clockdomains {
143 };
144 };
145
R Sricharan6e58b8f2013-08-14 19:08:20 +0530[diff] [blame]146 counter32k: counter@4ae04000 {
147 compatible = "ti,omap-counter32k";
148 reg = <0x4ae04000 0x40>;
149 ti,hwmods = "counter_32k";
150 };
151
152 dra7_pmx_core: pinmux@4a003400 {
153 compatible = "pinctrl-single";
154 reg = <0x4a003400 0x0464>;
155 #address-cells = <1>;
156 #size-cells = <0>;
157 pinctrl-single,register-width = <32>;
158 pinctrl-single,function-mask = <0x3fffffff>;
159 };
160
161 sdma: dma-controller@4a056000 {
162 compatible = "ti,omap4430-sdma";
163 reg = <0x4a056000 0x1000>;
164 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
165 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
166 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
167 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
168 #dma-cells = <1>;
169 #dma-channels = <32>;
170 #dma-requests = <127>;
171 };
172
173 gpio1: gpio@4ae10000 {
174 compatible = "ti,omap4-gpio";
175 reg = <0x4ae10000 0x200>;
176 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
177 ti,hwmods = "gpio1";
178 gpio-controller;
179 #gpio-cells = <2>;
180 interrupt-controller;
181 #interrupt-cells = <1>;
182 };
183
184 gpio2: gpio@48055000 {
185 compatible = "ti,omap4-gpio";
186 reg = <0x48055000 0x200>;
187 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
188 ti,hwmods = "gpio2";
189 gpio-controller;
190 #gpio-cells = <2>;
191 interrupt-controller;
192 #interrupt-cells = <1>;
193 };
194
195 gpio3: gpio@48057000 {
196 compatible = "ti,omap4-gpio";
197 reg = <0x48057000 0x200>;
198 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
199 ti,hwmods = "gpio3";
200 gpio-controller;
201 #gpio-cells = <2>;
202 interrupt-controller;
203 #interrupt-cells = <1>;
204 };
205
206 gpio4: gpio@48059000 {
207 compatible = "ti,omap4-gpio";
208 reg = <0x48059000 0x200>;
209 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
210 ti,hwmods = "gpio4";
211 gpio-controller;
212 #gpio-cells = <2>;
213 interrupt-controller;
214 #interrupt-cells = <1>;
215 };
216
217 gpio5: gpio@4805b000 {
218 compatible = "ti,omap4-gpio";
219 reg = <0x4805b000 0x200>;
220 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
221 ti,hwmods = "gpio5";
222 gpio-controller;
223 #gpio-cells = <2>;
224 interrupt-controller;
225 #interrupt-cells = <1>;
226 };
227
228 gpio6: gpio@4805d000 {
229 compatible = "ti,omap4-gpio";
230 reg = <0x4805d000 0x200>;
231 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
232 ti,hwmods = "gpio6";
233 gpio-controller;
234 #gpio-cells = <2>;
235 interrupt-controller;
236 #interrupt-cells = <1>;
237 };
238
239 gpio7: gpio@48051000 {
240 compatible = "ti,omap4-gpio";
241 reg = <0x48051000 0x200>;
242 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
243 ti,hwmods = "gpio7";
244 gpio-controller;
245 #gpio-cells = <2>;
246 interrupt-controller;
247 #interrupt-cells = <1>;
248 };
249
250 gpio8: gpio@48053000 {
251 compatible = "ti,omap4-gpio";
252 reg = <0x48053000 0x200>;
253 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
254 ti,hwmods = "gpio8";
255 gpio-controller;
256 #gpio-cells = <2>;
257 interrupt-controller;
258 #interrupt-cells = <1>;
259 };
260
261 uart1: serial@4806a000 {
262 compatible = "ti,omap4-uart";
263 reg = <0x4806a000 0x100>;
264 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
265 ti,hwmods = "uart1";
266 clock-frequency = <48000000>;
267 status = "disabled";
268 };
269
270 uart2: serial@4806c000 {
271 compatible = "ti,omap4-uart";
272 reg = <0x4806c000 0x100>;
273 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
274 ti,hwmods = "uart2";
275 clock-frequency = <48000000>;
276 status = "disabled";
277 };
278
279 uart3: serial@48020000 {
280 compatible = "ti,omap4-uart";
281 reg = <0x48020000 0x100>;
282 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
283 ti,hwmods = "uart3";
284 clock-frequency = <48000000>;
285 status = "disabled";
286 };
287
288 uart4: serial@4806e000 {
289 compatible = "ti,omap4-uart";
290 reg = <0x4806e000 0x100>;
291 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
292 ti,hwmods = "uart4";
293 clock-frequency = <48000000>;
294 status = "disabled";
295 };
296
297 uart5: serial@48066000 {
298 compatible = "ti,omap4-uart";
299 reg = <0x48066000 0x100>;
300 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
301 ti,hwmods = "uart5";
302 clock-frequency = <48000000>;
303 status = "disabled";
304 };
305
306 uart6: serial@48068000 {
307 compatible = "ti,omap4-uart";
308 reg = <0x48068000 0x100>;
309 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
310 ti,hwmods = "uart6";
311 clock-frequency = <48000000>;
312 status = "disabled";
313 };
314
315 uart7: serial@48420000 {
316 compatible = "ti,omap4-uart";
317 reg = <0x48420000 0x100>;
318 ti,hwmods = "uart7";
319 clock-frequency = <48000000>;
320 status = "disabled";
321 };
322
323 uart8: serial@48422000 {
324 compatible = "ti,omap4-uart";
325 reg = <0x48422000 0x100>;
326 ti,hwmods = "uart8";
327 clock-frequency = <48000000>;
328 status = "disabled";
329 };
330
331 uart9: serial@48424000 {
332 compatible = "ti,omap4-uart";
333 reg = <0x48424000 0x100>;
334 ti,hwmods = "uart9";
335 clock-frequency = <48000000>;
336 status = "disabled";
337 };
338
339 uart10: serial@4ae2b000 {
340 compatible = "ti,omap4-uart";
341 reg = <0x4ae2b000 0x100>;
342 ti,hwmods = "uart10";
343 clock-frequency = <48000000>;
344 status = "disabled";
345 };
346
347 timer1: timer@4ae18000 {
348 compatible = "ti,omap5430-timer";
349 reg = <0x4ae18000 0x80>;
350 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
351 ti,hwmods = "timer1";
352 ti,timer-alwon;
353 };
354
355 timer2: timer@48032000 {
356 compatible = "ti,omap5430-timer";
357 reg = <0x48032000 0x80>;
358 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
359 ti,hwmods = "timer2";
360 };
361
362 timer3: timer@48034000 {
363 compatible = "ti,omap5430-timer";
364 reg = <0x48034000 0x80>;
365 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
366 ti,hwmods = "timer3";
367 };
368
369 timer4: timer@48036000 {
370 compatible = "ti,omap5430-timer";
371 reg = <0x48036000 0x80>;
372 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
373 ti,hwmods = "timer4";
374 };
375
376 timer5: timer@48820000 {
377 compatible = "ti,omap5430-timer";
378 reg = <0x48820000 0x80>;
379 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
380 ti,hwmods = "timer5";
381 ti,timer-dsp;
382 };
383
384 timer6: timer@48822000 {
385 compatible = "ti,omap5430-timer";
386 reg = <0x48822000 0x80>;
387 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
388 ti,hwmods = "timer6";
389 ti,timer-dsp;
390 ti,timer-pwm;
391 };
392
393 timer7: timer@48824000 {
394 compatible = "ti,omap5430-timer";
395 reg = <0x48824000 0x80>;
396 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
397 ti,hwmods = "timer7";
398 ti,timer-dsp;
399 };
400
401 timer8: timer@48826000 {
402 compatible = "ti,omap5430-timer";
403 reg = <0x48826000 0x80>;
404 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
405 ti,hwmods = "timer8";
406 ti,timer-dsp;
407 ti,timer-pwm;
408 };
409
410 timer9: timer@4803e000 {
411 compatible = "ti,omap5430-timer";
412 reg = <0x4803e000 0x80>;
413 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
414 ti,hwmods = "timer9";
415 };
416
417 timer10: timer@48086000 {
418 compatible = "ti,omap5430-timer";
419 reg = <0x48086000 0x80>;
420 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
421 ti,hwmods = "timer10";
422 };
423
424 timer11: timer@48088000 {
425 compatible = "ti,omap5430-timer";
426 reg = <0x48088000 0x80>;
427 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
428 ti,hwmods = "timer11";
429 ti,timer-pwm;
430 };
431
432 timer13: timer@48828000 {
433 compatible = "ti,omap5430-timer";
434 reg = <0x48828000 0x80>;
435 ti,hwmods = "timer13";
436 status = "disabled";
437 };
438
439 timer14: timer@4882a000 {
440 compatible = "ti,omap5430-timer";
441 reg = <0x4882a000 0x80>;
442 ti,hwmods = "timer14";
443 status = "disabled";
444 };
445
446 timer15: timer@4882c000 {
447 compatible = "ti,omap5430-timer";
448 reg = <0x4882c000 0x80>;
449 ti,hwmods = "timer15";
450 status = "disabled";
451 };
452
453 timer16: timer@4882e000 {
454 compatible = "ti,omap5430-timer";
455 reg = <0x4882e000 0x80>;
456 ti,hwmods = "timer16";
457 status = "disabled";
458 };
459
460 wdt2: wdt@4ae14000 {
461 compatible = "ti,omap4-wdt";
462 reg = <0x4ae14000 0x80>;
463 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
464 ti,hwmods = "wd_timer2";
465 };
466
Suman Annadbd7c192014-01-13 18:26:46 -0600[diff] [blame^]467 hwspinlock: spinlock@4a0f6000 {
468 compatible = "ti,omap4-hwspinlock";
469 reg = <0x4a0f6000 0x1000>;
470 ti,hwmods = "spinlock";
471 #hwlock-cells = <1>;
472 };
473
R Sricharan6e58b8f2013-08-14 19:08:20 +0530[diff] [blame]474 i2c1: i2c@48070000 {
475 compatible = "ti,omap4-i2c";
476 reg = <0x48070000 0x100>;
477 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
478 #address-cells = <1>;
479 #size-cells = <0>;
480 ti,hwmods = "i2c1";
481 status = "disabled";
482 };
483
484 i2c2: i2c@48072000 {
485 compatible = "ti,omap4-i2c";
486 reg = <0x48072000 0x100>;
487 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
488 #address-cells = <1>;
489 #size-cells = <0>;
490 ti,hwmods = "i2c2";
491 status = "disabled";
492 };
493
494 i2c3: i2c@48060000 {
495 compatible = "ti,omap4-i2c";
496 reg = <0x48060000 0x100>;
497 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
498 #address-cells = <1>;
499 #size-cells = <0>;
500 ti,hwmods = "i2c3";
501 status = "disabled";
502 };
503
504 i2c4: i2c@4807a000 {
505 compatible = "ti,omap4-i2c";
506 reg = <0x4807a000 0x100>;
507 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
508 #address-cells = <1>;
509 #size-cells = <0>;
510 ti,hwmods = "i2c4";
511 status = "disabled";
512 };
513
514 i2c5: i2c@4807c000 {
515 compatible = "ti,omap4-i2c";
516 reg = <0x4807c000 0x100>;
517 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
518 #address-cells = <1>;
519 #size-cells = <0>;
520 ti,hwmods = "i2c5";
521 status = "disabled";
522 };
523
524 mmc1: mmc@4809c000 {
525 compatible = "ti,omap4-hsmmc";
526 reg = <0x4809c000 0x400>;
527 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
528 ti,hwmods = "mmc1";
529 ti,dual-volt;
530 ti,needs-special-reset;
531 dmas = <&sdma 61>, <&sdma 62>;
532 dma-names = "tx", "rx";
533 status = "disabled";
534 };
535
536 mmc2: mmc@480b4000 {
537 compatible = "ti,omap4-hsmmc";
538 reg = <0x480b4000 0x400>;
539 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
540 ti,hwmods = "mmc2";
541 ti,needs-special-reset;
542 dmas = <&sdma 47>, <&sdma 48>;
543 dma-names = "tx", "rx";
544 status = "disabled";
545 };
546
547 mmc3: mmc@480ad000 {
548 compatible = "ti,omap4-hsmmc";
549 reg = <0x480ad000 0x400>;
550 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
551 ti,hwmods = "mmc3";
552 ti,needs-special-reset;
553 dmas = <&sdma 77>, <&sdma 78>;
554 dma-names = "tx", "rx";
555 status = "disabled";
556 };
557
558 mmc4: mmc@480d1000 {
559 compatible = "ti,omap4-hsmmc";
560 reg = <0x480d1000 0x400>;
561 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
562 ti,hwmods = "mmc4";
563 ti,needs-special-reset;
564 dmas = <&sdma 57>, <&sdma 58>;
565 dma-names = "tx", "rx";
566 status = "disabled";
567 };
568
569 mcspi1: spi@48098000 {
570 compatible = "ti,omap4-mcspi";
571 reg = <0x48098000 0x200>;
572 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
573 #address-cells = <1>;
574 #size-cells = <0>;
575 ti,hwmods = "mcspi1";
576 ti,spi-num-cs = <4>;
577 dmas = <&sdma 35>,
578 <&sdma 36>,
579 <&sdma 37>,
580 <&sdma 38>,
581 <&sdma 39>,
582 <&sdma 40>,
583 <&sdma 41>,
584 <&sdma 42>;
585 dma-names = "tx0", "rx0", "tx1", "rx1",
586 "tx2", "rx2", "tx3", "rx3";
587 status = "disabled";
588 };
589
590 mcspi2: spi@4809a000 {
591 compatible = "ti,omap4-mcspi";
592 reg = <0x4809a000 0x200>;
593 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
594 #address-cells = <1>;
595 #size-cells = <0>;
596 ti,hwmods = "mcspi2";
597 ti,spi-num-cs = <2>;
598 dmas = <&sdma 43>,
599 <&sdma 44>,
600 <&sdma 45>,
601 <&sdma 46>;
602 dma-names = "tx0", "rx0", "tx1", "rx1";
603 status = "disabled";
604 };
605
606 mcspi3: spi@480b8000 {
607 compatible = "ti,omap4-mcspi";
608 reg = <0x480b8000 0x200>;
609 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
610 #address-cells = <1>;
611 #size-cells = <0>;
612 ti,hwmods = "mcspi3";
613 ti,spi-num-cs = <2>;
614 dmas = <&sdma 15>, <&sdma 16>;
615 dma-names = "tx0", "rx0";
616 status = "disabled";
617 };
618
619 mcspi4: spi@480ba000 {
620 compatible = "ti,omap4-mcspi";
621 reg = <0x480ba000 0x200>;
622 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
623 #address-cells = <1>;
624 #size-cells = <0>;
625 ti,hwmods = "mcspi4";
626 ti,spi-num-cs = <1>;
627 dmas = <&sdma 70>, <&sdma 71>;
628 dma-names = "tx0", "rx0";
629 status = "disabled";
630 };
631 };
632};
Tero Kristoee6c7502013-07-18 17:18:33 +0300[diff] [blame]633
634/include/ "dra7xx-clocks.dtsi"