Thomas Gleixner | ac1dc6b | 2019-06-03 07:44:49 +0200 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0-only |
Thierry Reding | 5b2b135 | 2017-11-07 19:15:56 +0100 | [diff] [blame] | 2 | /* |
| 3 | * Copyright (c) 2016-2017 NVIDIA Corporation |
| 4 | * |
| 5 | * Author: Thierry Reding <treding@nvidia.com> |
Thierry Reding | 5b2b135 | 2017-11-07 19:15:56 +0100 | [diff] [blame] | 6 | */ |
| 7 | |
| 8 | #include <linux/gpio/driver.h> |
| 9 | #include <linux/interrupt.h> |
| 10 | #include <linux/irq.h> |
| 11 | #include <linux/module.h> |
| 12 | #include <linux/of_device.h> |
| 13 | #include <linux/platform_device.h> |
| 14 | |
| 15 | #include <dt-bindings/gpio/tegra186-gpio.h> |
Mikko Perttunen | bac5c3b | 2018-06-20 15:54:03 +0300 | [diff] [blame] | 16 | #include <dt-bindings/gpio/tegra194-gpio.h> |
Thierry Reding | 5b2b135 | 2017-11-07 19:15:56 +0100 | [diff] [blame] | 17 | |
Thierry Reding | 22635ed | 2019-11-08 16:33:52 +0100 | [diff] [blame] | 18 | /* security registers */ |
| 19 | #define TEGRA186_GPIO_CTL_SCR 0x0c |
| 20 | #define TEGRA186_GPIO_CTL_SCR_SEC_WEN BIT(28) |
| 21 | #define TEGRA186_GPIO_CTL_SCR_SEC_REN BIT(27) |
| 22 | |
| 23 | #define TEGRA186_GPIO_INT_ROUTE_MAPPING(p, x) (0x14 + (p) * 0x20 + (x) * 4) |
| 24 | |
| 25 | /* control registers */ |
Thierry Reding | 5b2b135 | 2017-11-07 19:15:56 +0100 | [diff] [blame] | 26 | #define TEGRA186_GPIO_ENABLE_CONFIG 0x00 |
| 27 | #define TEGRA186_GPIO_ENABLE_CONFIG_ENABLE BIT(0) |
| 28 | #define TEGRA186_GPIO_ENABLE_CONFIG_OUT BIT(1) |
| 29 | #define TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_NONE (0x0 << 2) |
| 30 | #define TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_LEVEL (0x1 << 2) |
| 31 | #define TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_SINGLE_EDGE (0x2 << 2) |
| 32 | #define TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_DOUBLE_EDGE (0x3 << 2) |
| 33 | #define TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_MASK (0x3 << 2) |
| 34 | #define TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_LEVEL BIT(4) |
Thierry Reding | adce118 | 2019-11-08 16:33:53 +0100 | [diff] [blame] | 35 | #define TEGRA186_GPIO_ENABLE_CONFIG_DEBOUNCE BIT(5) |
Thierry Reding | 5b2b135 | 2017-11-07 19:15:56 +0100 | [diff] [blame] | 36 | #define TEGRA186_GPIO_ENABLE_CONFIG_INTERRUPT BIT(6) |
| 37 | |
| 38 | #define TEGRA186_GPIO_DEBOUNCE_CONTROL 0x04 |
| 39 | #define TEGRA186_GPIO_DEBOUNCE_CONTROL_THRESHOLD(x) ((x) & 0xff) |
| 40 | |
| 41 | #define TEGRA186_GPIO_INPUT 0x08 |
| 42 | #define TEGRA186_GPIO_INPUT_HIGH BIT(0) |
| 43 | |
| 44 | #define TEGRA186_GPIO_OUTPUT_CONTROL 0x0c |
| 45 | #define TEGRA186_GPIO_OUTPUT_CONTROL_FLOATED BIT(0) |
| 46 | |
| 47 | #define TEGRA186_GPIO_OUTPUT_VALUE 0x10 |
| 48 | #define TEGRA186_GPIO_OUTPUT_VALUE_HIGH BIT(0) |
| 49 | |
| 50 | #define TEGRA186_GPIO_INTERRUPT_CLEAR 0x14 |
| 51 | |
| 52 | #define TEGRA186_GPIO_INTERRUPT_STATUS(x) (0x100 + (x) * 4) |
| 53 | |
| 54 | struct tegra_gpio_port { |
| 55 | const char *name; |
Thierry Reding | 13a62a5 | 2019-11-08 16:33:51 +0100 | [diff] [blame] | 56 | unsigned int bank; |
| 57 | unsigned int port; |
Thierry Reding | 5b2b135 | 2017-11-07 19:15:56 +0100 | [diff] [blame] | 58 | unsigned int pins; |
Thierry Reding | 5b2b135 | 2017-11-07 19:15:56 +0100 | [diff] [blame] | 59 | }; |
| 60 | |
Thierry Reding | b64d6c9 | 2020-03-19 13:27:30 +0100 | [diff] [blame] | 61 | struct tegra186_pin_range { |
| 62 | unsigned int offset; |
| 63 | const char *group; |
| 64 | }; |
| 65 | |
Thierry Reding | 5b2b135 | 2017-11-07 19:15:56 +0100 | [diff] [blame] | 66 | struct tegra_gpio_soc { |
| 67 | const struct tegra_gpio_port *ports; |
| 68 | unsigned int num_ports; |
| 69 | const char *name; |
Thierry Reding | 2a36550 | 2019-10-02 16:45:02 +0200 | [diff] [blame] | 70 | unsigned int instance; |
Thierry Reding | b64d6c9 | 2020-03-19 13:27:30 +0100 | [diff] [blame] | 71 | |
| 72 | const struct tegra186_pin_range *pin_ranges; |
| 73 | unsigned int num_pin_ranges; |
| 74 | const char *pinmux; |
Thierry Reding | 5b2b135 | 2017-11-07 19:15:56 +0100 | [diff] [blame] | 75 | }; |
| 76 | |
| 77 | struct tegra_gpio { |
| 78 | struct gpio_chip gpio; |
| 79 | struct irq_chip intc; |
| 80 | unsigned int num_irq; |
| 81 | unsigned int *irq; |
| 82 | |
| 83 | const struct tegra_gpio_soc *soc; |
| 84 | |
Thierry Reding | 22635ed | 2019-11-08 16:33:52 +0100 | [diff] [blame] | 85 | void __iomem *secure; |
Thierry Reding | 5b2b135 | 2017-11-07 19:15:56 +0100 | [diff] [blame] | 86 | void __iomem *base; |
| 87 | }; |
| 88 | |
| 89 | static const struct tegra_gpio_port * |
| 90 | tegra186_gpio_get_port(struct tegra_gpio *gpio, unsigned int *pin) |
| 91 | { |
| 92 | unsigned int start = 0, i; |
| 93 | |
| 94 | for (i = 0; i < gpio->soc->num_ports; i++) { |
| 95 | const struct tegra_gpio_port *port = &gpio->soc->ports[i]; |
| 96 | |
| 97 | if (*pin >= start && *pin < start + port->pins) { |
| 98 | *pin -= start; |
| 99 | return port; |
| 100 | } |
| 101 | |
| 102 | start += port->pins; |
| 103 | } |
| 104 | |
| 105 | return NULL; |
| 106 | } |
| 107 | |
| 108 | static void __iomem *tegra186_gpio_get_base(struct tegra_gpio *gpio, |
| 109 | unsigned int pin) |
| 110 | { |
| 111 | const struct tegra_gpio_port *port; |
Thierry Reding | 13a62a5 | 2019-11-08 16:33:51 +0100 | [diff] [blame] | 112 | unsigned int offset; |
Thierry Reding | 5b2b135 | 2017-11-07 19:15:56 +0100 | [diff] [blame] | 113 | |
| 114 | port = tegra186_gpio_get_port(gpio, &pin); |
| 115 | if (!port) |
| 116 | return NULL; |
| 117 | |
Thierry Reding | 13a62a5 | 2019-11-08 16:33:51 +0100 | [diff] [blame] | 118 | offset = port->bank * 0x1000 + port->port * 0x200; |
| 119 | |
| 120 | return gpio->base + offset + pin * 0x20; |
Thierry Reding | 5b2b135 | 2017-11-07 19:15:56 +0100 | [diff] [blame] | 121 | } |
| 122 | |
| 123 | static int tegra186_gpio_get_direction(struct gpio_chip *chip, |
| 124 | unsigned int offset) |
| 125 | { |
| 126 | struct tegra_gpio *gpio = gpiochip_get_data(chip); |
| 127 | void __iomem *base; |
| 128 | u32 value; |
| 129 | |
| 130 | base = tegra186_gpio_get_base(gpio, offset); |
| 131 | if (WARN_ON(base == NULL)) |
| 132 | return -ENODEV; |
| 133 | |
| 134 | value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG); |
| 135 | if (value & TEGRA186_GPIO_ENABLE_CONFIG_OUT) |
Matti Vaittinen | e42615e | 2019-11-06 10:54:12 +0200 | [diff] [blame] | 136 | return GPIO_LINE_DIRECTION_OUT; |
Thierry Reding | 5b2b135 | 2017-11-07 19:15:56 +0100 | [diff] [blame] | 137 | |
Matti Vaittinen | e42615e | 2019-11-06 10:54:12 +0200 | [diff] [blame] | 138 | return GPIO_LINE_DIRECTION_IN; |
Thierry Reding | 5b2b135 | 2017-11-07 19:15:56 +0100 | [diff] [blame] | 139 | } |
| 140 | |
| 141 | static int tegra186_gpio_direction_input(struct gpio_chip *chip, |
| 142 | unsigned int offset) |
| 143 | { |
| 144 | struct tegra_gpio *gpio = gpiochip_get_data(chip); |
| 145 | void __iomem *base; |
| 146 | u32 value; |
| 147 | |
| 148 | base = tegra186_gpio_get_base(gpio, offset); |
| 149 | if (WARN_ON(base == NULL)) |
| 150 | return -ENODEV; |
| 151 | |
| 152 | value = readl(base + TEGRA186_GPIO_OUTPUT_CONTROL); |
| 153 | value |= TEGRA186_GPIO_OUTPUT_CONTROL_FLOATED; |
| 154 | writel(value, base + TEGRA186_GPIO_OUTPUT_CONTROL); |
| 155 | |
| 156 | value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG); |
| 157 | value |= TEGRA186_GPIO_ENABLE_CONFIG_ENABLE; |
| 158 | value &= ~TEGRA186_GPIO_ENABLE_CONFIG_OUT; |
| 159 | writel(value, base + TEGRA186_GPIO_ENABLE_CONFIG); |
| 160 | |
| 161 | return 0; |
| 162 | } |
| 163 | |
| 164 | static int tegra186_gpio_direction_output(struct gpio_chip *chip, |
| 165 | unsigned int offset, int level) |
| 166 | { |
| 167 | struct tegra_gpio *gpio = gpiochip_get_data(chip); |
| 168 | void __iomem *base; |
| 169 | u32 value; |
| 170 | |
| 171 | /* configure output level first */ |
| 172 | chip->set(chip, offset, level); |
| 173 | |
| 174 | base = tegra186_gpio_get_base(gpio, offset); |
| 175 | if (WARN_ON(base == NULL)) |
| 176 | return -EINVAL; |
| 177 | |
| 178 | /* set the direction */ |
| 179 | value = readl(base + TEGRA186_GPIO_OUTPUT_CONTROL); |
| 180 | value &= ~TEGRA186_GPIO_OUTPUT_CONTROL_FLOATED; |
| 181 | writel(value, base + TEGRA186_GPIO_OUTPUT_CONTROL); |
| 182 | |
| 183 | value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG); |
| 184 | value |= TEGRA186_GPIO_ENABLE_CONFIG_ENABLE; |
| 185 | value |= TEGRA186_GPIO_ENABLE_CONFIG_OUT; |
| 186 | writel(value, base + TEGRA186_GPIO_ENABLE_CONFIG); |
| 187 | |
| 188 | return 0; |
| 189 | } |
| 190 | |
| 191 | static int tegra186_gpio_get(struct gpio_chip *chip, unsigned int offset) |
| 192 | { |
| 193 | struct tegra_gpio *gpio = gpiochip_get_data(chip); |
| 194 | void __iomem *base; |
| 195 | u32 value; |
| 196 | |
| 197 | base = tegra186_gpio_get_base(gpio, offset); |
| 198 | if (WARN_ON(base == NULL)) |
| 199 | return -ENODEV; |
| 200 | |
| 201 | value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG); |
| 202 | if (value & TEGRA186_GPIO_ENABLE_CONFIG_OUT) |
| 203 | value = readl(base + TEGRA186_GPIO_OUTPUT_VALUE); |
| 204 | else |
| 205 | value = readl(base + TEGRA186_GPIO_INPUT); |
| 206 | |
| 207 | return value & BIT(0); |
| 208 | } |
| 209 | |
| 210 | static void tegra186_gpio_set(struct gpio_chip *chip, unsigned int offset, |
| 211 | int level) |
| 212 | { |
| 213 | struct tegra_gpio *gpio = gpiochip_get_data(chip); |
| 214 | void __iomem *base; |
| 215 | u32 value; |
| 216 | |
| 217 | base = tegra186_gpio_get_base(gpio, offset); |
| 218 | if (WARN_ON(base == NULL)) |
| 219 | return; |
| 220 | |
| 221 | value = readl(base + TEGRA186_GPIO_OUTPUT_VALUE); |
| 222 | if (level == 0) |
| 223 | value &= ~TEGRA186_GPIO_OUTPUT_VALUE_HIGH; |
| 224 | else |
| 225 | value |= TEGRA186_GPIO_OUTPUT_VALUE_HIGH; |
| 226 | |
| 227 | writel(value, base + TEGRA186_GPIO_OUTPUT_VALUE); |
| 228 | } |
| 229 | |
Thierry Reding | adce118 | 2019-11-08 16:33:53 +0100 | [diff] [blame] | 230 | static int tegra186_gpio_set_config(struct gpio_chip *chip, |
| 231 | unsigned int offset, |
| 232 | unsigned long config) |
| 233 | { |
| 234 | struct tegra_gpio *gpio = gpiochip_get_data(chip); |
| 235 | u32 debounce, value; |
| 236 | void __iomem *base; |
| 237 | |
| 238 | base = tegra186_gpio_get_base(gpio, offset); |
| 239 | if (base == NULL) |
| 240 | return -ENXIO; |
| 241 | |
| 242 | if (pinconf_to_config_param(config) != PIN_CONFIG_INPUT_DEBOUNCE) |
| 243 | return -ENOTSUPP; |
| 244 | |
| 245 | debounce = pinconf_to_config_argument(config); |
| 246 | |
| 247 | /* |
| 248 | * The Tegra186 GPIO controller supports a maximum of 255 ms debounce |
| 249 | * time. |
| 250 | */ |
| 251 | if (debounce > 255000) |
| 252 | return -EINVAL; |
| 253 | |
| 254 | debounce = DIV_ROUND_UP(debounce, USEC_PER_MSEC); |
| 255 | |
| 256 | value = TEGRA186_GPIO_DEBOUNCE_CONTROL_THRESHOLD(debounce); |
| 257 | writel(value, base + TEGRA186_GPIO_DEBOUNCE_CONTROL); |
| 258 | |
| 259 | value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG); |
| 260 | value |= TEGRA186_GPIO_ENABLE_CONFIG_DEBOUNCE; |
| 261 | writel(value, base + TEGRA186_GPIO_ENABLE_CONFIG); |
| 262 | |
| 263 | return 0; |
| 264 | } |
| 265 | |
Thierry Reding | b64d6c9 | 2020-03-19 13:27:30 +0100 | [diff] [blame] | 266 | static int tegra186_gpio_add_pin_ranges(struct gpio_chip *chip) |
| 267 | { |
| 268 | struct tegra_gpio *gpio = gpiochip_get_data(chip); |
| 269 | struct pinctrl_dev *pctldev; |
| 270 | struct device_node *np; |
| 271 | unsigned int i, j; |
| 272 | int err; |
| 273 | |
| 274 | if (!gpio->soc->pinmux || gpio->soc->num_pin_ranges == 0) |
| 275 | return 0; |
| 276 | |
| 277 | np = of_find_compatible_node(NULL, NULL, gpio->soc->pinmux); |
| 278 | if (!np) |
| 279 | return -ENODEV; |
| 280 | |
| 281 | pctldev = of_pinctrl_get(np); |
| 282 | of_node_put(np); |
| 283 | if (!pctldev) |
| 284 | return -EPROBE_DEFER; |
| 285 | |
| 286 | for (i = 0; i < gpio->soc->num_pin_ranges; i++) { |
| 287 | unsigned int pin = gpio->soc->pin_ranges[i].offset, port; |
| 288 | const char *group = gpio->soc->pin_ranges[i].group; |
| 289 | |
| 290 | port = pin / 8; |
| 291 | pin = pin % 8; |
| 292 | |
| 293 | if (port >= gpio->soc->num_ports) { |
| 294 | dev_warn(chip->parent, "invalid port %u for %s\n", |
| 295 | port, group); |
| 296 | continue; |
| 297 | } |
| 298 | |
| 299 | for (j = 0; j < port; j++) |
| 300 | pin += gpio->soc->ports[j].pins; |
| 301 | |
| 302 | err = gpiochip_add_pingroup_range(chip, pctldev, pin, group); |
| 303 | if (err < 0) |
| 304 | return err; |
| 305 | } |
| 306 | |
| 307 | return 0; |
| 308 | } |
| 309 | |
Thierry Reding | 5b2b135 | 2017-11-07 19:15:56 +0100 | [diff] [blame] | 310 | static int tegra186_gpio_of_xlate(struct gpio_chip *chip, |
| 311 | const struct of_phandle_args *spec, |
| 312 | u32 *flags) |
| 313 | { |
| 314 | struct tegra_gpio *gpio = gpiochip_get_data(chip); |
| 315 | unsigned int port, pin, i, offset = 0; |
| 316 | |
| 317 | if (WARN_ON(chip->of_gpio_n_cells < 2)) |
| 318 | return -EINVAL; |
| 319 | |
| 320 | if (WARN_ON(spec->args_count < chip->of_gpio_n_cells)) |
| 321 | return -EINVAL; |
| 322 | |
| 323 | port = spec->args[0] / 8; |
| 324 | pin = spec->args[0] % 8; |
| 325 | |
| 326 | if (port >= gpio->soc->num_ports) { |
| 327 | dev_err(chip->parent, "invalid port number: %u\n", port); |
| 328 | return -EINVAL; |
| 329 | } |
| 330 | |
| 331 | for (i = 0; i < port; i++) |
| 332 | offset += gpio->soc->ports[i].pins; |
| 333 | |
| 334 | if (flags) |
| 335 | *flags = spec->args[1]; |
| 336 | |
| 337 | return offset + pin; |
| 338 | } |
| 339 | |
| 340 | static void tegra186_irq_ack(struct irq_data *data) |
| 341 | { |
| 342 | struct tegra_gpio *gpio = irq_data_get_irq_chip_data(data); |
| 343 | void __iomem *base; |
| 344 | |
| 345 | base = tegra186_gpio_get_base(gpio, data->hwirq); |
| 346 | if (WARN_ON(base == NULL)) |
| 347 | return; |
| 348 | |
| 349 | writel(1, base + TEGRA186_GPIO_INTERRUPT_CLEAR); |
| 350 | } |
| 351 | |
| 352 | static void tegra186_irq_mask(struct irq_data *data) |
| 353 | { |
| 354 | struct tegra_gpio *gpio = irq_data_get_irq_chip_data(data); |
| 355 | void __iomem *base; |
| 356 | u32 value; |
| 357 | |
| 358 | base = tegra186_gpio_get_base(gpio, data->hwirq); |
| 359 | if (WARN_ON(base == NULL)) |
| 360 | return; |
| 361 | |
| 362 | value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG); |
| 363 | value &= ~TEGRA186_GPIO_ENABLE_CONFIG_INTERRUPT; |
| 364 | writel(value, base + TEGRA186_GPIO_ENABLE_CONFIG); |
| 365 | } |
| 366 | |
| 367 | static void tegra186_irq_unmask(struct irq_data *data) |
| 368 | { |
| 369 | struct tegra_gpio *gpio = irq_data_get_irq_chip_data(data); |
| 370 | void __iomem *base; |
| 371 | u32 value; |
| 372 | |
| 373 | base = tegra186_gpio_get_base(gpio, data->hwirq); |
| 374 | if (WARN_ON(base == NULL)) |
| 375 | return; |
| 376 | |
| 377 | value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG); |
| 378 | value |= TEGRA186_GPIO_ENABLE_CONFIG_INTERRUPT; |
| 379 | writel(value, base + TEGRA186_GPIO_ENABLE_CONFIG); |
| 380 | } |
| 381 | |
Thierry Reding | 3a2fa90 | 2018-11-29 18:03:10 +0100 | [diff] [blame] | 382 | static int tegra186_irq_set_type(struct irq_data *data, unsigned int type) |
Thierry Reding | 5b2b135 | 2017-11-07 19:15:56 +0100 | [diff] [blame] | 383 | { |
| 384 | struct tegra_gpio *gpio = irq_data_get_irq_chip_data(data); |
| 385 | void __iomem *base; |
| 386 | u32 value; |
| 387 | |
| 388 | base = tegra186_gpio_get_base(gpio, data->hwirq); |
| 389 | if (WARN_ON(base == NULL)) |
| 390 | return -ENODEV; |
| 391 | |
| 392 | value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG); |
| 393 | value &= ~TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_MASK; |
| 394 | value &= ~TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_LEVEL; |
| 395 | |
Thierry Reding | 3a2fa90 | 2018-11-29 18:03:10 +0100 | [diff] [blame] | 396 | switch (type & IRQ_TYPE_SENSE_MASK) { |
Thierry Reding | 5b2b135 | 2017-11-07 19:15:56 +0100 | [diff] [blame] | 397 | case IRQ_TYPE_NONE: |
| 398 | break; |
| 399 | |
| 400 | case IRQ_TYPE_EDGE_RISING: |
| 401 | value |= TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_SINGLE_EDGE; |
| 402 | value |= TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_LEVEL; |
| 403 | break; |
| 404 | |
| 405 | case IRQ_TYPE_EDGE_FALLING: |
| 406 | value |= TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_SINGLE_EDGE; |
| 407 | break; |
| 408 | |
| 409 | case IRQ_TYPE_EDGE_BOTH: |
| 410 | value |= TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_DOUBLE_EDGE; |
| 411 | break; |
| 412 | |
| 413 | case IRQ_TYPE_LEVEL_HIGH: |
| 414 | value |= TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_LEVEL; |
| 415 | value |= TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_LEVEL; |
| 416 | break; |
| 417 | |
| 418 | case IRQ_TYPE_LEVEL_LOW: |
| 419 | value |= TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_LEVEL; |
| 420 | break; |
| 421 | |
| 422 | default: |
| 423 | return -EINVAL; |
| 424 | } |
| 425 | |
| 426 | writel(value, base + TEGRA186_GPIO_ENABLE_CONFIG); |
| 427 | |
Thierry Reding | 3a2fa90 | 2018-11-29 18:03:10 +0100 | [diff] [blame] | 428 | if ((type & IRQ_TYPE_EDGE_BOTH) == 0) |
Thierry Reding | 5b2b135 | 2017-11-07 19:15:56 +0100 | [diff] [blame] | 429 | irq_set_handler_locked(data, handle_level_irq); |
| 430 | else |
| 431 | irq_set_handler_locked(data, handle_edge_irq); |
| 432 | |
Marc Zyngier | 986ec63 | 2020-10-05 10:27:27 +0100 | [diff] [blame] | 433 | if (data->parent_data) |
| 434 | return irq_chip_set_type_parent(data, type); |
| 435 | |
| 436 | return 0; |
| 437 | } |
| 438 | |
| 439 | static int tegra186_irq_set_wake(struct irq_data *data, unsigned int on) |
| 440 | { |
| 441 | if (data->parent_data) |
| 442 | return irq_chip_set_wake_parent(data, on); |
| 443 | |
| 444 | return 0; |
Thierry Reding | 5b2b135 | 2017-11-07 19:15:56 +0100 | [diff] [blame] | 445 | } |
| 446 | |
| 447 | static void tegra186_gpio_irq(struct irq_desc *desc) |
| 448 | { |
| 449 | struct tegra_gpio *gpio = irq_desc_get_handler_data(desc); |
| 450 | struct irq_domain *domain = gpio->gpio.irq.domain; |
| 451 | struct irq_chip *chip = irq_desc_get_chip(desc); |
| 452 | unsigned int parent = irq_desc_get_irq(desc); |
| 453 | unsigned int i, offset = 0; |
| 454 | |
| 455 | chained_irq_enter(chip, desc); |
| 456 | |
| 457 | for (i = 0; i < gpio->soc->num_ports; i++) { |
| 458 | const struct tegra_gpio_port *port = &gpio->soc->ports[i]; |
Marc Zyngier | dbd1c54 | 2021-05-04 17:42:18 +0100 | [diff] [blame^] | 459 | unsigned int pin; |
Thierry Reding | 5b2b135 | 2017-11-07 19:15:56 +0100 | [diff] [blame] | 460 | unsigned long value; |
Thierry Reding | 13a62a5 | 2019-11-08 16:33:51 +0100 | [diff] [blame] | 461 | void __iomem *base; |
Thierry Reding | 5b2b135 | 2017-11-07 19:15:56 +0100 | [diff] [blame] | 462 | |
Thierry Reding | 13a62a5 | 2019-11-08 16:33:51 +0100 | [diff] [blame] | 463 | base = gpio->base + port->bank * 0x1000 + port->port * 0x200; |
| 464 | |
| 465 | /* skip ports that are not associated with this bank */ |
| 466 | if (parent != gpio->irq[port->bank]) |
Thierry Reding | 5b2b135 | 2017-11-07 19:15:56 +0100 | [diff] [blame] | 467 | goto skip; |
| 468 | |
| 469 | value = readl(base + TEGRA186_GPIO_INTERRUPT_STATUS(1)); |
| 470 | |
| 471 | for_each_set_bit(pin, &value, port->pins) { |
Marc Zyngier | dbd1c54 | 2021-05-04 17:42:18 +0100 | [diff] [blame^] | 472 | int ret = generic_handle_domain_irq(domain, offset + pin); |
| 473 | WARN_RATELIMIT(ret, "hwirq = %d", offset + pin); |
Thierry Reding | 5b2b135 | 2017-11-07 19:15:56 +0100 | [diff] [blame] | 474 | } |
| 475 | |
| 476 | skip: |
| 477 | offset += port->pins; |
| 478 | } |
| 479 | |
| 480 | chained_irq_exit(chip, desc); |
| 481 | } |
| 482 | |
Thierry Reding | 2a36550 | 2019-10-02 16:45:02 +0200 | [diff] [blame] | 483 | static int tegra186_gpio_irq_domain_translate(struct irq_domain *domain, |
| 484 | struct irq_fwspec *fwspec, |
| 485 | unsigned long *hwirq, |
| 486 | unsigned int *type) |
Thierry Reding | 5b2b135 | 2017-11-07 19:15:56 +0100 | [diff] [blame] | 487 | { |
| 488 | struct tegra_gpio *gpio = gpiochip_get_data(domain->host_data); |
| 489 | unsigned int port, pin, i, offset = 0; |
| 490 | |
Thierry Reding | 2a36550 | 2019-10-02 16:45:02 +0200 | [diff] [blame] | 491 | if (WARN_ON(gpio->gpio.of_gpio_n_cells < 2)) |
Thierry Reding | 5b2b135 | 2017-11-07 19:15:56 +0100 | [diff] [blame] | 492 | return -EINVAL; |
| 493 | |
Thierry Reding | 2a36550 | 2019-10-02 16:45:02 +0200 | [diff] [blame] | 494 | if (WARN_ON(fwspec->param_count < gpio->gpio.of_gpio_n_cells)) |
Thierry Reding | 5b2b135 | 2017-11-07 19:15:56 +0100 | [diff] [blame] | 495 | return -EINVAL; |
Thierry Reding | 2a36550 | 2019-10-02 16:45:02 +0200 | [diff] [blame] | 496 | |
| 497 | port = fwspec->param[0] / 8; |
| 498 | pin = fwspec->param[0] % 8; |
| 499 | |
| 500 | if (port >= gpio->soc->num_ports) |
| 501 | return -EINVAL; |
Thierry Reding | 5b2b135 | 2017-11-07 19:15:56 +0100 | [diff] [blame] | 502 | |
| 503 | for (i = 0; i < port; i++) |
| 504 | offset += gpio->soc->ports[i].pins; |
| 505 | |
Thierry Reding | 2a36550 | 2019-10-02 16:45:02 +0200 | [diff] [blame] | 506 | *type = fwspec->param[1] & IRQ_TYPE_SENSE_MASK; |
Thierry Reding | 5b2b135 | 2017-11-07 19:15:56 +0100 | [diff] [blame] | 507 | *hwirq = offset + pin; |
| 508 | |
| 509 | return 0; |
| 510 | } |
| 511 | |
Kevin Hao | 2425876 | 2020-01-14 16:28:19 +0800 | [diff] [blame] | 512 | static void *tegra186_gpio_populate_parent_fwspec(struct gpio_chip *chip, |
Thierry Reding | 2a36550 | 2019-10-02 16:45:02 +0200 | [diff] [blame] | 513 | unsigned int parent_hwirq, |
| 514 | unsigned int parent_type) |
| 515 | { |
| 516 | struct tegra_gpio *gpio = gpiochip_get_data(chip); |
Kevin Hao | 2425876 | 2020-01-14 16:28:19 +0800 | [diff] [blame] | 517 | struct irq_fwspec *fwspec; |
Thierry Reding | 2a36550 | 2019-10-02 16:45:02 +0200 | [diff] [blame] | 518 | |
Kevin Hao | 2425876 | 2020-01-14 16:28:19 +0800 | [diff] [blame] | 519 | fwspec = kmalloc(sizeof(*fwspec), GFP_KERNEL); |
| 520 | if (!fwspec) |
| 521 | return NULL; |
| 522 | |
| 523 | fwspec->fwnode = chip->irq.parent_domain->fwnode; |
Thierry Reding | 2a36550 | 2019-10-02 16:45:02 +0200 | [diff] [blame] | 524 | fwspec->param_count = 3; |
| 525 | fwspec->param[0] = gpio->soc->instance; |
| 526 | fwspec->param[1] = parent_hwirq; |
| 527 | fwspec->param[2] = parent_type; |
Kevin Hao | 2425876 | 2020-01-14 16:28:19 +0800 | [diff] [blame] | 528 | |
| 529 | return fwspec; |
Thierry Reding | 2a36550 | 2019-10-02 16:45:02 +0200 | [diff] [blame] | 530 | } |
| 531 | |
| 532 | static int tegra186_gpio_child_to_parent_hwirq(struct gpio_chip *chip, |
| 533 | unsigned int hwirq, |
| 534 | unsigned int type, |
| 535 | unsigned int *parent_hwirq, |
| 536 | unsigned int *parent_type) |
| 537 | { |
| 538 | *parent_hwirq = chip->irq.child_offset_to_irq(chip, hwirq); |
| 539 | *parent_type = type; |
| 540 | |
| 541 | return 0; |
| 542 | } |
| 543 | |
| 544 | static unsigned int tegra186_gpio_child_offset_to_irq(struct gpio_chip *chip, |
| 545 | unsigned int offset) |
| 546 | { |
| 547 | struct tegra_gpio *gpio = gpiochip_get_data(chip); |
| 548 | unsigned int i; |
| 549 | |
| 550 | for (i = 0; i < gpio->soc->num_ports; i++) { |
| 551 | if (offset < gpio->soc->ports[i].pins) |
| 552 | break; |
| 553 | |
| 554 | offset -= gpio->soc->ports[i].pins; |
| 555 | } |
| 556 | |
| 557 | return offset + i * 8; |
| 558 | } |
| 559 | |
| 560 | static const struct of_device_id tegra186_pmc_of_match[] = { |
| 561 | { .compatible = "nvidia,tegra186-pmc" }, |
| 562 | { .compatible = "nvidia,tegra194-pmc" }, |
| 563 | { /* sentinel */ } |
Thierry Reding | 5b2b135 | 2017-11-07 19:15:56 +0100 | [diff] [blame] | 564 | }; |
| 565 | |
Thierry Reding | 22635ed | 2019-11-08 16:33:52 +0100 | [diff] [blame] | 566 | static void tegra186_gpio_init_route_mapping(struct tegra_gpio *gpio) |
| 567 | { |
| 568 | unsigned int i, j; |
| 569 | u32 value; |
| 570 | |
| 571 | for (i = 0; i < gpio->soc->num_ports; i++) { |
| 572 | const struct tegra_gpio_port *port = &gpio->soc->ports[i]; |
| 573 | unsigned int offset, p = port->port; |
| 574 | void __iomem *base; |
| 575 | |
| 576 | base = gpio->secure + port->bank * 0x1000 + 0x800; |
| 577 | |
| 578 | value = readl(base + TEGRA186_GPIO_CTL_SCR); |
| 579 | |
| 580 | /* |
| 581 | * For controllers that haven't been locked down yet, make |
| 582 | * sure to program the default interrupt route mapping. |
| 583 | */ |
| 584 | if ((value & TEGRA186_GPIO_CTL_SCR_SEC_REN) == 0 && |
| 585 | (value & TEGRA186_GPIO_CTL_SCR_SEC_WEN) == 0) { |
| 586 | for (j = 0; j < 8; j++) { |
| 587 | offset = TEGRA186_GPIO_INT_ROUTE_MAPPING(p, j); |
| 588 | |
| 589 | value = readl(base + offset); |
| 590 | value = BIT(port->pins) - 1; |
| 591 | writel(value, base + offset); |
| 592 | } |
| 593 | } |
| 594 | } |
| 595 | } |
| 596 | |
Thierry Reding | 5b2b135 | 2017-11-07 19:15:56 +0100 | [diff] [blame] | 597 | static int tegra186_gpio_probe(struct platform_device *pdev) |
| 598 | { |
| 599 | unsigned int i, j, offset; |
| 600 | struct gpio_irq_chip *irq; |
| 601 | struct tegra_gpio *gpio; |
Thierry Reding | 2a36550 | 2019-10-02 16:45:02 +0200 | [diff] [blame] | 602 | struct device_node *np; |
Thierry Reding | 5b2b135 | 2017-11-07 19:15:56 +0100 | [diff] [blame] | 603 | char **names; |
| 604 | int err; |
| 605 | |
| 606 | gpio = devm_kzalloc(&pdev->dev, sizeof(*gpio), GFP_KERNEL); |
| 607 | if (!gpio) |
| 608 | return -ENOMEM; |
| 609 | |
| 610 | gpio->soc = of_device_get_match_data(&pdev->dev); |
| 611 | |
Thierry Reding | 22635ed | 2019-11-08 16:33:52 +0100 | [diff] [blame] | 612 | gpio->secure = devm_platform_ioremap_resource_byname(pdev, "security"); |
| 613 | if (IS_ERR(gpio->secure)) |
| 614 | return PTR_ERR(gpio->secure); |
| 615 | |
Bartosz Golaszewski | cc4c831 | 2019-10-22 10:43:18 +0200 | [diff] [blame] | 616 | gpio->base = devm_platform_ioremap_resource_byname(pdev, "gpio"); |
Thierry Reding | 5b2b135 | 2017-11-07 19:15:56 +0100 | [diff] [blame] | 617 | if (IS_ERR(gpio->base)) |
| 618 | return PTR_ERR(gpio->base); |
| 619 | |
| 620 | err = platform_irq_count(pdev); |
| 621 | if (err < 0) |
| 622 | return err; |
| 623 | |
| 624 | gpio->num_irq = err; |
| 625 | |
| 626 | gpio->irq = devm_kcalloc(&pdev->dev, gpio->num_irq, sizeof(*gpio->irq), |
| 627 | GFP_KERNEL); |
| 628 | if (!gpio->irq) |
| 629 | return -ENOMEM; |
| 630 | |
| 631 | for (i = 0; i < gpio->num_irq; i++) { |
| 632 | err = platform_get_irq(pdev, i); |
| 633 | if (err < 0) |
| 634 | return err; |
| 635 | |
| 636 | gpio->irq[i] = err; |
| 637 | } |
| 638 | |
| 639 | gpio->gpio.label = gpio->soc->name; |
| 640 | gpio->gpio.parent = &pdev->dev; |
| 641 | |
Thierry Reding | b64d6c9 | 2020-03-19 13:27:30 +0100 | [diff] [blame] | 642 | gpio->gpio.request = gpiochip_generic_request; |
| 643 | gpio->gpio.free = gpiochip_generic_free; |
Thierry Reding | 5b2b135 | 2017-11-07 19:15:56 +0100 | [diff] [blame] | 644 | gpio->gpio.get_direction = tegra186_gpio_get_direction; |
| 645 | gpio->gpio.direction_input = tegra186_gpio_direction_input; |
| 646 | gpio->gpio.direction_output = tegra186_gpio_direction_output; |
Zheng Yongjun | 7de2e5f | 2021-01-08 17:23:55 +0800 | [diff] [blame] | 647 | gpio->gpio.get = tegra186_gpio_get; |
Thierry Reding | 5b2b135 | 2017-11-07 19:15:56 +0100 | [diff] [blame] | 648 | gpio->gpio.set = tegra186_gpio_set; |
Thierry Reding | adce118 | 2019-11-08 16:33:53 +0100 | [diff] [blame] | 649 | gpio->gpio.set_config = tegra186_gpio_set_config; |
Thierry Reding | b64d6c9 | 2020-03-19 13:27:30 +0100 | [diff] [blame] | 650 | gpio->gpio.add_pin_ranges = tegra186_gpio_add_pin_ranges; |
Thierry Reding | 5b2b135 | 2017-11-07 19:15:56 +0100 | [diff] [blame] | 651 | |
| 652 | gpio->gpio.base = -1; |
| 653 | |
| 654 | for (i = 0; i < gpio->soc->num_ports; i++) |
| 655 | gpio->gpio.ngpio += gpio->soc->ports[i].pins; |
| 656 | |
| 657 | names = devm_kcalloc(gpio->gpio.parent, gpio->gpio.ngpio, |
| 658 | sizeof(*names), GFP_KERNEL); |
| 659 | if (!names) |
| 660 | return -ENOMEM; |
| 661 | |
| 662 | for (i = 0, offset = 0; i < gpio->soc->num_ports; i++) { |
| 663 | const struct tegra_gpio_port *port = &gpio->soc->ports[i]; |
| 664 | char *name; |
| 665 | |
| 666 | for (j = 0; j < port->pins; j++) { |
| 667 | name = devm_kasprintf(gpio->gpio.parent, GFP_KERNEL, |
| 668 | "P%s.%02x", port->name, j); |
| 669 | if (!name) |
| 670 | return -ENOMEM; |
| 671 | |
| 672 | names[offset + j] = name; |
| 673 | } |
| 674 | |
| 675 | offset += port->pins; |
| 676 | } |
| 677 | |
| 678 | gpio->gpio.names = (const char * const *)names; |
| 679 | |
| 680 | gpio->gpio.of_node = pdev->dev.of_node; |
| 681 | gpio->gpio.of_gpio_n_cells = 2; |
| 682 | gpio->gpio.of_xlate = tegra186_gpio_of_xlate; |
| 683 | |
| 684 | gpio->intc.name = pdev->dev.of_node->name; |
| 685 | gpio->intc.irq_ack = tegra186_irq_ack; |
| 686 | gpio->intc.irq_mask = tegra186_irq_mask; |
| 687 | gpio->intc.irq_unmask = tegra186_irq_unmask; |
| 688 | gpio->intc.irq_set_type = tegra186_irq_set_type; |
Marc Zyngier | 986ec63 | 2020-10-05 10:27:27 +0100 | [diff] [blame] | 689 | gpio->intc.irq_set_wake = tegra186_irq_set_wake; |
Thierry Reding | 5b2b135 | 2017-11-07 19:15:56 +0100 | [diff] [blame] | 690 | |
| 691 | irq = &gpio->gpio.irq; |
| 692 | irq->chip = &gpio->intc; |
Thierry Reding | 2a36550 | 2019-10-02 16:45:02 +0200 | [diff] [blame] | 693 | irq->fwnode = of_node_to_fwnode(pdev->dev.of_node); |
| 694 | irq->child_to_parent_hwirq = tegra186_gpio_child_to_parent_hwirq; |
Kevin Hao | 2425876 | 2020-01-14 16:28:19 +0800 | [diff] [blame] | 695 | irq->populate_parent_alloc_arg = tegra186_gpio_populate_parent_fwspec; |
Thierry Reding | 2a36550 | 2019-10-02 16:45:02 +0200 | [diff] [blame] | 696 | irq->child_offset_to_irq = tegra186_gpio_child_offset_to_irq; |
| 697 | irq->child_irq_domain_ops.translate = tegra186_gpio_irq_domain_translate; |
Thierry Reding | 5b2b135 | 2017-11-07 19:15:56 +0100 | [diff] [blame] | 698 | irq->handler = handle_simple_irq; |
Thierry Reding | 5b2b135 | 2017-11-07 19:15:56 +0100 | [diff] [blame] | 699 | irq->default_type = IRQ_TYPE_NONE; |
| 700 | irq->parent_handler = tegra186_gpio_irq; |
| 701 | irq->parent_handler_data = gpio; |
| 702 | irq->num_parents = gpio->num_irq; |
| 703 | irq->parents = gpio->irq; |
| 704 | |
Thierry Reding | 2a36550 | 2019-10-02 16:45:02 +0200 | [diff] [blame] | 705 | np = of_find_matching_node(NULL, tegra186_pmc_of_match); |
| 706 | if (np) { |
| 707 | irq->parent_domain = irq_find_host(np); |
| 708 | of_node_put(np); |
| 709 | |
| 710 | if (!irq->parent_domain) |
| 711 | return -EPROBE_DEFER; |
| 712 | } |
| 713 | |
Thierry Reding | 22635ed | 2019-11-08 16:33:52 +0100 | [diff] [blame] | 714 | tegra186_gpio_init_route_mapping(gpio); |
| 715 | |
Thierry Reding | 5b2b135 | 2017-11-07 19:15:56 +0100 | [diff] [blame] | 716 | irq->map = devm_kcalloc(&pdev->dev, gpio->gpio.ngpio, |
| 717 | sizeof(*irq->map), GFP_KERNEL); |
| 718 | if (!irq->map) |
| 719 | return -ENOMEM; |
| 720 | |
| 721 | for (i = 0, offset = 0; i < gpio->soc->num_ports; i++) { |
| 722 | const struct tegra_gpio_port *port = &gpio->soc->ports[i]; |
| 723 | |
| 724 | for (j = 0; j < port->pins; j++) |
Thierry Reding | 13a62a5 | 2019-11-08 16:33:51 +0100 | [diff] [blame] | 725 | irq->map[offset + j] = irq->parents[port->bank]; |
Thierry Reding | 5b2b135 | 2017-11-07 19:15:56 +0100 | [diff] [blame] | 726 | |
| 727 | offset += port->pins; |
| 728 | } |
| 729 | |
Alexandru Ardelean | 6e15393 | 2021-05-15 10:59:05 +0300 | [diff] [blame] | 730 | return devm_gpiochip_add_data(&pdev->dev, &gpio->gpio, gpio); |
Thierry Reding | 5b2b135 | 2017-11-07 19:15:56 +0100 | [diff] [blame] | 731 | } |
| 732 | |
Thierry Reding | 13a62a5 | 2019-11-08 16:33:51 +0100 | [diff] [blame] | 733 | #define TEGRA186_MAIN_GPIO_PORT(_name, _bank, _port, _pins) \ |
| 734 | [TEGRA186_MAIN_GPIO_PORT_##_name] = { \ |
| 735 | .name = #_name, \ |
| 736 | .bank = _bank, \ |
| 737 | .port = _port, \ |
| 738 | .pins = _pins, \ |
Thierry Reding | 5b2b135 | 2017-11-07 19:15:56 +0100 | [diff] [blame] | 739 | } |
| 740 | |
| 741 | static const struct tegra_gpio_port tegra186_main_ports[] = { |
Thierry Reding | 13a62a5 | 2019-11-08 16:33:51 +0100 | [diff] [blame] | 742 | TEGRA186_MAIN_GPIO_PORT( A, 2, 0, 7), |
| 743 | TEGRA186_MAIN_GPIO_PORT( B, 3, 0, 7), |
| 744 | TEGRA186_MAIN_GPIO_PORT( C, 3, 1, 7), |
| 745 | TEGRA186_MAIN_GPIO_PORT( D, 3, 2, 6), |
| 746 | TEGRA186_MAIN_GPIO_PORT( E, 2, 1, 8), |
| 747 | TEGRA186_MAIN_GPIO_PORT( F, 2, 2, 6), |
| 748 | TEGRA186_MAIN_GPIO_PORT( G, 4, 1, 6), |
| 749 | TEGRA186_MAIN_GPIO_PORT( H, 1, 0, 7), |
| 750 | TEGRA186_MAIN_GPIO_PORT( I, 0, 4, 8), |
| 751 | TEGRA186_MAIN_GPIO_PORT( J, 5, 0, 8), |
| 752 | TEGRA186_MAIN_GPIO_PORT( K, 5, 1, 1), |
| 753 | TEGRA186_MAIN_GPIO_PORT( L, 1, 1, 8), |
| 754 | TEGRA186_MAIN_GPIO_PORT( M, 5, 3, 6), |
| 755 | TEGRA186_MAIN_GPIO_PORT( N, 0, 0, 7), |
| 756 | TEGRA186_MAIN_GPIO_PORT( O, 0, 1, 4), |
| 757 | TEGRA186_MAIN_GPIO_PORT( P, 4, 0, 7), |
| 758 | TEGRA186_MAIN_GPIO_PORT( Q, 0, 2, 6), |
| 759 | TEGRA186_MAIN_GPIO_PORT( R, 0, 5, 6), |
| 760 | TEGRA186_MAIN_GPIO_PORT( T, 0, 3, 4), |
| 761 | TEGRA186_MAIN_GPIO_PORT( X, 1, 2, 8), |
| 762 | TEGRA186_MAIN_GPIO_PORT( Y, 1, 3, 7), |
| 763 | TEGRA186_MAIN_GPIO_PORT(BB, 2, 3, 2), |
| 764 | TEGRA186_MAIN_GPIO_PORT(CC, 5, 2, 4), |
Thierry Reding | 5b2b135 | 2017-11-07 19:15:56 +0100 | [diff] [blame] | 765 | }; |
| 766 | |
| 767 | static const struct tegra_gpio_soc tegra186_main_soc = { |
| 768 | .num_ports = ARRAY_SIZE(tegra186_main_ports), |
| 769 | .ports = tegra186_main_ports, |
| 770 | .name = "tegra186-gpio", |
Thierry Reding | 2a36550 | 2019-10-02 16:45:02 +0200 | [diff] [blame] | 771 | .instance = 0, |
Thierry Reding | 5b2b135 | 2017-11-07 19:15:56 +0100 | [diff] [blame] | 772 | }; |
| 773 | |
Thierry Reding | 13a62a5 | 2019-11-08 16:33:51 +0100 | [diff] [blame] | 774 | #define TEGRA186_AON_GPIO_PORT(_name, _bank, _port, _pins) \ |
| 775 | [TEGRA186_AON_GPIO_PORT_##_name] = { \ |
| 776 | .name = #_name, \ |
| 777 | .bank = _bank, \ |
| 778 | .port = _port, \ |
| 779 | .pins = _pins, \ |
Thierry Reding | 5b2b135 | 2017-11-07 19:15:56 +0100 | [diff] [blame] | 780 | } |
| 781 | |
| 782 | static const struct tegra_gpio_port tegra186_aon_ports[] = { |
Thierry Reding | 13a62a5 | 2019-11-08 16:33:51 +0100 | [diff] [blame] | 783 | TEGRA186_AON_GPIO_PORT( S, 0, 1, 5), |
| 784 | TEGRA186_AON_GPIO_PORT( U, 0, 2, 6), |
| 785 | TEGRA186_AON_GPIO_PORT( V, 0, 4, 8), |
| 786 | TEGRA186_AON_GPIO_PORT( W, 0, 5, 8), |
| 787 | TEGRA186_AON_GPIO_PORT( Z, 0, 7, 4), |
| 788 | TEGRA186_AON_GPIO_PORT(AA, 0, 6, 8), |
| 789 | TEGRA186_AON_GPIO_PORT(EE, 0, 3, 3), |
| 790 | TEGRA186_AON_GPIO_PORT(FF, 0, 0, 5), |
Thierry Reding | 5b2b135 | 2017-11-07 19:15:56 +0100 | [diff] [blame] | 791 | }; |
| 792 | |
| 793 | static const struct tegra_gpio_soc tegra186_aon_soc = { |
| 794 | .num_ports = ARRAY_SIZE(tegra186_aon_ports), |
| 795 | .ports = tegra186_aon_ports, |
| 796 | .name = "tegra186-gpio-aon", |
Thierry Reding | 2a36550 | 2019-10-02 16:45:02 +0200 | [diff] [blame] | 797 | .instance = 1, |
Thierry Reding | 5b2b135 | 2017-11-07 19:15:56 +0100 | [diff] [blame] | 798 | }; |
| 799 | |
Thierry Reding | 13a62a5 | 2019-11-08 16:33:51 +0100 | [diff] [blame] | 800 | #define TEGRA194_MAIN_GPIO_PORT(_name, _bank, _port, _pins) \ |
| 801 | [TEGRA194_MAIN_GPIO_PORT_##_name] = { \ |
| 802 | .name = #_name, \ |
| 803 | .bank = _bank, \ |
| 804 | .port = _port, \ |
| 805 | .pins = _pins, \ |
Mikko Perttunen | bac5c3b | 2018-06-20 15:54:03 +0300 | [diff] [blame] | 806 | } |
| 807 | |
| 808 | static const struct tegra_gpio_port tegra194_main_ports[] = { |
Thierry Reding | 13a62a5 | 2019-11-08 16:33:51 +0100 | [diff] [blame] | 809 | TEGRA194_MAIN_GPIO_PORT( A, 1, 2, 8), |
| 810 | TEGRA194_MAIN_GPIO_PORT( B, 4, 7, 2), |
| 811 | TEGRA194_MAIN_GPIO_PORT( C, 4, 3, 8), |
| 812 | TEGRA194_MAIN_GPIO_PORT( D, 4, 4, 4), |
| 813 | TEGRA194_MAIN_GPIO_PORT( E, 4, 5, 8), |
| 814 | TEGRA194_MAIN_GPIO_PORT( F, 4, 6, 6), |
| 815 | TEGRA194_MAIN_GPIO_PORT( G, 4, 0, 8), |
| 816 | TEGRA194_MAIN_GPIO_PORT( H, 4, 1, 8), |
| 817 | TEGRA194_MAIN_GPIO_PORT( I, 4, 2, 5), |
| 818 | TEGRA194_MAIN_GPIO_PORT( J, 5, 1, 6), |
| 819 | TEGRA194_MAIN_GPIO_PORT( K, 3, 0, 8), |
| 820 | TEGRA194_MAIN_GPIO_PORT( L, 3, 1, 4), |
| 821 | TEGRA194_MAIN_GPIO_PORT( M, 2, 3, 8), |
| 822 | TEGRA194_MAIN_GPIO_PORT( N, 2, 4, 3), |
| 823 | TEGRA194_MAIN_GPIO_PORT( O, 5, 0, 6), |
| 824 | TEGRA194_MAIN_GPIO_PORT( P, 2, 5, 8), |
| 825 | TEGRA194_MAIN_GPIO_PORT( Q, 2, 6, 8), |
| 826 | TEGRA194_MAIN_GPIO_PORT( R, 2, 7, 6), |
| 827 | TEGRA194_MAIN_GPIO_PORT( S, 3, 3, 8), |
| 828 | TEGRA194_MAIN_GPIO_PORT( T, 3, 4, 8), |
| 829 | TEGRA194_MAIN_GPIO_PORT( U, 3, 5, 1), |
| 830 | TEGRA194_MAIN_GPIO_PORT( V, 1, 0, 8), |
| 831 | TEGRA194_MAIN_GPIO_PORT( W, 1, 1, 2), |
| 832 | TEGRA194_MAIN_GPIO_PORT( X, 2, 0, 8), |
| 833 | TEGRA194_MAIN_GPIO_PORT( Y, 2, 1, 8), |
| 834 | TEGRA194_MAIN_GPIO_PORT( Z, 2, 2, 8), |
| 835 | TEGRA194_MAIN_GPIO_PORT(FF, 3, 2, 2), |
| 836 | TEGRA194_MAIN_GPIO_PORT(GG, 0, 0, 2) |
Mikko Perttunen | bac5c3b | 2018-06-20 15:54:03 +0300 | [diff] [blame] | 837 | }; |
| 838 | |
Thierry Reding | ffa91e7 | 2020-03-19 13:27:31 +0100 | [diff] [blame] | 839 | static const struct tegra186_pin_range tegra194_main_pin_ranges[] = { |
| 840 | { TEGRA194_MAIN_GPIO(GG, 0), "pex_l5_clkreq_n_pgg0" }, |
| 841 | { TEGRA194_MAIN_GPIO(GG, 1), "pex_l5_rst_n_pgg1" }, |
| 842 | }; |
| 843 | |
Mikko Perttunen | bac5c3b | 2018-06-20 15:54:03 +0300 | [diff] [blame] | 844 | static const struct tegra_gpio_soc tegra194_main_soc = { |
| 845 | .num_ports = ARRAY_SIZE(tegra194_main_ports), |
| 846 | .ports = tegra194_main_ports, |
| 847 | .name = "tegra194-gpio", |
Thierry Reding | 2a36550 | 2019-10-02 16:45:02 +0200 | [diff] [blame] | 848 | .instance = 0, |
Thierry Reding | ffa91e7 | 2020-03-19 13:27:31 +0100 | [diff] [blame] | 849 | .num_pin_ranges = ARRAY_SIZE(tegra194_main_pin_ranges), |
| 850 | .pin_ranges = tegra194_main_pin_ranges, |
| 851 | .pinmux = "nvidia,tegra194-pinmux", |
Mikko Perttunen | bac5c3b | 2018-06-20 15:54:03 +0300 | [diff] [blame] | 852 | }; |
| 853 | |
Thierry Reding | 13a62a5 | 2019-11-08 16:33:51 +0100 | [diff] [blame] | 854 | #define TEGRA194_AON_GPIO_PORT(_name, _bank, _port, _pins) \ |
| 855 | [TEGRA194_AON_GPIO_PORT_##_name] = { \ |
| 856 | .name = #_name, \ |
| 857 | .bank = _bank, \ |
| 858 | .port = _port, \ |
| 859 | .pins = _pins, \ |
Mikko Perttunen | bac5c3b | 2018-06-20 15:54:03 +0300 | [diff] [blame] | 860 | } |
| 861 | |
| 862 | static const struct tegra_gpio_port tegra194_aon_ports[] = { |
Thierry Reding | 13a62a5 | 2019-11-08 16:33:51 +0100 | [diff] [blame] | 863 | TEGRA194_AON_GPIO_PORT(AA, 0, 3, 8), |
| 864 | TEGRA194_AON_GPIO_PORT(BB, 0, 4, 4), |
| 865 | TEGRA194_AON_GPIO_PORT(CC, 0, 1, 8), |
| 866 | TEGRA194_AON_GPIO_PORT(DD, 0, 2, 3), |
| 867 | TEGRA194_AON_GPIO_PORT(EE, 0, 0, 7) |
Mikko Perttunen | bac5c3b | 2018-06-20 15:54:03 +0300 | [diff] [blame] | 868 | }; |
| 869 | |
| 870 | static const struct tegra_gpio_soc tegra194_aon_soc = { |
| 871 | .num_ports = ARRAY_SIZE(tegra194_aon_ports), |
| 872 | .ports = tegra194_aon_ports, |
| 873 | .name = "tegra194-gpio-aon", |
Thierry Reding | 2a36550 | 2019-10-02 16:45:02 +0200 | [diff] [blame] | 874 | .instance = 1, |
Mikko Perttunen | bac5c3b | 2018-06-20 15:54:03 +0300 | [diff] [blame] | 875 | }; |
| 876 | |
Thierry Reding | 5b2b135 | 2017-11-07 19:15:56 +0100 | [diff] [blame] | 877 | static const struct of_device_id tegra186_gpio_of_match[] = { |
| 878 | { |
| 879 | .compatible = "nvidia,tegra186-gpio", |
| 880 | .data = &tegra186_main_soc |
| 881 | }, { |
| 882 | .compatible = "nvidia,tegra186-gpio-aon", |
| 883 | .data = &tegra186_aon_soc |
| 884 | }, { |
Mikko Perttunen | bac5c3b | 2018-06-20 15:54:03 +0300 | [diff] [blame] | 885 | .compatible = "nvidia,tegra194-gpio", |
| 886 | .data = &tegra194_main_soc |
| 887 | }, { |
| 888 | .compatible = "nvidia,tegra194-gpio-aon", |
| 889 | .data = &tegra194_aon_soc |
| 890 | }, { |
Thierry Reding | 5b2b135 | 2017-11-07 19:15:56 +0100 | [diff] [blame] | 891 | /* sentinel */ |
| 892 | } |
| 893 | }; |
Mian Yousaf Kaukab | fef2d3b | 2020-05-05 10:45:01 +0200 | [diff] [blame] | 894 | MODULE_DEVICE_TABLE(of, tegra186_gpio_of_match); |
Thierry Reding | 5b2b135 | 2017-11-07 19:15:56 +0100 | [diff] [blame] | 895 | |
| 896 | static struct platform_driver tegra186_gpio_driver = { |
| 897 | .driver = { |
| 898 | .name = "tegra186-gpio", |
| 899 | .of_match_table = tegra186_gpio_of_match, |
| 900 | }, |
| 901 | .probe = tegra186_gpio_probe, |
Thierry Reding | 5b2b135 | 2017-11-07 19:15:56 +0100 | [diff] [blame] | 902 | }; |
| 903 | module_platform_driver(tegra186_gpio_driver); |
| 904 | |
| 905 | MODULE_DESCRIPTION("NVIDIA Tegra186 GPIO controller driver"); |
| 906 | MODULE_AUTHOR("Thierry Reding <treding@nvidia.com>"); |
| 907 | MODULE_LICENSE("GPL v2"); |