blob: fbceae3c2ee700866995708c18bd634fca91019a [file] [log] [blame]
Thomas Gleixnerd2912cb2019-06-04 10:11:33 +02001// SPDX-License-Identifier: GPL-2.0-only
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +02002/*
3 * omap iommu: tlb and pagetable primitives
4 *
Hiroshi DOYUc127c7d2010-02-15 10:03:32 -08005 * Copyright (C) 2008-2010 Nokia Corporation
Suman Anna9d5018d2017-09-05 17:56:18 -05006 * Copyright (C) 2013-2017 Texas Instruments Incorporated - http://www.ti.com/
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +02007 *
8 * Written by Hiroshi DOYU <Hiroshi.DOYU@nokia.com>,
9 * Paul Mundt and Toshihiro Kobayashi
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +020010 */
11
Josue Albarranbfee0cf2017-07-28 15:49:14 -050012#include <linux/dma-mapping.h>
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +020013#include <linux/err.h>
Tejun Heo5a0e3ad2010-03-24 17:04:11 +090014#include <linux/slab.h>
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +020015#include <linux/interrupt.h>
16#include <linux/ioport.h>
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +020017#include <linux/platform_device.h>
Ohad Ben-Cohenf626b522011-06-02 01:46:12 +030018#include <linux/iommu.h>
Tony Lindgrenc8d35c82012-11-02 12:24:03 -070019#include <linux/omap-iommu.h>
Ohad Ben-Cohenf626b522011-06-02 01:46:12 +030020#include <linux/mutex.h>
21#include <linux/spinlock.h>
Tony Lindgrened1c7de2012-11-02 12:24:06 -070022#include <linux/io.h>
Omar Ramirez Lunaebf7cda2012-11-19 19:05:51 -060023#include <linux/pm_runtime.h>
Florian Vaussard3c927482014-02-28 14:42:36 -060024#include <linux/of.h>
25#include <linux/of_iommu.h>
26#include <linux/of_irq.h>
Suman Anna7d682772014-09-04 17:27:30 -050027#include <linux/of_platform.h>
Suman Anna3ca92992015-10-02 18:02:44 -050028#include <linux/regmap.h>
29#include <linux/mfd/syscon.h>
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +020030
Tony Lindgren2ab7c842012-11-02 12:24:14 -070031#include <linux/platform_data/iommu-omap.h>
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +020032
Ido Yariv2f7702a2012-11-02 12:24:00 -070033#include "omap-iopgtable.h"
Tony Lindgrened1c7de2012-11-02 12:24:06 -070034#include "omap-iommu.h"
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +020035
Joerg Roedel01611fe2017-04-12 00:21:30 -050036static const struct iommu_ops omap_iommu_ops;
37
Kefeng Wang6e8b5662019-04-23 15:50:08 +080038#define to_iommu(dev) ((struct omap_iommu *)dev_get_drvdata(dev))
Suman Anna5acc97d2014-03-17 20:31:34 -050039
Ohad Ben-Cohen66bc8cf2011-11-10 11:32:27 +020040/* bitmap of the page sizes currently supported */
41#define OMAP_IOMMU_PGSIZES (SZ_4K | SZ_64K | SZ_1M | SZ_16M)
42
Ido Yariv7bd9e252012-11-02 12:24:09 -070043#define MMU_LOCK_BASE_SHIFT 10
44#define MMU_LOCK_BASE_MASK (0x1f << MMU_LOCK_BASE_SHIFT)
45#define MMU_LOCK_BASE(x) \
46 ((x & MMU_LOCK_BASE_MASK) >> MMU_LOCK_BASE_SHIFT)
47
48#define MMU_LOCK_VICT_SHIFT 4
49#define MMU_LOCK_VICT_MASK (0x1f << MMU_LOCK_VICT_SHIFT)
50#define MMU_LOCK_VICT(x) \
51 ((x & MMU_LOCK_VICT_MASK) >> MMU_LOCK_VICT_SHIFT)
52
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +020053static struct platform_driver omap_iommu_driver;
54static struct kmem_cache *iopte_cachep;
55
56/**
Joerg Roedel8cf851e2015-03-26 13:43:09 +010057 * to_omap_domain - Get struct omap_iommu_domain from generic iommu_domain
58 * @dom: generic iommu domain handle
59 **/
60static struct omap_iommu_domain *to_omap_domain(struct iommu_domain *dom)
61{
62 return container_of(dom, struct omap_iommu_domain, domain);
63}
64
65/**
Ohad Ben-Cohen6c32df42011-08-17 22:57:56 +030066 * omap_iommu_save_ctx - Save registers for pm off-mode support
Ohad Ben-Cohenfabdbca2011-10-11 00:18:33 +020067 * @dev: client device
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +020068 **/
Ohad Ben-Cohenfabdbca2011-10-11 00:18:33 +020069void omap_iommu_save_ctx(struct device *dev)
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +020070{
Suman Anna9d5018d2017-09-05 17:56:18 -050071 struct omap_iommu_arch_data *arch_data = dev->archdata.iommu;
72 struct omap_iommu *obj;
73 u32 *p;
Suman Annabd4396f2014-10-22 17:22:27 -050074 int i;
Ohad Ben-Cohenfabdbca2011-10-11 00:18:33 +020075
Suman Anna9d5018d2017-09-05 17:56:18 -050076 if (!arch_data)
77 return;
78
79 while (arch_data->iommu_dev) {
80 obj = arch_data->iommu_dev;
81 p = obj->ctx;
82 for (i = 0; i < (MMU_REG_SIZE / sizeof(u32)); i++) {
83 p[i] = iommu_read_reg(obj, i * sizeof(u32));
84 dev_dbg(obj->dev, "%s\t[%02d] %08x\n", __func__, i,
85 p[i]);
86 }
87 arch_data++;
Suman Annabd4396f2014-10-22 17:22:27 -050088 }
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +020089}
Ohad Ben-Cohen6c32df42011-08-17 22:57:56 +030090EXPORT_SYMBOL_GPL(omap_iommu_save_ctx);
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +020091
92/**
Ohad Ben-Cohen6c32df42011-08-17 22:57:56 +030093 * omap_iommu_restore_ctx - Restore registers for pm off-mode support
Ohad Ben-Cohenfabdbca2011-10-11 00:18:33 +020094 * @dev: client device
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +020095 **/
Ohad Ben-Cohenfabdbca2011-10-11 00:18:33 +020096void omap_iommu_restore_ctx(struct device *dev)
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +020097{
Suman Anna9d5018d2017-09-05 17:56:18 -050098 struct omap_iommu_arch_data *arch_data = dev->archdata.iommu;
99 struct omap_iommu *obj;
100 u32 *p;
Suman Annabd4396f2014-10-22 17:22:27 -0500101 int i;
Ohad Ben-Cohenfabdbca2011-10-11 00:18:33 +0200102
Suman Anna9d5018d2017-09-05 17:56:18 -0500103 if (!arch_data)
104 return;
105
106 while (arch_data->iommu_dev) {
107 obj = arch_data->iommu_dev;
108 p = obj->ctx;
109 for (i = 0; i < (MMU_REG_SIZE / sizeof(u32)); i++) {
110 iommu_write_reg(obj, p[i], i * sizeof(u32));
111 dev_dbg(obj->dev, "%s\t[%02d] %08x\n", __func__, i,
112 p[i]);
113 }
114 arch_data++;
Suman Annabd4396f2014-10-22 17:22:27 -0500115 }
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200116}
Ohad Ben-Cohen6c32df42011-08-17 22:57:56 +0300117EXPORT_SYMBOL_GPL(omap_iommu_restore_ctx);
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200118
Suman Anna3ca92992015-10-02 18:02:44 -0500119static void dra7_cfg_dspsys_mmu(struct omap_iommu *obj, bool enable)
120{
121 u32 val, mask;
122
123 if (!obj->syscfg)
124 return;
125
126 mask = (1 << (obj->id * DSP_SYS_MMU_CONFIG_EN_SHIFT));
127 val = enable ? mask : 0;
128 regmap_update_bits(obj->syscfg, DSP_SYS_MMU_CONFIG, mask, val);
129}
130
Suman Annabd4396f2014-10-22 17:22:27 -0500131static void __iommu_set_twl(struct omap_iommu *obj, bool on)
132{
133 u32 l = iommu_read_reg(obj, MMU_CNTL);
134
135 if (on)
136 iommu_write_reg(obj, MMU_IRQ_TWL_MASK, MMU_IRQENABLE);
137 else
138 iommu_write_reg(obj, MMU_IRQ_TLB_MISS_MASK, MMU_IRQENABLE);
139
140 l &= ~MMU_CNTL_MASK;
141 if (on)
142 l |= (MMU_CNTL_MMU_EN | MMU_CNTL_TWL_EN);
143 else
144 l |= (MMU_CNTL_MMU_EN);
145
146 iommu_write_reg(obj, l, MMU_CNTL);
147}
148
149static int omap2_iommu_enable(struct omap_iommu *obj)
150{
151 u32 l, pa;
152
153 if (!obj->iopgd || !IS_ALIGNED((u32)obj->iopgd, SZ_16K))
154 return -EINVAL;
155
156 pa = virt_to_phys(obj->iopgd);
157 if (!IS_ALIGNED(pa, SZ_16K))
158 return -EINVAL;
159
160 l = iommu_read_reg(obj, MMU_REVISION);
161 dev_info(obj->dev, "%s: version %d.%d\n", obj->name,
162 (l >> 4) & 0xf, l & 0xf);
163
164 iommu_write_reg(obj, pa, MMU_TTB);
165
Suman Anna3ca92992015-10-02 18:02:44 -0500166 dra7_cfg_dspsys_mmu(obj, true);
167
Suman Annabd4396f2014-10-22 17:22:27 -0500168 if (obj->has_bus_err_back)
169 iommu_write_reg(obj, MMU_GP_REG_BUS_ERR_BACK_EN, MMU_GP_REG);
170
171 __iommu_set_twl(obj, true);
172
173 return 0;
174}
175
176static void omap2_iommu_disable(struct omap_iommu *obj)
177{
178 u32 l = iommu_read_reg(obj, MMU_CNTL);
179
180 l &= ~MMU_CNTL_MASK;
181 iommu_write_reg(obj, l, MMU_CNTL);
Suman Anna3ca92992015-10-02 18:02:44 -0500182 dra7_cfg_dspsys_mmu(obj, false);
Suman Annabd4396f2014-10-22 17:22:27 -0500183
184 dev_dbg(obj->dev, "%s is shutting down\n", obj->name);
185}
186
Ohad Ben-Cohen6c32df42011-08-17 22:57:56 +0300187static int iommu_enable(struct omap_iommu *obj)
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200188{
Suman Annadb8918f2019-08-07 11:26:47 +0300189 int ret;
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200190
Suman Annadb8918f2019-08-07 11:26:47 +0300191 ret = pm_runtime_get_sync(obj->dev);
192 if (ret < 0)
193 pm_runtime_put_noidle(obj->dev);
Suman Anna3846a3b92019-08-07 11:26:45 +0300194
Suman Annadb8918f2019-08-07 11:26:47 +0300195 return ret < 0 ? ret : 0;
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200196}
197
Ohad Ben-Cohen6c32df42011-08-17 22:57:56 +0300198static void iommu_disable(struct omap_iommu *obj)
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200199{
Omar Ramirez Lunaebf7cda2012-11-19 19:05:51 -0600200 pm_runtime_put_sync(obj->dev);
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200201}
202
203/*
204 * TLB operations
205 */
Ohad Ben-Cohene1f23812011-08-16 14:58:14 +0300206static u32 iotlb_cr_to_virt(struct cr_regs *cr)
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200207{
Suman Annabd4396f2014-10-22 17:22:27 -0500208 u32 page_size = cr->cam & MMU_CAM_PGSZ_MASK;
209 u32 mask = get_cam_va_mask(cr->cam & page_size);
210
211 return cr->cam & mask;
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200212}
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200213
214static u32 get_iopte_attr(struct iotlb_entry *e)
215{
Suman Annabd4396f2014-10-22 17:22:27 -0500216 u32 attr;
217
218 attr = e->mixed << 5;
219 attr |= e->endian;
220 attr |= e->elsz >> 3;
221 attr <<= (((e->pgsz == MMU_CAM_PGSZ_4K) ||
222 (e->pgsz == MMU_CAM_PGSZ_64K)) ? 0 : 6);
223 return attr;
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200224}
225
Ohad Ben-Cohen6c32df42011-08-17 22:57:56 +0300226static u32 iommu_report_fault(struct omap_iommu *obj, u32 *da)
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200227{
Suman Annabd4396f2014-10-22 17:22:27 -0500228 u32 status, fault_addr;
229
230 status = iommu_read_reg(obj, MMU_IRQSTATUS);
231 status &= MMU_IRQ_MASK;
232 if (!status) {
233 *da = 0;
234 return 0;
235 }
236
237 fault_addr = iommu_read_reg(obj, MMU_FAULT_AD);
238 *da = fault_addr;
239
240 iommu_write_reg(obj, status, MMU_IRQSTATUS);
241
242 return status;
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200243}
244
Suman Anna69c2c192015-07-20 17:33:25 -0500245void iotlb_lock_get(struct omap_iommu *obj, struct iotlb_lock *l)
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200246{
247 u32 val;
248
249 val = iommu_read_reg(obj, MMU_LOCK);
250
251 l->base = MMU_LOCK_BASE(val);
252 l->vict = MMU_LOCK_VICT(val);
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200253}
254
Suman Anna69c2c192015-07-20 17:33:25 -0500255void iotlb_lock_set(struct omap_iommu *obj, struct iotlb_lock *l)
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200256{
257 u32 val;
258
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200259 val = (l->base << MMU_LOCK_BASE_SHIFT);
260 val |= (l->vict << MMU_LOCK_VICT_SHIFT);
261
262 iommu_write_reg(obj, val, MMU_LOCK);
263}
264
Ohad Ben-Cohen6c32df42011-08-17 22:57:56 +0300265static void iotlb_read_cr(struct omap_iommu *obj, struct cr_regs *cr)
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200266{
Suman Annabd4396f2014-10-22 17:22:27 -0500267 cr->cam = iommu_read_reg(obj, MMU_READ_CAM);
268 cr->ram = iommu_read_reg(obj, MMU_READ_RAM);
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200269}
270
Ohad Ben-Cohen6c32df42011-08-17 22:57:56 +0300271static void iotlb_load_cr(struct omap_iommu *obj, struct cr_regs *cr)
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200272{
Suman Annabd4396f2014-10-22 17:22:27 -0500273 iommu_write_reg(obj, cr->cam | MMU_CAM_V, MMU_CAM);
274 iommu_write_reg(obj, cr->ram, MMU_RAM);
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200275
276 iommu_write_reg(obj, 1, MMU_FLUSH_ENTRY);
277 iommu_write_reg(obj, 1, MMU_LD_TLB);
278}
279
Hiroshi DOYU37c28362010-04-27 05:37:12 +0000280/* only used in iotlb iteration for-loop */
Suman Anna69c2c192015-07-20 17:33:25 -0500281struct cr_regs __iotlb_read_cr(struct omap_iommu *obj, int n)
Hiroshi DOYU37c28362010-04-27 05:37:12 +0000282{
283 struct cr_regs cr;
284 struct iotlb_lock l;
285
286 iotlb_lock_get(obj, &l);
287 l.vict = n;
288 iotlb_lock_set(obj, &l);
289 iotlb_read_cr(obj, &cr);
290
291 return cr;
292}
293
Suman Annabd4396f2014-10-22 17:22:27 -0500294#ifdef PREFETCH_IOTLB
295static struct cr_regs *iotlb_alloc_cr(struct omap_iommu *obj,
296 struct iotlb_entry *e)
297{
298 struct cr_regs *cr;
299
300 if (!e)
301 return NULL;
302
303 if (e->da & ~(get_cam_va_mask(e->pgsz))) {
304 dev_err(obj->dev, "%s:\twrong alignment: %08x\n", __func__,
305 e->da);
306 return ERR_PTR(-EINVAL);
307 }
308
309 cr = kmalloc(sizeof(*cr), GFP_KERNEL);
310 if (!cr)
311 return ERR_PTR(-ENOMEM);
312
313 cr->cam = (e->da & MMU_CAM_VATAG_MASK) | e->prsvd | e->pgsz | e->valid;
314 cr->ram = e->pa | e->endian | e->elsz | e->mixed;
315
316 return cr;
317}
318
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200319/**
320 * load_iotlb_entry - Set an iommu tlb entry
321 * @obj: target iommu
322 * @e: an iommu tlb entry info
323 **/
Ohad Ben-Cohen6c32df42011-08-17 22:57:56 +0300324static int load_iotlb_entry(struct omap_iommu *obj, struct iotlb_entry *e)
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200325{
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200326 int err = 0;
327 struct iotlb_lock l;
328 struct cr_regs *cr;
329
330 if (!obj || !obj->nr_tlb_entries || !e)
331 return -EINVAL;
332
Omar Ramirez Lunaebf7cda2012-11-19 19:05:51 -0600333 pm_runtime_get_sync(obj->dev);
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200334
Kanigeri, Haribe6d8022010-04-22 23:26:11 +0000335 iotlb_lock_get(obj, &l);
336 if (l.base == obj->nr_tlb_entries) {
337 dev_warn(obj->dev, "%s: preserve entries full\n", __func__);
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200338 err = -EBUSY;
339 goto out;
340 }
Kanigeri, Haribe6d8022010-04-22 23:26:11 +0000341 if (!e->prsvd) {
Hiroshi DOYU37c28362010-04-27 05:37:12 +0000342 int i;
343 struct cr_regs tmp;
Kanigeri, Haribe6d8022010-04-22 23:26:11 +0000344
Hiroshi DOYU37c28362010-04-27 05:37:12 +0000345 for_each_iotlb_cr(obj, obj->nr_tlb_entries, i, tmp)
Kanigeri, Haribe6d8022010-04-22 23:26:11 +0000346 if (!iotlb_cr_valid(&tmp))
347 break;
Hiroshi DOYU37c28362010-04-27 05:37:12 +0000348
Kanigeri, Haribe6d8022010-04-22 23:26:11 +0000349 if (i == obj->nr_tlb_entries) {
350 dev_dbg(obj->dev, "%s: full: no entry\n", __func__);
351 err = -EBUSY;
352 goto out;
353 }
Hiroshi DOYU37c28362010-04-27 05:37:12 +0000354
355 iotlb_lock_get(obj, &l);
Kanigeri, Haribe6d8022010-04-22 23:26:11 +0000356 } else {
357 l.vict = l.base;
358 iotlb_lock_set(obj, &l);
359 }
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200360
361 cr = iotlb_alloc_cr(obj, e);
362 if (IS_ERR(cr)) {
Omar Ramirez Lunaebf7cda2012-11-19 19:05:51 -0600363 pm_runtime_put_sync(obj->dev);
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200364 return PTR_ERR(cr);
365 }
366
367 iotlb_load_cr(obj, cr);
368 kfree(cr);
369
Kanigeri, Haribe6d8022010-04-22 23:26:11 +0000370 if (e->prsvd)
371 l.base++;
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200372 /* increment victim for next tlb load */
373 if (++l.vict == obj->nr_tlb_entries)
Kanigeri, Haribe6d8022010-04-22 23:26:11 +0000374 l.vict = l.base;
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200375 iotlb_lock_set(obj, &l);
376out:
Omar Ramirez Lunaebf7cda2012-11-19 19:05:51 -0600377 pm_runtime_put_sync(obj->dev);
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200378 return err;
379}
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200380
Ohad Ben-Cohen5da14a42011-08-16 15:19:10 +0300381#else /* !PREFETCH_IOTLB */
382
Ohad Ben-Cohen6c32df42011-08-17 22:57:56 +0300383static int load_iotlb_entry(struct omap_iommu *obj, struct iotlb_entry *e)
Ohad Ben-Cohen5da14a42011-08-16 15:19:10 +0300384{
385 return 0;
386}
387
388#endif /* !PREFETCH_IOTLB */
389
Ohad Ben-Cohen6c32df42011-08-17 22:57:56 +0300390static int prefetch_iotlb_entry(struct omap_iommu *obj, struct iotlb_entry *e)
Ohad Ben-Cohen5da14a42011-08-16 15:19:10 +0300391{
392 return load_iotlb_entry(obj, e);
393}
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200394
395/**
396 * flush_iotlb_page - Clear an iommu tlb entry
397 * @obj: target iommu
398 * @da: iommu device virtual address
399 *
400 * Clear an iommu tlb entry which includes 'da' address.
401 **/
Ohad Ben-Cohen6c32df42011-08-17 22:57:56 +0300402static void flush_iotlb_page(struct omap_iommu *obj, u32 da)
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200403{
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200404 int i;
Hiroshi DOYU37c28362010-04-27 05:37:12 +0000405 struct cr_regs cr;
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200406
Omar Ramirez Lunaebf7cda2012-11-19 19:05:51 -0600407 pm_runtime_get_sync(obj->dev);
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200408
Hiroshi DOYU37c28362010-04-27 05:37:12 +0000409 for_each_iotlb_cr(obj, obj->nr_tlb_entries, i, cr) {
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200410 u32 start;
411 size_t bytes;
412
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200413 if (!iotlb_cr_valid(&cr))
414 continue;
415
416 start = iotlb_cr_to_virt(&cr);
417 bytes = iopgsz_to_bytes(cr.cam & 3);
418
419 if ((start <= da) && (da < start + bytes)) {
420 dev_dbg(obj->dev, "%s: %08x<=%08x(%x)\n",
421 __func__, start, da, bytes);
Hari Kanigeri0fa035e2010-08-20 13:50:18 +0000422 iotlb_load_cr(obj, &cr);
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200423 iommu_write_reg(obj, 1, MMU_FLUSH_ENTRY);
Laurent Pinchartf7129a02014-03-07 23:47:03 +0100424 break;
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200425 }
426 }
Omar Ramirez Lunaebf7cda2012-11-19 19:05:51 -0600427 pm_runtime_put_sync(obj->dev);
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200428
429 if (i == obj->nr_tlb_entries)
430 dev_dbg(obj->dev, "%s: no page for %08x\n", __func__, da);
431}
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200432
433/**
434 * flush_iotlb_all - Clear all iommu tlb entries
435 * @obj: target iommu
436 **/
Ohad Ben-Cohen6c32df42011-08-17 22:57:56 +0300437static void flush_iotlb_all(struct omap_iommu *obj)
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200438{
439 struct iotlb_lock l;
440
Omar Ramirez Lunaebf7cda2012-11-19 19:05:51 -0600441 pm_runtime_get_sync(obj->dev);
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200442
443 l.base = 0;
444 l.vict = 0;
445 iotlb_lock_set(obj, &l);
446
447 iommu_write_reg(obj, 1, MMU_GFLUSH);
448
Omar Ramirez Lunaebf7cda2012-11-19 19:05:51 -0600449 pm_runtime_put_sync(obj->dev);
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200450}
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200451
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200452/*
453 * H/W pagetable operations
454 */
Josue Albarranbfee0cf2017-07-28 15:49:14 -0500455static void flush_iopte_range(struct device *dev, dma_addr_t dma,
456 unsigned long offset, int num_entries)
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200457{
Josue Albarranbfee0cf2017-07-28 15:49:14 -0500458 size_t size = num_entries * sizeof(u32);
459
460 dma_sync_single_range_for_device(dev, dma, offset, size, DMA_TO_DEVICE);
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200461}
462
Josue Albarranbfee0cf2017-07-28 15:49:14 -0500463static void iopte_free(struct omap_iommu *obj, u32 *iopte, bool dma_valid)
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200464{
Josue Albarranbfee0cf2017-07-28 15:49:14 -0500465 dma_addr_t pt_dma;
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200466
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200467 /* Note: freed iopte's must be clean ready for re-use */
Josue Albarranbfee0cf2017-07-28 15:49:14 -0500468 if (iopte) {
469 if (dma_valid) {
470 pt_dma = virt_to_phys(iopte);
471 dma_unmap_single(obj->dev, pt_dma, IOPTE_TABLE_SIZE,
472 DMA_TO_DEVICE);
473 }
474
Zhouyi Zhoue28045a2014-03-05 18:20:19 +0800475 kmem_cache_free(iopte_cachep, iopte);
Josue Albarranbfee0cf2017-07-28 15:49:14 -0500476 }
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200477}
478
Josue Albarranbfee0cf2017-07-28 15:49:14 -0500479static u32 *iopte_alloc(struct omap_iommu *obj, u32 *iopgd,
480 dma_addr_t *pt_dma, u32 da)
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200481{
482 u32 *iopte;
Josue Albarranbfee0cf2017-07-28 15:49:14 -0500483 unsigned long offset = iopgd_index(da) * sizeof(da);
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200484
485 /* a table has already existed */
486 if (*iopgd)
487 goto pte_ready;
488
489 /*
490 * do the allocation outside the page table lock
491 */
492 spin_unlock(&obj->page_table_lock);
493 iopte = kmem_cache_zalloc(iopte_cachep, GFP_KERNEL);
494 spin_lock(&obj->page_table_lock);
495
496 if (!*iopgd) {
497 if (!iopte)
498 return ERR_PTR(-ENOMEM);
499
Josue Albarranbfee0cf2017-07-28 15:49:14 -0500500 *pt_dma = dma_map_single(obj->dev, iopte, IOPTE_TABLE_SIZE,
501 DMA_TO_DEVICE);
502 if (dma_mapping_error(obj->dev, *pt_dma)) {
503 dev_err(obj->dev, "DMA map error for L2 table\n");
504 iopte_free(obj, iopte, false);
505 return ERR_PTR(-ENOMEM);
506 }
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200507
Josue Albarranbfee0cf2017-07-28 15:49:14 -0500508 /*
509 * we rely on dma address and the physical address to be
510 * the same for mapping the L2 table
511 */
512 if (WARN_ON(*pt_dma != virt_to_phys(iopte))) {
513 dev_err(obj->dev, "DMA translation error for L2 table\n");
514 dma_unmap_single(obj->dev, *pt_dma, IOPTE_TABLE_SIZE,
515 DMA_TO_DEVICE);
516 iopte_free(obj, iopte, false);
517 return ERR_PTR(-ENOMEM);
518 }
519
520 *iopgd = virt_to_phys(iopte) | IOPGD_TABLE;
521
522 flush_iopte_range(obj->dev, obj->pd_dma, offset, 1);
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200523 dev_vdbg(obj->dev, "%s: a new pte:%p\n", __func__, iopte);
524 } else {
525 /* We raced, free the reduniovant table */
Josue Albarranbfee0cf2017-07-28 15:49:14 -0500526 iopte_free(obj, iopte, false);
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200527 }
528
529pte_ready:
530 iopte = iopte_offset(iopgd, da);
Ralf Goebel04c532a2018-08-06 17:00:36 +0200531 *pt_dma = iopgd_page_paddr(iopgd);
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200532 dev_vdbg(obj->dev,
533 "%s: da:%08x pgd:%p *pgd:%08x pte:%p *pte:%08x\n",
534 __func__, da, iopgd, *iopgd, iopte, *iopte);
535
536 return iopte;
537}
538
Ohad Ben-Cohen6c32df42011-08-17 22:57:56 +0300539static int iopgd_alloc_section(struct omap_iommu *obj, u32 da, u32 pa, u32 prot)
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200540{
541 u32 *iopgd = iopgd_offset(obj, da);
Josue Albarranbfee0cf2017-07-28 15:49:14 -0500542 unsigned long offset = iopgd_index(da) * sizeof(da);
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200543
Hiroshi DOYU4abb7612010-05-06 18:24:04 +0300544 if ((da | pa) & ~IOSECTION_MASK) {
545 dev_err(obj->dev, "%s: %08x:%08x should aligned on %08lx\n",
546 __func__, da, pa, IOSECTION_SIZE);
547 return -EINVAL;
548 }
549
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200550 *iopgd = (pa & IOSECTION_MASK) | prot | IOPGD_SECTION;
Josue Albarranbfee0cf2017-07-28 15:49:14 -0500551 flush_iopte_range(obj->dev, obj->pd_dma, offset, 1);
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200552 return 0;
553}
554
Ohad Ben-Cohen6c32df42011-08-17 22:57:56 +0300555static int iopgd_alloc_super(struct omap_iommu *obj, u32 da, u32 pa, u32 prot)
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200556{
557 u32 *iopgd = iopgd_offset(obj, da);
Josue Albarranbfee0cf2017-07-28 15:49:14 -0500558 unsigned long offset = iopgd_index(da) * sizeof(da);
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200559 int i;
560
Hiroshi DOYU4abb7612010-05-06 18:24:04 +0300561 if ((da | pa) & ~IOSUPER_MASK) {
562 dev_err(obj->dev, "%s: %08x:%08x should aligned on %08lx\n",
563 __func__, da, pa, IOSUPER_SIZE);
564 return -EINVAL;
565 }
566
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200567 for (i = 0; i < 16; i++)
568 *(iopgd + i) = (pa & IOSUPER_MASK) | prot | IOPGD_SUPER;
Josue Albarranbfee0cf2017-07-28 15:49:14 -0500569 flush_iopte_range(obj->dev, obj->pd_dma, offset, 16);
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200570 return 0;
571}
572
Ohad Ben-Cohen6c32df42011-08-17 22:57:56 +0300573static int iopte_alloc_page(struct omap_iommu *obj, u32 da, u32 pa, u32 prot)
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200574{
575 u32 *iopgd = iopgd_offset(obj, da);
Josue Albarranbfee0cf2017-07-28 15:49:14 -0500576 dma_addr_t pt_dma;
577 u32 *iopte = iopte_alloc(obj, iopgd, &pt_dma, da);
578 unsigned long offset = iopte_index(da) * sizeof(da);
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200579
580 if (IS_ERR(iopte))
581 return PTR_ERR(iopte);
582
583 *iopte = (pa & IOPAGE_MASK) | prot | IOPTE_SMALL;
Josue Albarranbfee0cf2017-07-28 15:49:14 -0500584 flush_iopte_range(obj->dev, pt_dma, offset, 1);
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200585
586 dev_vdbg(obj->dev, "%s: da:%08x pa:%08x pte:%p *pte:%08x\n",
587 __func__, da, pa, iopte, *iopte);
588
589 return 0;
590}
591
Ohad Ben-Cohen6c32df42011-08-17 22:57:56 +0300592static int iopte_alloc_large(struct omap_iommu *obj, u32 da, u32 pa, u32 prot)
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200593{
594 u32 *iopgd = iopgd_offset(obj, da);
Josue Albarranbfee0cf2017-07-28 15:49:14 -0500595 dma_addr_t pt_dma;
596 u32 *iopte = iopte_alloc(obj, iopgd, &pt_dma, da);
597 unsigned long offset = iopte_index(da) * sizeof(da);
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200598 int i;
599
Hiroshi DOYU4abb7612010-05-06 18:24:04 +0300600 if ((da | pa) & ~IOLARGE_MASK) {
601 dev_err(obj->dev, "%s: %08x:%08x should aligned on %08lx\n",
602 __func__, da, pa, IOLARGE_SIZE);
603 return -EINVAL;
604 }
605
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200606 if (IS_ERR(iopte))
607 return PTR_ERR(iopte);
608
609 for (i = 0; i < 16; i++)
610 *(iopte + i) = (pa & IOLARGE_MASK) | prot | IOPTE_LARGE;
Josue Albarranbfee0cf2017-07-28 15:49:14 -0500611 flush_iopte_range(obj->dev, pt_dma, offset, 16);
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200612 return 0;
613}
614
Ohad Ben-Cohen6c32df42011-08-17 22:57:56 +0300615static int
616iopgtable_store_entry_core(struct omap_iommu *obj, struct iotlb_entry *e)
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200617{
Ohad Ben-Cohen6c32df42011-08-17 22:57:56 +0300618 int (*fn)(struct omap_iommu *, u32, u32, u32);
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200619 u32 prot;
620 int err;
621
622 if (!obj || !e)
623 return -EINVAL;
624
625 switch (e->pgsz) {
626 case MMU_CAM_PGSZ_16M:
627 fn = iopgd_alloc_super;
628 break;
629 case MMU_CAM_PGSZ_1M:
630 fn = iopgd_alloc_section;
631 break;
632 case MMU_CAM_PGSZ_64K:
633 fn = iopte_alloc_large;
634 break;
635 case MMU_CAM_PGSZ_4K:
636 fn = iopte_alloc_page;
637 break;
638 default:
639 fn = NULL;
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200640 break;
641 }
642
Suman Anna7c1ab602016-04-04 17:46:19 -0500643 if (WARN_ON(!fn))
644 return -EINVAL;
645
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200646 prot = get_iopte_attr(e);
647
648 spin_lock(&obj->page_table_lock);
649 err = fn(obj, e->da, e->pa, prot);
650 spin_unlock(&obj->page_table_lock);
651
652 return err;
653}
654
655/**
Ohad Ben-Cohen6c32df42011-08-17 22:57:56 +0300656 * omap_iopgtable_store_entry - Make an iommu pte entry
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200657 * @obj: target iommu
658 * @e: an iommu tlb entry info
659 **/
Suman Anna4899a562014-10-22 17:22:32 -0500660static int
661omap_iopgtable_store_entry(struct omap_iommu *obj, struct iotlb_entry *e)
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200662{
663 int err;
664
665 flush_iotlb_page(obj, e->da);
666 err = iopgtable_store_entry_core(obj, e);
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200667 if (!err)
Ohad Ben-Cohen5da14a42011-08-16 15:19:10 +0300668 prefetch_iotlb_entry(obj, e);
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200669 return err;
670}
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200671
672/**
673 * iopgtable_lookup_entry - Lookup an iommu pte entry
674 * @obj: target iommu
675 * @da: iommu device virtual address
676 * @ppgd: iommu pgd entry pointer to be returned
677 * @ppte: iommu pte entry pointer to be returned
678 **/
Ohad Ben-Cohene1f23812011-08-16 14:58:14 +0300679static void
680iopgtable_lookup_entry(struct omap_iommu *obj, u32 da, u32 **ppgd, u32 **ppte)
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200681{
682 u32 *iopgd, *iopte = NULL;
683
684 iopgd = iopgd_offset(obj, da);
685 if (!*iopgd)
686 goto out;
687
Hiroshi DOYUa1a54452010-05-13 09:45:35 +0300688 if (iopgd_is_table(*iopgd))
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200689 iopte = iopte_offset(iopgd, da);
690out:
691 *ppgd = iopgd;
692 *ppte = iopte;
693}
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200694
Ohad Ben-Cohen6c32df42011-08-17 22:57:56 +0300695static size_t iopgtable_clear_entry_core(struct omap_iommu *obj, u32 da)
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200696{
697 size_t bytes;
698 u32 *iopgd = iopgd_offset(obj, da);
699 int nent = 1;
Josue Albarranbfee0cf2017-07-28 15:49:14 -0500700 dma_addr_t pt_dma;
701 unsigned long pd_offset = iopgd_index(da) * sizeof(da);
702 unsigned long pt_offset = iopte_index(da) * sizeof(da);
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200703
704 if (!*iopgd)
705 return 0;
706
Hiroshi DOYUa1a54452010-05-13 09:45:35 +0300707 if (iopgd_is_table(*iopgd)) {
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200708 int i;
709 u32 *iopte = iopte_offset(iopgd, da);
710
711 bytes = IOPTE_SIZE;
712 if (*iopte & IOPTE_LARGE) {
713 nent *= 16;
714 /* rewind to the 1st entry */
Hiroshi DOYUc127c7d2010-02-15 10:03:32 -0800715 iopte = iopte_offset(iopgd, (da & IOLARGE_MASK));
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200716 }
717 bytes *= nent;
718 memset(iopte, 0, nent * sizeof(*iopte));
Ralf Goebel04c532a2018-08-06 17:00:36 +0200719 pt_dma = iopgd_page_paddr(iopgd);
Josue Albarranbfee0cf2017-07-28 15:49:14 -0500720 flush_iopte_range(obj->dev, pt_dma, pt_offset, nent);
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200721
722 /*
723 * do table walk to check if this table is necessary or not
724 */
725 iopte = iopte_offset(iopgd, 0);
726 for (i = 0; i < PTRS_PER_IOPTE; i++)
727 if (iopte[i])
728 goto out;
729
Josue Albarranbfee0cf2017-07-28 15:49:14 -0500730 iopte_free(obj, iopte, true);
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200731 nent = 1; /* for the next L1 entry */
732 } else {
733 bytes = IOPGD_SIZE;
Hiroshi DOYUdcc730d2009-10-22 14:46:32 -0700734 if ((*iopgd & IOPGD_SUPER) == IOPGD_SUPER) {
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200735 nent *= 16;
736 /* rewind to the 1st entry */
Hiroshi DOYU8d33ea52010-02-15 10:03:32 -0800737 iopgd = iopgd_offset(obj, (da & IOSUPER_MASK));
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200738 }
739 bytes *= nent;
740 }
741 memset(iopgd, 0, nent * sizeof(*iopgd));
Josue Albarranbfee0cf2017-07-28 15:49:14 -0500742 flush_iopte_range(obj->dev, obj->pd_dma, pd_offset, nent);
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200743out:
744 return bytes;
745}
746
747/**
748 * iopgtable_clear_entry - Remove an iommu pte entry
749 * @obj: target iommu
750 * @da: iommu device virtual address
751 **/
Ohad Ben-Cohen6c32df42011-08-17 22:57:56 +0300752static size_t iopgtable_clear_entry(struct omap_iommu *obj, u32 da)
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200753{
754 size_t bytes;
755
756 spin_lock(&obj->page_table_lock);
757
758 bytes = iopgtable_clear_entry_core(obj, da);
759 flush_iotlb_page(obj, da);
760
761 spin_unlock(&obj->page_table_lock);
762
763 return bytes;
764}
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200765
Ohad Ben-Cohen6c32df42011-08-17 22:57:56 +0300766static void iopgtable_clear_entry_all(struct omap_iommu *obj)
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200767{
Josue Albarranbfee0cf2017-07-28 15:49:14 -0500768 unsigned long offset;
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200769 int i;
770
771 spin_lock(&obj->page_table_lock);
772
773 for (i = 0; i < PTRS_PER_IOPGD; i++) {
774 u32 da;
775 u32 *iopgd;
776
777 da = i << IOPGD_SHIFT;
778 iopgd = iopgd_offset(obj, da);
Josue Albarranbfee0cf2017-07-28 15:49:14 -0500779 offset = iopgd_index(da) * sizeof(da);
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200780
781 if (!*iopgd)
782 continue;
783
Hiroshi DOYUa1a54452010-05-13 09:45:35 +0300784 if (iopgd_is_table(*iopgd))
Josue Albarranbfee0cf2017-07-28 15:49:14 -0500785 iopte_free(obj, iopte_offset(iopgd, 0), true);
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200786
787 *iopgd = 0;
Josue Albarranbfee0cf2017-07-28 15:49:14 -0500788 flush_iopte_range(obj->dev, obj->pd_dma, offset, 1);
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200789 }
790
791 flush_iotlb_all(obj);
792
793 spin_unlock(&obj->page_table_lock);
794}
795
796/*
797 * Device IOMMU generic operations
798 */
799static irqreturn_t iommu_fault_handler(int irq, void *data)
800{
David Cohend594f1f2011-02-16 19:35:51 +0000801 u32 da, errs;
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200802 u32 *iopgd, *iopte;
Ohad Ben-Cohen6c32df42011-08-17 22:57:56 +0300803 struct omap_iommu *obj = data;
Ohad Ben-Cohene7f10f02011-09-13 15:26:29 -0400804 struct iommu_domain *domain = obj->domain;
Joerg Roedel8cf851e2015-03-26 13:43:09 +0100805 struct omap_iommu_domain *omap_domain = to_omap_domain(domain);
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200806
Suman Anna0d364282017-09-05 17:56:17 -0500807 if (!omap_domain->dev)
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200808 return IRQ_NONE;
809
David Cohend594f1f2011-02-16 19:35:51 +0000810 errs = iommu_report_fault(obj, &da);
Laurent Pinchartc56b2dd2011-05-10 16:56:46 +0200811 if (errs == 0)
812 return IRQ_HANDLED;
David Cohend594f1f2011-02-16 19:35:51 +0000813
814 /* Fault callback or TLB/PTE Dynamic loading */
Ohad Ben-Cohene7f10f02011-09-13 15:26:29 -0400815 if (!report_iommu_fault(domain, obj->dev, da, 0))
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200816 return IRQ_HANDLED;
817
Fernando Guzman Lugo159d3e32017-07-28 15:49:13 -0500818 iommu_write_reg(obj, 0, MMU_IRQENABLE);
Hiroshi DOYU37b29812010-05-24 02:01:52 +0000819
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200820 iopgd = iopgd_offset(obj, da);
821
Hiroshi DOYUa1a54452010-05-13 09:45:35 +0300822 if (!iopgd_is_table(*iopgd)) {
Suman Annab6c2e092013-05-30 18:10:59 -0500823 dev_err(obj->dev, "%s: errs:0x%08x da:0x%08x pgd:0x%p *pgd:px%08x\n",
Suman Anna5835b6a2015-07-20 17:33:32 -0500824 obj->name, errs, da, iopgd, *iopgd);
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200825 return IRQ_NONE;
826 }
827
828 iopte = iopte_offset(iopgd, da);
829
Suman Annab6c2e092013-05-30 18:10:59 -0500830 dev_err(obj->dev, "%s: errs:0x%08x da:0x%08x pgd:0x%p *pgd:0x%08x pte:0x%p *pte:0x%08x\n",
Suman Anna5835b6a2015-07-20 17:33:32 -0500831 obj->name, errs, da, iopgd, *iopgd, iopte, *iopte);
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200832
833 return IRQ_NONE;
834}
835
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200836/**
Ohad Ben-Cohenf626b522011-06-02 01:46:12 +0300837 * omap_iommu_attach() - attach iommu device to an iommu domain
Joerg Roedelede1c2e2017-04-12 00:21:29 -0500838 * @obj: target omap iommu device
Ohad Ben-Cohenf626b522011-06-02 01:46:12 +0300839 * @iopgd: page table
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200840 **/
Joerg Roedelede1c2e2017-04-12 00:21:29 -0500841static int omap_iommu_attach(struct omap_iommu *obj, u32 *iopgd)
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200842{
Suman Anna7ee08b9e2014-02-28 14:42:33 -0600843 int err;
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200844
Ohad Ben-Cohenf626b522011-06-02 01:46:12 +0300845 spin_lock(&obj->iommu_lock);
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200846
Josue Albarranbfee0cf2017-07-28 15:49:14 -0500847 obj->pd_dma = dma_map_single(obj->dev, iopgd, IOPGD_TABLE_SIZE,
848 DMA_TO_DEVICE);
849 if (dma_mapping_error(obj->dev, obj->pd_dma)) {
850 dev_err(obj->dev, "DMA map error for L1 table\n");
851 err = -ENOMEM;
852 goto out_err;
853 }
854
Ohad Ben-Cohenf626b522011-06-02 01:46:12 +0300855 obj->iopgd = iopgd;
856 err = iommu_enable(obj);
857 if (err)
Josue Albarranbfee0cf2017-07-28 15:49:14 -0500858 goto out_err;
Ohad Ben-Cohenf626b522011-06-02 01:46:12 +0300859 flush_iotlb_all(obj);
860
Ohad Ben-Cohenf626b522011-06-02 01:46:12 +0300861 spin_unlock(&obj->iommu_lock);
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200862
863 dev_dbg(obj->dev, "%s: %s\n", __func__, obj->name);
Joerg Roedelede1c2e2017-04-12 00:21:29 -0500864
865 return 0;
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200866
Josue Albarranbfee0cf2017-07-28 15:49:14 -0500867out_err:
Ohad Ben-Cohenf626b522011-06-02 01:46:12 +0300868 spin_unlock(&obj->iommu_lock);
Joerg Roedelede1c2e2017-04-12 00:21:29 -0500869
870 return err;
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200871}
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200872
873/**
Ohad Ben-Cohenf626b522011-06-02 01:46:12 +0300874 * omap_iommu_detach - release iommu device
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200875 * @obj: target iommu
876 **/
Ohad Ben-Cohen6c32df42011-08-17 22:57:56 +0300877static void omap_iommu_detach(struct omap_iommu *obj)
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200878{
Roel Kluinacf9d462010-01-08 10:29:05 -0800879 if (!obj || IS_ERR(obj))
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200880 return;
881
Ohad Ben-Cohenf626b522011-06-02 01:46:12 +0300882 spin_lock(&obj->iommu_lock);
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200883
Josue Albarranbfee0cf2017-07-28 15:49:14 -0500884 dma_unmap_single(obj->dev, obj->pd_dma, IOPGD_TABLE_SIZE,
885 DMA_TO_DEVICE);
Suman Anna2088ecb2014-10-22 17:22:19 -0500886 iommu_disable(obj);
Josue Albarranbfee0cf2017-07-28 15:49:14 -0500887 obj->pd_dma = 0;
Ohad Ben-Cohenf626b522011-06-02 01:46:12 +0300888 obj->iopgd = NULL;
889
890 spin_unlock(&obj->iommu_lock);
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +0200891
892 dev_dbg(obj->dev, "%s: %s\n", __func__, obj->name);
893}
David Cohend594f1f2011-02-16 19:35:51 +0000894
Suman Annadb8918f2019-08-07 11:26:47 +0300895/**
896 * omap_iommu_runtime_suspend - disable an iommu device
897 * @dev: iommu device
898 *
899 * This function performs all that is necessary to disable an
900 * IOMMU device, either during final detachment from a client
901 * device, or during system/runtime suspend of the device. This
902 * includes programming all the appropriate IOMMU registers, and
903 * managing the associated omap_hwmod's state and the device's
904 * reset line.
905 **/
906static int omap_iommu_runtime_suspend(struct device *dev)
907{
908 struct platform_device *pdev = to_platform_device(dev);
909 struct iommu_platform_data *pdata = dev_get_platdata(dev);
910 struct omap_iommu *obj = to_iommu(dev);
911 int ret;
912
913 omap2_iommu_disable(obj);
914
915 if (pdata && pdata->device_idle)
916 pdata->device_idle(pdev);
917
918 if (pdata && pdata->assert_reset)
919 pdata->assert_reset(pdev, pdata->reset_name);
920
921 if (pdata && pdata->set_pwrdm_constraint) {
922 ret = pdata->set_pwrdm_constraint(pdev, false, &obj->pwrst);
923 if (ret) {
924 dev_warn(obj->dev, "pwrdm_constraint failed to be reset, status = %d\n",
925 ret);
926 }
927 }
928
929 return 0;
930}
931
932/**
933 * omap_iommu_runtime_resume - enable an iommu device
934 * @dev: iommu device
935 *
936 * This function performs all that is necessary to enable an
937 * IOMMU device, either during initial attachment to a client
938 * device, or during system/runtime resume of the device. This
939 * includes programming all the appropriate IOMMU registers, and
940 * managing the associated omap_hwmod's state and the device's
941 * reset line.
942 **/
943static int omap_iommu_runtime_resume(struct device *dev)
944{
945 struct platform_device *pdev = to_platform_device(dev);
946 struct iommu_platform_data *pdata = dev_get_platdata(dev);
947 struct omap_iommu *obj = to_iommu(dev);
948 int ret = 0;
949
950 if (pdata && pdata->set_pwrdm_constraint) {
951 ret = pdata->set_pwrdm_constraint(pdev, true, &obj->pwrst);
952 if (ret) {
953 dev_warn(obj->dev, "pwrdm_constraint failed to be set, status = %d\n",
954 ret);
955 }
956 }
957
958 if (pdata && pdata->deassert_reset) {
959 ret = pdata->deassert_reset(pdev, pdata->reset_name);
960 if (ret) {
961 dev_err(dev, "deassert_reset failed: %d\n", ret);
962 return ret;
963 }
964 }
965
966 if (pdata && pdata->device_enable)
967 pdata->device_enable(pdev);
968
969 ret = omap2_iommu_enable(obj);
970
971 return ret;
972}
973
Suman Anna9d5018d2017-09-05 17:56:18 -0500974static bool omap_iommu_can_register(struct platform_device *pdev)
975{
976 struct device_node *np = pdev->dev.of_node;
977
978 if (!of_device_is_compatible(np, "ti,dra7-dsp-iommu"))
979 return true;
980
981 /*
982 * restrict IOMMU core registration only for processor-port MDMA MMUs
983 * on DRA7 DSPs
984 */
985 if ((!strcmp(dev_name(&pdev->dev), "40d01000.mmu")) ||
986 (!strcmp(dev_name(&pdev->dev), "41501000.mmu")))
987 return true;
988
989 return false;
990}
991
Suman Anna3ca92992015-10-02 18:02:44 -0500992static int omap_iommu_dra7_get_dsp_system_cfg(struct platform_device *pdev,
993 struct omap_iommu *obj)
994{
995 struct device_node *np = pdev->dev.of_node;
996 int ret;
997
998 if (!of_device_is_compatible(np, "ti,dra7-dsp-iommu"))
999 return 0;
1000
1001 if (!of_property_read_bool(np, "ti,syscon-mmuconfig")) {
1002 dev_err(&pdev->dev, "ti,syscon-mmuconfig property is missing\n");
1003 return -EINVAL;
1004 }
1005
1006 obj->syscfg =
1007 syscon_regmap_lookup_by_phandle(np, "ti,syscon-mmuconfig");
1008 if (IS_ERR(obj->syscfg)) {
1009 /* can fail with -EPROBE_DEFER */
1010 ret = PTR_ERR(obj->syscfg);
1011 return ret;
1012 }
1013
1014 if (of_property_read_u32_index(np, "ti,syscon-mmuconfig", 1,
1015 &obj->id)) {
1016 dev_err(&pdev->dev, "couldn't get the IOMMU instance id within subsystem\n");
1017 return -EINVAL;
1018 }
1019
1020 if (obj->id != 0 && obj->id != 1) {
1021 dev_err(&pdev->dev, "invalid IOMMU instance id\n");
1022 return -EINVAL;
1023 }
1024
1025 return 0;
1026}
1027
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +02001028/*
1029 * OMAP Device MMU(IOMMU) detection
1030 */
Greg Kroah-Hartmand34d6512012-12-21 15:05:21 -08001031static int omap_iommu_probe(struct platform_device *pdev)
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +02001032{
1033 int err = -ENODEV;
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +02001034 int irq;
Ohad Ben-Cohen6c32df42011-08-17 22:57:56 +03001035 struct omap_iommu *obj;
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +02001036 struct resource *res;
Florian Vaussard3c927482014-02-28 14:42:36 -06001037 struct device_node *of = pdev->dev.of_node;
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +02001038
Suman Anna49a57ef2017-04-12 00:21:27 -05001039 if (!of) {
1040 pr_err("%s: only DT-based devices are supported\n", __func__);
1041 return -ENODEV;
1042 }
1043
Suman Annaf129b3d2014-02-28 14:42:32 -06001044 obj = devm_kzalloc(&pdev->dev, sizeof(*obj) + MMU_REG_SIZE, GFP_KERNEL);
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +02001045 if (!obj)
1046 return -ENOMEM;
1047
Suman Annadb8918f2019-08-07 11:26:47 +03001048 /*
1049 * self-manage the ordering dependencies between omap_device_enable/idle
1050 * and omap_device_assert/deassert_hardreset API
1051 */
1052 if (pdev->dev.pm_domain) {
1053 dev_dbg(&pdev->dev, "device pm_domain is being reset\n");
1054 pdev->dev.pm_domain = NULL;
1055 }
1056
Suman Anna49a57ef2017-04-12 00:21:27 -05001057 obj->name = dev_name(&pdev->dev);
1058 obj->nr_tlb_entries = 32;
1059 err = of_property_read_u32(of, "ti,#tlb-entries", &obj->nr_tlb_entries);
1060 if (err && err != -EINVAL)
1061 return err;
1062 if (obj->nr_tlb_entries != 32 && obj->nr_tlb_entries != 8)
1063 return -EINVAL;
1064 if (of_find_property(of, "ti,iommu-bus-err-back", NULL))
1065 obj->has_bus_err_back = MMU_GP_REG_BUS_ERR_BACK_EN;
Florian Vaussard3c927482014-02-28 14:42:36 -06001066
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +02001067 obj->dev = &pdev->dev;
1068 obj->ctx = (void *)obj + sizeof(*obj);
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +02001069
Ohad Ben-Cohenf626b522011-06-02 01:46:12 +03001070 spin_lock_init(&obj->iommu_lock);
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +02001071 spin_lock_init(&obj->page_table_lock);
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +02001072
1073 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
Suman Annaf129b3d2014-02-28 14:42:32 -06001074 obj->regbase = devm_ioremap_resource(obj->dev, res);
1075 if (IS_ERR(obj->regbase))
1076 return PTR_ERR(obj->regbase);
Aaro Koskinenda4a0f72011-03-14 12:28:32 +00001077
Suman Anna3ca92992015-10-02 18:02:44 -05001078 err = omap_iommu_dra7_get_dsp_system_cfg(pdev, obj);
1079 if (err)
1080 return err;
1081
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +02001082 irq = platform_get_irq(pdev, 0);
Suman Annaf129b3d2014-02-28 14:42:32 -06001083 if (irq < 0)
1084 return -ENODEV;
1085
1086 err = devm_request_irq(obj->dev, irq, iommu_fault_handler, IRQF_SHARED,
1087 dev_name(obj->dev), obj);
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +02001088 if (err < 0)
Suman Annaf129b3d2014-02-28 14:42:32 -06001089 return err;
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +02001090 platform_set_drvdata(pdev, obj);
1091
Suman Anna9d5018d2017-09-05 17:56:18 -05001092 if (omap_iommu_can_register(pdev)) {
1093 obj->group = iommu_group_alloc();
1094 if (IS_ERR(obj->group))
1095 return PTR_ERR(obj->group);
Joerg Roedel28ae1e32017-04-12 00:21:31 -05001096
Suman Anna9d5018d2017-09-05 17:56:18 -05001097 err = iommu_device_sysfs_add(&obj->iommu, obj->dev, NULL,
1098 obj->name);
1099 if (err)
1100 goto out_group;
Joerg Roedel01611fe2017-04-12 00:21:30 -05001101
Suman Anna9d5018d2017-09-05 17:56:18 -05001102 iommu_device_set_ops(&obj->iommu, &omap_iommu_ops);
Joerg Roedel01611fe2017-04-12 00:21:30 -05001103
Suman Anna9d5018d2017-09-05 17:56:18 -05001104 err = iommu_device_register(&obj->iommu);
1105 if (err)
1106 goto out_sysfs;
1107 }
Joerg Roedel01611fe2017-04-12 00:21:30 -05001108
Omar Ramirez Lunaebf7cda2012-11-19 19:05:51 -06001109 pm_runtime_irq_safe(obj->dev);
1110 pm_runtime_enable(obj->dev);
1111
Suman Anna61c75352014-10-22 17:22:30 -05001112 omap_iommu_debugfs_add(obj);
1113
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +02001114 dev_info(&pdev->dev, "%s registered\n", obj->name);
Joerg Roedel28ae1e32017-04-12 00:21:31 -05001115
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +02001116 return 0;
Joerg Roedel01611fe2017-04-12 00:21:30 -05001117
1118out_sysfs:
1119 iommu_device_sysfs_remove(&obj->iommu);
Joerg Roedel28ae1e32017-04-12 00:21:31 -05001120out_group:
1121 iommu_group_put(obj->group);
Joerg Roedel01611fe2017-04-12 00:21:30 -05001122 return err;
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +02001123}
1124
Greg Kroah-Hartmand34d6512012-12-21 15:05:21 -08001125static int omap_iommu_remove(struct platform_device *pdev)
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +02001126{
Ohad Ben-Cohen6c32df42011-08-17 22:57:56 +03001127 struct omap_iommu *obj = platform_get_drvdata(pdev);
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +02001128
Suman Anna9d5018d2017-09-05 17:56:18 -05001129 if (obj->group) {
1130 iommu_group_put(obj->group);
1131 obj->group = NULL;
Joerg Roedel28ae1e32017-04-12 00:21:31 -05001132
Suman Anna9d5018d2017-09-05 17:56:18 -05001133 iommu_device_sysfs_remove(&obj->iommu);
1134 iommu_device_unregister(&obj->iommu);
1135 }
Joerg Roedel01611fe2017-04-12 00:21:30 -05001136
Suman Anna61c75352014-10-22 17:22:30 -05001137 omap_iommu_debugfs_remove(obj);
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +02001138
Omar Ramirez Lunaebf7cda2012-11-19 19:05:51 -06001139 pm_runtime_disable(obj->dev);
1140
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +02001141 dev_info(&pdev->dev, "%s removed\n", obj->name);
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +02001142 return 0;
1143}
1144
Suman Annadb8918f2019-08-07 11:26:47 +03001145static const struct dev_pm_ops omap_iommu_pm_ops = {
1146 SET_RUNTIME_PM_OPS(omap_iommu_runtime_suspend,
1147 omap_iommu_runtime_resume, NULL)
1148};
1149
Kiran Padwald943b0f2014-09-11 19:07:36 +05301150static const struct of_device_id omap_iommu_of_match[] = {
Florian Vaussard3c927482014-02-28 14:42:36 -06001151 { .compatible = "ti,omap2-iommu" },
1152 { .compatible = "ti,omap4-iommu" },
1153 { .compatible = "ti,dra7-iommu" },
Suman Anna3ca92992015-10-02 18:02:44 -05001154 { .compatible = "ti,dra7-dsp-iommu" },
Florian Vaussard3c927482014-02-28 14:42:36 -06001155 {},
1156};
Florian Vaussard3c927482014-02-28 14:42:36 -06001157
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +02001158static struct platform_driver omap_iommu_driver = {
1159 .probe = omap_iommu_probe,
Greg Kroah-Hartmand34d6512012-12-21 15:05:21 -08001160 .remove = omap_iommu_remove,
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +02001161 .driver = {
1162 .name = "omap-iommu",
Suman Annadb8918f2019-08-07 11:26:47 +03001163 .pm = &omap_iommu_pm_ops,
Florian Vaussard3c927482014-02-28 14:42:36 -06001164 .of_match_table = of_match_ptr(omap_iommu_of_match),
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +02001165 },
1166};
1167
Laurent Pinchart286f6002014-03-08 00:44:38 +01001168static u32 iotlb_init_entry(struct iotlb_entry *e, u32 da, u32 pa, int pgsz)
Tony Lindgrened1c7de2012-11-02 12:24:06 -07001169{
1170 memset(e, 0, sizeof(*e));
1171
1172 e->da = da;
1173 e->pa = pa;
Suman Annad760e3e2014-03-17 20:31:32 -05001174 e->valid = MMU_CAM_V;
Laurent Pinchart286f6002014-03-08 00:44:38 +01001175 e->pgsz = pgsz;
1176 e->endian = MMU_RAM_ENDIAN_LITTLE;
1177 e->elsz = MMU_RAM_ELSZ_8;
1178 e->mixed = 0;
Tony Lindgrened1c7de2012-11-02 12:24:06 -07001179
1180 return iopgsz_to_bytes(e->pgsz);
1181}
1182
Ohad Ben-Cohenf626b522011-06-02 01:46:12 +03001183static int omap_iommu_map(struct iommu_domain *domain, unsigned long da,
Suman Anna5835b6a2015-07-20 17:33:32 -05001184 phys_addr_t pa, size_t bytes, int prot)
Ohad Ben-Cohenf626b522011-06-02 01:46:12 +03001185{
Joerg Roedel8cf851e2015-03-26 13:43:09 +01001186 struct omap_iommu_domain *omap_domain = to_omap_domain(domain);
Suman Anna9d5018d2017-09-05 17:56:18 -05001187 struct device *dev = omap_domain->dev;
1188 struct omap_iommu_device *iommu;
1189 struct omap_iommu *oiommu;
Ohad Ben-Cohenf626b522011-06-02 01:46:12 +03001190 struct iotlb_entry e;
1191 int omap_pgsz;
Suman Anna9d5018d2017-09-05 17:56:18 -05001192 u32 ret = -EINVAL;
1193 int i;
Ohad Ben-Cohenf626b522011-06-02 01:46:12 +03001194
Ohad Ben-Cohenf626b522011-06-02 01:46:12 +03001195 omap_pgsz = bytes_to_iopgsz(bytes);
1196 if (omap_pgsz < 0) {
1197 dev_err(dev, "invalid size to map: %d\n", bytes);
1198 return -EINVAL;
1199 }
1200
Joerg Roedel1d7f4492015-01-22 14:42:06 +01001201 dev_dbg(dev, "mapping da 0x%lx to pa %pa size 0x%x\n", da, &pa, bytes);
Ohad Ben-Cohenf626b522011-06-02 01:46:12 +03001202
Laurent Pinchart286f6002014-03-08 00:44:38 +01001203 iotlb_init_entry(&e, da, pa, omap_pgsz);
Ohad Ben-Cohenf626b522011-06-02 01:46:12 +03001204
Suman Anna9d5018d2017-09-05 17:56:18 -05001205 iommu = omap_domain->iommus;
1206 for (i = 0; i < omap_domain->num_iommus; i++, iommu++) {
1207 oiommu = iommu->iommu_dev;
1208 ret = omap_iopgtable_store_entry(oiommu, &e);
1209 if (ret) {
1210 dev_err(dev, "omap_iopgtable_store_entry failed: %d\n",
1211 ret);
1212 break;
1213 }
1214 }
1215
1216 if (ret) {
1217 while (i--) {
1218 iommu--;
1219 oiommu = iommu->iommu_dev;
1220 iopgtable_clear_entry(oiommu, da);
1221 }
1222 }
Ohad Ben-Cohenf626b522011-06-02 01:46:12 +03001223
Ohad Ben-Cohenb4550d42011-09-02 13:32:31 -04001224 return ret;
Ohad Ben-Cohenf626b522011-06-02 01:46:12 +03001225}
1226
Ohad Ben-Cohen50090652011-11-10 11:32:25 +02001227static size_t omap_iommu_unmap(struct iommu_domain *domain, unsigned long da,
Suman Anna5835b6a2015-07-20 17:33:32 -05001228 size_t size)
Ohad Ben-Cohenf626b522011-06-02 01:46:12 +03001229{
Joerg Roedel8cf851e2015-03-26 13:43:09 +01001230 struct omap_iommu_domain *omap_domain = to_omap_domain(domain);
Suman Anna9d5018d2017-09-05 17:56:18 -05001231 struct device *dev = omap_domain->dev;
1232 struct omap_iommu_device *iommu;
1233 struct omap_iommu *oiommu;
1234 bool error = false;
1235 size_t bytes = 0;
1236 int i;
Ohad Ben-Cohenf626b522011-06-02 01:46:12 +03001237
Ohad Ben-Cohen50090652011-11-10 11:32:25 +02001238 dev_dbg(dev, "unmapping da 0x%lx size %u\n", da, size);
Ohad Ben-Cohenf626b522011-06-02 01:46:12 +03001239
Suman Anna9d5018d2017-09-05 17:56:18 -05001240 iommu = omap_domain->iommus;
1241 for (i = 0; i < omap_domain->num_iommus; i++, iommu++) {
1242 oiommu = iommu->iommu_dev;
1243 bytes = iopgtable_clear_entry(oiommu, da);
1244 if (!bytes)
1245 error = true;
1246 }
1247
1248 /*
1249 * simplify return - we are only checking if any of the iommus
1250 * reported an error, but not if all of them are unmapping the
1251 * same number of entries. This should not occur due to the
1252 * mirror programming.
1253 */
1254 return error ? 0 : bytes;
1255}
1256
1257static int omap_iommu_count(struct device *dev)
1258{
1259 struct omap_iommu_arch_data *arch_data = dev->archdata.iommu;
1260 int count = 0;
1261
1262 while (arch_data->iommu_dev) {
1263 count++;
1264 arch_data++;
1265 }
1266
1267 return count;
1268}
1269
1270/* caller should call cleanup if this function fails */
1271static int omap_iommu_attach_init(struct device *dev,
1272 struct omap_iommu_domain *odomain)
1273{
1274 struct omap_iommu_device *iommu;
1275 int i;
1276
1277 odomain->num_iommus = omap_iommu_count(dev);
1278 if (!odomain->num_iommus)
1279 return -EINVAL;
1280
1281 odomain->iommus = kcalloc(odomain->num_iommus, sizeof(*iommu),
1282 GFP_ATOMIC);
1283 if (!odomain->iommus)
1284 return -ENOMEM;
1285
1286 iommu = odomain->iommus;
1287 for (i = 0; i < odomain->num_iommus; i++, iommu++) {
1288 iommu->pgtable = kzalloc(IOPGD_TABLE_SIZE, GFP_ATOMIC);
1289 if (!iommu->pgtable)
1290 return -ENOMEM;
1291
1292 /*
1293 * should never fail, but please keep this around to ensure
1294 * we keep the hardware happy
1295 */
1296 if (WARN_ON(!IS_ALIGNED((long)iommu->pgtable,
1297 IOPGD_TABLE_SIZE)))
1298 return -EINVAL;
1299 }
1300
1301 return 0;
1302}
1303
1304static void omap_iommu_detach_fini(struct omap_iommu_domain *odomain)
1305{
1306 int i;
1307 struct omap_iommu_device *iommu = odomain->iommus;
1308
1309 for (i = 0; iommu && i < odomain->num_iommus; i++, iommu++)
1310 kfree(iommu->pgtable);
1311
1312 kfree(odomain->iommus);
1313 odomain->num_iommus = 0;
1314 odomain->iommus = NULL;
Ohad Ben-Cohenf626b522011-06-02 01:46:12 +03001315}
1316
1317static int
1318omap_iommu_attach_dev(struct iommu_domain *domain, struct device *dev)
1319{
Joerg Roedel8cf851e2015-03-26 13:43:09 +01001320 struct omap_iommu_domain *omap_domain = to_omap_domain(domain);
Ohad Ben-Cohenfabdbca2011-10-11 00:18:33 +02001321 struct omap_iommu_arch_data *arch_data = dev->archdata.iommu;
Suman Anna9d5018d2017-09-05 17:56:18 -05001322 struct omap_iommu_device *iommu;
Joerg Roedelede1c2e2017-04-12 00:21:29 -05001323 struct omap_iommu *oiommu;
Ohad Ben-Cohenf626b522011-06-02 01:46:12 +03001324 int ret = 0;
Suman Anna9d5018d2017-09-05 17:56:18 -05001325 int i;
Ohad Ben-Cohenf626b522011-06-02 01:46:12 +03001326
Joerg Roedelede1c2e2017-04-12 00:21:29 -05001327 if (!arch_data || !arch_data->iommu_dev) {
Suman Annae3f595b2014-09-04 17:27:29 -05001328 dev_err(dev, "device doesn't have an associated iommu\n");
1329 return -EINVAL;
1330 }
1331
Ohad Ben-Cohenf626b522011-06-02 01:46:12 +03001332 spin_lock(&omap_domain->lock);
1333
Suman Anna0d364282017-09-05 17:56:17 -05001334 /* only a single client device can be attached to a domain */
1335 if (omap_domain->dev) {
Ohad Ben-Cohenf626b522011-06-02 01:46:12 +03001336 dev_err(dev, "iommu domain is already attached\n");
1337 ret = -EBUSY;
1338 goto out;
1339 }
1340
Suman Anna9d5018d2017-09-05 17:56:18 -05001341 ret = omap_iommu_attach_init(dev, omap_domain);
Joerg Roedelede1c2e2017-04-12 00:21:29 -05001342 if (ret) {
Suman Anna9d5018d2017-09-05 17:56:18 -05001343 dev_err(dev, "failed to allocate required iommu data %d\n",
1344 ret);
1345 goto init_fail;
Ohad Ben-Cohenf626b522011-06-02 01:46:12 +03001346 }
1347
Suman Anna9d5018d2017-09-05 17:56:18 -05001348 iommu = omap_domain->iommus;
1349 for (i = 0; i < omap_domain->num_iommus; i++, iommu++, arch_data++) {
1350 /* configure and enable the omap iommu */
1351 oiommu = arch_data->iommu_dev;
1352 ret = omap_iommu_attach(oiommu, iommu->pgtable);
1353 if (ret) {
1354 dev_err(dev, "can't get omap iommu: %d\n", ret);
1355 goto attach_fail;
1356 }
Ohad Ben-Cohenf626b522011-06-02 01:46:12 +03001357
Suman Anna9d5018d2017-09-05 17:56:18 -05001358 oiommu->domain = domain;
1359 iommu->iommu_dev = oiommu;
1360 }
1361
1362 omap_domain->dev = dev;
1363
1364 goto out;
1365
1366attach_fail:
1367 while (i--) {
1368 iommu--;
1369 arch_data--;
1370 oiommu = iommu->iommu_dev;
1371 omap_iommu_detach(oiommu);
1372 iommu->iommu_dev = NULL;
1373 oiommu->domain = NULL;
1374 }
1375init_fail:
1376 omap_iommu_detach_fini(omap_domain);
Ohad Ben-Cohenf626b522011-06-02 01:46:12 +03001377out:
1378 spin_unlock(&omap_domain->lock);
1379 return ret;
1380}
1381
Omar Ramirez Luna803b5272012-04-18 13:09:41 -05001382static void _omap_iommu_detach_dev(struct omap_iommu_domain *omap_domain,
Suman Anna5835b6a2015-07-20 17:33:32 -05001383 struct device *dev)
Ohad Ben-Cohenf626b522011-06-02 01:46:12 +03001384{
Suman Anna9d5018d2017-09-05 17:56:18 -05001385 struct omap_iommu_arch_data *arch_data = dev->archdata.iommu;
1386 struct omap_iommu_device *iommu = omap_domain->iommus;
1387 struct omap_iommu *oiommu;
1388 int i;
Ohad Ben-Cohenf626b522011-06-02 01:46:12 +03001389
Suman Anna0d364282017-09-05 17:56:17 -05001390 if (!omap_domain->dev) {
1391 dev_err(dev, "domain has no attached device\n");
1392 return;
1393 }
1394
Ohad Ben-Cohenf626b522011-06-02 01:46:12 +03001395 /* only a single device is supported per domain for now */
Suman Anna0d364282017-09-05 17:56:17 -05001396 if (omap_domain->dev != dev) {
1397 dev_err(dev, "invalid attached device\n");
Omar Ramirez Luna803b5272012-04-18 13:09:41 -05001398 return;
Ohad Ben-Cohenf626b522011-06-02 01:46:12 +03001399 }
1400
Suman Anna9d5018d2017-09-05 17:56:18 -05001401 /*
1402 * cleanup in the reverse order of attachment - this addresses
1403 * any h/w dependencies between multiple instances, if any
1404 */
1405 iommu += (omap_domain->num_iommus - 1);
1406 arch_data += (omap_domain->num_iommus - 1);
1407 for (i = 0; i < omap_domain->num_iommus; i++, iommu--, arch_data--) {
1408 oiommu = iommu->iommu_dev;
1409 iopgtable_clear_entry_all(oiommu);
Ohad Ben-Cohenf626b522011-06-02 01:46:12 +03001410
Suman Anna9d5018d2017-09-05 17:56:18 -05001411 omap_iommu_detach(oiommu);
1412 iommu->iommu_dev = NULL;
1413 oiommu->domain = NULL;
1414 }
Ohad Ben-Cohenf626b522011-06-02 01:46:12 +03001415
Suman Anna9d5018d2017-09-05 17:56:18 -05001416 omap_iommu_detach_fini(omap_domain);
1417
Omar Ramirez Luna803b5272012-04-18 13:09:41 -05001418 omap_domain->dev = NULL;
1419}
Ohad Ben-Cohenf626b522011-06-02 01:46:12 +03001420
Omar Ramirez Luna803b5272012-04-18 13:09:41 -05001421static void omap_iommu_detach_dev(struct iommu_domain *domain,
Suman Anna5835b6a2015-07-20 17:33:32 -05001422 struct device *dev)
Omar Ramirez Luna803b5272012-04-18 13:09:41 -05001423{
Joerg Roedel8cf851e2015-03-26 13:43:09 +01001424 struct omap_iommu_domain *omap_domain = to_omap_domain(domain);
Omar Ramirez Luna803b5272012-04-18 13:09:41 -05001425
1426 spin_lock(&omap_domain->lock);
1427 _omap_iommu_detach_dev(omap_domain, dev);
Ohad Ben-Cohenf626b522011-06-02 01:46:12 +03001428 spin_unlock(&omap_domain->lock);
1429}
1430
Joerg Roedel8cf851e2015-03-26 13:43:09 +01001431static struct iommu_domain *omap_iommu_domain_alloc(unsigned type)
Ohad Ben-Cohenf626b522011-06-02 01:46:12 +03001432{
1433 struct omap_iommu_domain *omap_domain;
1434
Joerg Roedel8cf851e2015-03-26 13:43:09 +01001435 if (type != IOMMU_DOMAIN_UNMANAGED)
1436 return NULL;
1437
Ohad Ben-Cohenf626b522011-06-02 01:46:12 +03001438 omap_domain = kzalloc(sizeof(*omap_domain), GFP_KERNEL);
Suman Anna99ee98d2015-07-20 17:33:29 -05001439 if (!omap_domain)
Suman Anna9d5018d2017-09-05 17:56:18 -05001440 return NULL;
Ohad Ben-Cohenf626b522011-06-02 01:46:12 +03001441
Ohad Ben-Cohenf626b522011-06-02 01:46:12 +03001442 spin_lock_init(&omap_domain->lock);
1443
Joerg Roedel8cf851e2015-03-26 13:43:09 +01001444 omap_domain->domain.geometry.aperture_start = 0;
1445 omap_domain->domain.geometry.aperture_end = (1ULL << 32) - 1;
1446 omap_domain->domain.geometry.force_aperture = true;
Ohad Ben-Cohenf626b522011-06-02 01:46:12 +03001447
Joerg Roedel8cf851e2015-03-26 13:43:09 +01001448 return &omap_domain->domain;
Ohad Ben-Cohenf626b522011-06-02 01:46:12 +03001449}
1450
Joerg Roedel8cf851e2015-03-26 13:43:09 +01001451static void omap_iommu_domain_free(struct iommu_domain *domain)
Ohad Ben-Cohenf626b522011-06-02 01:46:12 +03001452{
Joerg Roedel8cf851e2015-03-26 13:43:09 +01001453 struct omap_iommu_domain *omap_domain = to_omap_domain(domain);
Ohad Ben-Cohenf626b522011-06-02 01:46:12 +03001454
Omar Ramirez Luna803b5272012-04-18 13:09:41 -05001455 /*
1456 * An iommu device is still attached
1457 * (currently, only one device can be attached) ?
1458 */
Suman Anna0d364282017-09-05 17:56:17 -05001459 if (omap_domain->dev)
Omar Ramirez Luna803b5272012-04-18 13:09:41 -05001460 _omap_iommu_detach_dev(omap_domain, omap_domain->dev);
1461
Ohad Ben-Cohenf626b522011-06-02 01:46:12 +03001462 kfree(omap_domain);
1463}
1464
1465static phys_addr_t omap_iommu_iova_to_phys(struct iommu_domain *domain,
Suman Anna5835b6a2015-07-20 17:33:32 -05001466 dma_addr_t da)
Ohad Ben-Cohenf626b522011-06-02 01:46:12 +03001467{
Joerg Roedel8cf851e2015-03-26 13:43:09 +01001468 struct omap_iommu_domain *omap_domain = to_omap_domain(domain);
Suman Anna9d5018d2017-09-05 17:56:18 -05001469 struct omap_iommu_device *iommu = omap_domain->iommus;
1470 struct omap_iommu *oiommu = iommu->iommu_dev;
Ohad Ben-Cohenf626b522011-06-02 01:46:12 +03001471 struct device *dev = oiommu->dev;
1472 u32 *pgd, *pte;
1473 phys_addr_t ret = 0;
1474
Suman Anna9d5018d2017-09-05 17:56:18 -05001475 /*
1476 * all the iommus within the domain will have identical programming,
1477 * so perform the lookup using just the first iommu
1478 */
Ohad Ben-Cohenf626b522011-06-02 01:46:12 +03001479 iopgtable_lookup_entry(oiommu, da, &pgd, &pte);
1480
1481 if (pte) {
1482 if (iopte_is_small(*pte))
1483 ret = omap_iommu_translate(*pte, da, IOPTE_MASK);
1484 else if (iopte_is_large(*pte))
1485 ret = omap_iommu_translate(*pte, da, IOLARGE_MASK);
1486 else
Suman Anna2abfcfb2013-05-30 18:10:38 -05001487 dev_err(dev, "bogus pte 0x%x, da 0x%llx", *pte,
Suman Anna5835b6a2015-07-20 17:33:32 -05001488 (unsigned long long)da);
Ohad Ben-Cohenf626b522011-06-02 01:46:12 +03001489 } else {
1490 if (iopgd_is_section(*pgd))
1491 ret = omap_iommu_translate(*pgd, da, IOSECTION_MASK);
1492 else if (iopgd_is_super(*pgd))
1493 ret = omap_iommu_translate(*pgd, da, IOSUPER_MASK);
1494 else
Suman Anna2abfcfb2013-05-30 18:10:38 -05001495 dev_err(dev, "bogus pgd 0x%x, da 0x%llx", *pgd,
Suman Anna5835b6a2015-07-20 17:33:32 -05001496 (unsigned long long)da);
Ohad Ben-Cohenf626b522011-06-02 01:46:12 +03001497 }
1498
1499 return ret;
1500}
1501
Laurent Pinchart07a02032014-02-28 14:42:38 -06001502static int omap_iommu_add_device(struct device *dev)
1503{
Suman Anna9d5018d2017-09-05 17:56:18 -05001504 struct omap_iommu_arch_data *arch_data, *tmp;
Joerg Roedelede1c2e2017-04-12 00:21:29 -05001505 struct omap_iommu *oiommu;
Joerg Roedel28ae1e32017-04-12 00:21:31 -05001506 struct iommu_group *group;
Laurent Pinchart07a02032014-02-28 14:42:38 -06001507 struct device_node *np;
Suman Anna7d682772014-09-04 17:27:30 -05001508 struct platform_device *pdev;
Suman Anna9d5018d2017-09-05 17:56:18 -05001509 int num_iommus, i;
Joerg Roedel01611fe2017-04-12 00:21:30 -05001510 int ret;
Laurent Pinchart07a02032014-02-28 14:42:38 -06001511
1512 /*
1513 * Allocate the archdata iommu structure for DT-based devices.
1514 *
1515 * TODO: Simplify this when removing non-DT support completely from the
1516 * IOMMU users.
1517 */
1518 if (!dev->of_node)
1519 return 0;
1520
Suman Anna9d5018d2017-09-05 17:56:18 -05001521 /*
1522 * retrieve the count of IOMMU nodes using phandle size as element size
1523 * since #iommu-cells = 0 for OMAP
1524 */
1525 num_iommus = of_property_count_elems_of_size(dev->of_node, "iommus",
1526 sizeof(phandle));
1527 if (num_iommus < 0)
Laurent Pinchart07a02032014-02-28 14:42:38 -06001528 return 0;
1529
Kees Cook6396bb22018-06-12 14:03:40 -07001530 arch_data = kcalloc(num_iommus + 1, sizeof(*arch_data), GFP_KERNEL);
Suman Anna9d5018d2017-09-05 17:56:18 -05001531 if (!arch_data)
Laurent Pinchart07a02032014-02-28 14:42:38 -06001532 return -ENOMEM;
Suman Anna9d5018d2017-09-05 17:56:18 -05001533
1534 for (i = 0, tmp = arch_data; i < num_iommus; i++, tmp++) {
1535 np = of_parse_phandle(dev->of_node, "iommus", i);
1536 if (!np) {
1537 kfree(arch_data);
1538 return -EINVAL;
1539 }
1540
1541 pdev = of_find_device_by_node(np);
1542 if (WARN_ON(!pdev)) {
1543 of_node_put(np);
1544 kfree(arch_data);
1545 return -EINVAL;
1546 }
1547
1548 oiommu = platform_get_drvdata(pdev);
1549 if (!oiommu) {
1550 of_node_put(np);
1551 kfree(arch_data);
1552 return -EINVAL;
1553 }
1554
1555 tmp->iommu_dev = oiommu;
1556
1557 of_node_put(np);
Laurent Pinchart07a02032014-02-28 14:42:38 -06001558 }
1559
Suman Anna9d5018d2017-09-05 17:56:18 -05001560 /*
1561 * use the first IOMMU alone for the sysfs device linking.
1562 * TODO: Evaluate if a single iommu_group needs to be
1563 * maintained for both IOMMUs
1564 */
1565 oiommu = arch_data->iommu_dev;
Joerg Roedel01611fe2017-04-12 00:21:30 -05001566 ret = iommu_device_link(&oiommu->iommu, dev);
1567 if (ret) {
1568 kfree(arch_data);
Joerg Roedel01611fe2017-04-12 00:21:30 -05001569 return ret;
1570 }
1571
Laurent Pinchart07a02032014-02-28 14:42:38 -06001572 dev->archdata.iommu = arch_data;
1573
Joerg Roedel28ae1e32017-04-12 00:21:31 -05001574 /*
1575 * IOMMU group initialization calls into omap_iommu_device_group, which
1576 * needs a valid dev->archdata.iommu pointer
1577 */
1578 group = iommu_group_get_for_dev(dev);
1579 if (IS_ERR(group)) {
1580 iommu_device_unlink(&oiommu->iommu, dev);
1581 dev->archdata.iommu = NULL;
1582 kfree(arch_data);
1583 return PTR_ERR(group);
1584 }
1585 iommu_group_put(group);
1586
Laurent Pinchart07a02032014-02-28 14:42:38 -06001587 return 0;
1588}
1589
1590static void omap_iommu_remove_device(struct device *dev)
1591{
1592 struct omap_iommu_arch_data *arch_data = dev->archdata.iommu;
1593
1594 if (!dev->of_node || !arch_data)
1595 return;
1596
Joerg Roedel01611fe2017-04-12 00:21:30 -05001597 iommu_device_unlink(&arch_data->iommu_dev->iommu, dev);
Joerg Roedel28ae1e32017-04-12 00:21:31 -05001598 iommu_group_remove_device(dev);
Joerg Roedel01611fe2017-04-12 00:21:30 -05001599
Joerg Roedelede1c2e2017-04-12 00:21:29 -05001600 dev->archdata.iommu = NULL;
Laurent Pinchart07a02032014-02-28 14:42:38 -06001601 kfree(arch_data);
Joerg Roedel01611fe2017-04-12 00:21:30 -05001602
Laurent Pinchart07a02032014-02-28 14:42:38 -06001603}
1604
Joerg Roedel28ae1e32017-04-12 00:21:31 -05001605static struct iommu_group *omap_iommu_device_group(struct device *dev)
1606{
1607 struct omap_iommu_arch_data *arch_data = dev->archdata.iommu;
Joerg Roedel8faf5e52017-06-28 12:50:16 +02001608 struct iommu_group *group = ERR_PTR(-EINVAL);
Joerg Roedel28ae1e32017-04-12 00:21:31 -05001609
1610 if (arch_data->iommu_dev)
Jeffy Chenb6d57f12018-03-01 19:22:08 +08001611 group = iommu_group_ref_get(arch_data->iommu_dev->group);
Joerg Roedel28ae1e32017-04-12 00:21:31 -05001612
1613 return group;
1614}
1615
Thierry Redingb22f6432014-06-27 09:03:12 +02001616static const struct iommu_ops omap_iommu_ops = {
Joerg Roedel8cf851e2015-03-26 13:43:09 +01001617 .domain_alloc = omap_iommu_domain_alloc,
1618 .domain_free = omap_iommu_domain_free,
Ohad Ben-Cohenf626b522011-06-02 01:46:12 +03001619 .attach_dev = omap_iommu_attach_dev,
1620 .detach_dev = omap_iommu_detach_dev,
1621 .map = omap_iommu_map,
1622 .unmap = omap_iommu_unmap,
1623 .iova_to_phys = omap_iommu_iova_to_phys,
Laurent Pinchart07a02032014-02-28 14:42:38 -06001624 .add_device = omap_iommu_add_device,
1625 .remove_device = omap_iommu_remove_device,
Joerg Roedel28ae1e32017-04-12 00:21:31 -05001626 .device_group = omap_iommu_device_group,
Ohad Ben-Cohen66bc8cf2011-11-10 11:32:27 +02001627 .pgsize_bitmap = OMAP_IOMMU_PGSIZES,
Ohad Ben-Cohenf626b522011-06-02 01:46:12 +03001628};
1629
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +02001630static int __init omap_iommu_init(void)
1631{
1632 struct kmem_cache *p;
1633 const unsigned long flags = SLAB_HWCACHE_ALIGN;
1634 size_t align = 1 << 10; /* L2 pagetable alignement */
Thierry Redingf938aab2015-02-06 11:44:06 +01001635 struct device_node *np;
Suman Annaabaa7e52017-04-12 00:21:26 -05001636 int ret;
Thierry Redingf938aab2015-02-06 11:44:06 +01001637
1638 np = of_find_matching_node(NULL, omap_iommu_of_match);
1639 if (!np)
1640 return 0;
1641
1642 of_node_put(np);
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +02001643
1644 p = kmem_cache_create("iopte_cache", IOPTE_TABLE_SIZE, align, flags,
Josue Albarranbfee0cf2017-07-28 15:49:14 -05001645 NULL);
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +02001646 if (!p)
1647 return -ENOMEM;
1648 iopte_cachep = p;
1649
Suman Anna61c75352014-10-22 17:22:30 -05001650 omap_iommu_debugfs_init();
1651
Suman Annaabaa7e52017-04-12 00:21:26 -05001652 ret = platform_driver_register(&omap_iommu_driver);
1653 if (ret) {
1654 pr_err("%s: failed to register driver\n", __func__);
1655 goto fail_driver;
1656 }
1657
1658 ret = bus_set_iommu(&platform_bus_type, &omap_iommu_ops);
1659 if (ret)
1660 goto fail_bus;
1661
1662 return 0;
1663
1664fail_bus:
1665 platform_driver_unregister(&omap_iommu_driver);
1666fail_driver:
1667 kmem_cache_destroy(iopte_cachep);
1668 return ret;
Hiroshi DOYUa9dcad52009-01-26 15:13:40 +02001669}
Ohad Ben-Cohen435792d2012-02-26 12:14:14 +02001670subsys_initcall(omap_iommu_init);
Suman Anna0cdbf722015-07-20 17:33:24 -05001671/* must be ready before omap3isp is probed */