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review.shift-gmbh.com / SHIFTPHONES / mainline / linux / 622d9ac3d969d0f62bbe68f4844bb5b8adea5a40 / . / sound / soc / codecs / wcd938x.c
blob: 5fd708e013f98bb7957ae53f8201a2f833b18b75 [file] [log] [blame]
Srinivas Kandagatla8d786022021-06-09 10:09:37 +0100[diff] [blame]1// SPDX-License-Identifier: GPL-2.0-only
2// Copyright (c) 2018-2020, The Linux Foundation. All rights reserved.
3
4#include <linux/module.h>
5#include <linux/slab.h>
6#include <linux/platform_device.h>
7#include <linux/device.h>
8#include <linux/delay.h>
9#include <linux/kernel.h>
10#include <linux/pm_runtime.h>
11#include <linux/component.h>
Srinivas Kandagatla8d786022021-06-09 10:09:37 +0100[diff] [blame]12#include <sound/tlv.h>
13#include <linux/of_gpio.h>
14#include <linux/of.h>
15#include <sound/jack.h>
16#include <sound/pcm.h>
17#include <sound/pcm_params.h>
18#include <linux/regmap.h>
19#include <sound/soc.h>
20#include <sound/soc-dapm.h>
21#include <linux/regulator/consumer.h>
22
23#include "wcd-clsh-v2.h"
24#include "wcd938x.h"
25
26#define WCD938X_MAX_MICBIAS (4)
27#define WCD938X_MAX_SUPPLY (4)
28#define WCD938X_MBHC_MAX_BUTTONS (8)
29#define TX_ADC_MAX (4)
30#define WCD938X_TX_MAX_SWR_PORTS (5)
31
32#define WCD938X_RATES_MASK (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |\
33 SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_48000 |\
34 SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_192000)
35/* Fractional Rates */
36#define WCD938X_FRAC_RATES_MASK (SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_88200 |\
37 SNDRV_PCM_RATE_176400)
38#define WCD938X_FORMATS_S16_S24_LE (SNDRV_PCM_FMTBIT_S16_LE | \
39 SNDRV_PCM_FMTBIT_S24_LE)
40/* Convert from vout ctl to micbias voltage in mV */
41#define WCD_VOUT_CTL_TO_MICB(v) (1000 + v * 50)
42#define SWR_CLK_RATE_0P6MHZ (600000)
43#define SWR_CLK_RATE_1P2MHZ (1200000)
44#define SWR_CLK_RATE_2P4MHZ (2400000)
45#define SWR_CLK_RATE_4P8MHZ (4800000)
46#define SWR_CLK_RATE_9P6MHZ (9600000)
47#define SWR_CLK_RATE_11P2896MHZ (1128960)
48
49#define WCD938X_DRV_NAME "wcd938x_codec"
50#define WCD938X_VERSION_1_0 (1)
51#define EAR_RX_PATH_AUX (1)
52
53#define ADC_MODE_VAL_HIFI 0x01
54#define ADC_MODE_VAL_LO_HIF 0x02
55#define ADC_MODE_VAL_NORMAL 0x03
56#define ADC_MODE_VAL_LP 0x05
57#define ADC_MODE_VAL_ULP1 0x09
58#define ADC_MODE_VAL_ULP2 0x0B
59
60/* Z value defined in milliohm */
61#define WCD938X_ZDET_VAL_32 (32000)
62#define WCD938X_ZDET_VAL_400 (400000)
63#define WCD938X_ZDET_VAL_1200 (1200000)
64#define WCD938X_ZDET_VAL_100K (100000000)
65/* Z floating defined in ohms */
66#define WCD938X_ZDET_FLOATING_IMPEDANCE (0x0FFFFFFE)
67#define WCD938X_ZDET_NUM_MEASUREMENTS (900)
68#define WCD938X_MBHC_GET_C1(c) ((c & 0xC000) >> 14)
69#define WCD938X_MBHC_GET_X1(x) (x & 0x3FFF)
70/* Z value compared in milliOhm */
71#define WCD938X_MBHC_IS_SECOND_RAMP_REQUIRED(z) ((z > 400000) || (z < 32000))
72#define WCD938X_MBHC_ZDET_CONST (86 * 16384)
73#define WCD938X_MBHC_MOISTURE_RREF R_24_KOHM
74#define WCD_MBHC_HS_V_MAX 1600
75
Srinivas Kandagatlae8ba1e02021-06-09 10:09:40 +0100[diff] [blame]76#define WCD938X_EAR_PA_GAIN_TLV(xname, reg, shift, max, invert, tlv_array) \
77{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
78 .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ |\
79 SNDRV_CTL_ELEM_ACCESS_READWRITE,\
80 .tlv.p = (tlv_array), \
81 .info = snd_soc_info_volsw, .get = snd_soc_get_volsw,\
82 .put = wcd938x_ear_pa_put_gain, \
83 .private_value = SOC_SINGLE_VALUE(reg, shift, max, invert, 0) }
84
Srinivas Kandagatla8d786022021-06-09 10:09:37 +0100[diff] [blame]85enum {
86 WCD9380 = 0,
87 WCD9385 = 5,
88};
89
90enum {
91 TX_HDR12 = 0,
92 TX_HDR34,
93 TX_HDR_MAX,
94};
95
96enum {
97 WCD_RX1,
98 WCD_RX2,
99 WCD_RX3
100};
101
102enum {
103 /* INTR_CTRL_INT_MASK_0 */
104 WCD938X_IRQ_MBHC_BUTTON_PRESS_DET = 0,
105 WCD938X_IRQ_MBHC_BUTTON_RELEASE_DET,
106 WCD938X_IRQ_MBHC_ELECT_INS_REM_DET,
107 WCD938X_IRQ_MBHC_ELECT_INS_REM_LEG_DET,
108 WCD938X_IRQ_MBHC_SW_DET,
109 WCD938X_IRQ_HPHR_OCP_INT,
110 WCD938X_IRQ_HPHR_CNP_INT,
111 WCD938X_IRQ_HPHL_OCP_INT,
112
113 /* INTR_CTRL_INT_MASK_1 */
114 WCD938X_IRQ_HPHL_CNP_INT,
115 WCD938X_IRQ_EAR_CNP_INT,
116 WCD938X_IRQ_EAR_SCD_INT,
117 WCD938X_IRQ_AUX_CNP_INT,
118 WCD938X_IRQ_AUX_SCD_INT,
119 WCD938X_IRQ_HPHL_PDM_WD_INT,
120 WCD938X_IRQ_HPHR_PDM_WD_INT,
121 WCD938X_IRQ_AUX_PDM_WD_INT,
122
123 /* INTR_CTRL_INT_MASK_2 */
124 WCD938X_IRQ_LDORT_SCD_INT,
125 WCD938X_IRQ_MBHC_MOISTURE_INT,
126 WCD938X_IRQ_HPHL_SURGE_DET_INT,
127 WCD938X_IRQ_HPHR_SURGE_DET_INT,
128 WCD938X_NUM_IRQS,
129};
130
131enum {
132 WCD_ADC1 = 0,
133 WCD_ADC2,
134 WCD_ADC3,
135 WCD_ADC4,
136 ALLOW_BUCK_DISABLE,
137 HPH_COMP_DELAY,
138 HPH_PA_DELAY,
139 AMIC2_BCS_ENABLE,
140 WCD_SUPPLIES_LPM_MODE,
141};
142
143enum {
144 ADC_MODE_INVALID = 0,
145 ADC_MODE_HIFI,
146 ADC_MODE_LO_HIF,
147 ADC_MODE_NORMAL,
148 ADC_MODE_LP,
149 ADC_MODE_ULP1,
150 ADC_MODE_ULP2,
151};
152
153enum {
154 AIF1_PB = 0,
155 AIF1_CAP,
156 NUM_CODEC_DAIS,
157};
158
Srinivas Kandagatlad5add082021-06-09 10:09:42 +0100[diff] [blame]159static u8 tx_mode_bit[] = {
160 [ADC_MODE_INVALID] = 0x00,
161 [ADC_MODE_HIFI] = 0x01,
162 [ADC_MODE_LO_HIF] = 0x02,
163 [ADC_MODE_NORMAL] = 0x04,
164 [ADC_MODE_LP] = 0x08,
165 [ADC_MODE_ULP1] = 0x10,
166 [ADC_MODE_ULP2] = 0x20,
167};
168
Srinivas Kandagatla8d786022021-06-09 10:09:37 +0100[diff] [blame]169struct wcd938x_priv {
170 struct sdw_slave *tx_sdw_dev;
171 struct wcd938x_sdw_priv *sdw_priv[NUM_CODEC_DAIS];
172 struct device *txdev;
173 struct device *rxdev;
174 struct device_node *rxnode, *txnode;
175 struct regmap *regmap;
176 struct wcd_clsh_ctrl *clsh_info;
177 struct irq_domain *virq;
178 struct regmap_irq_chip *wcd_regmap_irq_chip;
179 struct regmap_irq_chip_data *irq_chip;
180 struct regulator_bulk_data supplies[WCD938X_MAX_SUPPLY];
181 struct snd_soc_jack *jack;
182 unsigned long status_mask;
183 s32 micb_ref[WCD938X_MAX_MICBIAS];
184 s32 pullup_ref[WCD938X_MAX_MICBIAS];
185 u32 hph_mode;
186 u32 tx_mode[TX_ADC_MAX];
187 int flyback_cur_det_disable;
188 int ear_rx_path;
189 int variant;
190 int reset_gpio;
191 u32 micb1_mv;
192 u32 micb2_mv;
193 u32 micb3_mv;
194 u32 micb4_mv;
195 int hphr_pdm_wd_int;
196 int hphl_pdm_wd_int;
197 int aux_pdm_wd_int;
198 bool comp1_enable;
199 bool comp2_enable;
200 bool ldoh;
201 bool bcs_dis;
202};
203
204enum {
205 MIC_BIAS_1 = 1,
206 MIC_BIAS_2,
207 MIC_BIAS_3,
208 MIC_BIAS_4
209};
210
211enum {
212 MICB_PULLUP_ENABLE,
213 MICB_PULLUP_DISABLE,
214 MICB_ENABLE,
215 MICB_DISABLE,
216};
217
Srinivas Kandagatlae8ba1e02021-06-09 10:09:40 +0100[diff] [blame]218static const SNDRV_CTL_TLVD_DECLARE_DB_MINMAX(ear_pa_gain, 600, -1800);
219static const SNDRV_CTL_TLVD_DECLARE_DB_MINMAX(line_gain, 600, -3000);
220static const SNDRV_CTL_TLVD_DECLARE_DB_MINMAX(analog_gain, 0, 3000);
221
Srinivas Kandagatla8d786022021-06-09 10:09:37 +0100[diff] [blame]222static const struct reg_default wcd938x_defaults[] = {
223 {WCD938X_ANA_PAGE_REGISTER, 0x00},
224 {WCD938X_ANA_BIAS, 0x00},
225 {WCD938X_ANA_RX_SUPPLIES, 0x00},
226 {WCD938X_ANA_HPH, 0x0C},
227 {WCD938X_ANA_EAR, 0x00},
228 {WCD938X_ANA_EAR_COMPANDER_CTL, 0x02},
229 {WCD938X_ANA_TX_CH1, 0x20},
230 {WCD938X_ANA_TX_CH2, 0x00},
231 {WCD938X_ANA_TX_CH3, 0x20},
232 {WCD938X_ANA_TX_CH4, 0x00},
233 {WCD938X_ANA_MICB1_MICB2_DSP_EN_LOGIC, 0x00},
234 {WCD938X_ANA_MICB3_DSP_EN_LOGIC, 0x00},
235 {WCD938X_ANA_MBHC_MECH, 0x39},
236 {WCD938X_ANA_MBHC_ELECT, 0x08},
237 {WCD938X_ANA_MBHC_ZDET, 0x00},
238 {WCD938X_ANA_MBHC_RESULT_1, 0x00},
239 {WCD938X_ANA_MBHC_RESULT_2, 0x00},
240 {WCD938X_ANA_MBHC_RESULT_3, 0x00},
241 {WCD938X_ANA_MBHC_BTN0, 0x00},
242 {WCD938X_ANA_MBHC_BTN1, 0x10},
243 {WCD938X_ANA_MBHC_BTN2, 0x20},
244 {WCD938X_ANA_MBHC_BTN3, 0x30},
245 {WCD938X_ANA_MBHC_BTN4, 0x40},
246 {WCD938X_ANA_MBHC_BTN5, 0x50},
247 {WCD938X_ANA_MBHC_BTN6, 0x60},
248 {WCD938X_ANA_MBHC_BTN7, 0x70},
249 {WCD938X_ANA_MICB1, 0x10},
250 {WCD938X_ANA_MICB2, 0x10},
251 {WCD938X_ANA_MICB2_RAMP, 0x00},
252 {WCD938X_ANA_MICB3, 0x10},
253 {WCD938X_ANA_MICB4, 0x10},
254 {WCD938X_BIAS_CTL, 0x2A},
255 {WCD938X_BIAS_VBG_FINE_ADJ, 0x55},
256 {WCD938X_LDOL_VDDCX_ADJUST, 0x01},
257 {WCD938X_LDOL_DISABLE_LDOL, 0x00},
258 {WCD938X_MBHC_CTL_CLK, 0x00},
259 {WCD938X_MBHC_CTL_ANA, 0x00},
260 {WCD938X_MBHC_CTL_SPARE_1, 0x00},
261 {WCD938X_MBHC_CTL_SPARE_2, 0x00},
262 {WCD938X_MBHC_CTL_BCS, 0x00},
263 {WCD938X_MBHC_MOISTURE_DET_FSM_STATUS, 0x00},
264 {WCD938X_MBHC_TEST_CTL, 0x00},
265 {WCD938X_LDOH_MODE, 0x2B},
266 {WCD938X_LDOH_BIAS, 0x68},
267 {WCD938X_LDOH_STB_LOADS, 0x00},
268 {WCD938X_LDOH_SLOWRAMP, 0x50},
269 {WCD938X_MICB1_TEST_CTL_1, 0x1A},
270 {WCD938X_MICB1_TEST_CTL_2, 0x00},
271 {WCD938X_MICB1_TEST_CTL_3, 0xA4},
272 {WCD938X_MICB2_TEST_CTL_1, 0x1A},
273 {WCD938X_MICB2_TEST_CTL_2, 0x00},
274 {WCD938X_MICB2_TEST_CTL_3, 0x24},
275 {WCD938X_MICB3_TEST_CTL_1, 0x1A},
276 {WCD938X_MICB3_TEST_CTL_2, 0x00},
277 {WCD938X_MICB3_TEST_CTL_3, 0xA4},
278 {WCD938X_MICB4_TEST_CTL_1, 0x1A},
279 {WCD938X_MICB4_TEST_CTL_2, 0x00},
280 {WCD938X_MICB4_TEST_CTL_3, 0xA4},
281 {WCD938X_TX_COM_ADC_VCM, 0x39},
282 {WCD938X_TX_COM_BIAS_ATEST, 0xE0},
283 {WCD938X_TX_COM_SPARE1, 0x00},
284 {WCD938X_TX_COM_SPARE2, 0x00},
285 {WCD938X_TX_COM_TXFE_DIV_CTL, 0x22},
286 {WCD938X_TX_COM_TXFE_DIV_START, 0x00},
287 {WCD938X_TX_COM_SPARE3, 0x00},
288 {WCD938X_TX_COM_SPARE4, 0x00},
289 {WCD938X_TX_1_2_TEST_EN, 0xCC},
290 {WCD938X_TX_1_2_ADC_IB, 0xE9},
291 {WCD938X_TX_1_2_ATEST_REFCTL, 0x0A},
292 {WCD938X_TX_1_2_TEST_CTL, 0x38},
293 {WCD938X_TX_1_2_TEST_BLK_EN1, 0xFF},
294 {WCD938X_TX_1_2_TXFE1_CLKDIV, 0x00},
295 {WCD938X_TX_1_2_SAR2_ERR, 0x00},
296 {WCD938X_TX_1_2_SAR1_ERR, 0x00},
297 {WCD938X_TX_3_4_TEST_EN, 0xCC},
298 {WCD938X_TX_3_4_ADC_IB, 0xE9},
299 {WCD938X_TX_3_4_ATEST_REFCTL, 0x0A},
300 {WCD938X_TX_3_4_TEST_CTL, 0x38},
301 {WCD938X_TX_3_4_TEST_BLK_EN3, 0xFF},
302 {WCD938X_TX_3_4_TXFE3_CLKDIV, 0x00},
303 {WCD938X_TX_3_4_SAR4_ERR, 0x00},
304 {WCD938X_TX_3_4_SAR3_ERR, 0x00},
305 {WCD938X_TX_3_4_TEST_BLK_EN2, 0xFB},
306 {WCD938X_TX_3_4_TXFE2_CLKDIV, 0x00},
307 {WCD938X_TX_3_4_SPARE1, 0x00},
308 {WCD938X_TX_3_4_TEST_BLK_EN4, 0xFB},
309 {WCD938X_TX_3_4_TXFE4_CLKDIV, 0x00},
310 {WCD938X_TX_3_4_SPARE2, 0x00},
311 {WCD938X_CLASSH_MODE_1, 0x40},
312 {WCD938X_CLASSH_MODE_2, 0x3A},
313 {WCD938X_CLASSH_MODE_3, 0x00},
314 {WCD938X_CLASSH_CTRL_VCL_1, 0x70},
315 {WCD938X_CLASSH_CTRL_VCL_2, 0x82},
316 {WCD938X_CLASSH_CTRL_CCL_1, 0x31},
317 {WCD938X_CLASSH_CTRL_CCL_2, 0x80},
318 {WCD938X_CLASSH_CTRL_CCL_3, 0x80},
319 {WCD938X_CLASSH_CTRL_CCL_4, 0x51},
320 {WCD938X_CLASSH_CTRL_CCL_5, 0x00},
321 {WCD938X_CLASSH_BUCK_TMUX_A_D, 0x00},
322 {WCD938X_CLASSH_BUCK_SW_DRV_CNTL, 0x77},
323 {WCD938X_CLASSH_SPARE, 0x00},
324 {WCD938X_FLYBACK_EN, 0x4E},
325 {WCD938X_FLYBACK_VNEG_CTRL_1, 0x0B},
326 {WCD938X_FLYBACK_VNEG_CTRL_2, 0x45},
327 {WCD938X_FLYBACK_VNEG_CTRL_3, 0x74},
328 {WCD938X_FLYBACK_VNEG_CTRL_4, 0x7F},
329 {WCD938X_FLYBACK_VNEG_CTRL_5, 0x83},
330 {WCD938X_FLYBACK_VNEG_CTRL_6, 0x98},
331 {WCD938X_FLYBACK_VNEG_CTRL_7, 0xA9},
332 {WCD938X_FLYBACK_VNEG_CTRL_8, 0x68},
333 {WCD938X_FLYBACK_VNEG_CTRL_9, 0x64},
334 {WCD938X_FLYBACK_VNEGDAC_CTRL_1, 0xED},
335 {WCD938X_FLYBACK_VNEGDAC_CTRL_2, 0xF0},
336 {WCD938X_FLYBACK_VNEGDAC_CTRL_3, 0xA6},
337 {WCD938X_FLYBACK_CTRL_1, 0x65},
338 {WCD938X_FLYBACK_TEST_CTL, 0x00},
339 {WCD938X_RX_AUX_SW_CTL, 0x00},
340 {WCD938X_RX_PA_AUX_IN_CONN, 0x01},
341 {WCD938X_RX_TIMER_DIV, 0x32},
342 {WCD938X_RX_OCP_CTL, 0x1F},
343 {WCD938X_RX_OCP_COUNT, 0x77},
344 {WCD938X_RX_BIAS_EAR_DAC, 0xA0},
345 {WCD938X_RX_BIAS_EAR_AMP, 0xAA},
346 {WCD938X_RX_BIAS_HPH_LDO, 0xA9},
347 {WCD938X_RX_BIAS_HPH_PA, 0xAA},
348 {WCD938X_RX_BIAS_HPH_RDACBUFF_CNP2, 0x8A},
349 {WCD938X_RX_BIAS_HPH_RDAC_LDO, 0x88},
350 {WCD938X_RX_BIAS_HPH_CNP1, 0x82},
351 {WCD938X_RX_BIAS_HPH_LOWPOWER, 0x82},
352 {WCD938X_RX_BIAS_AUX_DAC, 0xA0},
353 {WCD938X_RX_BIAS_AUX_AMP, 0xAA},
354 {WCD938X_RX_BIAS_VNEGDAC_BLEEDER, 0x50},
355 {WCD938X_RX_BIAS_MISC, 0x00},
356 {WCD938X_RX_BIAS_BUCK_RST, 0x08},
357 {WCD938X_RX_BIAS_BUCK_VREF_ERRAMP, 0x44},
358 {WCD938X_RX_BIAS_FLYB_ERRAMP, 0x40},
359 {WCD938X_RX_BIAS_FLYB_BUFF, 0xAA},
360 {WCD938X_RX_BIAS_FLYB_MID_RST, 0x14},
361 {WCD938X_HPH_L_STATUS, 0x04},
362 {WCD938X_HPH_R_STATUS, 0x04},
363 {WCD938X_HPH_CNP_EN, 0x80},
364 {WCD938X_HPH_CNP_WG_CTL, 0x9A},
365 {WCD938X_HPH_CNP_WG_TIME, 0x14},
366 {WCD938X_HPH_OCP_CTL, 0x28},
367 {WCD938X_HPH_AUTO_CHOP, 0x16},
368 {WCD938X_HPH_CHOP_CTL, 0x83},
369 {WCD938X_HPH_PA_CTL1, 0x46},
370 {WCD938X_HPH_PA_CTL2, 0x50},
371 {WCD938X_HPH_L_EN, 0x80},
372 {WCD938X_HPH_L_TEST, 0xE0},
373 {WCD938X_HPH_L_ATEST, 0x50},
374 {WCD938X_HPH_R_EN, 0x80},
375 {WCD938X_HPH_R_TEST, 0xE0},
376 {WCD938X_HPH_R_ATEST, 0x54},
377 {WCD938X_HPH_RDAC_CLK_CTL1, 0x99},
378 {WCD938X_HPH_RDAC_CLK_CTL2, 0x9B},
379 {WCD938X_HPH_RDAC_LDO_CTL, 0x33},
380 {WCD938X_HPH_RDAC_CHOP_CLK_LP_CTL, 0x00},
381 {WCD938X_HPH_REFBUFF_UHQA_CTL, 0x68},
382 {WCD938X_HPH_REFBUFF_LP_CTL, 0x0E},
383 {WCD938X_HPH_L_DAC_CTL, 0x20},
384 {WCD938X_HPH_R_DAC_CTL, 0x20},
385 {WCD938X_HPH_SURGE_HPHLR_SURGE_COMP_SEL, 0x55},
386 {WCD938X_HPH_SURGE_HPHLR_SURGE_EN, 0x19},
387 {WCD938X_HPH_SURGE_HPHLR_SURGE_MISC1, 0xA0},
388 {WCD938X_HPH_SURGE_HPHLR_SURGE_STATUS, 0x00},
389 {WCD938X_EAR_EAR_EN_REG, 0x22},
390 {WCD938X_EAR_EAR_PA_CON, 0x44},
391 {WCD938X_EAR_EAR_SP_CON, 0xDB},
392 {WCD938X_EAR_EAR_DAC_CON, 0x80},
393 {WCD938X_EAR_EAR_CNP_FSM_CON, 0xB2},
394 {WCD938X_EAR_TEST_CTL, 0x00},
395 {WCD938X_EAR_STATUS_REG_1, 0x00},
396 {WCD938X_EAR_STATUS_REG_2, 0x08},
397 {WCD938X_ANA_NEW_PAGE_REGISTER, 0x00},
398 {WCD938X_HPH_NEW_ANA_HPH2, 0x00},
399 {WCD938X_HPH_NEW_ANA_HPH3, 0x00},
400 {WCD938X_SLEEP_CTL, 0x16},
401 {WCD938X_SLEEP_WATCHDOG_CTL, 0x00},
402 {WCD938X_MBHC_NEW_ELECT_REM_CLAMP_CTL, 0x00},
403 {WCD938X_MBHC_NEW_CTL_1, 0x02},
404 {WCD938X_MBHC_NEW_CTL_2, 0x05},
405 {WCD938X_MBHC_NEW_PLUG_DETECT_CTL, 0xE9},
406 {WCD938X_MBHC_NEW_ZDET_ANA_CTL, 0x0F},
407 {WCD938X_MBHC_NEW_ZDET_RAMP_CTL, 0x00},
408 {WCD938X_MBHC_NEW_FSM_STATUS, 0x00},
409 {WCD938X_MBHC_NEW_ADC_RESULT, 0x00},
410 {WCD938X_TX_NEW_AMIC_MUX_CFG, 0x00},
411 {WCD938X_AUX_AUXPA, 0x00},
412 {WCD938X_LDORXTX_MODE, 0x0C},
413 {WCD938X_LDORXTX_CONFIG, 0x10},
414 {WCD938X_DIE_CRACK_DIE_CRK_DET_EN, 0x00},
415 {WCD938X_DIE_CRACK_DIE_CRK_DET_OUT, 0x00},
416 {WCD938X_HPH_NEW_INT_RDAC_GAIN_CTL, 0x40},
417 {WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_L, 0x81},
418 {WCD938X_HPH_NEW_INT_RDAC_VREF_CTL, 0x10},
419 {WCD938X_HPH_NEW_INT_RDAC_OVERRIDE_CTL, 0x00},
420 {WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_R, 0x81},
421 {WCD938X_HPH_NEW_INT_PA_MISC1, 0x22},
422 {WCD938X_HPH_NEW_INT_PA_MISC2, 0x00},
423 {WCD938X_HPH_NEW_INT_PA_RDAC_MISC, 0x00},
424 {WCD938X_HPH_NEW_INT_HPH_TIMER1, 0xFE},
425 {WCD938X_HPH_NEW_INT_HPH_TIMER2, 0x02},
426 {WCD938X_HPH_NEW_INT_HPH_TIMER3, 0x4E},
427 {WCD938X_HPH_NEW_INT_HPH_TIMER4, 0x54},
428 {WCD938X_HPH_NEW_INT_PA_RDAC_MISC2, 0x00},
429 {WCD938X_HPH_NEW_INT_PA_RDAC_MISC3, 0x00},
430 {WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_L_NEW, 0x90},
431 {WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_R_NEW, 0x90},
432 {WCD938X_RX_NEW_INT_HPH_RDAC_BIAS_LOHIFI, 0x62},
433 {WCD938X_RX_NEW_INT_HPH_RDAC_BIAS_ULP, 0x01},
434 {WCD938X_RX_NEW_INT_HPH_RDAC_LDO_LP, 0x11},
435 {WCD938X_MBHC_NEW_INT_MOISTURE_DET_DC_CTRL, 0x57},
436 {WCD938X_MBHC_NEW_INT_MOISTURE_DET_POLLING_CTRL, 0x01},
437 {WCD938X_MBHC_NEW_INT_MECH_DET_CURRENT, 0x00},
438 {WCD938X_MBHC_NEW_INT_SPARE_2, 0x00},
439 {WCD938X_EAR_INT_NEW_EAR_CHOPPER_CON, 0xA8},
440 {WCD938X_EAR_INT_NEW_CNP_VCM_CON1, 0x42},
441 {WCD938X_EAR_INT_NEW_CNP_VCM_CON2, 0x22},
442 {WCD938X_EAR_INT_NEW_EAR_DYNAMIC_BIAS, 0x00},
443 {WCD938X_AUX_INT_EN_REG, 0x00},
444 {WCD938X_AUX_INT_PA_CTRL, 0x06},
445 {WCD938X_AUX_INT_SP_CTRL, 0xD2},
446 {WCD938X_AUX_INT_DAC_CTRL, 0x80},
447 {WCD938X_AUX_INT_CLK_CTRL, 0x50},
448 {WCD938X_AUX_INT_TEST_CTRL, 0x00},
449 {WCD938X_AUX_INT_STATUS_REG, 0x00},
450 {WCD938X_AUX_INT_MISC, 0x00},
451 {WCD938X_LDORXTX_INT_BIAS, 0x6E},
452 {WCD938X_LDORXTX_INT_STB_LOADS_DTEST, 0x50},
453 {WCD938X_LDORXTX_INT_TEST0, 0x1C},
454 {WCD938X_LDORXTX_INT_STARTUP_TIMER, 0xFF},
455 {WCD938X_LDORXTX_INT_TEST1, 0x1F},
456 {WCD938X_LDORXTX_INT_STATUS, 0x00},
457 {WCD938X_SLEEP_INT_WATCHDOG_CTL_1, 0x0A},
458 {WCD938X_SLEEP_INT_WATCHDOG_CTL_2, 0x0A},
459 {WCD938X_DIE_CRACK_INT_DIE_CRK_DET_INT1, 0x02},
460 {WCD938X_DIE_CRACK_INT_DIE_CRK_DET_INT2, 0x60},
461 {WCD938X_TX_COM_NEW_INT_TXFE_DIVSTOP_L2, 0xFF},
462 {WCD938X_TX_COM_NEW_INT_TXFE_DIVSTOP_L1, 0x7F},
463 {WCD938X_TX_COM_NEW_INT_TXFE_DIVSTOP_L0, 0x3F},
464 {WCD938X_TX_COM_NEW_INT_TXFE_DIVSTOP_ULP1P2M, 0x1F},
465 {WCD938X_TX_COM_NEW_INT_TXFE_DIVSTOP_ULP0P6M, 0x0F},
466 {WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG1_L2L1, 0xD7},
467 {WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG1_L0, 0xC8},
468 {WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG1_ULP, 0xC6},
469 {WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG2MAIN_L2L1, 0xD5},
470 {WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG2MAIN_L0, 0xCA},
471 {WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG2MAIN_ULP, 0x05},
472 {WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG2CASC_L2L1L0, 0xA5},
473 {WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG2CASC_ULP, 0x13},
474 {WCD938X_TX_COM_NEW_INT_TXADC_SCBIAS_L2L1, 0x88},
475 {WCD938X_TX_COM_NEW_INT_TXADC_SCBIAS_L0ULP, 0x42},
476 {WCD938X_TX_COM_NEW_INT_TXADC_INT_L2, 0xFF},
477 {WCD938X_TX_COM_NEW_INT_TXADC_INT_L1, 0x64},
478 {WCD938X_TX_COM_NEW_INT_TXADC_INT_L0, 0x64},
479 {WCD938X_TX_COM_NEW_INT_TXADC_INT_ULP, 0x77},
480 {WCD938X_DIGITAL_PAGE_REGISTER, 0x00},
481 {WCD938X_DIGITAL_CHIP_ID0, 0x00},
482 {WCD938X_DIGITAL_CHIP_ID1, 0x00},
483 {WCD938X_DIGITAL_CHIP_ID2, 0x0D},
484 {WCD938X_DIGITAL_CHIP_ID3, 0x01},
485 {WCD938X_DIGITAL_SWR_TX_CLK_RATE, 0x00},
486 {WCD938X_DIGITAL_CDC_RST_CTL, 0x03},
487 {WCD938X_DIGITAL_TOP_CLK_CFG, 0x00},
488 {WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 0x00},
489 {WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0xF0},
490 {WCD938X_DIGITAL_SWR_RST_EN, 0x00},
491 {WCD938X_DIGITAL_CDC_PATH_MODE, 0x55},
492 {WCD938X_DIGITAL_CDC_RX_RST, 0x00},
493 {WCD938X_DIGITAL_CDC_RX0_CTL, 0xFC},
494 {WCD938X_DIGITAL_CDC_RX1_CTL, 0xFC},
495 {WCD938X_DIGITAL_CDC_RX2_CTL, 0xFC},
496 {WCD938X_DIGITAL_CDC_TX_ANA_MODE_0_1, 0x00},
497 {WCD938X_DIGITAL_CDC_TX_ANA_MODE_2_3, 0x00},
498 {WCD938X_DIGITAL_CDC_COMP_CTL_0, 0x00},
499 {WCD938X_DIGITAL_CDC_ANA_TX_CLK_CTL, 0x1E},
500 {WCD938X_DIGITAL_CDC_HPH_DSM_A1_0, 0x00},
501 {WCD938X_DIGITAL_CDC_HPH_DSM_A1_1, 0x01},
502 {WCD938X_DIGITAL_CDC_HPH_DSM_A2_0, 0x63},
503 {WCD938X_DIGITAL_CDC_HPH_DSM_A2_1, 0x04},
504 {WCD938X_DIGITAL_CDC_HPH_DSM_A3_0, 0xAC},
505 {WCD938X_DIGITAL_CDC_HPH_DSM_A3_1, 0x04},
506 {WCD938X_DIGITAL_CDC_HPH_DSM_A4_0, 0x1A},
507 {WCD938X_DIGITAL_CDC_HPH_DSM_A4_1, 0x03},
508 {WCD938X_DIGITAL_CDC_HPH_DSM_A5_0, 0xBC},
509 {WCD938X_DIGITAL_CDC_HPH_DSM_A5_1, 0x02},
510 {WCD938X_DIGITAL_CDC_HPH_DSM_A6_0, 0xC7},
511 {WCD938X_DIGITAL_CDC_HPH_DSM_A7_0, 0xF8},
512 {WCD938X_DIGITAL_CDC_HPH_DSM_C_0, 0x47},
513 {WCD938X_DIGITAL_CDC_HPH_DSM_C_1, 0x43},
514 {WCD938X_DIGITAL_CDC_HPH_DSM_C_2, 0xB1},
515 {WCD938X_DIGITAL_CDC_HPH_DSM_C_3, 0x17},
516 {WCD938X_DIGITAL_CDC_HPH_DSM_R1, 0x4D},
517 {WCD938X_DIGITAL_CDC_HPH_DSM_R2, 0x29},
518 {WCD938X_DIGITAL_CDC_HPH_DSM_R3, 0x34},
519 {WCD938X_DIGITAL_CDC_HPH_DSM_R4, 0x59},
520 {WCD938X_DIGITAL_CDC_HPH_DSM_R5, 0x66},
521 {WCD938X_DIGITAL_CDC_HPH_DSM_R6, 0x87},
522 {WCD938X_DIGITAL_CDC_HPH_DSM_R7, 0x64},
523 {WCD938X_DIGITAL_CDC_AUX_DSM_A1_0, 0x00},
524 {WCD938X_DIGITAL_CDC_AUX_DSM_A1_1, 0x01},
525 {WCD938X_DIGITAL_CDC_AUX_DSM_A2_0, 0x96},
526 {WCD938X_DIGITAL_CDC_AUX_DSM_A2_1, 0x09},
527 {WCD938X_DIGITAL_CDC_AUX_DSM_A3_0, 0xAB},
528 {WCD938X_DIGITAL_CDC_AUX_DSM_A3_1, 0x05},
529 {WCD938X_DIGITAL_CDC_AUX_DSM_A4_0, 0x1C},
530 {WCD938X_DIGITAL_CDC_AUX_DSM_A4_1, 0x02},
531 {WCD938X_DIGITAL_CDC_AUX_DSM_A5_0, 0x17},
532 {WCD938X_DIGITAL_CDC_AUX_DSM_A5_1, 0x02},
533 {WCD938X_DIGITAL_CDC_AUX_DSM_A6_0, 0xAA},
534 {WCD938X_DIGITAL_CDC_AUX_DSM_A7_0, 0xE3},
535 {WCD938X_DIGITAL_CDC_AUX_DSM_C_0, 0x69},
536 {WCD938X_DIGITAL_CDC_AUX_DSM_C_1, 0x54},
537 {WCD938X_DIGITAL_CDC_AUX_DSM_C_2, 0x02},
538 {WCD938X_DIGITAL_CDC_AUX_DSM_C_3, 0x15},
539 {WCD938X_DIGITAL_CDC_AUX_DSM_R1, 0xA4},
540 {WCD938X_DIGITAL_CDC_AUX_DSM_R2, 0xB5},
541 {WCD938X_DIGITAL_CDC_AUX_DSM_R3, 0x86},
542 {WCD938X_DIGITAL_CDC_AUX_DSM_R4, 0x85},
543 {WCD938X_DIGITAL_CDC_AUX_DSM_R5, 0xAA},
544 {WCD938X_DIGITAL_CDC_AUX_DSM_R6, 0xE2},
545 {WCD938X_DIGITAL_CDC_AUX_DSM_R7, 0x62},
546 {WCD938X_DIGITAL_CDC_HPH_GAIN_RX_0, 0x55},
547 {WCD938X_DIGITAL_CDC_HPH_GAIN_RX_1, 0xA9},
548 {WCD938X_DIGITAL_CDC_HPH_GAIN_DSD_0, 0x3D},
549 {WCD938X_DIGITAL_CDC_HPH_GAIN_DSD_1, 0x2E},
550 {WCD938X_DIGITAL_CDC_HPH_GAIN_DSD_2, 0x01},
551 {WCD938X_DIGITAL_CDC_AUX_GAIN_DSD_0, 0x00},
552 {WCD938X_DIGITAL_CDC_AUX_GAIN_DSD_1, 0xFC},
553 {WCD938X_DIGITAL_CDC_AUX_GAIN_DSD_2, 0x01},
554 {WCD938X_DIGITAL_CDC_HPH_GAIN_CTL, 0x00},
555 {WCD938X_DIGITAL_CDC_AUX_GAIN_CTL, 0x00},
556 {WCD938X_DIGITAL_CDC_EAR_PATH_CTL, 0x00},
557 {WCD938X_DIGITAL_CDC_SWR_CLH, 0x00},
558 {WCD938X_DIGITAL_SWR_CLH_BYP, 0x00},
559 {WCD938X_DIGITAL_CDC_TX0_CTL, 0x68},
560 {WCD938X_DIGITAL_CDC_TX1_CTL, 0x68},
561 {WCD938X_DIGITAL_CDC_TX2_CTL, 0x68},
562 {WCD938X_DIGITAL_CDC_TX_RST, 0x00},
563 {WCD938X_DIGITAL_CDC_REQ_CTL, 0x01},
564 {WCD938X_DIGITAL_CDC_RST, 0x00},
565 {WCD938X_DIGITAL_CDC_AMIC_CTL, 0x0F},
566 {WCD938X_DIGITAL_CDC_DMIC_CTL, 0x04},
567 {WCD938X_DIGITAL_CDC_DMIC1_CTL, 0x01},
568 {WCD938X_DIGITAL_CDC_DMIC2_CTL, 0x01},
569 {WCD938X_DIGITAL_CDC_DMIC3_CTL, 0x01},
570 {WCD938X_DIGITAL_CDC_DMIC4_CTL, 0x01},
571 {WCD938X_DIGITAL_EFUSE_PRG_CTL, 0x00},
572 {WCD938X_DIGITAL_EFUSE_CTL, 0x2B},
573 {WCD938X_DIGITAL_CDC_DMIC_RATE_1_2, 0x11},
574 {WCD938X_DIGITAL_CDC_DMIC_RATE_3_4, 0x11},
575 {WCD938X_DIGITAL_PDM_WD_CTL0, 0x00},
576 {WCD938X_DIGITAL_PDM_WD_CTL1, 0x00},
577 {WCD938X_DIGITAL_PDM_WD_CTL2, 0x00},
578 {WCD938X_DIGITAL_INTR_MODE, 0x00},
579 {WCD938X_DIGITAL_INTR_MASK_0, 0xFF},
580 {WCD938X_DIGITAL_INTR_MASK_1, 0xFF},
581 {WCD938X_DIGITAL_INTR_MASK_2, 0x3F},
582 {WCD938X_DIGITAL_INTR_STATUS_0, 0x00},
583 {WCD938X_DIGITAL_INTR_STATUS_1, 0x00},
584 {WCD938X_DIGITAL_INTR_STATUS_2, 0x00},
585 {WCD938X_DIGITAL_INTR_CLEAR_0, 0x00},
586 {WCD938X_DIGITAL_INTR_CLEAR_1, 0x00},
587 {WCD938X_DIGITAL_INTR_CLEAR_2, 0x00},
588 {WCD938X_DIGITAL_INTR_LEVEL_0, 0x00},
589 {WCD938X_DIGITAL_INTR_LEVEL_1, 0x00},
590 {WCD938X_DIGITAL_INTR_LEVEL_2, 0x00},
591 {WCD938X_DIGITAL_INTR_SET_0, 0x00},
592 {WCD938X_DIGITAL_INTR_SET_1, 0x00},
593 {WCD938X_DIGITAL_INTR_SET_2, 0x00},
594 {WCD938X_DIGITAL_INTR_TEST_0, 0x00},
595 {WCD938X_DIGITAL_INTR_TEST_1, 0x00},
596 {WCD938X_DIGITAL_INTR_TEST_2, 0x00},
597 {WCD938X_DIGITAL_TX_MODE_DBG_EN, 0x00},
598 {WCD938X_DIGITAL_TX_MODE_DBG_0_1, 0x00},
599 {WCD938X_DIGITAL_TX_MODE_DBG_2_3, 0x00},
600 {WCD938X_DIGITAL_LB_IN_SEL_CTL, 0x00},
601 {WCD938X_DIGITAL_LOOP_BACK_MODE, 0x00},
602 {WCD938X_DIGITAL_SWR_DAC_TEST, 0x00},
603 {WCD938X_DIGITAL_SWR_HM_TEST_RX_0, 0x40},
604 {WCD938X_DIGITAL_SWR_HM_TEST_TX_0, 0x40},
605 {WCD938X_DIGITAL_SWR_HM_TEST_RX_1, 0x00},
606 {WCD938X_DIGITAL_SWR_HM_TEST_TX_1, 0x00},
607 {WCD938X_DIGITAL_SWR_HM_TEST_TX_2, 0x00},
608 {WCD938X_DIGITAL_SWR_HM_TEST_0, 0x00},
609 {WCD938X_DIGITAL_SWR_HM_TEST_1, 0x00},
610 {WCD938X_DIGITAL_PAD_CTL_SWR_0, 0x8F},
611 {WCD938X_DIGITAL_PAD_CTL_SWR_1, 0x06},
612 {WCD938X_DIGITAL_I2C_CTL, 0x00},
613 {WCD938X_DIGITAL_CDC_TX_TANGGU_SW_MODE, 0x00},
614 {WCD938X_DIGITAL_EFUSE_TEST_CTL_0, 0x00},
615 {WCD938X_DIGITAL_EFUSE_TEST_CTL_1, 0x00},
616 {WCD938X_DIGITAL_EFUSE_T_DATA_0, 0x00},
617 {WCD938X_DIGITAL_EFUSE_T_DATA_1, 0x00},
618 {WCD938X_DIGITAL_PAD_CTL_PDM_RX0, 0xF1},
619 {WCD938X_DIGITAL_PAD_CTL_PDM_RX1, 0xF1},
620 {WCD938X_DIGITAL_PAD_CTL_PDM_TX0, 0xF1},
621 {WCD938X_DIGITAL_PAD_CTL_PDM_TX1, 0xF1},
622 {WCD938X_DIGITAL_PAD_CTL_PDM_TX2, 0xF1},
623 {WCD938X_DIGITAL_PAD_INP_DIS_0, 0x00},
624 {WCD938X_DIGITAL_PAD_INP_DIS_1, 0x00},
625 {WCD938X_DIGITAL_DRIVE_STRENGTH_0, 0x00},
626 {WCD938X_DIGITAL_DRIVE_STRENGTH_1, 0x00},
627 {WCD938X_DIGITAL_DRIVE_STRENGTH_2, 0x00},
628 {WCD938X_DIGITAL_RX_DATA_EDGE_CTL, 0x1F},
629 {WCD938X_DIGITAL_TX_DATA_EDGE_CTL, 0x80},
630 {WCD938X_DIGITAL_GPIO_MODE, 0x00},
631 {WCD938X_DIGITAL_PIN_CTL_OE, 0x00},
632 {WCD938X_DIGITAL_PIN_CTL_DATA_0, 0x00},
633 {WCD938X_DIGITAL_PIN_CTL_DATA_1, 0x00},
634 {WCD938X_DIGITAL_PIN_STATUS_0, 0x00},
635 {WCD938X_DIGITAL_PIN_STATUS_1, 0x00},
636 {WCD938X_DIGITAL_DIG_DEBUG_CTL, 0x00},
637 {WCD938X_DIGITAL_DIG_DEBUG_EN, 0x00},
638 {WCD938X_DIGITAL_ANA_CSR_DBG_ADD, 0x00},
639 {WCD938X_DIGITAL_ANA_CSR_DBG_CTL, 0x48},
640 {WCD938X_DIGITAL_SSP_DBG, 0x00},
641 {WCD938X_DIGITAL_MODE_STATUS_0, 0x00},
642 {WCD938X_DIGITAL_MODE_STATUS_1, 0x00},
643 {WCD938X_DIGITAL_SPARE_0, 0x00},
644 {WCD938X_DIGITAL_SPARE_1, 0x00},
645 {WCD938X_DIGITAL_SPARE_2, 0x00},
646 {WCD938X_DIGITAL_EFUSE_REG_0, 0x00},
647 {WCD938X_DIGITAL_EFUSE_REG_1, 0xFF},
648 {WCD938X_DIGITAL_EFUSE_REG_2, 0xFF},
649 {WCD938X_DIGITAL_EFUSE_REG_3, 0xFF},
650 {WCD938X_DIGITAL_EFUSE_REG_4, 0xFF},
651 {WCD938X_DIGITAL_EFUSE_REG_5, 0xFF},
652 {WCD938X_DIGITAL_EFUSE_REG_6, 0xFF},
653 {WCD938X_DIGITAL_EFUSE_REG_7, 0xFF},
654 {WCD938X_DIGITAL_EFUSE_REG_8, 0xFF},
655 {WCD938X_DIGITAL_EFUSE_REG_9, 0xFF},
656 {WCD938X_DIGITAL_EFUSE_REG_10, 0xFF},
657 {WCD938X_DIGITAL_EFUSE_REG_11, 0xFF},
658 {WCD938X_DIGITAL_EFUSE_REG_12, 0xFF},
659 {WCD938X_DIGITAL_EFUSE_REG_13, 0xFF},
660 {WCD938X_DIGITAL_EFUSE_REG_14, 0xFF},
661 {WCD938X_DIGITAL_EFUSE_REG_15, 0xFF},
662 {WCD938X_DIGITAL_EFUSE_REG_16, 0xFF},
663 {WCD938X_DIGITAL_EFUSE_REG_17, 0xFF},
664 {WCD938X_DIGITAL_EFUSE_REG_18, 0xFF},
665 {WCD938X_DIGITAL_EFUSE_REG_19, 0xFF},
666 {WCD938X_DIGITAL_EFUSE_REG_20, 0x0E},
667 {WCD938X_DIGITAL_EFUSE_REG_21, 0x00},
668 {WCD938X_DIGITAL_EFUSE_REG_22, 0x00},
669 {WCD938X_DIGITAL_EFUSE_REG_23, 0xF8},
670 {WCD938X_DIGITAL_EFUSE_REG_24, 0x16},
671 {WCD938X_DIGITAL_EFUSE_REG_25, 0x00},
672 {WCD938X_DIGITAL_EFUSE_REG_26, 0x00},
673 {WCD938X_DIGITAL_EFUSE_REG_27, 0x00},
674 {WCD938X_DIGITAL_EFUSE_REG_28, 0x00},
675 {WCD938X_DIGITAL_EFUSE_REG_29, 0x00},
676 {WCD938X_DIGITAL_EFUSE_REG_30, 0x00},
677 {WCD938X_DIGITAL_EFUSE_REG_31, 0x00},
678 {WCD938X_DIGITAL_TX_REQ_FB_CTL_0, 0x88},
679 {WCD938X_DIGITAL_TX_REQ_FB_CTL_1, 0x88},
680 {WCD938X_DIGITAL_TX_REQ_FB_CTL_2, 0x88},
681 {WCD938X_DIGITAL_TX_REQ_FB_CTL_3, 0x88},
682 {WCD938X_DIGITAL_TX_REQ_FB_CTL_4, 0x88},
683 {WCD938X_DIGITAL_DEM_BYPASS_DATA0, 0x55},
684 {WCD938X_DIGITAL_DEM_BYPASS_DATA1, 0x55},
685 {WCD938X_DIGITAL_DEM_BYPASS_DATA2, 0x55},
686 {WCD938X_DIGITAL_DEM_BYPASS_DATA3, 0x01},
687};
688
689static bool wcd938x_rdwr_register(struct device *dev, unsigned int reg)
690{
691 switch (reg) {
692 case WCD938X_ANA_PAGE_REGISTER:
693 case WCD938X_ANA_BIAS:
694 case WCD938X_ANA_RX_SUPPLIES:
695 case WCD938X_ANA_HPH:
696 case WCD938X_ANA_EAR:
697 case WCD938X_ANA_EAR_COMPANDER_CTL:
698 case WCD938X_ANA_TX_CH1:
699 case WCD938X_ANA_TX_CH2:
700 case WCD938X_ANA_TX_CH3:
701 case WCD938X_ANA_TX_CH4:
702 case WCD938X_ANA_MICB1_MICB2_DSP_EN_LOGIC:
703 case WCD938X_ANA_MICB3_DSP_EN_LOGIC:
704 case WCD938X_ANA_MBHC_MECH:
705 case WCD938X_ANA_MBHC_ELECT:
706 case WCD938X_ANA_MBHC_ZDET:
707 case WCD938X_ANA_MBHC_BTN0:
708 case WCD938X_ANA_MBHC_BTN1:
709 case WCD938X_ANA_MBHC_BTN2:
710 case WCD938X_ANA_MBHC_BTN3:
711 case WCD938X_ANA_MBHC_BTN4:
712 case WCD938X_ANA_MBHC_BTN5:
713 case WCD938X_ANA_MBHC_BTN6:
714 case WCD938X_ANA_MBHC_BTN7:
715 case WCD938X_ANA_MICB1:
716 case WCD938X_ANA_MICB2:
717 case WCD938X_ANA_MICB2_RAMP:
718 case WCD938X_ANA_MICB3:
719 case WCD938X_ANA_MICB4:
720 case WCD938X_BIAS_CTL:
721 case WCD938X_BIAS_VBG_FINE_ADJ:
722 case WCD938X_LDOL_VDDCX_ADJUST:
723 case WCD938X_LDOL_DISABLE_LDOL:
724 case WCD938X_MBHC_CTL_CLK:
725 case WCD938X_MBHC_CTL_ANA:
726 case WCD938X_MBHC_CTL_SPARE_1:
727 case WCD938X_MBHC_CTL_SPARE_2:
728 case WCD938X_MBHC_CTL_BCS:
729 case WCD938X_MBHC_TEST_CTL:
730 case WCD938X_LDOH_MODE:
731 case WCD938X_LDOH_BIAS:
732 case WCD938X_LDOH_STB_LOADS:
733 case WCD938X_LDOH_SLOWRAMP:
734 case WCD938X_MICB1_TEST_CTL_1:
735 case WCD938X_MICB1_TEST_CTL_2:
736 case WCD938X_MICB1_TEST_CTL_3:
737 case WCD938X_MICB2_TEST_CTL_1:
738 case WCD938X_MICB2_TEST_CTL_2:
739 case WCD938X_MICB2_TEST_CTL_3:
740 case WCD938X_MICB3_TEST_CTL_1:
741 case WCD938X_MICB3_TEST_CTL_2:
742 case WCD938X_MICB3_TEST_CTL_3:
743 case WCD938X_MICB4_TEST_CTL_1:
744 case WCD938X_MICB4_TEST_CTL_2:
745 case WCD938X_MICB4_TEST_CTL_3:
746 case WCD938X_TX_COM_ADC_VCM:
747 case WCD938X_TX_COM_BIAS_ATEST:
748 case WCD938X_TX_COM_SPARE1:
749 case WCD938X_TX_COM_SPARE2:
750 case WCD938X_TX_COM_TXFE_DIV_CTL:
751 case WCD938X_TX_COM_TXFE_DIV_START:
752 case WCD938X_TX_COM_SPARE3:
753 case WCD938X_TX_COM_SPARE4:
754 case WCD938X_TX_1_2_TEST_EN:
755 case WCD938X_TX_1_2_ADC_IB:
756 case WCD938X_TX_1_2_ATEST_REFCTL:
757 case WCD938X_TX_1_2_TEST_CTL:
758 case WCD938X_TX_1_2_TEST_BLK_EN1:
759 case WCD938X_TX_1_2_TXFE1_CLKDIV:
760 case WCD938X_TX_3_4_TEST_EN:
761 case WCD938X_TX_3_4_ADC_IB:
762 case WCD938X_TX_3_4_ATEST_REFCTL:
763 case WCD938X_TX_3_4_TEST_CTL:
764 case WCD938X_TX_3_4_TEST_BLK_EN3:
765 case WCD938X_TX_3_4_TXFE3_CLKDIV:
766 case WCD938X_TX_3_4_TEST_BLK_EN2:
767 case WCD938X_TX_3_4_TXFE2_CLKDIV:
768 case WCD938X_TX_3_4_SPARE1:
769 case WCD938X_TX_3_4_TEST_BLK_EN4:
770 case WCD938X_TX_3_4_TXFE4_CLKDIV:
771 case WCD938X_TX_3_4_SPARE2:
772 case WCD938X_CLASSH_MODE_1:
773 case WCD938X_CLASSH_MODE_2:
774 case WCD938X_CLASSH_MODE_3:
775 case WCD938X_CLASSH_CTRL_VCL_1:
776 case WCD938X_CLASSH_CTRL_VCL_2:
777 case WCD938X_CLASSH_CTRL_CCL_1:
778 case WCD938X_CLASSH_CTRL_CCL_2:
779 case WCD938X_CLASSH_CTRL_CCL_3:
780 case WCD938X_CLASSH_CTRL_CCL_4:
781 case WCD938X_CLASSH_CTRL_CCL_5:
782 case WCD938X_CLASSH_BUCK_TMUX_A_D:
783 case WCD938X_CLASSH_BUCK_SW_DRV_CNTL:
784 case WCD938X_CLASSH_SPARE:
785 case WCD938X_FLYBACK_EN:
786 case WCD938X_FLYBACK_VNEG_CTRL_1:
787 case WCD938X_FLYBACK_VNEG_CTRL_2:
788 case WCD938X_FLYBACK_VNEG_CTRL_3:
789 case WCD938X_FLYBACK_VNEG_CTRL_4:
790 case WCD938X_FLYBACK_VNEG_CTRL_5:
791 case WCD938X_FLYBACK_VNEG_CTRL_6:
792 case WCD938X_FLYBACK_VNEG_CTRL_7:
793 case WCD938X_FLYBACK_VNEG_CTRL_8:
794 case WCD938X_FLYBACK_VNEG_CTRL_9:
795 case WCD938X_FLYBACK_VNEGDAC_CTRL_1:
796 case WCD938X_FLYBACK_VNEGDAC_CTRL_2:
797 case WCD938X_FLYBACK_VNEGDAC_CTRL_3:
798 case WCD938X_FLYBACK_CTRL_1:
799 case WCD938X_FLYBACK_TEST_CTL:
800 case WCD938X_RX_AUX_SW_CTL:
801 case WCD938X_RX_PA_AUX_IN_CONN:
802 case WCD938X_RX_TIMER_DIV:
803 case WCD938X_RX_OCP_CTL:
804 case WCD938X_RX_OCP_COUNT:
805 case WCD938X_RX_BIAS_EAR_DAC:
806 case WCD938X_RX_BIAS_EAR_AMP:
807 case WCD938X_RX_BIAS_HPH_LDO:
808 case WCD938X_RX_BIAS_HPH_PA:
809 case WCD938X_RX_BIAS_HPH_RDACBUFF_CNP2:
810 case WCD938X_RX_BIAS_HPH_RDAC_LDO:
811 case WCD938X_RX_BIAS_HPH_CNP1:
812 case WCD938X_RX_BIAS_HPH_LOWPOWER:
813 case WCD938X_RX_BIAS_AUX_DAC:
814 case WCD938X_RX_BIAS_AUX_AMP:
815 case WCD938X_RX_BIAS_VNEGDAC_BLEEDER:
816 case WCD938X_RX_BIAS_MISC:
817 case WCD938X_RX_BIAS_BUCK_RST:
818 case WCD938X_RX_BIAS_BUCK_VREF_ERRAMP:
819 case WCD938X_RX_BIAS_FLYB_ERRAMP:
820 case WCD938X_RX_BIAS_FLYB_BUFF:
821 case WCD938X_RX_BIAS_FLYB_MID_RST:
822 case WCD938X_HPH_CNP_EN:
823 case WCD938X_HPH_CNP_WG_CTL:
824 case WCD938X_HPH_CNP_WG_TIME:
825 case WCD938X_HPH_OCP_CTL:
826 case WCD938X_HPH_AUTO_CHOP:
827 case WCD938X_HPH_CHOP_CTL:
828 case WCD938X_HPH_PA_CTL1:
829 case WCD938X_HPH_PA_CTL2:
830 case WCD938X_HPH_L_EN:
831 case WCD938X_HPH_L_TEST:
832 case WCD938X_HPH_L_ATEST:
833 case WCD938X_HPH_R_EN:
834 case WCD938X_HPH_R_TEST:
835 case WCD938X_HPH_R_ATEST:
836 case WCD938X_HPH_RDAC_CLK_CTL1:
837 case WCD938X_HPH_RDAC_CLK_CTL2:
838 case WCD938X_HPH_RDAC_LDO_CTL:
839 case WCD938X_HPH_RDAC_CHOP_CLK_LP_CTL:
840 case WCD938X_HPH_REFBUFF_UHQA_CTL:
841 case WCD938X_HPH_REFBUFF_LP_CTL:
842 case WCD938X_HPH_L_DAC_CTL:
843 case WCD938X_HPH_R_DAC_CTL:
844 case WCD938X_HPH_SURGE_HPHLR_SURGE_COMP_SEL:
845 case WCD938X_HPH_SURGE_HPHLR_SURGE_EN:
846 case WCD938X_HPH_SURGE_HPHLR_SURGE_MISC1:
847 case WCD938X_EAR_EAR_EN_REG:
848 case WCD938X_EAR_EAR_PA_CON:
849 case WCD938X_EAR_EAR_SP_CON:
850 case WCD938X_EAR_EAR_DAC_CON:
851 case WCD938X_EAR_EAR_CNP_FSM_CON:
852 case WCD938X_EAR_TEST_CTL:
853 case WCD938X_ANA_NEW_PAGE_REGISTER:
854 case WCD938X_HPH_NEW_ANA_HPH2:
855 case WCD938X_HPH_NEW_ANA_HPH3:
856 case WCD938X_SLEEP_CTL:
857 case WCD938X_SLEEP_WATCHDOG_CTL:
858 case WCD938X_MBHC_NEW_ELECT_REM_CLAMP_CTL:
859 case WCD938X_MBHC_NEW_CTL_1:
860 case WCD938X_MBHC_NEW_CTL_2:
861 case WCD938X_MBHC_NEW_PLUG_DETECT_CTL:
862 case WCD938X_MBHC_NEW_ZDET_ANA_CTL:
863 case WCD938X_MBHC_NEW_ZDET_RAMP_CTL:
864 case WCD938X_TX_NEW_AMIC_MUX_CFG:
865 case WCD938X_AUX_AUXPA:
866 case WCD938X_LDORXTX_MODE:
867 case WCD938X_LDORXTX_CONFIG:
868 case WCD938X_DIE_CRACK_DIE_CRK_DET_EN:
869 case WCD938X_HPH_NEW_INT_RDAC_GAIN_CTL:
870 case WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_L:
871 case WCD938X_HPH_NEW_INT_RDAC_VREF_CTL:
872 case WCD938X_HPH_NEW_INT_RDAC_OVERRIDE_CTL:
873 case WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_R:
874 case WCD938X_HPH_NEW_INT_PA_MISC1:
875 case WCD938X_HPH_NEW_INT_PA_MISC2:
876 case WCD938X_HPH_NEW_INT_PA_RDAC_MISC:
877 case WCD938X_HPH_NEW_INT_HPH_TIMER1:
878 case WCD938X_HPH_NEW_INT_HPH_TIMER2:
879 case WCD938X_HPH_NEW_INT_HPH_TIMER3:
880 case WCD938X_HPH_NEW_INT_HPH_TIMER4:
881 case WCD938X_HPH_NEW_INT_PA_RDAC_MISC2:
882 case WCD938X_HPH_NEW_INT_PA_RDAC_MISC3:
883 case WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_L_NEW:
884 case WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_R_NEW:
885 case WCD938X_RX_NEW_INT_HPH_RDAC_BIAS_LOHIFI:
886 case WCD938X_RX_NEW_INT_HPH_RDAC_BIAS_ULP:
887 case WCD938X_RX_NEW_INT_HPH_RDAC_LDO_LP:
888 case WCD938X_MBHC_NEW_INT_MOISTURE_DET_DC_CTRL:
889 case WCD938X_MBHC_NEW_INT_MOISTURE_DET_POLLING_CTRL:
890 case WCD938X_MBHC_NEW_INT_MECH_DET_CURRENT:
891 case WCD938X_MBHC_NEW_INT_SPARE_2:
892 case WCD938X_EAR_INT_NEW_EAR_CHOPPER_CON:
893 case WCD938X_EAR_INT_NEW_CNP_VCM_CON1:
894 case WCD938X_EAR_INT_NEW_CNP_VCM_CON2:
895 case WCD938X_EAR_INT_NEW_EAR_DYNAMIC_BIAS:
896 case WCD938X_AUX_INT_EN_REG:
897 case WCD938X_AUX_INT_PA_CTRL:
898 case WCD938X_AUX_INT_SP_CTRL:
899 case WCD938X_AUX_INT_DAC_CTRL:
900 case WCD938X_AUX_INT_CLK_CTRL:
901 case WCD938X_AUX_INT_TEST_CTRL:
902 case WCD938X_AUX_INT_MISC:
903 case WCD938X_LDORXTX_INT_BIAS:
904 case WCD938X_LDORXTX_INT_STB_LOADS_DTEST:
905 case WCD938X_LDORXTX_INT_TEST0:
906 case WCD938X_LDORXTX_INT_STARTUP_TIMER:
907 case WCD938X_LDORXTX_INT_TEST1:
908 case WCD938X_SLEEP_INT_WATCHDOG_CTL_1:
909 case WCD938X_SLEEP_INT_WATCHDOG_CTL_2:
910 case WCD938X_DIE_CRACK_INT_DIE_CRK_DET_INT1:
911 case WCD938X_DIE_CRACK_INT_DIE_CRK_DET_INT2:
912 case WCD938X_TX_COM_NEW_INT_TXFE_DIVSTOP_L2:
913 case WCD938X_TX_COM_NEW_INT_TXFE_DIVSTOP_L1:
914 case WCD938X_TX_COM_NEW_INT_TXFE_DIVSTOP_L0:
915 case WCD938X_TX_COM_NEW_INT_TXFE_DIVSTOP_ULP1P2M:
916 case WCD938X_TX_COM_NEW_INT_TXFE_DIVSTOP_ULP0P6M:
917 case WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG1_L2L1:
918 case WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG1_L0:
919 case WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG1_ULP:
920 case WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG2MAIN_L2L1:
921 case WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG2MAIN_L0:
922 case WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG2MAIN_ULP:
923 case WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG2CASC_L2L1L0:
924 case WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG2CASC_ULP:
925 case WCD938X_TX_COM_NEW_INT_TXADC_SCBIAS_L2L1:
926 case WCD938X_TX_COM_NEW_INT_TXADC_SCBIAS_L0ULP:
927 case WCD938X_TX_COM_NEW_INT_TXADC_INT_L2:
928 case WCD938X_TX_COM_NEW_INT_TXADC_INT_L1:
929 case WCD938X_TX_COM_NEW_INT_TXADC_INT_L0:
930 case WCD938X_TX_COM_NEW_INT_TXADC_INT_ULP:
931 case WCD938X_DIGITAL_PAGE_REGISTER:
932 case WCD938X_DIGITAL_SWR_TX_CLK_RATE:
933 case WCD938X_DIGITAL_CDC_RST_CTL:
934 case WCD938X_DIGITAL_TOP_CLK_CFG:
935 case WCD938X_DIGITAL_CDC_ANA_CLK_CTL:
936 case WCD938X_DIGITAL_CDC_DIG_CLK_CTL:
937 case WCD938X_DIGITAL_SWR_RST_EN:
938 case WCD938X_DIGITAL_CDC_PATH_MODE:
939 case WCD938X_DIGITAL_CDC_RX_RST:
940 case WCD938X_DIGITAL_CDC_RX0_CTL:
941 case WCD938X_DIGITAL_CDC_RX1_CTL:
942 case WCD938X_DIGITAL_CDC_RX2_CTL:
943 case WCD938X_DIGITAL_CDC_TX_ANA_MODE_0_1:
944 case WCD938X_DIGITAL_CDC_TX_ANA_MODE_2_3:
945 case WCD938X_DIGITAL_CDC_COMP_CTL_0:
946 case WCD938X_DIGITAL_CDC_ANA_TX_CLK_CTL:
947 case WCD938X_DIGITAL_CDC_HPH_DSM_A1_0:
948 case WCD938X_DIGITAL_CDC_HPH_DSM_A1_1:
949 case WCD938X_DIGITAL_CDC_HPH_DSM_A2_0:
950 case WCD938X_DIGITAL_CDC_HPH_DSM_A2_1:
951 case WCD938X_DIGITAL_CDC_HPH_DSM_A3_0:
952 case WCD938X_DIGITAL_CDC_HPH_DSM_A3_1:
953 case WCD938X_DIGITAL_CDC_HPH_DSM_A4_0:
954 case WCD938X_DIGITAL_CDC_HPH_DSM_A4_1:
955 case WCD938X_DIGITAL_CDC_HPH_DSM_A5_0:
956 case WCD938X_DIGITAL_CDC_HPH_DSM_A5_1:
957 case WCD938X_DIGITAL_CDC_HPH_DSM_A6_0:
958 case WCD938X_DIGITAL_CDC_HPH_DSM_A7_0:
959 case WCD938X_DIGITAL_CDC_HPH_DSM_C_0:
960 case WCD938X_DIGITAL_CDC_HPH_DSM_C_1:
961 case WCD938X_DIGITAL_CDC_HPH_DSM_C_2:
962 case WCD938X_DIGITAL_CDC_HPH_DSM_C_3:
963 case WCD938X_DIGITAL_CDC_HPH_DSM_R1:
964 case WCD938X_DIGITAL_CDC_HPH_DSM_R2:
965 case WCD938X_DIGITAL_CDC_HPH_DSM_R3:
966 case WCD938X_DIGITAL_CDC_HPH_DSM_R4:
967 case WCD938X_DIGITAL_CDC_HPH_DSM_R5:
968 case WCD938X_DIGITAL_CDC_HPH_DSM_R6:
969 case WCD938X_DIGITAL_CDC_HPH_DSM_R7:
970 case WCD938X_DIGITAL_CDC_AUX_DSM_A1_0:
971 case WCD938X_DIGITAL_CDC_AUX_DSM_A1_1:
972 case WCD938X_DIGITAL_CDC_AUX_DSM_A2_0:
973 case WCD938X_DIGITAL_CDC_AUX_DSM_A2_1:
974 case WCD938X_DIGITAL_CDC_AUX_DSM_A3_0:
975 case WCD938X_DIGITAL_CDC_AUX_DSM_A3_1:
976 case WCD938X_DIGITAL_CDC_AUX_DSM_A4_0:
977 case WCD938X_DIGITAL_CDC_AUX_DSM_A4_1:
978 case WCD938X_DIGITAL_CDC_AUX_DSM_A5_0:
979 case WCD938X_DIGITAL_CDC_AUX_DSM_A5_1:
980 case WCD938X_DIGITAL_CDC_AUX_DSM_A6_0:
981 case WCD938X_DIGITAL_CDC_AUX_DSM_A7_0:
982 case WCD938X_DIGITAL_CDC_AUX_DSM_C_0:
983 case WCD938X_DIGITAL_CDC_AUX_DSM_C_1:
984 case WCD938X_DIGITAL_CDC_AUX_DSM_C_2:
985 case WCD938X_DIGITAL_CDC_AUX_DSM_C_3:
986 case WCD938X_DIGITAL_CDC_AUX_DSM_R1:
987 case WCD938X_DIGITAL_CDC_AUX_DSM_R2:
988 case WCD938X_DIGITAL_CDC_AUX_DSM_R3:
989 case WCD938X_DIGITAL_CDC_AUX_DSM_R4:
990 case WCD938X_DIGITAL_CDC_AUX_DSM_R5:
991 case WCD938X_DIGITAL_CDC_AUX_DSM_R6:
992 case WCD938X_DIGITAL_CDC_AUX_DSM_R7:
993 case WCD938X_DIGITAL_CDC_HPH_GAIN_RX_0:
994 case WCD938X_DIGITAL_CDC_HPH_GAIN_RX_1:
995 case WCD938X_DIGITAL_CDC_HPH_GAIN_DSD_0:
996 case WCD938X_DIGITAL_CDC_HPH_GAIN_DSD_1:
997 case WCD938X_DIGITAL_CDC_HPH_GAIN_DSD_2:
998 case WCD938X_DIGITAL_CDC_AUX_GAIN_DSD_0:
999 case WCD938X_DIGITAL_CDC_AUX_GAIN_DSD_1:
1000 case WCD938X_DIGITAL_CDC_AUX_GAIN_DSD_2:
1001 case WCD938X_DIGITAL_CDC_HPH_GAIN_CTL:
1002 case WCD938X_DIGITAL_CDC_AUX_GAIN_CTL:
1003 case WCD938X_DIGITAL_CDC_EAR_PATH_CTL:
1004 case WCD938X_DIGITAL_CDC_SWR_CLH:
1005 case WCD938X_DIGITAL_SWR_CLH_BYP:
1006 case WCD938X_DIGITAL_CDC_TX0_CTL:
1007 case WCD938X_DIGITAL_CDC_TX1_CTL:
1008 case WCD938X_DIGITAL_CDC_TX2_CTL:
1009 case WCD938X_DIGITAL_CDC_TX_RST:
1010 case WCD938X_DIGITAL_CDC_REQ_CTL:
1011 case WCD938X_DIGITAL_CDC_RST:
1012 case WCD938X_DIGITAL_CDC_AMIC_CTL:
1013 case WCD938X_DIGITAL_CDC_DMIC_CTL:
1014 case WCD938X_DIGITAL_CDC_DMIC1_CTL:
1015 case WCD938X_DIGITAL_CDC_DMIC2_CTL:
1016 case WCD938X_DIGITAL_CDC_DMIC3_CTL:
1017 case WCD938X_DIGITAL_CDC_DMIC4_CTL:
1018 case WCD938X_DIGITAL_EFUSE_PRG_CTL:
1019 case WCD938X_DIGITAL_EFUSE_CTL:
1020 case WCD938X_DIGITAL_CDC_DMIC_RATE_1_2:
1021 case WCD938X_DIGITAL_CDC_DMIC_RATE_3_4:
1022 case WCD938X_DIGITAL_PDM_WD_CTL0:
1023 case WCD938X_DIGITAL_PDM_WD_CTL1:
1024 case WCD938X_DIGITAL_PDM_WD_CTL2:
1025 case WCD938X_DIGITAL_INTR_MODE:
1026 case WCD938X_DIGITAL_INTR_MASK_0:
1027 case WCD938X_DIGITAL_INTR_MASK_1:
1028 case WCD938X_DIGITAL_INTR_MASK_2:
1029 case WCD938X_DIGITAL_INTR_CLEAR_0:
1030 case WCD938X_DIGITAL_INTR_CLEAR_1:
1031 case WCD938X_DIGITAL_INTR_CLEAR_2:
1032 case WCD938X_DIGITAL_INTR_LEVEL_0:
1033 case WCD938X_DIGITAL_INTR_LEVEL_1:
1034 case WCD938X_DIGITAL_INTR_LEVEL_2:
1035 case WCD938X_DIGITAL_INTR_SET_0:
1036 case WCD938X_DIGITAL_INTR_SET_1:
1037 case WCD938X_DIGITAL_INTR_SET_2:
1038 case WCD938X_DIGITAL_INTR_TEST_0:
1039 case WCD938X_DIGITAL_INTR_TEST_1:
1040 case WCD938X_DIGITAL_INTR_TEST_2:
1041 case WCD938X_DIGITAL_TX_MODE_DBG_EN:
1042 case WCD938X_DIGITAL_TX_MODE_DBG_0_1:
1043 case WCD938X_DIGITAL_TX_MODE_DBG_2_3:
1044 case WCD938X_DIGITAL_LB_IN_SEL_CTL:
1045 case WCD938X_DIGITAL_LOOP_BACK_MODE:
1046 case WCD938X_DIGITAL_SWR_DAC_TEST:
1047 case WCD938X_DIGITAL_SWR_HM_TEST_RX_0:
1048 case WCD938X_DIGITAL_SWR_HM_TEST_TX_0:
1049 case WCD938X_DIGITAL_SWR_HM_TEST_RX_1:
1050 case WCD938X_DIGITAL_SWR_HM_TEST_TX_1:
1051 case WCD938X_DIGITAL_SWR_HM_TEST_TX_2:
1052 case WCD938X_DIGITAL_PAD_CTL_SWR_0:
1053 case WCD938X_DIGITAL_PAD_CTL_SWR_1:
1054 case WCD938X_DIGITAL_I2C_CTL:
1055 case WCD938X_DIGITAL_CDC_TX_TANGGU_SW_MODE:
1056 case WCD938X_DIGITAL_EFUSE_TEST_CTL_0:
1057 case WCD938X_DIGITAL_EFUSE_TEST_CTL_1:
1058 case WCD938X_DIGITAL_PAD_CTL_PDM_RX0:
1059 case WCD938X_DIGITAL_PAD_CTL_PDM_RX1:
1060 case WCD938X_DIGITAL_PAD_CTL_PDM_TX0:
1061 case WCD938X_DIGITAL_PAD_CTL_PDM_TX1:
1062 case WCD938X_DIGITAL_PAD_CTL_PDM_TX2:
1063 case WCD938X_DIGITAL_PAD_INP_DIS_0:
1064 case WCD938X_DIGITAL_PAD_INP_DIS_1:
1065 case WCD938X_DIGITAL_DRIVE_STRENGTH_0:
1066 case WCD938X_DIGITAL_DRIVE_STRENGTH_1:
1067 case WCD938X_DIGITAL_DRIVE_STRENGTH_2:
1068 case WCD938X_DIGITAL_RX_DATA_EDGE_CTL:
1069 case WCD938X_DIGITAL_TX_DATA_EDGE_CTL:
1070 case WCD938X_DIGITAL_GPIO_MODE:
1071 case WCD938X_DIGITAL_PIN_CTL_OE:
1072 case WCD938X_DIGITAL_PIN_CTL_DATA_0:
1073 case WCD938X_DIGITAL_PIN_CTL_DATA_1:
1074 case WCD938X_DIGITAL_DIG_DEBUG_CTL:
1075 case WCD938X_DIGITAL_DIG_DEBUG_EN:
1076 case WCD938X_DIGITAL_ANA_CSR_DBG_ADD:
1077 case WCD938X_DIGITAL_ANA_CSR_DBG_CTL:
1078 case WCD938X_DIGITAL_SSP_DBG:
1079 case WCD938X_DIGITAL_SPARE_0:
1080 case WCD938X_DIGITAL_SPARE_1:
1081 case WCD938X_DIGITAL_SPARE_2:
1082 case WCD938X_DIGITAL_TX_REQ_FB_CTL_0:
1083 case WCD938X_DIGITAL_TX_REQ_FB_CTL_1:
1084 case WCD938X_DIGITAL_TX_REQ_FB_CTL_2:
1085 case WCD938X_DIGITAL_TX_REQ_FB_CTL_3:
1086 case WCD938X_DIGITAL_TX_REQ_FB_CTL_4:
1087 case WCD938X_DIGITAL_DEM_BYPASS_DATA0:
1088 case WCD938X_DIGITAL_DEM_BYPASS_DATA1:
1089 case WCD938X_DIGITAL_DEM_BYPASS_DATA2:
1090 case WCD938X_DIGITAL_DEM_BYPASS_DATA3:
1091 return true;
1092 }
1093
1094 return false;
1095}
1096
1097static bool wcd938x_readonly_register(struct device *dev, unsigned int reg)
1098{
1099 switch (reg) {
1100 case WCD938X_ANA_MBHC_RESULT_1:
1101 case WCD938X_ANA_MBHC_RESULT_2:
1102 case WCD938X_ANA_MBHC_RESULT_3:
1103 case WCD938X_MBHC_MOISTURE_DET_FSM_STATUS:
1104 case WCD938X_TX_1_2_SAR2_ERR:
1105 case WCD938X_TX_1_2_SAR1_ERR:
1106 case WCD938X_TX_3_4_SAR4_ERR:
1107 case WCD938X_TX_3_4_SAR3_ERR:
1108 case WCD938X_HPH_L_STATUS:
1109 case WCD938X_HPH_R_STATUS:
1110 case WCD938X_HPH_SURGE_HPHLR_SURGE_STATUS:
1111 case WCD938X_EAR_STATUS_REG_1:
1112 case WCD938X_EAR_STATUS_REG_2:
1113 case WCD938X_MBHC_NEW_FSM_STATUS:
1114 case WCD938X_MBHC_NEW_ADC_RESULT:
1115 case WCD938X_DIE_CRACK_DIE_CRK_DET_OUT:
1116 case WCD938X_AUX_INT_STATUS_REG:
1117 case WCD938X_LDORXTX_INT_STATUS:
1118 case WCD938X_DIGITAL_CHIP_ID0:
1119 case WCD938X_DIGITAL_CHIP_ID1:
1120 case WCD938X_DIGITAL_CHIP_ID2:
1121 case WCD938X_DIGITAL_CHIP_ID3:
1122 case WCD938X_DIGITAL_INTR_STATUS_0:
1123 case WCD938X_DIGITAL_INTR_STATUS_1:
1124 case WCD938X_DIGITAL_INTR_STATUS_2:
1125 case WCD938X_DIGITAL_SWR_HM_TEST_0:
1126 case WCD938X_DIGITAL_SWR_HM_TEST_1:
1127 case WCD938X_DIGITAL_EFUSE_T_DATA_0:
1128 case WCD938X_DIGITAL_EFUSE_T_DATA_1:
1129 case WCD938X_DIGITAL_PIN_STATUS_0:
1130 case WCD938X_DIGITAL_PIN_STATUS_1:
1131 case WCD938X_DIGITAL_MODE_STATUS_0:
1132 case WCD938X_DIGITAL_MODE_STATUS_1:
1133 case WCD938X_DIGITAL_EFUSE_REG_0:
1134 case WCD938X_DIGITAL_EFUSE_REG_1:
1135 case WCD938X_DIGITAL_EFUSE_REG_2:
1136 case WCD938X_DIGITAL_EFUSE_REG_3:
1137 case WCD938X_DIGITAL_EFUSE_REG_4:
1138 case WCD938X_DIGITAL_EFUSE_REG_5:
1139 case WCD938X_DIGITAL_EFUSE_REG_6:
1140 case WCD938X_DIGITAL_EFUSE_REG_7:
1141 case WCD938X_DIGITAL_EFUSE_REG_8:
1142 case WCD938X_DIGITAL_EFUSE_REG_9:
1143 case WCD938X_DIGITAL_EFUSE_REG_10:
1144 case WCD938X_DIGITAL_EFUSE_REG_11:
1145 case WCD938X_DIGITAL_EFUSE_REG_12:
1146 case WCD938X_DIGITAL_EFUSE_REG_13:
1147 case WCD938X_DIGITAL_EFUSE_REG_14:
1148 case WCD938X_DIGITAL_EFUSE_REG_15:
1149 case WCD938X_DIGITAL_EFUSE_REG_16:
1150 case WCD938X_DIGITAL_EFUSE_REG_17:
1151 case WCD938X_DIGITAL_EFUSE_REG_18:
1152 case WCD938X_DIGITAL_EFUSE_REG_19:
1153 case WCD938X_DIGITAL_EFUSE_REG_20:
1154 case WCD938X_DIGITAL_EFUSE_REG_21:
1155 case WCD938X_DIGITAL_EFUSE_REG_22:
1156 case WCD938X_DIGITAL_EFUSE_REG_23:
1157 case WCD938X_DIGITAL_EFUSE_REG_24:
1158 case WCD938X_DIGITAL_EFUSE_REG_25:
1159 case WCD938X_DIGITAL_EFUSE_REG_26:
1160 case WCD938X_DIGITAL_EFUSE_REG_27:
1161 case WCD938X_DIGITAL_EFUSE_REG_28:
1162 case WCD938X_DIGITAL_EFUSE_REG_29:
1163 case WCD938X_DIGITAL_EFUSE_REG_30:
1164 case WCD938X_DIGITAL_EFUSE_REG_31:
1165 return true;
1166 }
1167 return false;
1168}
1169
1170static bool wcd938x_readable_register(struct device *dev, unsigned int reg)
1171{
1172 bool ret;
1173
1174 ret = wcd938x_readonly_register(dev, reg);
1175 if (!ret)
1176 return wcd938x_rdwr_register(dev, reg);
1177
1178 return ret;
1179}
1180
1181static bool wcd938x_writeable_register(struct device *dev, unsigned int reg)
1182{
1183 return wcd938x_rdwr_register(dev, reg);
1184}
1185
1186static bool wcd938x_volatile_register(struct device *dev, unsigned int reg)
1187{
1188 if (reg <= WCD938X_BASE_ADDRESS)
Yang Li83bd5c52021-06-16 10:45:35 +0800[diff] [blame]1189 return false;
Srinivas Kandagatla8d786022021-06-09 10:09:37 +0100[diff] [blame]1190
1191 if (reg == WCD938X_DIGITAL_SWR_TX_CLK_RATE)
1192 return true;
1193
1194 if (wcd938x_readonly_register(dev, reg))
1195 return true;
1196
1197 return false;
1198}
1199
Srinivas Kandagatlab90d9392021-06-15 14:28:29 +0100[diff] [blame]1200static struct regmap_config wcd938x_regmap_config = {
Srinivas Kandagatla8d786022021-06-09 10:09:37 +0100[diff] [blame]1201 .name = "wcd938x_csr",
1202 .reg_bits = 32,
1203 .val_bits = 8,
1204 .cache_type = REGCACHE_RBTREE,
1205 .reg_defaults = wcd938x_defaults,
1206 .num_reg_defaults = ARRAY_SIZE(wcd938x_defaults),
1207 .max_register = WCD938X_MAX_REGISTER,
1208 .readable_reg = wcd938x_readable_register,
1209 .writeable_reg = wcd938x_writeable_register,
1210 .volatile_reg = wcd938x_volatile_register,
1211 .can_multi_write = true,
1212};
Srinivas Kandagatla8d786022021-06-09 10:09:37 +0100[diff] [blame]1213
1214static const struct regmap_irq wcd938x_irqs[WCD938X_NUM_IRQS] = {
1215 REGMAP_IRQ_REG(WCD938X_IRQ_MBHC_BUTTON_PRESS_DET, 0, 0x01),
1216 REGMAP_IRQ_REG(WCD938X_IRQ_MBHC_BUTTON_RELEASE_DET, 0, 0x02),
1217 REGMAP_IRQ_REG(WCD938X_IRQ_MBHC_ELECT_INS_REM_DET, 0, 0x04),
1218 REGMAP_IRQ_REG(WCD938X_IRQ_MBHC_ELECT_INS_REM_LEG_DET, 0, 0x08),
1219 REGMAP_IRQ_REG(WCD938X_IRQ_MBHC_SW_DET, 0, 0x10),
1220 REGMAP_IRQ_REG(WCD938X_IRQ_HPHR_OCP_INT, 0, 0x20),
1221 REGMAP_IRQ_REG(WCD938X_IRQ_HPHR_CNP_INT, 0, 0x40),
1222 REGMAP_IRQ_REG(WCD938X_IRQ_HPHL_OCP_INT, 0, 0x80),
1223 REGMAP_IRQ_REG(WCD938X_IRQ_HPHL_CNP_INT, 1, 0x01),
1224 REGMAP_IRQ_REG(WCD938X_IRQ_EAR_CNP_INT, 1, 0x02),
1225 REGMAP_IRQ_REG(WCD938X_IRQ_EAR_SCD_INT, 1, 0x04),
1226 REGMAP_IRQ_REG(WCD938X_IRQ_AUX_CNP_INT, 1, 0x08),
1227 REGMAP_IRQ_REG(WCD938X_IRQ_AUX_SCD_INT, 1, 0x10),
1228 REGMAP_IRQ_REG(WCD938X_IRQ_HPHL_PDM_WD_INT, 1, 0x20),
1229 REGMAP_IRQ_REG(WCD938X_IRQ_HPHR_PDM_WD_INT, 1, 0x40),
1230 REGMAP_IRQ_REG(WCD938X_IRQ_AUX_PDM_WD_INT, 1, 0x80),
1231 REGMAP_IRQ_REG(WCD938X_IRQ_LDORT_SCD_INT, 2, 0x01),
1232 REGMAP_IRQ_REG(WCD938X_IRQ_MBHC_MOISTURE_INT, 2, 0x02),
1233 REGMAP_IRQ_REG(WCD938X_IRQ_HPHL_SURGE_DET_INT, 2, 0x04),
1234 REGMAP_IRQ_REG(WCD938X_IRQ_HPHR_SURGE_DET_INT, 2, 0x08),
1235};
1236
1237static struct regmap_irq_chip wcd938x_regmap_irq_chip = {
1238 .name = "wcd938x",
1239 .irqs = wcd938x_irqs,
1240 .num_irqs = ARRAY_SIZE(wcd938x_irqs),
1241 .num_regs = 3,
1242 .status_base = WCD938X_DIGITAL_INTR_STATUS_0,
1243 .mask_base = WCD938X_DIGITAL_INTR_MASK_0,
1244 .type_base = WCD938X_DIGITAL_INTR_LEVEL_0,
1245 .ack_base = WCD938X_DIGITAL_INTR_CLEAR_0,
1246 .use_ack = 1,
1247 .runtime_pm = true,
1248 .irq_drv_data = NULL,
1249};
1250
Srinivas Kandagatlad5add082021-06-09 10:09:42 +0100[diff] [blame]1251static int wcd938x_get_clk_rate(int mode)
1252{
1253 int rate;
1254
1255 switch (mode) {
1256 case ADC_MODE_ULP2:
1257 rate = SWR_CLK_RATE_0P6MHZ;
1258 break;
1259 case ADC_MODE_ULP1:
1260 rate = SWR_CLK_RATE_1P2MHZ;
1261 break;
1262 case ADC_MODE_LP:
1263 rate = SWR_CLK_RATE_4P8MHZ;
1264 break;
1265 case ADC_MODE_NORMAL:
1266 case ADC_MODE_LO_HIF:
1267 case ADC_MODE_HIFI:
1268 case ADC_MODE_INVALID:
1269 default:
1270 rate = SWR_CLK_RATE_9P6MHZ;
1271 break;
1272 }
1273
1274 return rate;
1275}
1276
1277static int wcd938x_set_swr_clk_rate(struct snd_soc_component *component, int rate, int bank)
1278{
1279 u8 mask = (bank ? 0xF0 : 0x0F);
1280 u8 val = 0;
1281
1282 switch (rate) {
1283 case SWR_CLK_RATE_0P6MHZ:
1284 val = (bank ? 0x60 : 0x06);
1285 break;
1286 case SWR_CLK_RATE_1P2MHZ:
1287 val = (bank ? 0x50 : 0x05);
1288 break;
1289 case SWR_CLK_RATE_2P4MHZ:
1290 val = (bank ? 0x30 : 0x03);
1291 break;
1292 case SWR_CLK_RATE_4P8MHZ:
1293 val = (bank ? 0x10 : 0x01);
1294 break;
1295 case SWR_CLK_RATE_9P6MHZ:
1296 default:
1297 val = 0x00;
1298 break;
1299 }
1300 snd_soc_component_update_bits(component, WCD938X_DIGITAL_SWR_TX_CLK_RATE,
1301 mask, val);
1302
1303 return 0;
1304}
1305
Srinivas Kandagatla8d786022021-06-09 10:09:37 +0100[diff] [blame]1306static int wcd938x_io_init(struct wcd938x_priv *wcd938x)
1307{
1308 struct regmap *rm = wcd938x->regmap;
1309
1310 regmap_update_bits(rm, WCD938X_SLEEP_CTL, 0x0E, 0x0E);
1311 regmap_update_bits(rm, WCD938X_SLEEP_CTL, 0x80, 0x80);
1312 /* 1 msec delay as per HW requirement */
1313 usleep_range(1000, 1010);
1314 regmap_update_bits(rm, WCD938X_SLEEP_CTL, 0x40, 0x40);
1315 /* 1 msec delay as per HW requirement */
1316 usleep_range(1000, 1010);
1317 regmap_update_bits(rm, WCD938X_LDORXTX_CONFIG, 0x10, 0x00);
1318 regmap_update_bits(rm, WCD938X_BIAS_VBG_FINE_ADJ,
1319 0xF0, 0x80);
1320 regmap_update_bits(rm, WCD938X_ANA_BIAS, 0x80, 0x80);
1321 regmap_update_bits(rm, WCD938X_ANA_BIAS, 0x40, 0x40);
1322 /* 10 msec delay as per HW requirement */
1323 usleep_range(10000, 10010);
1324
1325 regmap_update_bits(rm, WCD938X_ANA_BIAS, 0x40, 0x00);
1326 regmap_update_bits(rm, WCD938X_HPH_NEW_INT_RDAC_GAIN_CTL,
1327 0xF0, 0x00);
1328 regmap_update_bits(rm, WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_L_NEW,
1329 0x1F, 0x15);
1330 regmap_update_bits(rm, WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_R_NEW,
1331 0x1F, 0x15);
1332 regmap_update_bits(rm, WCD938X_HPH_REFBUFF_UHQA_CTL,
1333 0xC0, 0x80);
1334 regmap_update_bits(rm, WCD938X_DIGITAL_CDC_DMIC_CTL,
1335 0x02, 0x02);
1336
1337 regmap_update_bits(rm, WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG2CASC_ULP,
1338 0xFF, 0x14);
1339 regmap_update_bits(rm, WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG2MAIN_ULP,
1340 0x1F, 0x08);
1341
1342 regmap_update_bits(rm, WCD938X_DIGITAL_TX_REQ_FB_CTL_0, 0xFF, 0x55);
1343 regmap_update_bits(rm, WCD938X_DIGITAL_TX_REQ_FB_CTL_1, 0xFF, 0x44);
1344 regmap_update_bits(rm, WCD938X_DIGITAL_TX_REQ_FB_CTL_2, 0xFF, 0x11);
1345 regmap_update_bits(rm, WCD938X_DIGITAL_TX_REQ_FB_CTL_3, 0xFF, 0x00);
1346 regmap_update_bits(rm, WCD938X_DIGITAL_TX_REQ_FB_CTL_4, 0xFF, 0x00);
1347
1348 /* Set Noise Filter Resistor value */
1349 regmap_update_bits(rm, WCD938X_MICB1_TEST_CTL_1, 0xE0, 0xE0);
1350 regmap_update_bits(rm, WCD938X_MICB2_TEST_CTL_1, 0xE0, 0xE0);
1351 regmap_update_bits(rm, WCD938X_MICB3_TEST_CTL_1, 0xE0, 0xE0);
1352 regmap_update_bits(rm, WCD938X_MICB4_TEST_CTL_1, 0xE0, 0xE0);
1353
1354 regmap_update_bits(rm, WCD938X_TX_3_4_TEST_BLK_EN2, 0x01, 0x00);
1355 regmap_update_bits(rm, WCD938X_HPH_SURGE_HPHLR_SURGE_EN, 0xC0, 0xC0);
1356
1357 return 0;
1358
1359}
1360
Srinivas Kandagatlae8ba1e02021-06-09 10:09:40 +0100[diff] [blame]1361static int wcd938x_sdw_connect_port(struct wcd938x_sdw_ch_info *ch_info,
1362 struct sdw_port_config *port_config,
1363 u32 mstr_port_num,
1364 u8 enable)
1365{
1366 u8 ch_mask, port_num;
1367
1368 port_num = ch_info->port_num;
1369 ch_mask = ch_info->ch_mask;
1370
1371 port_config->num = port_num;
1372
1373 if (enable)
1374 port_config->ch_mask |= ch_mask;
1375 else
1376 port_config->ch_mask &= ~ch_mask;
1377
1378 return 0;
1379}
1380
1381static int wcd938x_connect_port(struct wcd938x_sdw_priv *wcd, u8 ch_id, u8 enable)
1382{
1383 u8 port_num, mstr_port_num;
1384
1385 port_num = wcd->ch_info[ch_id].port_num;
1386 mstr_port_num = wcd->port_map[port_num - 1];
1387
1388 return wcd938x_sdw_connect_port(&wcd->ch_info[ch_id],
1389 &wcd->port_config[port_num],
1390 mstr_port_num,
1391 enable);
1392}
1393
Srinivas Kandagatla8da9db02021-06-09 10:09:41 +0100[diff] [blame]1394static int wcd938x_codec_enable_rxclk(struct snd_soc_dapm_widget *w,
1395 struct snd_kcontrol *kcontrol,
1396 int event)
1397{
1398 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
1399
1400 switch (event) {
1401 case SND_SOC_DAPM_PRE_PMU:
1402 snd_soc_component_write_field(component, WCD938X_DIGITAL_CDC_ANA_CLK_CTL,
1403 WCD938X_ANA_RX_CLK_EN_MASK, 1);
1404 snd_soc_component_write_field(component, WCD938X_ANA_RX_SUPPLIES,
1405 WCD938X_RX_BIAS_EN_MASK, 1);
1406 snd_soc_component_write_field(component, WCD938X_DIGITAL_CDC_RX0_CTL,
1407 WCD938X_DEM_DITHER_ENABLE_MASK, 0);
1408 snd_soc_component_write_field(component, WCD938X_DIGITAL_CDC_RX1_CTL,
1409 WCD938X_DEM_DITHER_ENABLE_MASK, 0);
1410 snd_soc_component_write_field(component, WCD938X_DIGITAL_CDC_RX2_CTL,
1411 WCD938X_DEM_DITHER_ENABLE_MASK, 0);
1412 snd_soc_component_write_field(component, WCD938X_DIGITAL_CDC_ANA_CLK_CTL,
1413 WCD938X_ANA_RX_DIV2_CLK_EN_MASK, 1);
1414 snd_soc_component_write_field(component, WCD938X_AUX_AUXPA,
1415 WCD938X_AUXPA_CLK_EN_MASK, 1);
1416 break;
1417 case SND_SOC_DAPM_POST_PMD:
1418 snd_soc_component_write_field(component, WCD938X_ANA_RX_SUPPLIES,
1419 WCD938X_VNEG_EN_MASK, 0);
1420 snd_soc_component_write_field(component, WCD938X_ANA_RX_SUPPLIES,
1421 WCD938X_VPOS_EN_MASK, 0);
1422 snd_soc_component_write_field(component, WCD938X_ANA_RX_SUPPLIES,
1423 WCD938X_RX_BIAS_EN_MASK, 0);
1424 snd_soc_component_write_field(component, WCD938X_DIGITAL_CDC_ANA_CLK_CTL,
1425 WCD938X_ANA_RX_DIV2_CLK_EN_MASK, 0);
1426 snd_soc_component_write_field(component, WCD938X_DIGITAL_CDC_ANA_CLK_CTL,
1427 WCD938X_ANA_RX_CLK_EN_MASK, 0);
1428 break;
1429 }
1430 return 0;
1431}
1432
1433static int wcd938x_codec_hphl_dac_event(struct snd_soc_dapm_widget *w,
1434 struct snd_kcontrol *kcontrol,
1435 int event)
1436{
1437 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
1438 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
1439
1440 switch (event) {
1441 case SND_SOC_DAPM_PRE_PMU:
1442 snd_soc_component_write_field(component,
1443 WCD938X_DIGITAL_CDC_DIG_CLK_CTL,
1444 WCD938X_RXD0_CLK_EN_MASK, 0x01);
1445 snd_soc_component_write_field(component,
1446 WCD938X_DIGITAL_CDC_HPH_GAIN_CTL,
1447 WCD938X_HPHL_RX_EN_MASK, 1);
1448 snd_soc_component_write_field(component,
1449 WCD938X_HPH_RDAC_CLK_CTL1,
1450 WCD938X_CHOP_CLK_EN_MASK, 0);
1451 break;
1452 case SND_SOC_DAPM_POST_PMU:
1453 snd_soc_component_write_field(component,
1454 WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_L,
1455 WCD938X_HPH_RES_DIV_MASK, 0x02);
1456 if (wcd938x->comp1_enable) {
1457 snd_soc_component_write_field(component,
1458 WCD938X_DIGITAL_CDC_COMP_CTL_0,
1459 WCD938X_HPHL_COMP_EN_MASK, 1);
1460 /* 5msec compander delay as per HW requirement */
1461 if (!wcd938x->comp2_enable || (snd_soc_component_read(component,
1462 WCD938X_DIGITAL_CDC_COMP_CTL_0) & 0x01))
1463 usleep_range(5000, 5010);
1464 snd_soc_component_write_field(component, WCD938X_HPH_NEW_INT_HPH_TIMER1,
1465 WCD938X_AUTOCHOP_TIMER_EN, 0);
1466 } else {
1467 snd_soc_component_write_field(component,
1468 WCD938X_DIGITAL_CDC_COMP_CTL_0,
1469 WCD938X_HPHL_COMP_EN_MASK, 0);
1470 snd_soc_component_write_field(component,
1471 WCD938X_HPH_L_EN,
1472 WCD938X_GAIN_SRC_SEL_MASK,
1473 WCD938X_GAIN_SRC_SEL_REGISTER);
1474
1475 }
1476 break;
1477 case SND_SOC_DAPM_POST_PMD:
1478 snd_soc_component_write_field(component,
1479 WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_R,
1480 WCD938X_HPH_RES_DIV_MASK, 0x1);
1481 break;
1482 }
1483
1484 return 0;
1485}
1486
1487static int wcd938x_codec_hphr_dac_event(struct snd_soc_dapm_widget *w,
1488 struct snd_kcontrol *kcontrol,
1489 int event)
1490{
1491 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
1492 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
1493
1494 switch (event) {
1495 case SND_SOC_DAPM_PRE_PMU:
1496 snd_soc_component_write_field(component,
1497 WCD938X_DIGITAL_CDC_DIG_CLK_CTL,
1498 WCD938X_RXD1_CLK_EN_MASK, 1);
1499 snd_soc_component_write_field(component,
1500 WCD938X_DIGITAL_CDC_HPH_GAIN_CTL,
1501 WCD938X_HPHR_RX_EN_MASK, 1);
1502 snd_soc_component_write_field(component,
1503 WCD938X_HPH_RDAC_CLK_CTL1,
1504 WCD938X_CHOP_CLK_EN_MASK, 0);
1505 break;
1506 case SND_SOC_DAPM_POST_PMU:
1507 snd_soc_component_write_field(component,
1508 WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_R,
1509 WCD938X_HPH_RES_DIV_MASK, 0x02);
1510 if (wcd938x->comp2_enable) {
1511 snd_soc_component_write_field(component,
1512 WCD938X_DIGITAL_CDC_COMP_CTL_0,
1513 WCD938X_HPHR_COMP_EN_MASK, 1);
1514 /* 5msec compander delay as per HW requirement */
1515 if (!wcd938x->comp1_enable ||
1516 (snd_soc_component_read(component,
1517 WCD938X_DIGITAL_CDC_COMP_CTL_0) & 0x02))
1518 usleep_range(5000, 5010);
1519 snd_soc_component_write_field(component, WCD938X_HPH_NEW_INT_HPH_TIMER1,
1520 WCD938X_AUTOCHOP_TIMER_EN, 0);
1521 } else {
1522 snd_soc_component_write_field(component,
1523 WCD938X_DIGITAL_CDC_COMP_CTL_0,
1524 WCD938X_HPHR_COMP_EN_MASK, 0);
1525 snd_soc_component_write_field(component,
1526 WCD938X_HPH_R_EN,
1527 WCD938X_GAIN_SRC_SEL_MASK,
1528 WCD938X_GAIN_SRC_SEL_REGISTER);
1529 }
1530 break;
1531 case SND_SOC_DAPM_POST_PMD:
1532 snd_soc_component_write_field(component,
1533 WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_R,
1534 WCD938X_HPH_RES_DIV_MASK, 0x01);
1535 break;
1536 }
1537
1538 return 0;
1539}
1540
1541static int wcd938x_codec_ear_dac_event(struct snd_soc_dapm_widget *w,
1542 struct snd_kcontrol *kcontrol,
1543 int event)
1544{
1545 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
1546 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
1547
1548 switch (event) {
1549 case SND_SOC_DAPM_PRE_PMU:
1550 wcd938x->ear_rx_path =
1551 snd_soc_component_read(
1552 component, WCD938X_DIGITAL_CDC_EAR_PATH_CTL);
1553 if (wcd938x->ear_rx_path & EAR_RX_PATH_AUX) {
1554 snd_soc_component_write_field(component,
1555 WCD938X_EAR_EAR_DAC_CON,
1556 WCD938X_DAC_SAMPLE_EDGE_SEL_MASK, 0);
1557 snd_soc_component_write_field(component,
1558 WCD938X_DIGITAL_CDC_AUX_GAIN_CTL,
1559 WCD938X_AUX_EN_MASK, 1);
1560 snd_soc_component_write_field(component,
1561 WCD938X_DIGITAL_CDC_DIG_CLK_CTL,
1562 WCD938X_RXD2_CLK_EN_MASK, 1);
1563 snd_soc_component_write_field(component,
1564 WCD938X_ANA_EAR_COMPANDER_CTL,
1565 WCD938X_GAIN_OVRD_REG_MASK, 1);
1566 } else {
1567 snd_soc_component_write_field(component,
1568 WCD938X_DIGITAL_CDC_HPH_GAIN_CTL,
1569 WCD938X_HPHL_RX_EN_MASK, 1);
1570 snd_soc_component_write_field(component,
1571 WCD938X_DIGITAL_CDC_DIG_CLK_CTL,
1572 WCD938X_RXD0_CLK_EN_MASK, 1);
1573 if (wcd938x->comp1_enable)
1574 snd_soc_component_write_field(component,
1575 WCD938X_DIGITAL_CDC_COMP_CTL_0,
1576 WCD938X_HPHL_COMP_EN_MASK, 1);
1577 }
1578 /* 5 msec delay as per HW requirement */
1579 usleep_range(5000, 5010);
1580 if (wcd938x->flyback_cur_det_disable == 0)
1581 snd_soc_component_write_field(component, WCD938X_FLYBACK_EN,
1582 WCD938X_EN_CUR_DET_MASK, 0);
1583 wcd938x->flyback_cur_det_disable++;
1584 wcd_clsh_ctrl_set_state(wcd938x->clsh_info,
1585 WCD_CLSH_EVENT_PRE_DAC,
1586 WCD_CLSH_STATE_EAR,
1587 wcd938x->hph_mode);
1588 break;
1589 case SND_SOC_DAPM_POST_PMD:
1590 if (wcd938x->ear_rx_path & EAR_RX_PATH_AUX) {
1591 snd_soc_component_write_field(component,
1592 WCD938X_DIGITAL_CDC_AUX_GAIN_CTL,
1593 WCD938X_AUX_EN_MASK, 0);
1594 snd_soc_component_write_field(component,
1595 WCD938X_DIGITAL_CDC_DIG_CLK_CTL,
1596 WCD938X_RXD2_CLK_EN_MASK, 0);
1597 } else {
1598 snd_soc_component_write_field(component,
1599 WCD938X_DIGITAL_CDC_HPH_GAIN_CTL,
1600 WCD938X_HPHL_RX_EN_MASK, 0);
1601 snd_soc_component_write_field(component,
1602 WCD938X_DIGITAL_CDC_DIG_CLK_CTL,
1603 WCD938X_RXD0_CLK_EN_MASK, 0);
1604 if (wcd938x->comp1_enable)
1605 snd_soc_component_write_field(component,
1606 WCD938X_DIGITAL_CDC_COMP_CTL_0,
1607 WCD938X_HPHL_COMP_EN_MASK, 0);
1608 }
1609 snd_soc_component_write_field(component, WCD938X_ANA_EAR_COMPANDER_CTL,
1610 WCD938X_GAIN_OVRD_REG_MASK, 0);
1611 snd_soc_component_write_field(component,
1612 WCD938X_EAR_EAR_DAC_CON,
1613 WCD938X_DAC_SAMPLE_EDGE_SEL_MASK, 1);
1614 break;
1615 }
1616 return 0;
1617
1618}
1619
1620static int wcd938x_codec_aux_dac_event(struct snd_soc_dapm_widget *w,
1621 struct snd_kcontrol *kcontrol,
1622 int event)
1623{
1624 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
1625 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
Srinivas Kandagatla8da9db02021-06-09 10:09:41 +0100[diff] [blame]1626
1627 switch (event) {
1628 case SND_SOC_DAPM_PRE_PMU:
1629 snd_soc_component_write_field(component,
1630 WCD938X_DIGITAL_CDC_ANA_CLK_CTL,
1631 WCD938X_ANA_RX_DIV4_CLK_EN_MASK, 1);
1632 snd_soc_component_write_field(component,
1633 WCD938X_DIGITAL_CDC_DIG_CLK_CTL,
1634 WCD938X_RXD2_CLK_EN_MASK, 1);
1635 snd_soc_component_write_field(component,
1636 WCD938X_DIGITAL_CDC_AUX_GAIN_CTL,
1637 WCD938X_AUX_EN_MASK, 1);
1638 if (wcd938x->flyback_cur_det_disable == 0)
1639 snd_soc_component_write_field(component, WCD938X_FLYBACK_EN,
1640 WCD938X_EN_CUR_DET_MASK, 0);
1641 wcd938x->flyback_cur_det_disable++;
1642 wcd_clsh_ctrl_set_state(wcd938x->clsh_info,
1643 WCD_CLSH_EVENT_PRE_DAC,
1644 WCD_CLSH_STATE_AUX,
1645 wcd938x->hph_mode);
1646 break;
1647 case SND_SOC_DAPM_POST_PMD:
1648 snd_soc_component_write_field(component,
1649 WCD938X_DIGITAL_CDC_ANA_CLK_CTL,
1650 WCD938X_ANA_RX_DIV4_CLK_EN_MASK, 0);
1651 break;
1652 }
kernel test robot4d0b79e2021-06-29 21:29:09 +0800[diff] [blame]1653 return 0;
Srinivas Kandagatla8da9db02021-06-09 10:09:41 +0100[diff] [blame]1654
1655}
1656
1657static int wcd938x_codec_enable_hphr_pa(struct snd_soc_dapm_widget *w,
1658 struct snd_kcontrol *kcontrol, int event)
1659{
1660 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
1661 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
1662 int hph_mode = wcd938x->hph_mode;
1663
1664 switch (event) {
1665 case SND_SOC_DAPM_PRE_PMU:
1666 if (wcd938x->ldoh)
1667 snd_soc_component_write_field(component, WCD938X_LDOH_MODE,
1668 WCD938X_LDOH_EN_MASK, 1);
1669 wcd_clsh_ctrl_set_state(wcd938x->clsh_info, WCD_CLSH_EVENT_PRE_DAC,
1670 WCD_CLSH_STATE_HPHR, hph_mode);
1671 wcd_clsh_set_hph_mode(wcd938x->clsh_info, CLS_H_HIFI);
1672
1673 if (hph_mode == CLS_H_LP || hph_mode == CLS_H_LOHIFI ||
1674 hph_mode == CLS_H_ULP) {
1675 snd_soc_component_write_field(component,
1676 WCD938X_HPH_REFBUFF_LP_CTL,
1677 WCD938X_PREREF_FLIT_BYPASS_MASK, 1);
1678 }
1679 snd_soc_component_write_field(component, WCD938X_ANA_HPH,
1680 WCD938X_HPHR_REF_EN_MASK, 1);
1681 wcd_clsh_set_hph_mode(wcd938x->clsh_info, hph_mode);
1682 /* 100 usec delay as per HW requirement */
1683 usleep_range(100, 110);
1684 set_bit(HPH_PA_DELAY, &wcd938x->status_mask);
1685 snd_soc_component_write_field(component,
1686 WCD938X_DIGITAL_PDM_WD_CTL1,
1687 WCD938X_PDM_WD_EN_MASK, 0x3);
1688 break;
1689 case SND_SOC_DAPM_POST_PMU:
1690 /*
1691 * 7ms sleep is required if compander is enabled as per
1692 * HW requirement. If compander is disabled, then
1693 * 20ms delay is required.
1694 */
1695 if (test_bit(HPH_PA_DELAY, &wcd938x->status_mask)) {
1696 if (!wcd938x->comp2_enable)
1697 usleep_range(20000, 20100);
1698 else
1699 usleep_range(7000, 7100);
1700
1701 if (hph_mode == CLS_H_LP || hph_mode == CLS_H_LOHIFI ||
1702 hph_mode == CLS_H_ULP)
1703 snd_soc_component_write_field(component,
1704 WCD938X_HPH_REFBUFF_LP_CTL,
1705 WCD938X_PREREF_FLIT_BYPASS_MASK, 0);
1706 clear_bit(HPH_PA_DELAY, &wcd938x->status_mask);
1707 }
1708 snd_soc_component_write_field(component, WCD938X_HPH_NEW_INT_HPH_TIMER1,
1709 WCD938X_AUTOCHOP_TIMER_EN, 1);
1710 if (hph_mode == CLS_AB || hph_mode == CLS_AB_HIFI ||
1711 hph_mode == CLS_AB_LP || hph_mode == CLS_AB_LOHIFI)
1712 snd_soc_component_write_field(component, WCD938X_ANA_RX_SUPPLIES,
1713 WCD938X_REGULATOR_MODE_MASK,
1714 WCD938X_REGULATOR_MODE_CLASS_AB);
1715 enable_irq(wcd938x->hphr_pdm_wd_int);
1716 break;
1717 case SND_SOC_DAPM_PRE_PMD:
1718 disable_irq_nosync(wcd938x->hphr_pdm_wd_int);
1719 /*
1720 * 7ms sleep is required if compander is enabled as per
1721 * HW requirement. If compander is disabled, then
1722 * 20ms delay is required.
1723 */
1724 if (!wcd938x->comp2_enable)
1725 usleep_range(20000, 20100);
1726 else
1727 usleep_range(7000, 7100);
1728 snd_soc_component_write_field(component, WCD938X_ANA_HPH,
1729 WCD938X_HPHR_EN_MASK, 0);
1730 set_bit(HPH_PA_DELAY, &wcd938x->status_mask);
1731 break;
1732 case SND_SOC_DAPM_POST_PMD:
1733 /*
1734 * 7ms sleep is required if compander is enabled as per
1735 * HW requirement. If compander is disabled, then
1736 * 20ms delay is required.
1737 */
1738 if (test_bit(HPH_PA_DELAY, &wcd938x->status_mask)) {
1739 if (!wcd938x->comp2_enable)
1740 usleep_range(20000, 20100);
1741 else
1742 usleep_range(7000, 7100);
1743 clear_bit(HPH_PA_DELAY, &wcd938x->status_mask);
1744 }
1745 snd_soc_component_write_field(component, WCD938X_ANA_HPH,
1746 WCD938X_HPHR_REF_EN_MASK, 0);
1747 snd_soc_component_write_field(component, WCD938X_DIGITAL_PDM_WD_CTL1,
1748 WCD938X_PDM_WD_EN_MASK, 0);
1749 wcd_clsh_ctrl_set_state(wcd938x->clsh_info, WCD_CLSH_EVENT_POST_PA,
1750 WCD_CLSH_STATE_HPHR, hph_mode);
1751 if (wcd938x->ldoh)
1752 snd_soc_component_write_field(component, WCD938X_LDOH_MODE,
1753 WCD938X_LDOH_EN_MASK, 0);
1754 break;
1755 }
1756
1757 return 0;
1758}
1759
1760static int wcd938x_codec_enable_hphl_pa(struct snd_soc_dapm_widget *w,
1761 struct snd_kcontrol *kcontrol, int event)
1762{
1763 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
1764 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
1765 int hph_mode = wcd938x->hph_mode;
1766
1767 switch (event) {
1768 case SND_SOC_DAPM_PRE_PMU:
1769 if (wcd938x->ldoh)
1770 snd_soc_component_write_field(component, WCD938X_LDOH_MODE,
1771 WCD938X_LDOH_EN_MASK, 1);
1772 wcd_clsh_ctrl_set_state(wcd938x->clsh_info, WCD_CLSH_EVENT_PRE_DAC,
1773 WCD_CLSH_STATE_HPHL, hph_mode);
1774 wcd_clsh_set_hph_mode(wcd938x->clsh_info, CLS_H_HIFI);
1775 if (hph_mode == CLS_H_LP || hph_mode == CLS_H_LOHIFI ||
1776 hph_mode == CLS_H_ULP) {
1777 snd_soc_component_write_field(component,
1778 WCD938X_HPH_REFBUFF_LP_CTL,
1779 WCD938X_PREREF_FLIT_BYPASS_MASK, 1);
1780 }
1781 snd_soc_component_write_field(component, WCD938X_ANA_HPH,
1782 WCD938X_HPHL_REF_EN_MASK, 1);
1783 wcd_clsh_set_hph_mode(wcd938x->clsh_info, hph_mode);
1784 /* 100 usec delay as per HW requirement */
1785 usleep_range(100, 110);
1786 set_bit(HPH_PA_DELAY, &wcd938x->status_mask);
1787 snd_soc_component_write_field(component,
1788 WCD938X_DIGITAL_PDM_WD_CTL0,
1789 WCD938X_PDM_WD_EN_MASK, 0x3);
1790 break;
1791 case SND_SOC_DAPM_POST_PMU:
1792 /*
1793 * 7ms sleep is required if compander is enabled as per
1794 * HW requirement. If compander is disabled, then
1795 * 20ms delay is required.
1796 */
1797 if (test_bit(HPH_PA_DELAY, &wcd938x->status_mask)) {
1798 if (!wcd938x->comp1_enable)
1799 usleep_range(20000, 20100);
1800 else
1801 usleep_range(7000, 7100);
1802 if (hph_mode == CLS_H_LP || hph_mode == CLS_H_LOHIFI ||
1803 hph_mode == CLS_H_ULP)
1804 snd_soc_component_write_field(component,
1805 WCD938X_HPH_REFBUFF_LP_CTL,
1806 WCD938X_PREREF_FLIT_BYPASS_MASK, 0);
1807 clear_bit(HPH_PA_DELAY, &wcd938x->status_mask);
1808 }
1809
1810 snd_soc_component_write_field(component, WCD938X_HPH_NEW_INT_HPH_TIMER1,
1811 WCD938X_AUTOCHOP_TIMER_EN, 1);
1812 if (hph_mode == CLS_AB || hph_mode == CLS_AB_HIFI ||
1813 hph_mode == CLS_AB_LP || hph_mode == CLS_AB_LOHIFI)
1814 snd_soc_component_write_field(component, WCD938X_ANA_RX_SUPPLIES,
1815 WCD938X_REGULATOR_MODE_MASK,
1816 WCD938X_REGULATOR_MODE_CLASS_AB);
1817 enable_irq(wcd938x->hphl_pdm_wd_int);
1818 break;
1819 case SND_SOC_DAPM_PRE_PMD:
1820 disable_irq_nosync(wcd938x->hphl_pdm_wd_int);
1821 /*
1822 * 7ms sleep is required if compander is enabled as per
1823 * HW requirement. If compander is disabled, then
1824 * 20ms delay is required.
1825 */
1826 if (!wcd938x->comp1_enable)
1827 usleep_range(20000, 20100);
1828 else
1829 usleep_range(7000, 7100);
1830 snd_soc_component_write_field(component, WCD938X_ANA_HPH,
1831 WCD938X_HPHL_EN_MASK, 0);
1832 set_bit(HPH_PA_DELAY, &wcd938x->status_mask);
1833 break;
1834 case SND_SOC_DAPM_POST_PMD:
1835 /*
1836 * 7ms sleep is required if compander is enabled as per
1837 * HW requirement. If compander is disabled, then
1838 * 20ms delay is required.
1839 */
1840 if (test_bit(HPH_PA_DELAY, &wcd938x->status_mask)) {
1841 if (!wcd938x->comp1_enable)
1842 usleep_range(21000, 21100);
1843 else
1844 usleep_range(7000, 7100);
1845 clear_bit(HPH_PA_DELAY, &wcd938x->status_mask);
1846 }
1847 snd_soc_component_write_field(component, WCD938X_ANA_HPH,
1848 WCD938X_HPHL_REF_EN_MASK, 0);
1849 snd_soc_component_write_field(component, WCD938X_DIGITAL_PDM_WD_CTL0,
1850 WCD938X_PDM_WD_EN_MASK, 0);
1851 wcd_clsh_ctrl_set_state(wcd938x->clsh_info, WCD_CLSH_EVENT_POST_PA,
1852 WCD_CLSH_STATE_HPHL, hph_mode);
1853 if (wcd938x->ldoh)
1854 snd_soc_component_write_field(component, WCD938X_LDOH_MODE,
1855 WCD938X_LDOH_EN_MASK, 0);
1856 break;
1857 }
1858
1859 return 0;
1860}
1861
1862static int wcd938x_codec_enable_aux_pa(struct snd_soc_dapm_widget *w,
1863 struct snd_kcontrol *kcontrol, int event)
1864{
1865 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
1866 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
1867 int hph_mode = wcd938x->hph_mode;
Srinivas Kandagatla8da9db02021-06-09 10:09:41 +0100[diff] [blame]1868
1869 switch (event) {
1870 case SND_SOC_DAPM_PRE_PMU:
1871 snd_soc_component_write_field(component, WCD938X_DIGITAL_PDM_WD_CTL2,
1872 WCD938X_AUX_PDM_WD_EN_MASK, 1);
1873 break;
1874 case SND_SOC_DAPM_POST_PMU:
1875 /* 1 msec delay as per HW requirement */
1876 usleep_range(1000, 1010);
1877 if (hph_mode == CLS_AB || hph_mode == CLS_AB_HIFI ||
1878 hph_mode == CLS_AB_LP || hph_mode == CLS_AB_LOHIFI)
1879 snd_soc_component_write_field(component, WCD938X_ANA_RX_SUPPLIES,
1880 WCD938X_REGULATOR_MODE_MASK,
1881 WCD938X_REGULATOR_MODE_CLASS_AB);
1882 enable_irq(wcd938x->aux_pdm_wd_int);
1883 break;
1884 case SND_SOC_DAPM_PRE_PMD:
1885 disable_irq_nosync(wcd938x->aux_pdm_wd_int);
1886 break;
1887 case SND_SOC_DAPM_POST_PMD:
1888 /* 1 msec delay as per HW requirement */
1889 usleep_range(1000, 1010);
1890 snd_soc_component_write_field(component, WCD938X_DIGITAL_PDM_WD_CTL2,
1891 WCD938X_AUX_PDM_WD_EN_MASK, 0);
1892 wcd_clsh_ctrl_set_state(wcd938x->clsh_info,
1893 WCD_CLSH_EVENT_POST_PA,
1894 WCD_CLSH_STATE_AUX,
1895 hph_mode);
1896
1897 wcd938x->flyback_cur_det_disable--;
1898 if (wcd938x->flyback_cur_det_disable == 0)
1899 snd_soc_component_write_field(component, WCD938X_FLYBACK_EN,
1900 WCD938X_EN_CUR_DET_MASK, 1);
1901 break;
1902 }
kernel test robot4d0b79e2021-06-29 21:29:09 +0800[diff] [blame]1903 return 0;
Srinivas Kandagatla8da9db02021-06-09 10:09:41 +0100[diff] [blame]1904}
1905
1906static int wcd938x_codec_enable_ear_pa(struct snd_soc_dapm_widget *w,
1907 struct snd_kcontrol *kcontrol, int event)
1908{
1909 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
1910 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
1911 int hph_mode = wcd938x->hph_mode;
1912
1913 switch (event) {
1914 case SND_SOC_DAPM_PRE_PMU:
1915 /*
1916 * Enable watchdog interrupt for HPHL or AUX
1917 * depending on mux value
1918 */
1919 wcd938x->ear_rx_path = snd_soc_component_read(component,
1920 WCD938X_DIGITAL_CDC_EAR_PATH_CTL);
1921 if (wcd938x->ear_rx_path & EAR_RX_PATH_AUX)
1922 snd_soc_component_write_field(component, WCD938X_DIGITAL_PDM_WD_CTL2,
1923 WCD938X_AUX_PDM_WD_EN_MASK, 1);
1924 else
1925 snd_soc_component_write_field(component,
1926 WCD938X_DIGITAL_PDM_WD_CTL0,
1927 WCD938X_PDM_WD_EN_MASK, 0x3);
1928 if (!wcd938x->comp1_enable)
1929 snd_soc_component_write_field(component,
1930 WCD938X_ANA_EAR_COMPANDER_CTL,
1931 WCD938X_GAIN_OVRD_REG_MASK, 1);
1932
1933 break;
1934 case SND_SOC_DAPM_POST_PMU:
1935 /* 6 msec delay as per HW requirement */
1936 usleep_range(6000, 6010);
1937 if (hph_mode == CLS_AB || hph_mode == CLS_AB_HIFI ||
1938 hph_mode == CLS_AB_LP || hph_mode == CLS_AB_LOHIFI)
1939 snd_soc_component_write_field(component, WCD938X_ANA_RX_SUPPLIES,
1940 WCD938X_REGULATOR_MODE_MASK,
1941 WCD938X_REGULATOR_MODE_CLASS_AB);
1942 if (wcd938x->ear_rx_path & EAR_RX_PATH_AUX)
1943 enable_irq(wcd938x->aux_pdm_wd_int);
1944 else
1945 enable_irq(wcd938x->hphl_pdm_wd_int);
1946 break;
1947 case SND_SOC_DAPM_PRE_PMD:
1948 if (wcd938x->ear_rx_path & EAR_RX_PATH_AUX)
1949 disable_irq_nosync(wcd938x->aux_pdm_wd_int);
1950 else
1951 disable_irq_nosync(wcd938x->hphl_pdm_wd_int);
1952 break;
1953 case SND_SOC_DAPM_POST_PMD:
1954 if (!wcd938x->comp1_enable)
1955 snd_soc_component_write_field(component, WCD938X_ANA_EAR_COMPANDER_CTL,
1956 WCD938X_GAIN_OVRD_REG_MASK, 0);
1957 /* 7 msec delay as per HW requirement */
1958 usleep_range(7000, 7010);
1959 if (wcd938x->ear_rx_path & EAR_RX_PATH_AUX)
1960 snd_soc_component_write_field(component, WCD938X_DIGITAL_PDM_WD_CTL2,
1961 WCD938X_AUX_PDM_WD_EN_MASK, 0);
1962 else
1963 snd_soc_component_write_field(component, WCD938X_DIGITAL_PDM_WD_CTL0,
1964 WCD938X_PDM_WD_EN_MASK, 0);
1965
1966 wcd_clsh_ctrl_set_state(wcd938x->clsh_info, WCD_CLSH_EVENT_POST_PA,
1967 WCD_CLSH_STATE_EAR, hph_mode);
1968
1969 wcd938x->flyback_cur_det_disable--;
1970 if (wcd938x->flyback_cur_det_disable == 0)
1971 snd_soc_component_write_field(component, WCD938X_FLYBACK_EN,
1972 WCD938X_EN_CUR_DET_MASK, 1);
1973 break;
1974 }
1975
1976 return 0;
1977}
1978
Srinivas Kandagatlad5add082021-06-09 10:09:42 +0100[diff] [blame]1979static int wcd938x_codec_enable_dmic(struct snd_soc_dapm_widget *w,
1980 struct snd_kcontrol *kcontrol,
1981 int event)
1982{
1983 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
1984 u16 dmic_clk_reg, dmic_clk_en_reg;
1985 u8 dmic_sel_mask, dmic_clk_mask;
1986
1987 switch (w->shift) {
1988 case 0:
1989 case 1:
1990 dmic_clk_reg = WCD938X_DIGITAL_CDC_DMIC_RATE_1_2;
1991 dmic_clk_en_reg = WCD938X_DIGITAL_CDC_DMIC1_CTL;
1992 dmic_clk_mask = WCD938X_DMIC1_RATE_MASK;
1993 dmic_sel_mask = WCD938X_AMIC1_IN_SEL_MASK;
1994 break;
1995 case 2:
1996 case 3:
1997 dmic_clk_reg = WCD938X_DIGITAL_CDC_DMIC_RATE_1_2;
1998 dmic_clk_en_reg = WCD938X_DIGITAL_CDC_DMIC2_CTL;
1999 dmic_clk_mask = WCD938X_DMIC2_RATE_MASK;
2000 dmic_sel_mask = WCD938X_AMIC3_IN_SEL_MASK;
2001 break;
2002 case 4:
2003 case 5:
2004 dmic_clk_reg = WCD938X_DIGITAL_CDC_DMIC_RATE_3_4;
2005 dmic_clk_en_reg = WCD938X_DIGITAL_CDC_DMIC3_CTL;
2006 dmic_clk_mask = WCD938X_DMIC3_RATE_MASK;
2007 dmic_sel_mask = WCD938X_AMIC4_IN_SEL_MASK;
2008 break;
2009 case 6:
2010 case 7:
2011 dmic_clk_reg = WCD938X_DIGITAL_CDC_DMIC_RATE_3_4;
2012 dmic_clk_en_reg = WCD938X_DIGITAL_CDC_DMIC4_CTL;
2013 dmic_clk_mask = WCD938X_DMIC4_RATE_MASK;
2014 dmic_sel_mask = WCD938X_AMIC5_IN_SEL_MASK;
2015 break;
2016 default:
2017 dev_err(component->dev, "%s: Invalid DMIC Selection\n",
2018 __func__);
2019 return -EINVAL;
2020 }
2021
2022 switch (event) {
2023 case SND_SOC_DAPM_PRE_PMU:
2024 snd_soc_component_write_field(component,
2025 WCD938X_DIGITAL_CDC_AMIC_CTL,
2026 dmic_sel_mask,
2027 WCD938X_AMIC1_IN_SEL_DMIC);
2028 /* 250us sleep as per HW requirement */
2029 usleep_range(250, 260);
2030 /* Setting DMIC clock rate to 2.4MHz */
2031 snd_soc_component_write_field(component, dmic_clk_reg,
2032 dmic_clk_mask,
2033 WCD938X_DMIC4_RATE_2P4MHZ);
2034 snd_soc_component_write_field(component, dmic_clk_en_reg,
2035 WCD938X_DMIC_CLK_EN_MASK, 1);
2036 /* enable clock scaling */
2037 snd_soc_component_write_field(component, WCD938X_DIGITAL_CDC_DMIC_CTL,
2038 WCD938X_DMIC_CLK_SCALING_EN_MASK, 0x3);
2039 break;
2040 case SND_SOC_DAPM_POST_PMD:
2041 snd_soc_component_write_field(component,
2042 WCD938X_DIGITAL_CDC_AMIC_CTL,
2043 dmic_sel_mask, WCD938X_AMIC1_IN_SEL_AMIC);
2044 snd_soc_component_write_field(component, dmic_clk_en_reg,
2045 WCD938X_DMIC_CLK_EN_MASK, 0);
2046 break;
2047 }
2048 return 0;
2049}
2050
2051static int wcd938x_tx_swr_ctrl(struct snd_soc_dapm_widget *w,
2052 struct snd_kcontrol *kcontrol, int event)
2053{
2054 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
2055 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
2056 int bank;
2057 int rate;
2058
2059 bank = (wcd938x_swr_get_current_bank(wcd938x->sdw_priv[AIF1_CAP]->sdev)) ? 0 : 1;
2060 bank = bank ? 0 : 1;
2061
2062 switch (event) {
2063 case SND_SOC_DAPM_PRE_PMU:
2064 if (strnstr(w->name, "ADC", sizeof("ADC"))) {
2065 int i = 0, mode = 0;
2066
2067 if (test_bit(WCD_ADC1, &wcd938x->status_mask))
2068 mode |= tx_mode_bit[wcd938x->tx_mode[WCD_ADC1]];
2069 if (test_bit(WCD_ADC2, &wcd938x->status_mask))
2070 mode |= tx_mode_bit[wcd938x->tx_mode[WCD_ADC2]];
2071 if (test_bit(WCD_ADC3, &wcd938x->status_mask))
2072 mode |= tx_mode_bit[wcd938x->tx_mode[WCD_ADC3]];
2073 if (test_bit(WCD_ADC4, &wcd938x->status_mask))
2074 mode |= tx_mode_bit[wcd938x->tx_mode[WCD_ADC4]];
2075
2076 if (mode != 0) {
2077 for (i = 0; i < ADC_MODE_ULP2; i++) {
2078 if (mode & (1 << i)) {
2079 i++;
2080 break;
2081 }
2082 }
2083 }
2084 rate = wcd938x_get_clk_rate(i);
2085 wcd938x_set_swr_clk_rate(component, rate, bank);
Srinivas Kandagatlad5add082021-06-09 10:09:42 +0100[diff] [blame]2086 /* Copy clk settings to active bank */
2087 wcd938x_set_swr_clk_rate(component, rate, !bank);
Srinivas Kandagatlad245fff2021-06-21 14:45:02 +0100[diff] [blame]2088 }
Srinivas Kandagatlad5add082021-06-09 10:09:42 +0100[diff] [blame]2089 break;
2090 case SND_SOC_DAPM_POST_PMD:
2091 if (strnstr(w->name, "ADC", sizeof("ADC"))) {
2092 rate = wcd938x_get_clk_rate(ADC_MODE_INVALID);
2093 wcd938x_set_swr_clk_rate(component, rate, !bank);
2094 wcd938x_set_swr_clk_rate(component, rate, bank);
2095 }
2096 break;
2097 }
2098
2099 return 0;
2100}
2101
2102static int wcd938x_get_adc_mode(int val)
2103{
2104 int ret = 0;
2105
2106 switch (val) {
2107 case ADC_MODE_INVALID:
2108 ret = ADC_MODE_VAL_NORMAL;
2109 break;
2110 case ADC_MODE_HIFI:
2111 ret = ADC_MODE_VAL_HIFI;
2112 break;
2113 case ADC_MODE_LO_HIF:
2114 ret = ADC_MODE_VAL_LO_HIF;
2115 break;
2116 case ADC_MODE_NORMAL:
2117 ret = ADC_MODE_VAL_NORMAL;
2118 break;
2119 case ADC_MODE_LP:
2120 ret = ADC_MODE_VAL_LP;
2121 break;
2122 case ADC_MODE_ULP1:
2123 ret = ADC_MODE_VAL_ULP1;
2124 break;
2125 case ADC_MODE_ULP2:
2126 ret = ADC_MODE_VAL_ULP2;
2127 break;
2128 default:
2129 ret = -EINVAL;
2130 break;
2131 }
2132 return ret;
2133}
2134
2135static int wcd938x_codec_enable_adc(struct snd_soc_dapm_widget *w,
2136 struct snd_kcontrol *kcontrol, int event)
2137{
2138 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
2139 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
2140
2141 switch (event) {
2142 case SND_SOC_DAPM_PRE_PMU:
2143 snd_soc_component_write_field(component,
2144 WCD938X_DIGITAL_CDC_ANA_CLK_CTL,
2145 WCD938X_ANA_TX_CLK_EN_MASK, 1);
2146 snd_soc_component_write_field(component,
2147 WCD938X_DIGITAL_CDC_ANA_CLK_CTL,
2148 WCD938X_ANA_TX_DIV2_CLK_EN_MASK, 1);
2149 set_bit(w->shift, &wcd938x->status_mask);
2150 break;
2151 case SND_SOC_DAPM_POST_PMD:
2152 snd_soc_component_write_field(component, WCD938X_DIGITAL_CDC_ANA_CLK_CTL,
2153 WCD938X_ANA_TX_CLK_EN_MASK, 0);
2154 clear_bit(w->shift, &wcd938x->status_mask);
2155 break;
2156 }
2157
2158 return 0;
2159}
2160
2161static void wcd938x_tx_channel_config(struct snd_soc_component *component,
2162 int channel, int mode)
2163{
2164 int reg, mask;
2165
2166 switch (channel) {
2167 case 0:
2168 reg = WCD938X_ANA_TX_CH2;
2169 mask = WCD938X_HPF1_INIT_MASK;
2170 break;
2171 case 1:
2172 reg = WCD938X_ANA_TX_CH2;
2173 mask = WCD938X_HPF2_INIT_MASK;
2174 break;
2175 case 2:
2176 reg = WCD938X_ANA_TX_CH4;
2177 mask = WCD938X_HPF3_INIT_MASK;
2178 break;
2179 case 3:
2180 reg = WCD938X_ANA_TX_CH4;
2181 mask = WCD938X_HPF4_INIT_MASK;
2182 break;
Srinivas Kandagatlad245fff2021-06-21 14:45:02 +0100[diff] [blame]2183 default:
2184 return;
Srinivas Kandagatlad5add082021-06-09 10:09:42 +0100[diff] [blame]2185 }
2186
2187 snd_soc_component_write_field(component, reg, mask, mode);
2188}
2189
2190static int wcd938x_adc_enable_req(struct snd_soc_dapm_widget *w,
2191 struct snd_kcontrol *kcontrol, int event)
2192{
2193 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
2194 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
2195 int mode;
2196
2197 switch (event) {
2198 case SND_SOC_DAPM_PRE_PMU:
2199 snd_soc_component_write_field(component,
2200 WCD938X_DIGITAL_CDC_REQ_CTL,
2201 WCD938X_FS_RATE_4P8_MASK, 1);
2202 snd_soc_component_write_field(component,
2203 WCD938X_DIGITAL_CDC_REQ_CTL,
2204 WCD938X_NO_NOTCH_MASK, 0);
2205 wcd938x_tx_channel_config(component, w->shift, 1);
2206 mode = wcd938x_get_adc_mode(wcd938x->tx_mode[w->shift]);
2207 if (mode < 0) {
2208 dev_info(component->dev, "Invalid ADC mode\n");
2209 return -EINVAL;
2210 }
2211 switch (w->shift) {
2212 case 0:
2213 snd_soc_component_write_field(component,
2214 WCD938X_DIGITAL_CDC_TX_ANA_MODE_0_1,
2215 WCD938X_TXD0_MODE_MASK, mode);
2216 snd_soc_component_write_field(component,
2217 WCD938X_DIGITAL_CDC_DIG_CLK_CTL,
2218 WCD938X_TXD0_CLK_EN_MASK, 1);
2219 break;
2220 case 1:
2221 snd_soc_component_write_field(component,
2222 WCD938X_DIGITAL_CDC_TX_ANA_MODE_0_1,
2223 WCD938X_TXD1_MODE_MASK, mode);
2224 snd_soc_component_write_field(component,
2225 WCD938X_DIGITAL_CDC_DIG_CLK_CTL,
2226 WCD938X_TXD1_CLK_EN_MASK, 1);
2227 break;
2228 case 2:
2229 snd_soc_component_write_field(component,
2230 WCD938X_DIGITAL_CDC_TX_ANA_MODE_2_3,
2231 WCD938X_TXD2_MODE_MASK, mode);
2232 snd_soc_component_write_field(component,
2233 WCD938X_DIGITAL_CDC_DIG_CLK_CTL,
2234 WCD938X_TXD2_CLK_EN_MASK, 1);
2235 break;
2236 case 3:
2237 snd_soc_component_write_field(component,
2238 WCD938X_DIGITAL_CDC_TX_ANA_MODE_2_3,
2239 WCD938X_TXD3_MODE_MASK, mode);
2240 snd_soc_component_write_field(component,
2241 WCD938X_DIGITAL_CDC_DIG_CLK_CTL,
2242 WCD938X_TXD3_CLK_EN_MASK, 1);
2243 break;
2244 default:
2245 break;
2246 }
2247
2248 wcd938x_tx_channel_config(component, w->shift, 0);
2249 break;
2250 case SND_SOC_DAPM_POST_PMD:
2251 switch (w->shift) {
2252 case 0:
2253 snd_soc_component_write_field(component,
2254 WCD938X_DIGITAL_CDC_TX_ANA_MODE_0_1,
2255 WCD938X_TXD0_MODE_MASK, 0);
2256 snd_soc_component_write_field(component,
2257 WCD938X_DIGITAL_CDC_DIG_CLK_CTL,
2258 WCD938X_TXD0_CLK_EN_MASK, 0);
2259 break;
2260 case 1:
2261 snd_soc_component_write_field(component,
2262 WCD938X_DIGITAL_CDC_TX_ANA_MODE_0_1,
2263 WCD938X_TXD1_MODE_MASK, 0);
2264 snd_soc_component_write_field(component,
2265 WCD938X_DIGITAL_CDC_DIG_CLK_CTL,
2266 WCD938X_TXD1_CLK_EN_MASK, 0);
2267 break;
2268 case 2:
2269 snd_soc_component_write_field(component,
2270 WCD938X_DIGITAL_CDC_TX_ANA_MODE_2_3,
2271 WCD938X_TXD2_MODE_MASK, 0);
2272 snd_soc_component_write_field(component,
2273 WCD938X_DIGITAL_CDC_DIG_CLK_CTL,
2274 WCD938X_TXD2_CLK_EN_MASK, 0);
2275 break;
2276 case 3:
2277 snd_soc_component_write_field(component,
2278 WCD938X_DIGITAL_CDC_TX_ANA_MODE_2_3,
2279 WCD938X_TXD3_MODE_MASK, 0);
2280 snd_soc_component_write_field(component,
2281 WCD938X_DIGITAL_CDC_DIG_CLK_CTL,
2282 WCD938X_TXD3_CLK_EN_MASK, 0);
2283 break;
2284 default:
2285 break;
2286 }
2287 snd_soc_component_write_field(component,
2288 WCD938X_DIGITAL_CDC_ANA_CLK_CTL,
2289 WCD938X_ANA_TX_DIV2_CLK_EN_MASK, 0);
2290 break;
2291 }
2292
2293 return 0;
2294}
2295
2296static int wcd938x_micbias_control(struct snd_soc_component *component,
2297 int micb_num, int req, bool is_dapm)
2298{
2299 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
2300 int micb_index = micb_num - 1;
2301 u16 micb_reg;
2302
2303 switch (micb_num) {
2304 case MIC_BIAS_1:
2305 micb_reg = WCD938X_ANA_MICB1;
2306 break;
2307 case MIC_BIAS_2:
2308 micb_reg = WCD938X_ANA_MICB2;
2309 break;
2310 case MIC_BIAS_3:
2311 micb_reg = WCD938X_ANA_MICB3;
2312 break;
2313 case MIC_BIAS_4:
2314 micb_reg = WCD938X_ANA_MICB4;
2315 break;
2316 default:
2317 dev_err(component->dev, "%s: Invalid micbias number: %d\n",
2318 __func__, micb_num);
2319 return -EINVAL;
2320 }
2321
2322 switch (req) {
2323 case MICB_PULLUP_ENABLE:
2324 wcd938x->pullup_ref[micb_index]++;
2325 if ((wcd938x->pullup_ref[micb_index] == 1) &&
2326 (wcd938x->micb_ref[micb_index] == 0))
2327 snd_soc_component_write_field(component, micb_reg,
2328 WCD938X_MICB_EN_MASK,
2329 WCD938X_MICB_PULL_UP);
2330 break;
2331 case MICB_PULLUP_DISABLE:
2332 if (wcd938x->pullup_ref[micb_index] > 0)
2333 wcd938x->pullup_ref[micb_index]--;
2334
2335 if ((wcd938x->pullup_ref[micb_index] == 0) &&
2336 (wcd938x->micb_ref[micb_index] == 0))
2337 snd_soc_component_write_field(component, micb_reg,
2338 WCD938X_MICB_EN_MASK, 0);
2339 break;
2340 case MICB_ENABLE:
2341 wcd938x->micb_ref[micb_index]++;
2342 if (wcd938x->micb_ref[micb_index] == 1) {
2343 snd_soc_component_write_field(component,
2344 WCD938X_DIGITAL_CDC_DIG_CLK_CTL,
2345 WCD938X_TX_CLK_EN_MASK, 0xF);
2346 snd_soc_component_write_field(component,
2347 WCD938X_DIGITAL_CDC_ANA_CLK_CTL,
2348 WCD938X_ANA_TX_DIV2_CLK_EN_MASK, 1);
2349 snd_soc_component_write_field(component,
2350 WCD938X_DIGITAL_CDC_ANA_TX_CLK_CTL,
2351 WCD938X_TX_SC_CLK_EN_MASK, 1);
2352
2353 snd_soc_component_write_field(component, micb_reg,
2354 WCD938X_MICB_EN_MASK,
2355 WCD938X_MICB_ENABLE);
2356 }
2357
2358 break;
2359 case MICB_DISABLE:
2360 if (wcd938x->micb_ref[micb_index] > 0)
2361 wcd938x->micb_ref[micb_index]--;
2362
2363 if ((wcd938x->micb_ref[micb_index] == 0) &&
2364 (wcd938x->pullup_ref[micb_index] > 0))
2365 snd_soc_component_write_field(component, micb_reg,
2366 WCD938X_MICB_EN_MASK,
2367 WCD938X_MICB_PULL_UP);
2368 else if ((wcd938x->micb_ref[micb_index] == 0) &&
2369 (wcd938x->pullup_ref[micb_index] == 0)) {
2370
2371 snd_soc_component_write_field(component, micb_reg,
2372 WCD938X_MICB_EN_MASK, 0);
2373 }
2374 break;
2375 }
2376
2377 return 0;
2378}
2379
2380static int wcd938x_codec_enable_micbias(struct snd_soc_dapm_widget *w,
2381 struct snd_kcontrol *kcontrol,
2382 int event)
2383{
2384 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
2385 int micb_num = w->shift;
2386
2387 switch (event) {
2388 case SND_SOC_DAPM_PRE_PMU:
2389 wcd938x_micbias_control(component, micb_num, MICB_ENABLE, true);
2390 break;
2391 case SND_SOC_DAPM_POST_PMU:
2392 /* 1 msec delay as per HW requirement */
2393 usleep_range(1000, 1100);
2394 break;
2395 case SND_SOC_DAPM_POST_PMD:
2396 wcd938x_micbias_control(component, micb_num, MICB_DISABLE, true);
2397 break;
2398 }
2399
2400 return 0;
2401}
2402
2403static int wcd938x_codec_enable_micbias_pullup(struct snd_soc_dapm_widget *w,
2404 struct snd_kcontrol *kcontrol,
2405 int event)
2406{
2407 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
2408 int micb_num = w->shift;
2409
2410 switch (event) {
2411 case SND_SOC_DAPM_PRE_PMU:
2412 wcd938x_micbias_control(component, micb_num,
2413 MICB_PULLUP_ENABLE, true);
2414 break;
2415 case SND_SOC_DAPM_POST_PMU:
2416 /* 1 msec delay as per HW requirement */
2417 usleep_range(1000, 1100);
2418 break;
2419 case SND_SOC_DAPM_POST_PMD:
2420 wcd938x_micbias_control(component, micb_num,
2421 MICB_PULLUP_DISABLE, true);
2422 break;
2423 }
2424
2425 return 0;
2426}
2427
Srinivas Kandagatlae8ba1e02021-06-09 10:09:40 +0100[diff] [blame]2428static int wcd938x_tx_mode_get(struct snd_kcontrol *kcontrol,
2429 struct snd_ctl_elem_value *ucontrol)
2430{
2431 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
2432 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
2433 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
2434 int path = e->shift_l;
2435
2436 ucontrol->value.integer.value[0] = wcd938x->tx_mode[path];
2437
2438 return 0;
2439}
2440
2441static int wcd938x_tx_mode_put(struct snd_kcontrol *kcontrol,
2442 struct snd_ctl_elem_value *ucontrol)
2443{
2444 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
2445 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
2446 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
2447 int path = e->shift_l;
2448
2449 wcd938x->tx_mode[path] = ucontrol->value.enumerated.item[0];
2450
2451 return 1;
2452}
2453
2454static int wcd938x_rx_hph_mode_get(struct snd_kcontrol *kcontrol,
2455 struct snd_ctl_elem_value *ucontrol)
2456{
2457 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
2458 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
2459
2460 ucontrol->value.integer.value[0] = wcd938x->hph_mode;
2461
2462 return 0;
2463}
2464
2465static int wcd938x_rx_hph_mode_put(struct snd_kcontrol *kcontrol,
2466 struct snd_ctl_elem_value *ucontrol)
2467{
2468 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
2469 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
2470
2471 wcd938x->hph_mode = ucontrol->value.enumerated.item[0];
2472
2473 return 1;
2474}
2475
2476static int wcd938x_ear_pa_put_gain(struct snd_kcontrol *kcontrol,
2477 struct snd_ctl_elem_value *ucontrol)
2478{
2479 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
2480 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
2481
2482 if (wcd938x->comp1_enable) {
2483 dev_err(component->dev, "Can not set EAR PA Gain, compander1 is enabled\n");
2484 return -EINVAL;
2485 }
2486
2487 snd_soc_component_write_field(component, WCD938X_ANA_EAR_COMPANDER_CTL,
2488 WCD938X_EAR_GAIN_MASK,
2489 ucontrol->value.integer.value[0]);
2490
2491 return 0;
2492}
2493
2494static int wcd938x_get_compander(struct snd_kcontrol *kcontrol,
2495 struct snd_ctl_elem_value *ucontrol)
2496{
2497
2498 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
2499 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
2500 struct soc_mixer_control *mc;
2501 bool hphr;
2502
2503 mc = (struct soc_mixer_control *)(kcontrol->private_value);
2504 hphr = mc->shift;
2505
2506 if (hphr)
2507 ucontrol->value.integer.value[0] = wcd938x->comp2_enable;
2508 else
2509 ucontrol->value.integer.value[0] = wcd938x->comp1_enable;
2510
2511 return 0;
2512}
2513
2514static int wcd938x_set_compander(struct snd_kcontrol *kcontrol,
2515 struct snd_ctl_elem_value *ucontrol)
2516{
2517 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
2518 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
2519 struct wcd938x_sdw_priv *wcd;
2520 int value = ucontrol->value.integer.value[0];
2521 struct soc_mixer_control *mc;
2522 bool hphr;
2523
2524 mc = (struct soc_mixer_control *)(kcontrol->private_value);
2525 hphr = mc->shift;
2526
2527 wcd = wcd938x->sdw_priv[AIF1_PB];
2528
2529 if (hphr)
2530 wcd938x->comp2_enable = value;
2531 else
2532 wcd938x->comp1_enable = value;
2533
2534 if (value)
2535 wcd938x_connect_port(wcd, mc->reg, true);
2536 else
2537 wcd938x_connect_port(wcd, mc->reg, false);
2538
2539 return 0;
2540}
2541
2542static int wcd938x_ldoh_get(struct snd_kcontrol *kcontrol,
2543 struct snd_ctl_elem_value *ucontrol)
2544{
2545 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
2546 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
2547
2548 ucontrol->value.integer.value[0] = wcd938x->ldoh;
2549
2550 return 0;
2551}
2552
2553static int wcd938x_ldoh_put(struct snd_kcontrol *kcontrol,
2554 struct snd_ctl_elem_value *ucontrol)
2555{
2556 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
2557 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
2558
2559 wcd938x->ldoh = ucontrol->value.integer.value[0];
2560
2561 return 1;
2562}
2563
2564static int wcd938x_bcs_get(struct snd_kcontrol *kcontrol,
2565 struct snd_ctl_elem_value *ucontrol)
2566{
2567 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
2568 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
2569
2570 ucontrol->value.integer.value[0] = wcd938x->bcs_dis;
2571
2572 return 0;
2573}
2574
2575static int wcd938x_bcs_put(struct snd_kcontrol *kcontrol,
2576 struct snd_ctl_elem_value *ucontrol)
2577{
2578 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
2579 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
2580
2581 wcd938x->bcs_dis = ucontrol->value.integer.value[0];
2582
2583 return 1;
2584}
2585
2586static const char * const tx_mode_mux_text_wcd9380[] = {
2587 "ADC_INVALID", "ADC_HIFI", "ADC_LO_HIF", "ADC_NORMAL", "ADC_LP",
2588};
2589
2590static const char * const tx_mode_mux_text[] = {
2591 "ADC_INVALID", "ADC_HIFI", "ADC_LO_HIF", "ADC_NORMAL", "ADC_LP",
2592 "ADC_ULP1", "ADC_ULP2",
2593};
2594
2595static const char * const rx_hph_mode_mux_text_wcd9380[] = {
2596 "CLS_H_INVALID", "CLS_H_INVALID_1", "CLS_H_LP", "CLS_AB",
2597 "CLS_H_LOHIFI", "CLS_H_ULP", "CLS_H_INVALID_2", "CLS_AB_LP",
2598 "CLS_AB_LOHIFI",
2599};
2600
2601static const char * const rx_hph_mode_mux_text[] = {
2602 "CLS_H_INVALID", "CLS_H_HIFI", "CLS_H_LP", "CLS_AB", "CLS_H_LOHIFI",
2603 "CLS_H_ULP", "CLS_AB_HIFI", "CLS_AB_LP", "CLS_AB_LOHIFI",
2604};
2605
Srinivas Kandagatla8da9db02021-06-09 10:09:41 +0100[diff] [blame]2606static const char * const adc2_mux_text[] = {
2607 "INP2", "INP3"
2608};
2609
2610static const char * const adc3_mux_text[] = {
2611 "INP4", "INP6"
2612};
2613
2614static const char * const adc4_mux_text[] = {
2615 "INP5", "INP7"
2616};
2617
2618static const char * const rdac3_mux_text[] = {
2619 "RX1", "RX3"
2620};
2621
2622static const char * const hdr12_mux_text[] = {
2623 "NO_HDR12", "HDR12"
2624};
2625
2626static const char * const hdr34_mux_text[] = {
2627 "NO_HDR34", "HDR34"
2628};
2629
Srinivas Kandagatlae8ba1e02021-06-09 10:09:40 +0100[diff] [blame]2630static const struct soc_enum tx0_mode_enum_wcd9380 =
2631 SOC_ENUM_SINGLE(SND_SOC_NOPM, 0, ARRAY_SIZE(tx_mode_mux_text_wcd9380),
2632 tx_mode_mux_text_wcd9380);
2633
2634static const struct soc_enum tx1_mode_enum_wcd9380 =
2635 SOC_ENUM_SINGLE(SND_SOC_NOPM, 1, ARRAY_SIZE(tx_mode_mux_text_wcd9380),
2636 tx_mode_mux_text_wcd9380);
2637
2638static const struct soc_enum tx2_mode_enum_wcd9380 =
2639 SOC_ENUM_SINGLE(SND_SOC_NOPM, 2, ARRAY_SIZE(tx_mode_mux_text_wcd9380),
2640 tx_mode_mux_text_wcd9380);
2641
2642static const struct soc_enum tx3_mode_enum_wcd9380 =
2643 SOC_ENUM_SINGLE(SND_SOC_NOPM, 3, ARRAY_SIZE(tx_mode_mux_text_wcd9380),
2644 tx_mode_mux_text_wcd9380);
2645
2646static const struct soc_enum tx0_mode_enum_wcd9385 =
2647 SOC_ENUM_SINGLE(SND_SOC_NOPM, 0, ARRAY_SIZE(tx_mode_mux_text),
2648 tx_mode_mux_text);
2649
2650static const struct soc_enum tx1_mode_enum_wcd9385 =
2651 SOC_ENUM_SINGLE(SND_SOC_NOPM, 1, ARRAY_SIZE(tx_mode_mux_text),
2652 tx_mode_mux_text);
2653
2654static const struct soc_enum tx2_mode_enum_wcd9385 =
2655 SOC_ENUM_SINGLE(SND_SOC_NOPM, 2, ARRAY_SIZE(tx_mode_mux_text),
2656 tx_mode_mux_text);
2657
2658static const struct soc_enum tx3_mode_enum_wcd9385 =
2659 SOC_ENUM_SINGLE(SND_SOC_NOPM, 3, ARRAY_SIZE(tx_mode_mux_text),
2660 tx_mode_mux_text);
2661
2662static const struct soc_enum rx_hph_mode_mux_enum_wcd9380 =
2663 SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(rx_hph_mode_mux_text_wcd9380),
2664 rx_hph_mode_mux_text_wcd9380);
2665
2666static const struct soc_enum rx_hph_mode_mux_enum =
2667 SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(rx_hph_mode_mux_text),
2668 rx_hph_mode_mux_text);
2669
Srinivas Kandagatlad5add082021-06-09 10:09:42 +0100[diff] [blame]2670static const struct soc_enum adc2_enum =
2671 SOC_ENUM_SINGLE(WCD938X_TX_NEW_AMIC_MUX_CFG, 7,
2672 ARRAY_SIZE(adc2_mux_text), adc2_mux_text);
2673
2674static const struct soc_enum adc3_enum =
2675 SOC_ENUM_SINGLE(WCD938X_TX_NEW_AMIC_MUX_CFG, 6,
2676 ARRAY_SIZE(adc3_mux_text), adc3_mux_text);
2677
2678static const struct soc_enum adc4_enum =
2679 SOC_ENUM_SINGLE(WCD938X_TX_NEW_AMIC_MUX_CFG, 5,
2680 ARRAY_SIZE(adc4_mux_text), adc4_mux_text);
2681
2682static const struct soc_enum hdr12_enum =
2683 SOC_ENUM_SINGLE(WCD938X_TX_NEW_AMIC_MUX_CFG, 4,
2684 ARRAY_SIZE(hdr12_mux_text), hdr12_mux_text);
2685
2686static const struct soc_enum hdr34_enum =
2687 SOC_ENUM_SINGLE(WCD938X_TX_NEW_AMIC_MUX_CFG, 3,
2688 ARRAY_SIZE(hdr34_mux_text), hdr34_mux_text);
2689
Srinivas Kandagatla8da9db02021-06-09 10:09:41 +0100[diff] [blame]2690static const struct soc_enum rdac3_enum =
2691 SOC_ENUM_SINGLE(WCD938X_DIGITAL_CDC_EAR_PATH_CTL, 0,
2692 ARRAY_SIZE(rdac3_mux_text), rdac3_mux_text);
2693
Srinivas Kandagatlad5add082021-06-09 10:09:42 +0100[diff] [blame]2694static const struct snd_kcontrol_new adc1_switch[] = {
2695 SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
2696};
2697
2698static const struct snd_kcontrol_new adc2_switch[] = {
2699 SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
2700};
2701
2702static const struct snd_kcontrol_new adc3_switch[] = {
2703 SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
2704};
2705
2706static const struct snd_kcontrol_new adc4_switch[] = {
2707 SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
2708};
2709
2710static const struct snd_kcontrol_new dmic1_switch[] = {
2711 SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
2712};
2713
2714static const struct snd_kcontrol_new dmic2_switch[] = {
2715 SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
2716};
2717
2718static const struct snd_kcontrol_new dmic3_switch[] = {
2719 SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
2720};
2721
2722static const struct snd_kcontrol_new dmic4_switch[] = {
2723 SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
2724};
2725
2726static const struct snd_kcontrol_new dmic5_switch[] = {
2727 SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
2728};
2729
2730static const struct snd_kcontrol_new dmic6_switch[] = {
2731 SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
2732};
2733
2734static const struct snd_kcontrol_new dmic7_switch[] = {
2735 SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
2736};
2737
2738static const struct snd_kcontrol_new dmic8_switch[] = {
2739 SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
2740};
2741
Srinivas Kandagatla8da9db02021-06-09 10:09:41 +0100[diff] [blame]2742static const struct snd_kcontrol_new ear_rdac_switch[] = {
2743 SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
2744};
2745
2746static const struct snd_kcontrol_new aux_rdac_switch[] = {
2747 SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
2748};
2749
2750static const struct snd_kcontrol_new hphl_rdac_switch[] = {
2751 SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
2752};
2753
2754static const struct snd_kcontrol_new hphr_rdac_switch[] = {
2755 SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
2756};
2757
Srinivas Kandagatlad5add082021-06-09 10:09:42 +0100[diff] [blame]2758static const struct snd_kcontrol_new tx_adc2_mux =
2759 SOC_DAPM_ENUM("ADC2 MUX Mux", adc2_enum);
2760
2761static const struct snd_kcontrol_new tx_adc3_mux =
2762 SOC_DAPM_ENUM("ADC3 MUX Mux", adc3_enum);
2763
2764static const struct snd_kcontrol_new tx_adc4_mux =
2765 SOC_DAPM_ENUM("ADC4 MUX Mux", adc4_enum);
2766
2767static const struct snd_kcontrol_new tx_hdr12_mux =
2768 SOC_DAPM_ENUM("HDR12 MUX Mux", hdr12_enum);
2769
2770static const struct snd_kcontrol_new tx_hdr34_mux =
2771 SOC_DAPM_ENUM("HDR34 MUX Mux", hdr34_enum);
2772
Srinivas Kandagatla8da9db02021-06-09 10:09:41 +0100[diff] [blame]2773static const struct snd_kcontrol_new rx_rdac3_mux =
2774 SOC_DAPM_ENUM("RDAC3_MUX Mux", rdac3_enum);
2775
Srinivas Kandagatlae8ba1e02021-06-09 10:09:40 +0100[diff] [blame]2776static const struct snd_kcontrol_new wcd9380_snd_controls[] = {
2777 SOC_ENUM_EXT("RX HPH Mode", rx_hph_mode_mux_enum_wcd9380,
2778 wcd938x_rx_hph_mode_get, wcd938x_rx_hph_mode_put),
2779 SOC_ENUM_EXT("TX0 MODE", tx0_mode_enum_wcd9380,
2780 wcd938x_tx_mode_get, wcd938x_tx_mode_put),
2781 SOC_ENUM_EXT("TX1 MODE", tx1_mode_enum_wcd9380,
2782 wcd938x_tx_mode_get, wcd938x_tx_mode_put),
2783 SOC_ENUM_EXT("TX2 MODE", tx2_mode_enum_wcd9380,
2784 wcd938x_tx_mode_get, wcd938x_tx_mode_put),
2785 SOC_ENUM_EXT("TX3 MODE", tx3_mode_enum_wcd9380,
2786 wcd938x_tx_mode_get, wcd938x_tx_mode_put),
2787};
2788
2789static const struct snd_kcontrol_new wcd9385_snd_controls[] = {
2790 SOC_ENUM_EXT("RX HPH Mode", rx_hph_mode_mux_enum,
2791 wcd938x_rx_hph_mode_get, wcd938x_rx_hph_mode_put),
2792 SOC_ENUM_EXT("TX0 MODE", tx0_mode_enum_wcd9385,
2793 wcd938x_tx_mode_get, wcd938x_tx_mode_put),
2794 SOC_ENUM_EXT("TX1 MODE", tx1_mode_enum_wcd9385,
2795 wcd938x_tx_mode_get, wcd938x_tx_mode_put),
2796 SOC_ENUM_EXT("TX2 MODE", tx2_mode_enum_wcd9385,
2797 wcd938x_tx_mode_get, wcd938x_tx_mode_put),
2798 SOC_ENUM_EXT("TX3 MODE", tx3_mode_enum_wcd9385,
2799 wcd938x_tx_mode_get, wcd938x_tx_mode_put),
2800};
2801
2802static int wcd938x_get_swr_port(struct snd_kcontrol *kcontrol,
2803 struct snd_ctl_elem_value *ucontrol)
2804{
2805 struct snd_soc_component *comp = snd_soc_kcontrol_component(kcontrol);
2806 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(comp);
2807 struct wcd938x_sdw_priv *wcd;
2808 struct soc_mixer_control *mixer = (struct soc_mixer_control *)kcontrol->private_value;
2809 int dai_id = mixer->shift;
2810 int portidx = mixer->reg;
2811
2812 wcd = wcd938x->sdw_priv[dai_id];
2813
2814 ucontrol->value.integer.value[0] = wcd->port_enable[portidx];
2815
2816 return 0;
2817}
2818
2819static int wcd938x_set_swr_port(struct snd_kcontrol *kcontrol,
2820 struct snd_ctl_elem_value *ucontrol)
2821{
2822 struct snd_soc_component *comp = snd_soc_kcontrol_component(kcontrol);
2823 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(comp);
2824 struct wcd938x_sdw_priv *wcd;
2825 struct soc_mixer_control *mixer =
2826 (struct soc_mixer_control *)kcontrol->private_value;
2827 int portidx = mixer->reg;
2828 int dai_id = mixer->shift;
2829 bool enable;
2830
2831 wcd = wcd938x->sdw_priv[dai_id];
2832
2833 if (ucontrol->value.integer.value[0])
2834 enable = true;
2835 else
2836 enable = false;
2837
2838 wcd->port_enable[portidx] = enable;
2839
2840 wcd938x_connect_port(wcd, portidx, enable);
2841
2842 return 0;
2843
2844}
2845
2846static const struct snd_kcontrol_new wcd938x_snd_controls[] = {
2847 SOC_SINGLE_EXT("HPHL_COMP Switch", WCD938X_COMP_L, 0, 1, 0,
2848 wcd938x_get_compander, wcd938x_set_compander),
2849 SOC_SINGLE_EXT("HPHR_COMP Switch", WCD938X_COMP_R, 1, 1, 0,
2850 wcd938x_get_compander, wcd938x_set_compander),
2851 SOC_SINGLE_EXT("HPHL Switch", WCD938X_HPH_L, 0, 1, 0,
2852 wcd938x_get_swr_port, wcd938x_set_swr_port),
2853 SOC_SINGLE_EXT("HPHR Switch", WCD938X_HPH_R, 0, 1, 0,
2854 wcd938x_get_swr_port, wcd938x_set_swr_port),
2855 SOC_SINGLE_EXT("CLSH Switch", WCD938X_CLSH, 0, 1, 0,
2856 wcd938x_get_swr_port, wcd938x_set_swr_port),
2857 SOC_SINGLE_EXT("LO Switch", WCD938X_LO, 0, 1, 0,
2858 wcd938x_get_swr_port, wcd938x_set_swr_port),
2859 SOC_SINGLE_EXT("DSD_L Switch", WCD938X_DSD_L, 0, 1, 0,
2860 wcd938x_get_swr_port, wcd938x_set_swr_port),
2861 SOC_SINGLE_EXT("DSD_R Switch", WCD938X_DSD_R, 0, 1, 0,
2862 wcd938x_get_swr_port, wcd938x_set_swr_port),
2863 SOC_SINGLE_TLV("HPHL Volume", WCD938X_HPH_L_EN, 0, 0x18, 0, line_gain),
2864 SOC_SINGLE_TLV("HPHR Volume", WCD938X_HPH_R_EN, 0, 0x18, 0, line_gain),
2865 WCD938X_EAR_PA_GAIN_TLV("EAR_PA Volume", WCD938X_ANA_EAR_COMPANDER_CTL,
2866 2, 0x10, 0, ear_pa_gain),
2867 SOC_SINGLE_EXT("ADC1 Switch", WCD938X_ADC1, 1, 1, 0,
2868 wcd938x_get_swr_port, wcd938x_set_swr_port),
2869 SOC_SINGLE_EXT("ADC2 Switch", WCD938X_ADC2, 1, 1, 0,
2870 wcd938x_get_swr_port, wcd938x_set_swr_port),
2871 SOC_SINGLE_EXT("ADC3 Switch", WCD938X_ADC3, 1, 1, 0,
2872 wcd938x_get_swr_port, wcd938x_set_swr_port),
2873 SOC_SINGLE_EXT("ADC4 Switch", WCD938X_ADC4, 1, 1, 0,
2874 wcd938x_get_swr_port, wcd938x_set_swr_port),
2875 SOC_SINGLE_EXT("DMIC0 Switch", WCD938X_DMIC0, 1, 1, 0,
2876 wcd938x_get_swr_port, wcd938x_set_swr_port),
2877 SOC_SINGLE_EXT("DMIC1 Switch", WCD938X_DMIC1, 1, 1, 0,
2878 wcd938x_get_swr_port, wcd938x_set_swr_port),
2879 SOC_SINGLE_EXT("MBHC Switch", WCD938X_MBHC, 1, 1, 0,
2880 wcd938x_get_swr_port, wcd938x_set_swr_port),
2881 SOC_SINGLE_EXT("DMIC2 Switch", WCD938X_DMIC2, 1, 1, 0,
2882 wcd938x_get_swr_port, wcd938x_set_swr_port),
2883 SOC_SINGLE_EXT("DMIC3 Switch", WCD938X_DMIC3, 1, 1, 0,
2884 wcd938x_get_swr_port, wcd938x_set_swr_port),
2885 SOC_SINGLE_EXT("DMIC4 Switch", WCD938X_DMIC4, 1, 1, 0,
2886 wcd938x_get_swr_port, wcd938x_set_swr_port),
2887 SOC_SINGLE_EXT("DMIC5 Switch", WCD938X_DMIC5, 1, 1, 0,
2888 wcd938x_get_swr_port, wcd938x_set_swr_port),
2889 SOC_SINGLE_EXT("DMIC6 Switch", WCD938X_DMIC6, 1, 1, 0,
2890 wcd938x_get_swr_port, wcd938x_set_swr_port),
2891 SOC_SINGLE_EXT("DMIC7 Switch", WCD938X_DMIC7, 1, 1, 0,
2892 wcd938x_get_swr_port, wcd938x_set_swr_port),
2893 SOC_SINGLE_EXT("LDOH Enable Switch", SND_SOC_NOPM, 0, 1, 0,
2894 wcd938x_ldoh_get, wcd938x_ldoh_put),
2895 SOC_SINGLE_EXT("ADC2_BCS Disable Switch", SND_SOC_NOPM, 0, 1, 0,
2896 wcd938x_bcs_get, wcd938x_bcs_put),
2897
2898 SOC_SINGLE_TLV("ADC1 Volume", WCD938X_ANA_TX_CH1, 0, 20, 0, analog_gain),
2899 SOC_SINGLE_TLV("ADC2 Volume", WCD938X_ANA_TX_CH2, 0, 20, 0, analog_gain),
2900 SOC_SINGLE_TLV("ADC3 Volume", WCD938X_ANA_TX_CH3, 0, 20, 0, analog_gain),
2901 SOC_SINGLE_TLV("ADC4 Volume", WCD938X_ANA_TX_CH4, 0, 20, 0, analog_gain),
2902};
2903
Srinivas Kandagatla8da9db02021-06-09 10:09:41 +0100[diff] [blame]2904static const struct snd_soc_dapm_widget wcd938x_dapm_widgets[] = {
Srinivas Kandagatlad5add082021-06-09 10:09:42 +0100[diff] [blame]2905
2906 /*input widgets*/
2907 SND_SOC_DAPM_INPUT("AMIC1"),
2908 SND_SOC_DAPM_INPUT("AMIC2"),
2909 SND_SOC_DAPM_INPUT("AMIC3"),
2910 SND_SOC_DAPM_INPUT("AMIC4"),
2911 SND_SOC_DAPM_INPUT("AMIC5"),
2912 SND_SOC_DAPM_INPUT("AMIC6"),
2913 SND_SOC_DAPM_INPUT("AMIC7"),
2914 SND_SOC_DAPM_MIC("Analog Mic1", NULL),
2915 SND_SOC_DAPM_MIC("Analog Mic2", NULL),
2916 SND_SOC_DAPM_MIC("Analog Mic3", NULL),
2917 SND_SOC_DAPM_MIC("Analog Mic4", NULL),
2918 SND_SOC_DAPM_MIC("Analog Mic5", NULL),
2919
2920 /*tx widgets*/
2921 SND_SOC_DAPM_ADC_E("ADC1", NULL, SND_SOC_NOPM, 0, 0,
2922 wcd938x_codec_enable_adc,
2923 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
2924 SND_SOC_DAPM_ADC_E("ADC2", NULL, SND_SOC_NOPM, 1, 0,
2925 wcd938x_codec_enable_adc,
2926 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
2927 SND_SOC_DAPM_ADC_E("ADC3", NULL, SND_SOC_NOPM, 2, 0,
2928 wcd938x_codec_enable_adc,
2929 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
2930 SND_SOC_DAPM_ADC_E("ADC4", NULL, SND_SOC_NOPM, 3, 0,
2931 wcd938x_codec_enable_adc,
2932 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
2933 SND_SOC_DAPM_ADC_E("DMIC1", NULL, SND_SOC_NOPM, 0, 0,
2934 wcd938x_codec_enable_dmic,
2935 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
2936 SND_SOC_DAPM_ADC_E("DMIC2", NULL, SND_SOC_NOPM, 1, 0,
2937 wcd938x_codec_enable_dmic,
2938 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
2939 SND_SOC_DAPM_ADC_E("DMIC3", NULL, SND_SOC_NOPM, 2, 0,
2940 wcd938x_codec_enable_dmic,
2941 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
2942 SND_SOC_DAPM_ADC_E("DMIC4", NULL, SND_SOC_NOPM, 3, 0,
2943 wcd938x_codec_enable_dmic,
2944 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
2945 SND_SOC_DAPM_ADC_E("DMIC5", NULL, SND_SOC_NOPM, 4, 0,
2946 wcd938x_codec_enable_dmic,
2947 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
2948 SND_SOC_DAPM_ADC_E("DMIC6", NULL, SND_SOC_NOPM, 5, 0,
2949 wcd938x_codec_enable_dmic,
2950 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
2951 SND_SOC_DAPM_ADC_E("DMIC7", NULL, SND_SOC_NOPM, 6, 0,
2952 wcd938x_codec_enable_dmic,
2953 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
2954 SND_SOC_DAPM_ADC_E("DMIC8", NULL, SND_SOC_NOPM, 7, 0,
2955 wcd938x_codec_enable_dmic,
2956 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
2957
2958 SND_SOC_DAPM_MIXER_E("ADC1 REQ", SND_SOC_NOPM, 0, 0,
2959 NULL, 0, wcd938x_adc_enable_req,
2960 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
2961 SND_SOC_DAPM_MIXER_E("ADC2 REQ", SND_SOC_NOPM, 1, 0,
2962 NULL, 0, wcd938x_adc_enable_req,
2963 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
2964 SND_SOC_DAPM_MIXER_E("ADC3 REQ", SND_SOC_NOPM, 2, 0,
2965 NULL, 0, wcd938x_adc_enable_req,
2966 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
2967 SND_SOC_DAPM_MIXER_E("ADC4 REQ", SND_SOC_NOPM, 3, 0, NULL, 0,
2968 wcd938x_adc_enable_req,
2969 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
2970
2971 SND_SOC_DAPM_MUX("ADC2 MUX", SND_SOC_NOPM, 0, 0, &tx_adc2_mux),
2972 SND_SOC_DAPM_MUX("ADC3 MUX", SND_SOC_NOPM, 0, 0, &tx_adc3_mux),
2973 SND_SOC_DAPM_MUX("ADC4 MUX", SND_SOC_NOPM, 0, 0, &tx_adc4_mux),
2974 SND_SOC_DAPM_MUX("HDR12 MUX", SND_SOC_NOPM, 0, 0, &tx_hdr12_mux),
2975 SND_SOC_DAPM_MUX("HDR34 MUX", SND_SOC_NOPM, 0, 0, &tx_hdr34_mux),
2976
2977 /*tx mixers*/
2978 SND_SOC_DAPM_MIXER_E("ADC1_MIXER", SND_SOC_NOPM, 0, 0, adc1_switch,
2979 ARRAY_SIZE(adc1_switch), wcd938x_tx_swr_ctrl,
2980 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
2981 SND_SOC_DAPM_MIXER_E("ADC2_MIXER", SND_SOC_NOPM, 0, 0, adc2_switch,
2982 ARRAY_SIZE(adc2_switch), wcd938x_tx_swr_ctrl,
2983 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
2984 SND_SOC_DAPM_MIXER_E("ADC3_MIXER", SND_SOC_NOPM, 0, 0, adc3_switch,
2985 ARRAY_SIZE(adc3_switch), wcd938x_tx_swr_ctrl,
2986 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
2987 SND_SOC_DAPM_MIXER_E("ADC4_MIXER", SND_SOC_NOPM, 0, 0, adc4_switch,
2988 ARRAY_SIZE(adc4_switch), wcd938x_tx_swr_ctrl,
2989 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
2990 SND_SOC_DAPM_MIXER_E("DMIC1_MIXER", SND_SOC_NOPM, 0, 0, dmic1_switch,
2991 ARRAY_SIZE(dmic1_switch), wcd938x_tx_swr_ctrl,
2992 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
2993 SND_SOC_DAPM_MIXER_E("DMIC2_MIXER", SND_SOC_NOPM, 0, 0, dmic2_switch,
2994 ARRAY_SIZE(dmic2_switch), wcd938x_tx_swr_ctrl,
2995 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
2996 SND_SOC_DAPM_MIXER_E("DMIC3_MIXER", SND_SOC_NOPM, 0, 0, dmic3_switch,
2997 ARRAY_SIZE(dmic3_switch), wcd938x_tx_swr_ctrl,
2998 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
2999 SND_SOC_DAPM_MIXER_E("DMIC4_MIXER", SND_SOC_NOPM, 0, 0, dmic4_switch,
3000 ARRAY_SIZE(dmic4_switch), wcd938x_tx_swr_ctrl,
3001 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
3002 SND_SOC_DAPM_MIXER_E("DMIC5_MIXER", SND_SOC_NOPM, 0, 0, dmic5_switch,
3003 ARRAY_SIZE(dmic5_switch), wcd938x_tx_swr_ctrl,
3004 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
3005 SND_SOC_DAPM_MIXER_E("DMIC6_MIXER", SND_SOC_NOPM, 0, 0, dmic6_switch,
3006 ARRAY_SIZE(dmic6_switch), wcd938x_tx_swr_ctrl,
3007 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
3008 SND_SOC_DAPM_MIXER_E("DMIC7_MIXER", SND_SOC_NOPM, 0, 0, dmic7_switch,
3009 ARRAY_SIZE(dmic7_switch), wcd938x_tx_swr_ctrl,
3010 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
3011 SND_SOC_DAPM_MIXER_E("DMIC8_MIXER", SND_SOC_NOPM, 0, 0, dmic8_switch,
3012 ARRAY_SIZE(dmic8_switch), wcd938x_tx_swr_ctrl,
3013 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
3014 /* micbias widgets*/
3015 SND_SOC_DAPM_SUPPLY("MIC BIAS1", SND_SOC_NOPM, MIC_BIAS_1, 0,
3016 wcd938x_codec_enable_micbias,
3017 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
3018 SND_SOC_DAPM_POST_PMD),
3019 SND_SOC_DAPM_SUPPLY("MIC BIAS2", SND_SOC_NOPM, MIC_BIAS_2, 0,
3020 wcd938x_codec_enable_micbias,
3021 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
3022 SND_SOC_DAPM_POST_PMD),
3023 SND_SOC_DAPM_SUPPLY("MIC BIAS3", SND_SOC_NOPM, MIC_BIAS_3, 0,
3024 wcd938x_codec_enable_micbias,
3025 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
3026 SND_SOC_DAPM_POST_PMD),
3027 SND_SOC_DAPM_SUPPLY("MIC BIAS4", SND_SOC_NOPM, MIC_BIAS_4, 0,
3028 wcd938x_codec_enable_micbias,
3029 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
3030 SND_SOC_DAPM_POST_PMD),
3031
3032 /* micbias pull up widgets*/
3033 SND_SOC_DAPM_SUPPLY("VA MIC BIAS1", SND_SOC_NOPM, MIC_BIAS_1, 0,
3034 wcd938x_codec_enable_micbias_pullup,
3035 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
3036 SND_SOC_DAPM_POST_PMD),
3037 SND_SOC_DAPM_SUPPLY("VA MIC BIAS2", SND_SOC_NOPM, MIC_BIAS_2, 0,
3038 wcd938x_codec_enable_micbias_pullup,
3039 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
3040 SND_SOC_DAPM_POST_PMD),
3041 SND_SOC_DAPM_SUPPLY("VA MIC BIAS3", SND_SOC_NOPM, MIC_BIAS_3, 0,
3042 wcd938x_codec_enable_micbias_pullup,
3043 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
3044 SND_SOC_DAPM_POST_PMD),
3045 SND_SOC_DAPM_SUPPLY("VA MIC BIAS4", SND_SOC_NOPM, MIC_BIAS_4, 0,
3046 wcd938x_codec_enable_micbias_pullup,
3047 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
3048 SND_SOC_DAPM_POST_PMD),
3049
3050 /*output widgets tx*/
3051 SND_SOC_DAPM_OUTPUT("ADC1_OUTPUT"),
3052 SND_SOC_DAPM_OUTPUT("ADC2_OUTPUT"),
3053 SND_SOC_DAPM_OUTPUT("ADC3_OUTPUT"),
3054 SND_SOC_DAPM_OUTPUT("ADC4_OUTPUT"),
3055 SND_SOC_DAPM_OUTPUT("DMIC1_OUTPUT"),
3056 SND_SOC_DAPM_OUTPUT("DMIC2_OUTPUT"),
3057 SND_SOC_DAPM_OUTPUT("DMIC3_OUTPUT"),
3058 SND_SOC_DAPM_OUTPUT("DMIC4_OUTPUT"),
3059 SND_SOC_DAPM_OUTPUT("DMIC5_OUTPUT"),
3060 SND_SOC_DAPM_OUTPUT("DMIC6_OUTPUT"),
3061 SND_SOC_DAPM_OUTPUT("DMIC7_OUTPUT"),
3062 SND_SOC_DAPM_OUTPUT("DMIC8_OUTPUT"),
3063
Srinivas Kandagatla8da9db02021-06-09 10:09:41 +0100[diff] [blame]3064 SND_SOC_DAPM_INPUT("IN1_HPHL"),
3065 SND_SOC_DAPM_INPUT("IN2_HPHR"),
3066 SND_SOC_DAPM_INPUT("IN3_AUX"),
3067
3068 /*rx widgets*/
3069 SND_SOC_DAPM_PGA_E("EAR PGA", WCD938X_ANA_EAR, 7, 0, NULL, 0,
3070 wcd938x_codec_enable_ear_pa,
3071 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
3072 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
3073 SND_SOC_DAPM_PGA_E("AUX PGA", WCD938X_AUX_AUXPA, 7, 0, NULL, 0,
3074 wcd938x_codec_enable_aux_pa,
3075 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
3076 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
3077 SND_SOC_DAPM_PGA_E("HPHL PGA", WCD938X_ANA_HPH, 7, 0, NULL, 0,
3078 wcd938x_codec_enable_hphl_pa,
3079 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
3080 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
3081 SND_SOC_DAPM_PGA_E("HPHR PGA", WCD938X_ANA_HPH, 6, 0, NULL, 0,
3082 wcd938x_codec_enable_hphr_pa,
3083 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
3084 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
3085
3086 SND_SOC_DAPM_DAC_E("RDAC1", NULL, SND_SOC_NOPM, 0, 0,
3087 wcd938x_codec_hphl_dac_event,
3088 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
3089 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
3090 SND_SOC_DAPM_DAC_E("RDAC2", NULL, SND_SOC_NOPM, 0, 0,
3091 wcd938x_codec_hphr_dac_event,
3092 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
3093 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
3094 SND_SOC_DAPM_DAC_E("RDAC3", NULL, SND_SOC_NOPM, 0, 0,
3095 wcd938x_codec_ear_dac_event,
3096 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
3097 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
3098 SND_SOC_DAPM_DAC_E("RDAC4", NULL, SND_SOC_NOPM, 0, 0,
3099 wcd938x_codec_aux_dac_event,
3100 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
3101 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
3102
3103 SND_SOC_DAPM_MUX("RDAC3_MUX", SND_SOC_NOPM, 0, 0, &rx_rdac3_mux),
3104
3105 SND_SOC_DAPM_SUPPLY("VDD_BUCK", SND_SOC_NOPM, 0, 0, NULL, 0),
3106 SND_SOC_DAPM_SUPPLY("RXCLK", SND_SOC_NOPM, 0, 0,
3107 wcd938x_codec_enable_rxclk,
3108 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
3109 SND_SOC_DAPM_POST_PMD),
3110
3111 SND_SOC_DAPM_SUPPLY_S("CLS_H_PORT", 1, SND_SOC_NOPM, 0, 0, NULL, 0),
3112
3113 SND_SOC_DAPM_MIXER_E("RX1", SND_SOC_NOPM, 0, 0, NULL, 0, NULL, 0),
3114 SND_SOC_DAPM_MIXER_E("RX2", SND_SOC_NOPM, 0, 0, NULL, 0, NULL, 0),
3115 SND_SOC_DAPM_MIXER_E("RX3", SND_SOC_NOPM, 0, 0, NULL, 0, NULL, 0),
3116
3117 /* rx mixer widgets*/
3118 SND_SOC_DAPM_MIXER("EAR_RDAC", SND_SOC_NOPM, 0, 0,
3119 ear_rdac_switch, ARRAY_SIZE(ear_rdac_switch)),
3120 SND_SOC_DAPM_MIXER("AUX_RDAC", SND_SOC_NOPM, 0, 0,
3121 aux_rdac_switch, ARRAY_SIZE(aux_rdac_switch)),
3122 SND_SOC_DAPM_MIXER("HPHL_RDAC", SND_SOC_NOPM, 0, 0,
3123 hphl_rdac_switch, ARRAY_SIZE(hphl_rdac_switch)),
3124 SND_SOC_DAPM_MIXER("HPHR_RDAC", SND_SOC_NOPM, 0, 0,
3125 hphr_rdac_switch, ARRAY_SIZE(hphr_rdac_switch)),
3126
3127 /*output widgets rx*/
3128 SND_SOC_DAPM_OUTPUT("EAR"),
3129 SND_SOC_DAPM_OUTPUT("AUX"),
3130 SND_SOC_DAPM_OUTPUT("HPHL"),
3131 SND_SOC_DAPM_OUTPUT("HPHR"),
Srinivas Kandagatla04544222021-06-09 10:09:43 +0100[diff] [blame]3132
3133};
3134
3135static const struct snd_soc_dapm_route wcd938x_audio_map[] = {
3136 {"ADC1_OUTPUT", NULL, "ADC1_MIXER"},
3137 {"ADC1_MIXER", "Switch", "ADC1 REQ"},
3138 {"ADC1 REQ", NULL, "ADC1"},
3139 {"ADC1", NULL, "AMIC1"},
3140
3141 {"ADC2_OUTPUT", NULL, "ADC2_MIXER"},
3142 {"ADC2_MIXER", "Switch", "ADC2 REQ"},
3143 {"ADC2 REQ", NULL, "ADC2"},
3144 {"ADC2", NULL, "HDR12 MUX"},
3145 {"HDR12 MUX", "NO_HDR12", "ADC2 MUX"},
3146 {"HDR12 MUX", "HDR12", "AMIC1"},
3147 {"ADC2 MUX", "INP3", "AMIC3"},
3148 {"ADC2 MUX", "INP2", "AMIC2"},
3149
3150 {"ADC3_OUTPUT", NULL, "ADC3_MIXER"},
3151 {"ADC3_MIXER", "Switch", "ADC3 REQ"},
3152 {"ADC3 REQ", NULL, "ADC3"},
3153 {"ADC3", NULL, "HDR34 MUX"},
3154 {"HDR34 MUX", "NO_HDR34", "ADC3 MUX"},
3155 {"HDR34 MUX", "HDR34", "AMIC5"},
3156 {"ADC3 MUX", "INP4", "AMIC4"},
3157 {"ADC3 MUX", "INP6", "AMIC6"},
3158
3159 {"ADC4_OUTPUT", NULL, "ADC4_MIXER"},
3160 {"ADC4_MIXER", "Switch", "ADC4 REQ"},
3161 {"ADC4 REQ", NULL, "ADC4"},
3162 {"ADC4", NULL, "ADC4 MUX"},
3163 {"ADC4 MUX", "INP5", "AMIC5"},
3164 {"ADC4 MUX", "INP7", "AMIC7"},
3165
3166 {"DMIC1_OUTPUT", NULL, "DMIC1_MIXER"},
3167 {"DMIC1_MIXER", "Switch", "DMIC1"},
3168
3169 {"DMIC2_OUTPUT", NULL, "DMIC2_MIXER"},
3170 {"DMIC2_MIXER", "Switch", "DMIC2"},
3171
3172 {"DMIC3_OUTPUT", NULL, "DMIC3_MIXER"},
3173 {"DMIC3_MIXER", "Switch", "DMIC3"},
3174
3175 {"DMIC4_OUTPUT", NULL, "DMIC4_MIXER"},
3176 {"DMIC4_MIXER", "Switch", "DMIC4"},
3177
3178 {"DMIC5_OUTPUT", NULL, "DMIC5_MIXER"},
3179 {"DMIC5_MIXER", "Switch", "DMIC5"},
3180
3181 {"DMIC6_OUTPUT", NULL, "DMIC6_MIXER"},
3182 {"DMIC6_MIXER", "Switch", "DMIC6"},
3183
3184 {"DMIC7_OUTPUT", NULL, "DMIC7_MIXER"},
3185 {"DMIC7_MIXER", "Switch", "DMIC7"},
3186
3187 {"DMIC8_OUTPUT", NULL, "DMIC8_MIXER"},
3188 {"DMIC8_MIXER", "Switch", "DMIC8"},
3189
3190 {"IN1_HPHL", NULL, "VDD_BUCK"},
3191 {"IN1_HPHL", NULL, "CLS_H_PORT"},
3192
3193 {"RX1", NULL, "IN1_HPHL"},
3194 {"RX1", NULL, "RXCLK"},
3195 {"RDAC1", NULL, "RX1"},
3196 {"HPHL_RDAC", "Switch", "RDAC1"},
3197 {"HPHL PGA", NULL, "HPHL_RDAC"},
3198 {"HPHL", NULL, "HPHL PGA"},
3199
3200 {"IN2_HPHR", NULL, "VDD_BUCK"},
3201 {"IN2_HPHR", NULL, "CLS_H_PORT"},
3202 {"RX2", NULL, "IN2_HPHR"},
3203 {"RDAC2", NULL, "RX2"},
3204 {"RX2", NULL, "RXCLK"},
3205 {"HPHR_RDAC", "Switch", "RDAC2"},
3206 {"HPHR PGA", NULL, "HPHR_RDAC"},
3207 {"HPHR", NULL, "HPHR PGA"},
3208
3209 {"IN3_AUX", NULL, "VDD_BUCK"},
3210 {"IN3_AUX", NULL, "CLS_H_PORT"},
3211 {"RX3", NULL, "IN3_AUX"},
3212 {"RDAC4", NULL, "RX3"},
3213 {"RX3", NULL, "RXCLK"},
3214 {"AUX_RDAC", "Switch", "RDAC4"},
3215 {"AUX PGA", NULL, "AUX_RDAC"},
3216 {"AUX", NULL, "AUX PGA"},
3217
3218 {"RDAC3_MUX", "RX3", "RX3"},
3219 {"RDAC3_MUX", "RX1", "RX1"},
3220 {"RDAC3", NULL, "RDAC3_MUX"},
3221 {"EAR_RDAC", "Switch", "RDAC3"},
3222 {"EAR PGA", NULL, "EAR_RDAC"},
3223 {"EAR", NULL, "EAR PGA"},
Srinivas Kandagatla8da9db02021-06-09 10:09:41 +0100[diff] [blame]3224};
3225
Srinivas Kandagatla8d786022021-06-09 10:09:37 +0100[diff] [blame]3226static int wcd938x_get_micb_vout_ctl_val(u32 micb_mv)
3227{
3228 /* min micbias voltage is 1V and maximum is 2.85V */
3229 if (micb_mv < 1000 || micb_mv > 2850)
3230 return -EINVAL;
3231
3232 return (micb_mv - 1000) / 50;
3233}
3234
3235static int wcd938x_set_micbias_data(struct wcd938x_priv *wcd938x)
3236{
3237 int vout_ctl_1, vout_ctl_2, vout_ctl_3, vout_ctl_4;
3238
3239 /* set micbias voltage */
3240 vout_ctl_1 = wcd938x_get_micb_vout_ctl_val(wcd938x->micb1_mv);
3241 vout_ctl_2 = wcd938x_get_micb_vout_ctl_val(wcd938x->micb2_mv);
3242 vout_ctl_3 = wcd938x_get_micb_vout_ctl_val(wcd938x->micb3_mv);
3243 vout_ctl_4 = wcd938x_get_micb_vout_ctl_val(wcd938x->micb4_mv);
3244 if (vout_ctl_1 < 0 || vout_ctl_2 < 0 || vout_ctl_3 < 0 || vout_ctl_4 < 0)
3245 return -EINVAL;
3246
3247 regmap_update_bits(wcd938x->regmap, WCD938X_ANA_MICB1,
3248 WCD938X_MICB_VOUT_MASK, vout_ctl_1);
3249 regmap_update_bits(wcd938x->regmap, WCD938X_ANA_MICB2,
3250 WCD938X_MICB_VOUT_MASK, vout_ctl_2);
3251 regmap_update_bits(wcd938x->regmap, WCD938X_ANA_MICB3,
3252 WCD938X_MICB_VOUT_MASK, vout_ctl_3);
3253 regmap_update_bits(wcd938x->regmap, WCD938X_ANA_MICB4,
3254 WCD938X_MICB_VOUT_MASK, vout_ctl_4);
3255
3256 return 0;
3257}
3258
3259static irqreturn_t wcd938x_wd_handle_irq(int irq, void *data)
3260{
3261 return IRQ_HANDLED;
3262}
3263
3264static struct irq_chip wcd_irq_chip = {
3265 .name = "WCD938x",
3266};
3267
3268static int wcd_irq_chip_map(struct irq_domain *irqd, unsigned int virq,
3269 irq_hw_number_t hw)
3270{
3271 irq_set_chip_and_handler(virq, &wcd_irq_chip, handle_simple_irq);
3272 irq_set_nested_thread(virq, 1);
3273 irq_set_noprobe(virq);
3274
3275 return 0;
3276}
3277
3278static const struct irq_domain_ops wcd_domain_ops = {
3279 .map = wcd_irq_chip_map,
3280};
3281
3282static int wcd938x_irq_init(struct wcd938x_priv *wcd, struct device *dev)
3283{
3284
3285 wcd->virq = irq_domain_add_linear(NULL, 1, &wcd_domain_ops, NULL);
3286 if (!(wcd->virq)) {
3287 dev_err(dev, "%s: Failed to add IRQ domain\n", __func__);
3288 return -EINVAL;
3289 }
3290
3291 return devm_regmap_add_irq_chip(dev, wcd->regmap,
3292 irq_create_mapping(wcd->virq, 0),
3293 IRQF_ONESHOT, 0, &wcd938x_regmap_irq_chip,
3294 &wcd->irq_chip);
3295}
3296
3297static int wcd938x_soc_codec_probe(struct snd_soc_component *component)
3298{
3299 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
3300 struct device *dev = component->dev;
3301 int ret, i;
3302
3303 snd_soc_component_init_regmap(component, wcd938x->regmap);
3304
3305 wcd938x->variant = snd_soc_component_read_field(component,
3306 WCD938X_DIGITAL_EFUSE_REG_0,
3307 WCD938X_ID_MASK);
3308
3309 wcd938x->clsh_info = wcd_clsh_ctrl_alloc(component, WCD938X);
3310
3311 wcd938x_io_init(wcd938x);
3312 /* Set all interrupts as edge triggered */
3313 for (i = 0; i < wcd938x_regmap_irq_chip.num_regs; i++) {
3314 regmap_write(wcd938x->regmap,
3315 (WCD938X_DIGITAL_INTR_LEVEL_0 + i), 0);
3316 }
3317
3318 ret = wcd938x_irq_init(wcd938x, component->dev);
3319 if (ret) {
3320 dev_err(component->dev, "%s: IRQ init failed: %d\n",
3321 __func__, ret);
3322 return ret;
3323 }
3324
3325 wcd938x->hphr_pdm_wd_int = regmap_irq_get_virq(wcd938x->irq_chip,
3326 WCD938X_IRQ_HPHR_PDM_WD_INT);
3327 wcd938x->hphl_pdm_wd_int = regmap_irq_get_virq(wcd938x->irq_chip,
3328 WCD938X_IRQ_HPHL_PDM_WD_INT);
3329 wcd938x->aux_pdm_wd_int = regmap_irq_get_virq(wcd938x->irq_chip,
3330 WCD938X_IRQ_AUX_PDM_WD_INT);
3331
3332 /* Request for watchdog interrupt */
3333 ret = request_threaded_irq(wcd938x->hphr_pdm_wd_int, NULL, wcd938x_wd_handle_irq,
3334 IRQF_ONESHOT | IRQF_TRIGGER_RISING,
3335 "HPHR PDM WD INT", wcd938x);
3336 if (ret)
3337 dev_err(dev, "Failed to request HPHR WD interrupt (%d)\n", ret);
3338
3339 ret = request_threaded_irq(wcd938x->hphl_pdm_wd_int, NULL, wcd938x_wd_handle_irq,
3340 IRQF_ONESHOT | IRQF_TRIGGER_RISING,
3341 "HPHL PDM WD INT", wcd938x);
3342 if (ret)
3343 dev_err(dev, "Failed to request HPHL WD interrupt (%d)\n", ret);
3344
3345 ret = request_threaded_irq(wcd938x->aux_pdm_wd_int, NULL, wcd938x_wd_handle_irq,
3346 IRQF_ONESHOT | IRQF_TRIGGER_RISING,
3347 "AUX PDM WD INT", wcd938x);
3348 if (ret)
3349 dev_err(dev, "Failed to request Aux WD interrupt (%d)\n", ret);
3350
3351 /* Disable watchdog interrupt for HPH and AUX */
3352 disable_irq_nosync(wcd938x->hphr_pdm_wd_int);
3353 disable_irq_nosync(wcd938x->hphl_pdm_wd_int);
3354 disable_irq_nosync(wcd938x->aux_pdm_wd_int);
3355
Srinivas Kandagatlae8ba1e02021-06-09 10:09:40 +0100[diff] [blame]3356 switch (wcd938x->variant) {
3357 case WCD9380:
3358 ret = snd_soc_add_component_controls(component, wcd9380_snd_controls,
3359 ARRAY_SIZE(wcd9380_snd_controls));
3360 if (ret < 0) {
3361 dev_err(component->dev,
3362 "%s: Failed to add snd ctrls for variant: %d\n",
3363 __func__, wcd938x->variant);
3364 goto err;
3365 }
3366 break;
3367 case WCD9385:
3368 ret = snd_soc_add_component_controls(component, wcd9385_snd_controls,
3369 ARRAY_SIZE(wcd9385_snd_controls));
3370 if (ret < 0) {
3371 dev_err(component->dev,
3372 "%s: Failed to add snd ctrls for variant: %d\n",
3373 __func__, wcd938x->variant);
3374 goto err;
3375 }
3376 break;
3377 default:
3378 break;
3379 }
3380err:
Srinivas Kandagatla8d786022021-06-09 10:09:37 +0100[diff] [blame]3381 return ret;
3382}
3383
3384static const struct snd_soc_component_driver soc_codec_dev_wcd938x = {
3385 .name = "wcd938x_codec",
3386 .probe = wcd938x_soc_codec_probe,
Srinivas Kandagatlae8ba1e02021-06-09 10:09:40 +0100[diff] [blame]3387 .controls = wcd938x_snd_controls,
3388 .num_controls = ARRAY_SIZE(wcd938x_snd_controls),
Srinivas Kandagatla8da9db02021-06-09 10:09:41 +0100[diff] [blame]3389 .dapm_widgets = wcd938x_dapm_widgets,
3390 .num_dapm_widgets = ARRAY_SIZE(wcd938x_dapm_widgets),
Srinivas Kandagatla04544222021-06-09 10:09:43 +0100[diff] [blame]3391 .dapm_routes = wcd938x_audio_map,
3392 .num_dapm_routes = ARRAY_SIZE(wcd938x_audio_map),
Srinivas Kandagatla8d786022021-06-09 10:09:37 +0100[diff] [blame]3393};
3394
3395static void wcd938x_dt_parse_micbias_info(struct device *dev, struct wcd938x_priv *wcd)
3396{
3397 struct device_node *np = dev->of_node;
3398 u32 prop_val = 0;
3399 int rc = 0;
3400
3401 rc = of_property_read_u32(np, "qcom,micbias1-microvolt", &prop_val);
3402 if (!rc)
3403 wcd->micb1_mv = prop_val/1000;
3404 else
3405 dev_info(dev, "%s: Micbias1 DT property not found\n", __func__);
3406
3407 rc = of_property_read_u32(np, "qcom,micbias2-microvolt", &prop_val);
3408 if (!rc)
3409 wcd->micb2_mv = prop_val/1000;
3410 else
3411 dev_info(dev, "%s: Micbias2 DT property not found\n", __func__);
3412
3413 rc = of_property_read_u32(np, "qcom,micbias3-microvolt", &prop_val);
3414 if (!rc)
3415 wcd->micb3_mv = prop_val/1000;
3416 else
3417 dev_info(dev, "%s: Micbias3 DT property not found\n", __func__);
3418
3419 rc = of_property_read_u32(np, "qcom,micbias4-microvolt", &prop_val);
3420 if (!rc)
3421 wcd->micb4_mv = prop_val/1000;
3422 else
3423 dev_info(dev, "%s: Micbias4 DT property not found\n", __func__);
3424}
3425
3426static int wcd938x_populate_dt_data(struct wcd938x_priv *wcd938x, struct device *dev)
3427{
3428 int ret;
3429
3430 wcd938x->reset_gpio = of_get_named_gpio(dev->of_node, "reset-gpios", 0);
3431 if (wcd938x->reset_gpio < 0) {
3432 dev_err(dev, "Failed to get reset gpio: err = %d\n",
3433 wcd938x->reset_gpio);
3434 return wcd938x->reset_gpio;
3435 }
3436
3437 wcd938x->supplies[0].supply = "vdd-rxtx";
3438 wcd938x->supplies[1].supply = "vdd-io";
3439 wcd938x->supplies[2].supply = "vdd-buck";
3440 wcd938x->supplies[3].supply = "vdd-mic-bias";
3441
3442 ret = regulator_bulk_get(dev, WCD938X_MAX_SUPPLY, wcd938x->supplies);
3443 if (ret) {
3444 dev_err(dev, "Failed to get supplies: err = %d\n", ret);
3445 return ret;
3446 }
3447
3448 ret = regulator_bulk_enable(WCD938X_MAX_SUPPLY, wcd938x->supplies);
3449 if (ret) {
3450 dev_err(dev, "Failed to enable supplies: err = %d\n", ret);
3451 return ret;
3452 }
3453
3454 wcd938x_dt_parse_micbias_info(dev, wcd938x);
3455
3456 return 0;
3457}
3458
3459static int wcd938x_reset(struct wcd938x_priv *wcd938x)
3460{
3461 gpio_direction_output(wcd938x->reset_gpio, 0);
3462 /* 20us sleep required after pulling the reset gpio to LOW */
3463 usleep_range(20, 30);
3464 gpio_set_value(wcd938x->reset_gpio, 1);
3465 /* 20us sleep required after pulling the reset gpio to HIGH */
3466 usleep_range(20, 30);
3467
3468 return 0;
3469}
3470
Srinivas Kandagatla16572522021-06-09 10:09:39 +0100[diff] [blame]3471static int wcd938x_codec_hw_params(struct snd_pcm_substream *substream,
3472 struct snd_pcm_hw_params *params,
3473 struct snd_soc_dai *dai)
3474{
3475 struct wcd938x_priv *wcd938x = dev_get_drvdata(dai->dev);
3476 struct wcd938x_sdw_priv *wcd = wcd938x->sdw_priv[dai->id];
3477
3478 return wcd938x_sdw_hw_params(wcd, substream, params, dai);
3479}
3480
3481static int wcd938x_codec_free(struct snd_pcm_substream *substream,
3482 struct snd_soc_dai *dai)
3483{
3484 struct wcd938x_priv *wcd938x = dev_get_drvdata(dai->dev);
3485 struct wcd938x_sdw_priv *wcd = wcd938x->sdw_priv[dai->id];
3486
3487 return wcd938x_sdw_free(wcd, substream, dai);
3488}
3489
3490static int wcd938x_codec_set_sdw_stream(struct snd_soc_dai *dai,
3491 void *stream, int direction)
3492{
3493 struct wcd938x_priv *wcd938x = dev_get_drvdata(dai->dev);
3494 struct wcd938x_sdw_priv *wcd = wcd938x->sdw_priv[dai->id];
3495
3496 return wcd938x_sdw_set_sdw_stream(wcd, dai, stream, direction);
3497
3498}
3499
Pu Lehui355af6c2021-06-15 19:33:24 +0800[diff] [blame]3500static const struct snd_soc_dai_ops wcd938x_sdw_dai_ops = {
Srinivas Kandagatla16572522021-06-09 10:09:39 +0100[diff] [blame]3501 .hw_params = wcd938x_codec_hw_params,
3502 .hw_free = wcd938x_codec_free,
3503 .set_sdw_stream = wcd938x_codec_set_sdw_stream,
Srinivas Kandagatla8d786022021-06-09 10:09:37 +0100[diff] [blame]3504};
3505
3506static struct snd_soc_dai_driver wcd938x_dais[] = {
3507 [0] = {
3508 .name = "wcd938x-sdw-rx",
3509 .playback = {
3510 .stream_name = "WCD AIF1 Playback",
3511 .rates = WCD938X_RATES_MASK | WCD938X_FRAC_RATES_MASK,
3512 .formats = WCD938X_FORMATS_S16_S24_LE,
3513 .rate_max = 192000,
3514 .rate_min = 8000,
3515 .channels_min = 1,
3516 .channels_max = 2,
3517 },
3518 .ops = &wcd938x_sdw_dai_ops,
3519 },
3520 [1] = {
3521 .name = "wcd938x-sdw-tx",
3522 .capture = {
3523 .stream_name = "WCD AIF1 Capture",
3524 .rates = WCD938X_RATES_MASK,
3525 .formats = SNDRV_PCM_FMTBIT_S16_LE,
3526 .rate_min = 8000,
3527 .rate_max = 192000,
3528 .channels_min = 1,
3529 .channels_max = 4,
3530 },
3531 .ops = &wcd938x_sdw_dai_ops,
3532 },
3533};
3534
3535static int wcd938x_bind(struct device *dev)
3536{
3537 struct wcd938x_priv *wcd938x = dev_get_drvdata(dev);
3538 int ret;
3539
3540 ret = component_bind_all(dev, wcd938x);
3541 if (ret) {
3542 dev_err(dev, "%s: Slave bind failed, ret = %d\n",
3543 __func__, ret);
3544 return ret;
3545 }
3546
Srinivas Kandagatla16572522021-06-09 10:09:39 +0100[diff] [blame]3547 wcd938x->rxdev = wcd938x_sdw_device_get(wcd938x->rxnode);
3548 if (!wcd938x->rxdev) {
3549 dev_err(dev, "could not find slave with matching of node\n");
3550 return -EINVAL;
3551 }
3552 wcd938x->sdw_priv[AIF1_PB] = dev_get_drvdata(wcd938x->rxdev);
3553 wcd938x->sdw_priv[AIF1_PB]->wcd938x = wcd938x;
Srinivas Kandagatlab90d9392021-06-15 14:28:29 +0100[diff] [blame]3554 wcd938x->sdw_priv[AIF1_PB]->slave_irq = wcd938x->virq;
Srinivas Kandagatla16572522021-06-09 10:09:39 +0100[diff] [blame]3555
3556 wcd938x->txdev = wcd938x_sdw_device_get(wcd938x->txnode);
3557 if (!wcd938x->txdev) {
3558 dev_err(dev, "could not find txslave with matching of node\n");
3559 return -EINVAL;
3560 }
3561 wcd938x->sdw_priv[AIF1_CAP] = dev_get_drvdata(wcd938x->txdev);
3562 wcd938x->sdw_priv[AIF1_CAP]->wcd938x = wcd938x;
Srinivas Kandagatlab90d9392021-06-15 14:28:29 +0100[diff] [blame]3563 wcd938x->sdw_priv[AIF1_CAP]->slave_irq = wcd938x->virq;
Srinivas Kandagatla16572522021-06-09 10:09:39 +0100[diff] [blame]3564 wcd938x->tx_sdw_dev = dev_to_sdw_dev(wcd938x->txdev);
3565 if (!wcd938x->tx_sdw_dev) {
3566 dev_err(dev, "could not get txslave with matching of dev\n");
3567 return -EINVAL;
3568 }
3569
3570 /* As TX is main CSR reg interface, which should not be suspended first.
3571 * expicilty add the dependency link */
3572 if (!device_link_add(wcd938x->rxdev, wcd938x->txdev, DL_FLAG_STATELESS |
3573 DL_FLAG_PM_RUNTIME)) {
3574 dev_err(dev, "could not devlink tx and rx\n");
3575 return -EINVAL;
3576 }
3577
3578 if (!device_link_add(dev, wcd938x->txdev, DL_FLAG_STATELESS |
3579 DL_FLAG_PM_RUNTIME)) {
3580 dev_err(dev, "could not devlink wcd and tx\n");
3581 return -EINVAL;
3582 }
3583
3584 if (!device_link_add(dev, wcd938x->rxdev, DL_FLAG_STATELESS |
3585 DL_FLAG_PM_RUNTIME)) {
3586 dev_err(dev, "could not devlink wcd and rx\n");
3587 return -EINVAL;
3588 }
3589
Srinivas Kandagatlab90d9392021-06-15 14:28:29 +0100[diff] [blame]3590 wcd938x->regmap = devm_regmap_init_sdw(wcd938x->tx_sdw_dev, &wcd938x_regmap_config);
3591 if (IS_ERR(wcd938x->regmap)) {
Srinivas Kandagatla16572522021-06-09 10:09:39 +0100[diff] [blame]3592 dev_err(dev, "%s: tx csr regmap not found\n", __func__);
3593 return PTR_ERR(wcd938x->regmap);
3594 }
3595
Srinivas Kandagatla8d786022021-06-09 10:09:37 +0100[diff] [blame]3596 ret = wcd938x_set_micbias_data(wcd938x);
3597 if (ret < 0) {
3598 dev_err(dev, "%s: bad micbias pdata\n", __func__);
3599 return ret;
3600 }
3601
3602 ret = snd_soc_register_component(dev, &soc_codec_dev_wcd938x,
3603 wcd938x_dais, ARRAY_SIZE(wcd938x_dais));
3604 if (ret)
3605 dev_err(dev, "%s: Codec registration failed\n",
3606 __func__);
3607
3608 return ret;
3609
3610}
3611
3612static void wcd938x_unbind(struct device *dev)
3613{
3614 struct wcd938x_priv *wcd938x = dev_get_drvdata(dev);
3615
Srinivas Kandagatla16572522021-06-09 10:09:39 +0100[diff] [blame]3616 device_link_remove(dev, wcd938x->txdev);
3617 device_link_remove(dev, wcd938x->rxdev);
3618 device_link_remove(wcd938x->rxdev, wcd938x->txdev);
Srinivas Kandagatla8d786022021-06-09 10:09:37 +0100[diff] [blame]3619 snd_soc_unregister_component(dev);
3620 component_unbind_all(dev, wcd938x);
3621}
3622
3623static const struct component_master_ops wcd938x_comp_ops = {
3624 .bind = wcd938x_bind,
3625 .unbind = wcd938x_unbind,
3626};
3627
3628static int wcd938x_compare_of(struct device *dev, void *data)
3629{
3630 return dev->of_node == data;
3631}
3632
3633static void wcd938x_release_of(struct device *dev, void *data)
3634{
3635 of_node_put(data);
3636}
3637
3638static int wcd938x_add_slave_components(struct wcd938x_priv *wcd938x,
3639 struct device *dev,
3640 struct component_match **matchptr)
3641{
3642 struct device_node *np;
3643
3644 np = dev->of_node;
3645
3646 wcd938x->rxnode = of_parse_phandle(np, "qcom,rx-device", 0);
3647 if (!wcd938x->rxnode) {
3648 dev_err(dev, "%s: Rx-device node not defined\n", __func__);
3649 return -ENODEV;
3650 }
3651
3652 of_node_get(wcd938x->rxnode);
3653 component_match_add_release(dev, matchptr, wcd938x_release_of,
3654 wcd938x_compare_of, wcd938x->rxnode);
3655
3656 wcd938x->txnode = of_parse_phandle(np, "qcom,tx-device", 0);
3657 if (!wcd938x->txnode) {
3658 dev_err(dev, "%s: Tx-device node not defined\n", __func__);
3659 return -ENODEV;
3660 }
3661 of_node_get(wcd938x->txnode);
3662 component_match_add_release(dev, matchptr, wcd938x_release_of,
3663 wcd938x_compare_of, wcd938x->txnode);
3664 return 0;
3665}
3666
3667static int wcd938x_probe(struct platform_device *pdev)
3668{
3669 struct component_match *match = NULL;
3670 struct wcd938x_priv *wcd938x = NULL;
3671 struct device *dev = &pdev->dev;
3672 int ret;
3673
3674 wcd938x = devm_kzalloc(dev, sizeof(struct wcd938x_priv),
3675 GFP_KERNEL);
3676 if (!wcd938x)
3677 return -ENOMEM;
3678
3679 dev_set_drvdata(dev, wcd938x);
3680
3681 ret = wcd938x_populate_dt_data(wcd938x, dev);
3682 if (ret) {
3683 dev_err(dev, "%s: Fail to obtain platform data\n", __func__);
3684 return -EINVAL;
3685 }
3686
3687 ret = wcd938x_add_slave_components(wcd938x, dev, &match);
3688 if (ret)
3689 return ret;
3690
3691 wcd938x_reset(wcd938x);
3692
3693 ret = component_master_add_with_match(dev, &wcd938x_comp_ops, match);
3694 if (ret)
3695 return ret;
3696
3697 pm_runtime_set_autosuspend_delay(dev, 1000);
3698 pm_runtime_use_autosuspend(dev);
3699 pm_runtime_mark_last_busy(dev);
3700 pm_runtime_set_active(dev);
3701 pm_runtime_enable(dev);
3702 pm_runtime_idle(dev);
3703
3704 return ret;
3705}
3706
3707static int wcd938x_remove(struct platform_device *pdev)
3708{
3709 component_master_del(&pdev->dev, &wcd938x_comp_ops);
3710
3711 return 0;
3712}
3713
Srinivas Kandagatla8c4863c2021-06-21 14:45:01 +0100[diff] [blame]3714#if defined(CONFIG_OF)
Srinivas Kandagatla8d786022021-06-09 10:09:37 +0100[diff] [blame]3715static const struct of_device_id wcd938x_dt_match[] = {
3716 { .compatible = "qcom,wcd9380-codec" },
3717 { .compatible = "qcom,wcd9385-codec" },
3718 {}
3719};
3720MODULE_DEVICE_TABLE(of, wcd938x_dt_match);
Srinivas Kandagatla8c4863c2021-06-21 14:45:01 +0100[diff] [blame]3721#endif
Srinivas Kandagatla8d786022021-06-09 10:09:37 +0100[diff] [blame]3722
3723static struct platform_driver wcd938x_codec_driver = {
3724 .probe = wcd938x_probe,
3725 .remove = wcd938x_remove,
3726 .driver = {
3727 .name = "wcd938x_codec",
3728 .of_match_table = of_match_ptr(wcd938x_dt_match),
3729 .suppress_bind_attrs = true,
3730 },
3731};
3732
3733module_platform_driver(wcd938x_codec_driver);
3734MODULE_DESCRIPTION("WCD938X Codec driver");
3735MODULE_LICENSE("GPL");