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review.shift-gmbh.com / SHIFTPHONES / mainline / linux / 8da9db0cd6694c98f64b6ec413337ac834e05bb0 / . / sound / soc / codecs / wcd938x.c
blob: c953493279afde837729184fa21d1a1c623f84bc [file] [log] [blame]
Srinivas Kandagatla8d786022021-06-09 10:09:37 +0100[diff] [blame]1// SPDX-License-Identifier: GPL-2.0-only
2// Copyright (c) 2018-2020, The Linux Foundation. All rights reserved.
3
4#include <linux/module.h>
5#include <linux/slab.h>
6#include <linux/platform_device.h>
7#include <linux/device.h>
8#include <linux/delay.h>
9#include <linux/kernel.h>
10#include <linux/pm_runtime.h>
11#include <linux/component.h>
12#include <sound/soc.h>
13#include <sound/tlv.h>
14#include <linux/of_gpio.h>
15#include <linux/of.h>
16#include <sound/jack.h>
17#include <sound/pcm.h>
18#include <sound/pcm_params.h>
19#include <linux/regmap.h>
20#include <sound/soc.h>
21#include <sound/soc-dapm.h>
22#include <linux/regulator/consumer.h>
23
24#include "wcd-clsh-v2.h"
25#include "wcd938x.h"
26
27#define WCD938X_MAX_MICBIAS (4)
28#define WCD938X_MAX_SUPPLY (4)
29#define WCD938X_MBHC_MAX_BUTTONS (8)
30#define TX_ADC_MAX (4)
31#define WCD938X_TX_MAX_SWR_PORTS (5)
32
33#define WCD938X_RATES_MASK (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |\
34 SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_48000 |\
35 SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_192000)
36/* Fractional Rates */
37#define WCD938X_FRAC_RATES_MASK (SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_88200 |\
38 SNDRV_PCM_RATE_176400)
39#define WCD938X_FORMATS_S16_S24_LE (SNDRV_PCM_FMTBIT_S16_LE | \
40 SNDRV_PCM_FMTBIT_S24_LE)
41/* Convert from vout ctl to micbias voltage in mV */
42#define WCD_VOUT_CTL_TO_MICB(v) (1000 + v * 50)
43#define SWR_CLK_RATE_0P6MHZ (600000)
44#define SWR_CLK_RATE_1P2MHZ (1200000)
45#define SWR_CLK_RATE_2P4MHZ (2400000)
46#define SWR_CLK_RATE_4P8MHZ (4800000)
47#define SWR_CLK_RATE_9P6MHZ (9600000)
48#define SWR_CLK_RATE_11P2896MHZ (1128960)
49
50#define WCD938X_DRV_NAME "wcd938x_codec"
51#define WCD938X_VERSION_1_0 (1)
52#define EAR_RX_PATH_AUX (1)
53
54#define ADC_MODE_VAL_HIFI 0x01
55#define ADC_MODE_VAL_LO_HIF 0x02
56#define ADC_MODE_VAL_NORMAL 0x03
57#define ADC_MODE_VAL_LP 0x05
58#define ADC_MODE_VAL_ULP1 0x09
59#define ADC_MODE_VAL_ULP2 0x0B
60
61/* Z value defined in milliohm */
62#define WCD938X_ZDET_VAL_32 (32000)
63#define WCD938X_ZDET_VAL_400 (400000)
64#define WCD938X_ZDET_VAL_1200 (1200000)
65#define WCD938X_ZDET_VAL_100K (100000000)
66/* Z floating defined in ohms */
67#define WCD938X_ZDET_FLOATING_IMPEDANCE (0x0FFFFFFE)
68#define WCD938X_ZDET_NUM_MEASUREMENTS (900)
69#define WCD938X_MBHC_GET_C1(c) ((c & 0xC000) >> 14)
70#define WCD938X_MBHC_GET_X1(x) (x & 0x3FFF)
71/* Z value compared in milliOhm */
72#define WCD938X_MBHC_IS_SECOND_RAMP_REQUIRED(z) ((z > 400000) || (z < 32000))
73#define WCD938X_MBHC_ZDET_CONST (86 * 16384)
74#define WCD938X_MBHC_MOISTURE_RREF R_24_KOHM
75#define WCD_MBHC_HS_V_MAX 1600
76
Srinivas Kandagatlae8ba1e02021-06-09 10:09:40 +0100[diff] [blame]77#define WCD938X_EAR_PA_GAIN_TLV(xname, reg, shift, max, invert, tlv_array) \
78{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
79 .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ |\
80 SNDRV_CTL_ELEM_ACCESS_READWRITE,\
81 .tlv.p = (tlv_array), \
82 .info = snd_soc_info_volsw, .get = snd_soc_get_volsw,\
83 .put = wcd938x_ear_pa_put_gain, \
84 .private_value = SOC_SINGLE_VALUE(reg, shift, max, invert, 0) }
85
Srinivas Kandagatla8d786022021-06-09 10:09:37 +0100[diff] [blame]86enum {
87 WCD9380 = 0,
88 WCD9385 = 5,
89};
90
91enum {
92 TX_HDR12 = 0,
93 TX_HDR34,
94 TX_HDR_MAX,
95};
96
97enum {
98 WCD_RX1,
99 WCD_RX2,
100 WCD_RX3
101};
102
103enum {
104 /* INTR_CTRL_INT_MASK_0 */
105 WCD938X_IRQ_MBHC_BUTTON_PRESS_DET = 0,
106 WCD938X_IRQ_MBHC_BUTTON_RELEASE_DET,
107 WCD938X_IRQ_MBHC_ELECT_INS_REM_DET,
108 WCD938X_IRQ_MBHC_ELECT_INS_REM_LEG_DET,
109 WCD938X_IRQ_MBHC_SW_DET,
110 WCD938X_IRQ_HPHR_OCP_INT,
111 WCD938X_IRQ_HPHR_CNP_INT,
112 WCD938X_IRQ_HPHL_OCP_INT,
113
114 /* INTR_CTRL_INT_MASK_1 */
115 WCD938X_IRQ_HPHL_CNP_INT,
116 WCD938X_IRQ_EAR_CNP_INT,
117 WCD938X_IRQ_EAR_SCD_INT,
118 WCD938X_IRQ_AUX_CNP_INT,
119 WCD938X_IRQ_AUX_SCD_INT,
120 WCD938X_IRQ_HPHL_PDM_WD_INT,
121 WCD938X_IRQ_HPHR_PDM_WD_INT,
122 WCD938X_IRQ_AUX_PDM_WD_INT,
123
124 /* INTR_CTRL_INT_MASK_2 */
125 WCD938X_IRQ_LDORT_SCD_INT,
126 WCD938X_IRQ_MBHC_MOISTURE_INT,
127 WCD938X_IRQ_HPHL_SURGE_DET_INT,
128 WCD938X_IRQ_HPHR_SURGE_DET_INT,
129 WCD938X_NUM_IRQS,
130};
131
132enum {
133 WCD_ADC1 = 0,
134 WCD_ADC2,
135 WCD_ADC3,
136 WCD_ADC4,
137 ALLOW_BUCK_DISABLE,
138 HPH_COMP_DELAY,
139 HPH_PA_DELAY,
140 AMIC2_BCS_ENABLE,
141 WCD_SUPPLIES_LPM_MODE,
142};
143
144enum {
145 ADC_MODE_INVALID = 0,
146 ADC_MODE_HIFI,
147 ADC_MODE_LO_HIF,
148 ADC_MODE_NORMAL,
149 ADC_MODE_LP,
150 ADC_MODE_ULP1,
151 ADC_MODE_ULP2,
152};
153
154enum {
155 AIF1_PB = 0,
156 AIF1_CAP,
157 NUM_CODEC_DAIS,
158};
159
160struct wcd938x_priv {
161 struct sdw_slave *tx_sdw_dev;
162 struct wcd938x_sdw_priv *sdw_priv[NUM_CODEC_DAIS];
163 struct device *txdev;
164 struct device *rxdev;
165 struct device_node *rxnode, *txnode;
166 struct regmap *regmap;
167 struct wcd_clsh_ctrl *clsh_info;
168 struct irq_domain *virq;
169 struct regmap_irq_chip *wcd_regmap_irq_chip;
170 struct regmap_irq_chip_data *irq_chip;
171 struct regulator_bulk_data supplies[WCD938X_MAX_SUPPLY];
172 struct snd_soc_jack *jack;
173 unsigned long status_mask;
174 s32 micb_ref[WCD938X_MAX_MICBIAS];
175 s32 pullup_ref[WCD938X_MAX_MICBIAS];
176 u32 hph_mode;
177 u32 tx_mode[TX_ADC_MAX];
178 int flyback_cur_det_disable;
179 int ear_rx_path;
180 int variant;
181 int reset_gpio;
182 u32 micb1_mv;
183 u32 micb2_mv;
184 u32 micb3_mv;
185 u32 micb4_mv;
186 int hphr_pdm_wd_int;
187 int hphl_pdm_wd_int;
188 int aux_pdm_wd_int;
189 bool comp1_enable;
190 bool comp2_enable;
191 bool ldoh;
192 bool bcs_dis;
193};
194
195enum {
196 MIC_BIAS_1 = 1,
197 MIC_BIAS_2,
198 MIC_BIAS_3,
199 MIC_BIAS_4
200};
201
202enum {
203 MICB_PULLUP_ENABLE,
204 MICB_PULLUP_DISABLE,
205 MICB_ENABLE,
206 MICB_DISABLE,
207};
208
Srinivas Kandagatlae8ba1e02021-06-09 10:09:40 +0100[diff] [blame]209static const SNDRV_CTL_TLVD_DECLARE_DB_MINMAX(ear_pa_gain, 600, -1800);
210static const SNDRV_CTL_TLVD_DECLARE_DB_MINMAX(line_gain, 600, -3000);
211static const SNDRV_CTL_TLVD_DECLARE_DB_MINMAX(analog_gain, 0, 3000);
212
Srinivas Kandagatla8d786022021-06-09 10:09:37 +0100[diff] [blame]213static const struct reg_default wcd938x_defaults[] = {
214 {WCD938X_ANA_PAGE_REGISTER, 0x00},
215 {WCD938X_ANA_BIAS, 0x00},
216 {WCD938X_ANA_RX_SUPPLIES, 0x00},
217 {WCD938X_ANA_HPH, 0x0C},
218 {WCD938X_ANA_EAR, 0x00},
219 {WCD938X_ANA_EAR_COMPANDER_CTL, 0x02},
220 {WCD938X_ANA_TX_CH1, 0x20},
221 {WCD938X_ANA_TX_CH2, 0x00},
222 {WCD938X_ANA_TX_CH3, 0x20},
223 {WCD938X_ANA_TX_CH4, 0x00},
224 {WCD938X_ANA_MICB1_MICB2_DSP_EN_LOGIC, 0x00},
225 {WCD938X_ANA_MICB3_DSP_EN_LOGIC, 0x00},
226 {WCD938X_ANA_MBHC_MECH, 0x39},
227 {WCD938X_ANA_MBHC_ELECT, 0x08},
228 {WCD938X_ANA_MBHC_ZDET, 0x00},
229 {WCD938X_ANA_MBHC_RESULT_1, 0x00},
230 {WCD938X_ANA_MBHC_RESULT_2, 0x00},
231 {WCD938X_ANA_MBHC_RESULT_3, 0x00},
232 {WCD938X_ANA_MBHC_BTN0, 0x00},
233 {WCD938X_ANA_MBHC_BTN1, 0x10},
234 {WCD938X_ANA_MBHC_BTN2, 0x20},
235 {WCD938X_ANA_MBHC_BTN3, 0x30},
236 {WCD938X_ANA_MBHC_BTN4, 0x40},
237 {WCD938X_ANA_MBHC_BTN5, 0x50},
238 {WCD938X_ANA_MBHC_BTN6, 0x60},
239 {WCD938X_ANA_MBHC_BTN7, 0x70},
240 {WCD938X_ANA_MICB1, 0x10},
241 {WCD938X_ANA_MICB2, 0x10},
242 {WCD938X_ANA_MICB2_RAMP, 0x00},
243 {WCD938X_ANA_MICB3, 0x10},
244 {WCD938X_ANA_MICB4, 0x10},
245 {WCD938X_BIAS_CTL, 0x2A},
246 {WCD938X_BIAS_VBG_FINE_ADJ, 0x55},
247 {WCD938X_LDOL_VDDCX_ADJUST, 0x01},
248 {WCD938X_LDOL_DISABLE_LDOL, 0x00},
249 {WCD938X_MBHC_CTL_CLK, 0x00},
250 {WCD938X_MBHC_CTL_ANA, 0x00},
251 {WCD938X_MBHC_CTL_SPARE_1, 0x00},
252 {WCD938X_MBHC_CTL_SPARE_2, 0x00},
253 {WCD938X_MBHC_CTL_BCS, 0x00},
254 {WCD938X_MBHC_MOISTURE_DET_FSM_STATUS, 0x00},
255 {WCD938X_MBHC_TEST_CTL, 0x00},
256 {WCD938X_LDOH_MODE, 0x2B},
257 {WCD938X_LDOH_BIAS, 0x68},
258 {WCD938X_LDOH_STB_LOADS, 0x00},
259 {WCD938X_LDOH_SLOWRAMP, 0x50},
260 {WCD938X_MICB1_TEST_CTL_1, 0x1A},
261 {WCD938X_MICB1_TEST_CTL_2, 0x00},
262 {WCD938X_MICB1_TEST_CTL_3, 0xA4},
263 {WCD938X_MICB2_TEST_CTL_1, 0x1A},
264 {WCD938X_MICB2_TEST_CTL_2, 0x00},
265 {WCD938X_MICB2_TEST_CTL_3, 0x24},
266 {WCD938X_MICB3_TEST_CTL_1, 0x1A},
267 {WCD938X_MICB3_TEST_CTL_2, 0x00},
268 {WCD938X_MICB3_TEST_CTL_3, 0xA4},
269 {WCD938X_MICB4_TEST_CTL_1, 0x1A},
270 {WCD938X_MICB4_TEST_CTL_2, 0x00},
271 {WCD938X_MICB4_TEST_CTL_3, 0xA4},
272 {WCD938X_TX_COM_ADC_VCM, 0x39},
273 {WCD938X_TX_COM_BIAS_ATEST, 0xE0},
274 {WCD938X_TX_COM_SPARE1, 0x00},
275 {WCD938X_TX_COM_SPARE2, 0x00},
276 {WCD938X_TX_COM_TXFE_DIV_CTL, 0x22},
277 {WCD938X_TX_COM_TXFE_DIV_START, 0x00},
278 {WCD938X_TX_COM_SPARE3, 0x00},
279 {WCD938X_TX_COM_SPARE4, 0x00},
280 {WCD938X_TX_1_2_TEST_EN, 0xCC},
281 {WCD938X_TX_1_2_ADC_IB, 0xE9},
282 {WCD938X_TX_1_2_ATEST_REFCTL, 0x0A},
283 {WCD938X_TX_1_2_TEST_CTL, 0x38},
284 {WCD938X_TX_1_2_TEST_BLK_EN1, 0xFF},
285 {WCD938X_TX_1_2_TXFE1_CLKDIV, 0x00},
286 {WCD938X_TX_1_2_SAR2_ERR, 0x00},
287 {WCD938X_TX_1_2_SAR1_ERR, 0x00},
288 {WCD938X_TX_3_4_TEST_EN, 0xCC},
289 {WCD938X_TX_3_4_ADC_IB, 0xE9},
290 {WCD938X_TX_3_4_ATEST_REFCTL, 0x0A},
291 {WCD938X_TX_3_4_TEST_CTL, 0x38},
292 {WCD938X_TX_3_4_TEST_BLK_EN3, 0xFF},
293 {WCD938X_TX_3_4_TXFE3_CLKDIV, 0x00},
294 {WCD938X_TX_3_4_SAR4_ERR, 0x00},
295 {WCD938X_TX_3_4_SAR3_ERR, 0x00},
296 {WCD938X_TX_3_4_TEST_BLK_EN2, 0xFB},
297 {WCD938X_TX_3_4_TXFE2_CLKDIV, 0x00},
298 {WCD938X_TX_3_4_SPARE1, 0x00},
299 {WCD938X_TX_3_4_TEST_BLK_EN4, 0xFB},
300 {WCD938X_TX_3_4_TXFE4_CLKDIV, 0x00},
301 {WCD938X_TX_3_4_SPARE2, 0x00},
302 {WCD938X_CLASSH_MODE_1, 0x40},
303 {WCD938X_CLASSH_MODE_2, 0x3A},
304 {WCD938X_CLASSH_MODE_3, 0x00},
305 {WCD938X_CLASSH_CTRL_VCL_1, 0x70},
306 {WCD938X_CLASSH_CTRL_VCL_2, 0x82},
307 {WCD938X_CLASSH_CTRL_CCL_1, 0x31},
308 {WCD938X_CLASSH_CTRL_CCL_2, 0x80},
309 {WCD938X_CLASSH_CTRL_CCL_3, 0x80},
310 {WCD938X_CLASSH_CTRL_CCL_4, 0x51},
311 {WCD938X_CLASSH_CTRL_CCL_5, 0x00},
312 {WCD938X_CLASSH_BUCK_TMUX_A_D, 0x00},
313 {WCD938X_CLASSH_BUCK_SW_DRV_CNTL, 0x77},
314 {WCD938X_CLASSH_SPARE, 0x00},
315 {WCD938X_FLYBACK_EN, 0x4E},
316 {WCD938X_FLYBACK_VNEG_CTRL_1, 0x0B},
317 {WCD938X_FLYBACK_VNEG_CTRL_2, 0x45},
318 {WCD938X_FLYBACK_VNEG_CTRL_3, 0x74},
319 {WCD938X_FLYBACK_VNEG_CTRL_4, 0x7F},
320 {WCD938X_FLYBACK_VNEG_CTRL_5, 0x83},
321 {WCD938X_FLYBACK_VNEG_CTRL_6, 0x98},
322 {WCD938X_FLYBACK_VNEG_CTRL_7, 0xA9},
323 {WCD938X_FLYBACK_VNEG_CTRL_8, 0x68},
324 {WCD938X_FLYBACK_VNEG_CTRL_9, 0x64},
325 {WCD938X_FLYBACK_VNEGDAC_CTRL_1, 0xED},
326 {WCD938X_FLYBACK_VNEGDAC_CTRL_2, 0xF0},
327 {WCD938X_FLYBACK_VNEGDAC_CTRL_3, 0xA6},
328 {WCD938X_FLYBACK_CTRL_1, 0x65},
329 {WCD938X_FLYBACK_TEST_CTL, 0x00},
330 {WCD938X_RX_AUX_SW_CTL, 0x00},
331 {WCD938X_RX_PA_AUX_IN_CONN, 0x01},
332 {WCD938X_RX_TIMER_DIV, 0x32},
333 {WCD938X_RX_OCP_CTL, 0x1F},
334 {WCD938X_RX_OCP_COUNT, 0x77},
335 {WCD938X_RX_BIAS_EAR_DAC, 0xA0},
336 {WCD938X_RX_BIAS_EAR_AMP, 0xAA},
337 {WCD938X_RX_BIAS_HPH_LDO, 0xA9},
338 {WCD938X_RX_BIAS_HPH_PA, 0xAA},
339 {WCD938X_RX_BIAS_HPH_RDACBUFF_CNP2, 0x8A},
340 {WCD938X_RX_BIAS_HPH_RDAC_LDO, 0x88},
341 {WCD938X_RX_BIAS_HPH_CNP1, 0x82},
342 {WCD938X_RX_BIAS_HPH_LOWPOWER, 0x82},
343 {WCD938X_RX_BIAS_AUX_DAC, 0xA0},
344 {WCD938X_RX_BIAS_AUX_AMP, 0xAA},
345 {WCD938X_RX_BIAS_VNEGDAC_BLEEDER, 0x50},
346 {WCD938X_RX_BIAS_MISC, 0x00},
347 {WCD938X_RX_BIAS_BUCK_RST, 0x08},
348 {WCD938X_RX_BIAS_BUCK_VREF_ERRAMP, 0x44},
349 {WCD938X_RX_BIAS_FLYB_ERRAMP, 0x40},
350 {WCD938X_RX_BIAS_FLYB_BUFF, 0xAA},
351 {WCD938X_RX_BIAS_FLYB_MID_RST, 0x14},
352 {WCD938X_HPH_L_STATUS, 0x04},
353 {WCD938X_HPH_R_STATUS, 0x04},
354 {WCD938X_HPH_CNP_EN, 0x80},
355 {WCD938X_HPH_CNP_WG_CTL, 0x9A},
356 {WCD938X_HPH_CNP_WG_TIME, 0x14},
357 {WCD938X_HPH_OCP_CTL, 0x28},
358 {WCD938X_HPH_AUTO_CHOP, 0x16},
359 {WCD938X_HPH_CHOP_CTL, 0x83},
360 {WCD938X_HPH_PA_CTL1, 0x46},
361 {WCD938X_HPH_PA_CTL2, 0x50},
362 {WCD938X_HPH_L_EN, 0x80},
363 {WCD938X_HPH_L_TEST, 0xE0},
364 {WCD938X_HPH_L_ATEST, 0x50},
365 {WCD938X_HPH_R_EN, 0x80},
366 {WCD938X_HPH_R_TEST, 0xE0},
367 {WCD938X_HPH_R_ATEST, 0x54},
368 {WCD938X_HPH_RDAC_CLK_CTL1, 0x99},
369 {WCD938X_HPH_RDAC_CLK_CTL2, 0x9B},
370 {WCD938X_HPH_RDAC_LDO_CTL, 0x33},
371 {WCD938X_HPH_RDAC_CHOP_CLK_LP_CTL, 0x00},
372 {WCD938X_HPH_REFBUFF_UHQA_CTL, 0x68},
373 {WCD938X_HPH_REFBUFF_LP_CTL, 0x0E},
374 {WCD938X_HPH_L_DAC_CTL, 0x20},
375 {WCD938X_HPH_R_DAC_CTL, 0x20},
376 {WCD938X_HPH_SURGE_HPHLR_SURGE_COMP_SEL, 0x55},
377 {WCD938X_HPH_SURGE_HPHLR_SURGE_EN, 0x19},
378 {WCD938X_HPH_SURGE_HPHLR_SURGE_MISC1, 0xA0},
379 {WCD938X_HPH_SURGE_HPHLR_SURGE_STATUS, 0x00},
380 {WCD938X_EAR_EAR_EN_REG, 0x22},
381 {WCD938X_EAR_EAR_PA_CON, 0x44},
382 {WCD938X_EAR_EAR_SP_CON, 0xDB},
383 {WCD938X_EAR_EAR_DAC_CON, 0x80},
384 {WCD938X_EAR_EAR_CNP_FSM_CON, 0xB2},
385 {WCD938X_EAR_TEST_CTL, 0x00},
386 {WCD938X_EAR_STATUS_REG_1, 0x00},
387 {WCD938X_EAR_STATUS_REG_2, 0x08},
388 {WCD938X_ANA_NEW_PAGE_REGISTER, 0x00},
389 {WCD938X_HPH_NEW_ANA_HPH2, 0x00},
390 {WCD938X_HPH_NEW_ANA_HPH3, 0x00},
391 {WCD938X_SLEEP_CTL, 0x16},
392 {WCD938X_SLEEP_WATCHDOG_CTL, 0x00},
393 {WCD938X_MBHC_NEW_ELECT_REM_CLAMP_CTL, 0x00},
394 {WCD938X_MBHC_NEW_CTL_1, 0x02},
395 {WCD938X_MBHC_NEW_CTL_2, 0x05},
396 {WCD938X_MBHC_NEW_PLUG_DETECT_CTL, 0xE9},
397 {WCD938X_MBHC_NEW_ZDET_ANA_CTL, 0x0F},
398 {WCD938X_MBHC_NEW_ZDET_RAMP_CTL, 0x00},
399 {WCD938X_MBHC_NEW_FSM_STATUS, 0x00},
400 {WCD938X_MBHC_NEW_ADC_RESULT, 0x00},
401 {WCD938X_TX_NEW_AMIC_MUX_CFG, 0x00},
402 {WCD938X_AUX_AUXPA, 0x00},
403 {WCD938X_LDORXTX_MODE, 0x0C},
404 {WCD938X_LDORXTX_CONFIG, 0x10},
405 {WCD938X_DIE_CRACK_DIE_CRK_DET_EN, 0x00},
406 {WCD938X_DIE_CRACK_DIE_CRK_DET_OUT, 0x00},
407 {WCD938X_HPH_NEW_INT_RDAC_GAIN_CTL, 0x40},
408 {WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_L, 0x81},
409 {WCD938X_HPH_NEW_INT_RDAC_VREF_CTL, 0x10},
410 {WCD938X_HPH_NEW_INT_RDAC_OVERRIDE_CTL, 0x00},
411 {WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_R, 0x81},
412 {WCD938X_HPH_NEW_INT_PA_MISC1, 0x22},
413 {WCD938X_HPH_NEW_INT_PA_MISC2, 0x00},
414 {WCD938X_HPH_NEW_INT_PA_RDAC_MISC, 0x00},
415 {WCD938X_HPH_NEW_INT_HPH_TIMER1, 0xFE},
416 {WCD938X_HPH_NEW_INT_HPH_TIMER2, 0x02},
417 {WCD938X_HPH_NEW_INT_HPH_TIMER3, 0x4E},
418 {WCD938X_HPH_NEW_INT_HPH_TIMER4, 0x54},
419 {WCD938X_HPH_NEW_INT_PA_RDAC_MISC2, 0x00},
420 {WCD938X_HPH_NEW_INT_PA_RDAC_MISC3, 0x00},
421 {WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_L_NEW, 0x90},
422 {WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_R_NEW, 0x90},
423 {WCD938X_RX_NEW_INT_HPH_RDAC_BIAS_LOHIFI, 0x62},
424 {WCD938X_RX_NEW_INT_HPH_RDAC_BIAS_ULP, 0x01},
425 {WCD938X_RX_NEW_INT_HPH_RDAC_LDO_LP, 0x11},
426 {WCD938X_MBHC_NEW_INT_MOISTURE_DET_DC_CTRL, 0x57},
427 {WCD938X_MBHC_NEW_INT_MOISTURE_DET_POLLING_CTRL, 0x01},
428 {WCD938X_MBHC_NEW_INT_MECH_DET_CURRENT, 0x00},
429 {WCD938X_MBHC_NEW_INT_SPARE_2, 0x00},
430 {WCD938X_EAR_INT_NEW_EAR_CHOPPER_CON, 0xA8},
431 {WCD938X_EAR_INT_NEW_CNP_VCM_CON1, 0x42},
432 {WCD938X_EAR_INT_NEW_CNP_VCM_CON2, 0x22},
433 {WCD938X_EAR_INT_NEW_EAR_DYNAMIC_BIAS, 0x00},
434 {WCD938X_AUX_INT_EN_REG, 0x00},
435 {WCD938X_AUX_INT_PA_CTRL, 0x06},
436 {WCD938X_AUX_INT_SP_CTRL, 0xD2},
437 {WCD938X_AUX_INT_DAC_CTRL, 0x80},
438 {WCD938X_AUX_INT_CLK_CTRL, 0x50},
439 {WCD938X_AUX_INT_TEST_CTRL, 0x00},
440 {WCD938X_AUX_INT_STATUS_REG, 0x00},
441 {WCD938X_AUX_INT_MISC, 0x00},
442 {WCD938X_LDORXTX_INT_BIAS, 0x6E},
443 {WCD938X_LDORXTX_INT_STB_LOADS_DTEST, 0x50},
444 {WCD938X_LDORXTX_INT_TEST0, 0x1C},
445 {WCD938X_LDORXTX_INT_STARTUP_TIMER, 0xFF},
446 {WCD938X_LDORXTX_INT_TEST1, 0x1F},
447 {WCD938X_LDORXTX_INT_STATUS, 0x00},
448 {WCD938X_SLEEP_INT_WATCHDOG_CTL_1, 0x0A},
449 {WCD938X_SLEEP_INT_WATCHDOG_CTL_2, 0x0A},
450 {WCD938X_DIE_CRACK_INT_DIE_CRK_DET_INT1, 0x02},
451 {WCD938X_DIE_CRACK_INT_DIE_CRK_DET_INT2, 0x60},
452 {WCD938X_TX_COM_NEW_INT_TXFE_DIVSTOP_L2, 0xFF},
453 {WCD938X_TX_COM_NEW_INT_TXFE_DIVSTOP_L1, 0x7F},
454 {WCD938X_TX_COM_NEW_INT_TXFE_DIVSTOP_L0, 0x3F},
455 {WCD938X_TX_COM_NEW_INT_TXFE_DIVSTOP_ULP1P2M, 0x1F},
456 {WCD938X_TX_COM_NEW_INT_TXFE_DIVSTOP_ULP0P6M, 0x0F},
457 {WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG1_L2L1, 0xD7},
458 {WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG1_L0, 0xC8},
459 {WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG1_ULP, 0xC6},
460 {WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG2MAIN_L2L1, 0xD5},
461 {WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG2MAIN_L0, 0xCA},
462 {WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG2MAIN_ULP, 0x05},
463 {WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG2CASC_L2L1L0, 0xA5},
464 {WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG2CASC_ULP, 0x13},
465 {WCD938X_TX_COM_NEW_INT_TXADC_SCBIAS_L2L1, 0x88},
466 {WCD938X_TX_COM_NEW_INT_TXADC_SCBIAS_L0ULP, 0x42},
467 {WCD938X_TX_COM_NEW_INT_TXADC_INT_L2, 0xFF},
468 {WCD938X_TX_COM_NEW_INT_TXADC_INT_L1, 0x64},
469 {WCD938X_TX_COM_NEW_INT_TXADC_INT_L0, 0x64},
470 {WCD938X_TX_COM_NEW_INT_TXADC_INT_ULP, 0x77},
471 {WCD938X_DIGITAL_PAGE_REGISTER, 0x00},
472 {WCD938X_DIGITAL_CHIP_ID0, 0x00},
473 {WCD938X_DIGITAL_CHIP_ID1, 0x00},
474 {WCD938X_DIGITAL_CHIP_ID2, 0x0D},
475 {WCD938X_DIGITAL_CHIP_ID3, 0x01},
476 {WCD938X_DIGITAL_SWR_TX_CLK_RATE, 0x00},
477 {WCD938X_DIGITAL_CDC_RST_CTL, 0x03},
478 {WCD938X_DIGITAL_TOP_CLK_CFG, 0x00},
479 {WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 0x00},
480 {WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0xF0},
481 {WCD938X_DIGITAL_SWR_RST_EN, 0x00},
482 {WCD938X_DIGITAL_CDC_PATH_MODE, 0x55},
483 {WCD938X_DIGITAL_CDC_RX_RST, 0x00},
484 {WCD938X_DIGITAL_CDC_RX0_CTL, 0xFC},
485 {WCD938X_DIGITAL_CDC_RX1_CTL, 0xFC},
486 {WCD938X_DIGITAL_CDC_RX2_CTL, 0xFC},
487 {WCD938X_DIGITAL_CDC_TX_ANA_MODE_0_1, 0x00},
488 {WCD938X_DIGITAL_CDC_TX_ANA_MODE_2_3, 0x00},
489 {WCD938X_DIGITAL_CDC_COMP_CTL_0, 0x00},
490 {WCD938X_DIGITAL_CDC_ANA_TX_CLK_CTL, 0x1E},
491 {WCD938X_DIGITAL_CDC_HPH_DSM_A1_0, 0x00},
492 {WCD938X_DIGITAL_CDC_HPH_DSM_A1_1, 0x01},
493 {WCD938X_DIGITAL_CDC_HPH_DSM_A2_0, 0x63},
494 {WCD938X_DIGITAL_CDC_HPH_DSM_A2_1, 0x04},
495 {WCD938X_DIGITAL_CDC_HPH_DSM_A3_0, 0xAC},
496 {WCD938X_DIGITAL_CDC_HPH_DSM_A3_1, 0x04},
497 {WCD938X_DIGITAL_CDC_HPH_DSM_A4_0, 0x1A},
498 {WCD938X_DIGITAL_CDC_HPH_DSM_A4_1, 0x03},
499 {WCD938X_DIGITAL_CDC_HPH_DSM_A5_0, 0xBC},
500 {WCD938X_DIGITAL_CDC_HPH_DSM_A5_1, 0x02},
501 {WCD938X_DIGITAL_CDC_HPH_DSM_A6_0, 0xC7},
502 {WCD938X_DIGITAL_CDC_HPH_DSM_A7_0, 0xF8},
503 {WCD938X_DIGITAL_CDC_HPH_DSM_C_0, 0x47},
504 {WCD938X_DIGITAL_CDC_HPH_DSM_C_1, 0x43},
505 {WCD938X_DIGITAL_CDC_HPH_DSM_C_2, 0xB1},
506 {WCD938X_DIGITAL_CDC_HPH_DSM_C_3, 0x17},
507 {WCD938X_DIGITAL_CDC_HPH_DSM_R1, 0x4D},
508 {WCD938X_DIGITAL_CDC_HPH_DSM_R2, 0x29},
509 {WCD938X_DIGITAL_CDC_HPH_DSM_R3, 0x34},
510 {WCD938X_DIGITAL_CDC_HPH_DSM_R4, 0x59},
511 {WCD938X_DIGITAL_CDC_HPH_DSM_R5, 0x66},
512 {WCD938X_DIGITAL_CDC_HPH_DSM_R6, 0x87},
513 {WCD938X_DIGITAL_CDC_HPH_DSM_R7, 0x64},
514 {WCD938X_DIGITAL_CDC_AUX_DSM_A1_0, 0x00},
515 {WCD938X_DIGITAL_CDC_AUX_DSM_A1_1, 0x01},
516 {WCD938X_DIGITAL_CDC_AUX_DSM_A2_0, 0x96},
517 {WCD938X_DIGITAL_CDC_AUX_DSM_A2_1, 0x09},
518 {WCD938X_DIGITAL_CDC_AUX_DSM_A3_0, 0xAB},
519 {WCD938X_DIGITAL_CDC_AUX_DSM_A3_1, 0x05},
520 {WCD938X_DIGITAL_CDC_AUX_DSM_A4_0, 0x1C},
521 {WCD938X_DIGITAL_CDC_AUX_DSM_A4_1, 0x02},
522 {WCD938X_DIGITAL_CDC_AUX_DSM_A5_0, 0x17},
523 {WCD938X_DIGITAL_CDC_AUX_DSM_A5_1, 0x02},
524 {WCD938X_DIGITAL_CDC_AUX_DSM_A6_0, 0xAA},
525 {WCD938X_DIGITAL_CDC_AUX_DSM_A7_0, 0xE3},
526 {WCD938X_DIGITAL_CDC_AUX_DSM_C_0, 0x69},
527 {WCD938X_DIGITAL_CDC_AUX_DSM_C_1, 0x54},
528 {WCD938X_DIGITAL_CDC_AUX_DSM_C_2, 0x02},
529 {WCD938X_DIGITAL_CDC_AUX_DSM_C_3, 0x15},
530 {WCD938X_DIGITAL_CDC_AUX_DSM_R1, 0xA4},
531 {WCD938X_DIGITAL_CDC_AUX_DSM_R2, 0xB5},
532 {WCD938X_DIGITAL_CDC_AUX_DSM_R3, 0x86},
533 {WCD938X_DIGITAL_CDC_AUX_DSM_R4, 0x85},
534 {WCD938X_DIGITAL_CDC_AUX_DSM_R5, 0xAA},
535 {WCD938X_DIGITAL_CDC_AUX_DSM_R6, 0xE2},
536 {WCD938X_DIGITAL_CDC_AUX_DSM_R7, 0x62},
537 {WCD938X_DIGITAL_CDC_HPH_GAIN_RX_0, 0x55},
538 {WCD938X_DIGITAL_CDC_HPH_GAIN_RX_1, 0xA9},
539 {WCD938X_DIGITAL_CDC_HPH_GAIN_DSD_0, 0x3D},
540 {WCD938X_DIGITAL_CDC_HPH_GAIN_DSD_1, 0x2E},
541 {WCD938X_DIGITAL_CDC_HPH_GAIN_DSD_2, 0x01},
542 {WCD938X_DIGITAL_CDC_AUX_GAIN_DSD_0, 0x00},
543 {WCD938X_DIGITAL_CDC_AUX_GAIN_DSD_1, 0xFC},
544 {WCD938X_DIGITAL_CDC_AUX_GAIN_DSD_2, 0x01},
545 {WCD938X_DIGITAL_CDC_HPH_GAIN_CTL, 0x00},
546 {WCD938X_DIGITAL_CDC_AUX_GAIN_CTL, 0x00},
547 {WCD938X_DIGITAL_CDC_EAR_PATH_CTL, 0x00},
548 {WCD938X_DIGITAL_CDC_SWR_CLH, 0x00},
549 {WCD938X_DIGITAL_SWR_CLH_BYP, 0x00},
550 {WCD938X_DIGITAL_CDC_TX0_CTL, 0x68},
551 {WCD938X_DIGITAL_CDC_TX1_CTL, 0x68},
552 {WCD938X_DIGITAL_CDC_TX2_CTL, 0x68},
553 {WCD938X_DIGITAL_CDC_TX_RST, 0x00},
554 {WCD938X_DIGITAL_CDC_REQ_CTL, 0x01},
555 {WCD938X_DIGITAL_CDC_RST, 0x00},
556 {WCD938X_DIGITAL_CDC_AMIC_CTL, 0x0F},
557 {WCD938X_DIGITAL_CDC_DMIC_CTL, 0x04},
558 {WCD938X_DIGITAL_CDC_DMIC1_CTL, 0x01},
559 {WCD938X_DIGITAL_CDC_DMIC2_CTL, 0x01},
560 {WCD938X_DIGITAL_CDC_DMIC3_CTL, 0x01},
561 {WCD938X_DIGITAL_CDC_DMIC4_CTL, 0x01},
562 {WCD938X_DIGITAL_EFUSE_PRG_CTL, 0x00},
563 {WCD938X_DIGITAL_EFUSE_CTL, 0x2B},
564 {WCD938X_DIGITAL_CDC_DMIC_RATE_1_2, 0x11},
565 {WCD938X_DIGITAL_CDC_DMIC_RATE_3_4, 0x11},
566 {WCD938X_DIGITAL_PDM_WD_CTL0, 0x00},
567 {WCD938X_DIGITAL_PDM_WD_CTL1, 0x00},
568 {WCD938X_DIGITAL_PDM_WD_CTL2, 0x00},
569 {WCD938X_DIGITAL_INTR_MODE, 0x00},
570 {WCD938X_DIGITAL_INTR_MASK_0, 0xFF},
571 {WCD938X_DIGITAL_INTR_MASK_1, 0xFF},
572 {WCD938X_DIGITAL_INTR_MASK_2, 0x3F},
573 {WCD938X_DIGITAL_INTR_STATUS_0, 0x00},
574 {WCD938X_DIGITAL_INTR_STATUS_1, 0x00},
575 {WCD938X_DIGITAL_INTR_STATUS_2, 0x00},
576 {WCD938X_DIGITAL_INTR_CLEAR_0, 0x00},
577 {WCD938X_DIGITAL_INTR_CLEAR_1, 0x00},
578 {WCD938X_DIGITAL_INTR_CLEAR_2, 0x00},
579 {WCD938X_DIGITAL_INTR_LEVEL_0, 0x00},
580 {WCD938X_DIGITAL_INTR_LEVEL_1, 0x00},
581 {WCD938X_DIGITAL_INTR_LEVEL_2, 0x00},
582 {WCD938X_DIGITAL_INTR_SET_0, 0x00},
583 {WCD938X_DIGITAL_INTR_SET_1, 0x00},
584 {WCD938X_DIGITAL_INTR_SET_2, 0x00},
585 {WCD938X_DIGITAL_INTR_TEST_0, 0x00},
586 {WCD938X_DIGITAL_INTR_TEST_1, 0x00},
587 {WCD938X_DIGITAL_INTR_TEST_2, 0x00},
588 {WCD938X_DIGITAL_TX_MODE_DBG_EN, 0x00},
589 {WCD938X_DIGITAL_TX_MODE_DBG_0_1, 0x00},
590 {WCD938X_DIGITAL_TX_MODE_DBG_2_3, 0x00},
591 {WCD938X_DIGITAL_LB_IN_SEL_CTL, 0x00},
592 {WCD938X_DIGITAL_LOOP_BACK_MODE, 0x00},
593 {WCD938X_DIGITAL_SWR_DAC_TEST, 0x00},
594 {WCD938X_DIGITAL_SWR_HM_TEST_RX_0, 0x40},
595 {WCD938X_DIGITAL_SWR_HM_TEST_TX_0, 0x40},
596 {WCD938X_DIGITAL_SWR_HM_TEST_RX_1, 0x00},
597 {WCD938X_DIGITAL_SWR_HM_TEST_TX_1, 0x00},
598 {WCD938X_DIGITAL_SWR_HM_TEST_TX_2, 0x00},
599 {WCD938X_DIGITAL_SWR_HM_TEST_0, 0x00},
600 {WCD938X_DIGITAL_SWR_HM_TEST_1, 0x00},
601 {WCD938X_DIGITAL_PAD_CTL_SWR_0, 0x8F},
602 {WCD938X_DIGITAL_PAD_CTL_SWR_1, 0x06},
603 {WCD938X_DIGITAL_I2C_CTL, 0x00},
604 {WCD938X_DIGITAL_CDC_TX_TANGGU_SW_MODE, 0x00},
605 {WCD938X_DIGITAL_EFUSE_TEST_CTL_0, 0x00},
606 {WCD938X_DIGITAL_EFUSE_TEST_CTL_1, 0x00},
607 {WCD938X_DIGITAL_EFUSE_T_DATA_0, 0x00},
608 {WCD938X_DIGITAL_EFUSE_T_DATA_1, 0x00},
609 {WCD938X_DIGITAL_PAD_CTL_PDM_RX0, 0xF1},
610 {WCD938X_DIGITAL_PAD_CTL_PDM_RX1, 0xF1},
611 {WCD938X_DIGITAL_PAD_CTL_PDM_TX0, 0xF1},
612 {WCD938X_DIGITAL_PAD_CTL_PDM_TX1, 0xF1},
613 {WCD938X_DIGITAL_PAD_CTL_PDM_TX2, 0xF1},
614 {WCD938X_DIGITAL_PAD_INP_DIS_0, 0x00},
615 {WCD938X_DIGITAL_PAD_INP_DIS_1, 0x00},
616 {WCD938X_DIGITAL_DRIVE_STRENGTH_0, 0x00},
617 {WCD938X_DIGITAL_DRIVE_STRENGTH_1, 0x00},
618 {WCD938X_DIGITAL_DRIVE_STRENGTH_2, 0x00},
619 {WCD938X_DIGITAL_RX_DATA_EDGE_CTL, 0x1F},
620 {WCD938X_DIGITAL_TX_DATA_EDGE_CTL, 0x80},
621 {WCD938X_DIGITAL_GPIO_MODE, 0x00},
622 {WCD938X_DIGITAL_PIN_CTL_OE, 0x00},
623 {WCD938X_DIGITAL_PIN_CTL_DATA_0, 0x00},
624 {WCD938X_DIGITAL_PIN_CTL_DATA_1, 0x00},
625 {WCD938X_DIGITAL_PIN_STATUS_0, 0x00},
626 {WCD938X_DIGITAL_PIN_STATUS_1, 0x00},
627 {WCD938X_DIGITAL_DIG_DEBUG_CTL, 0x00},
628 {WCD938X_DIGITAL_DIG_DEBUG_EN, 0x00},
629 {WCD938X_DIGITAL_ANA_CSR_DBG_ADD, 0x00},
630 {WCD938X_DIGITAL_ANA_CSR_DBG_CTL, 0x48},
631 {WCD938X_DIGITAL_SSP_DBG, 0x00},
632 {WCD938X_DIGITAL_MODE_STATUS_0, 0x00},
633 {WCD938X_DIGITAL_MODE_STATUS_1, 0x00},
634 {WCD938X_DIGITAL_SPARE_0, 0x00},
635 {WCD938X_DIGITAL_SPARE_1, 0x00},
636 {WCD938X_DIGITAL_SPARE_2, 0x00},
637 {WCD938X_DIGITAL_EFUSE_REG_0, 0x00},
638 {WCD938X_DIGITAL_EFUSE_REG_1, 0xFF},
639 {WCD938X_DIGITAL_EFUSE_REG_2, 0xFF},
640 {WCD938X_DIGITAL_EFUSE_REG_3, 0xFF},
641 {WCD938X_DIGITAL_EFUSE_REG_4, 0xFF},
642 {WCD938X_DIGITAL_EFUSE_REG_5, 0xFF},
643 {WCD938X_DIGITAL_EFUSE_REG_6, 0xFF},
644 {WCD938X_DIGITAL_EFUSE_REG_7, 0xFF},
645 {WCD938X_DIGITAL_EFUSE_REG_8, 0xFF},
646 {WCD938X_DIGITAL_EFUSE_REG_9, 0xFF},
647 {WCD938X_DIGITAL_EFUSE_REG_10, 0xFF},
648 {WCD938X_DIGITAL_EFUSE_REG_11, 0xFF},
649 {WCD938X_DIGITAL_EFUSE_REG_12, 0xFF},
650 {WCD938X_DIGITAL_EFUSE_REG_13, 0xFF},
651 {WCD938X_DIGITAL_EFUSE_REG_14, 0xFF},
652 {WCD938X_DIGITAL_EFUSE_REG_15, 0xFF},
653 {WCD938X_DIGITAL_EFUSE_REG_16, 0xFF},
654 {WCD938X_DIGITAL_EFUSE_REG_17, 0xFF},
655 {WCD938X_DIGITAL_EFUSE_REG_18, 0xFF},
656 {WCD938X_DIGITAL_EFUSE_REG_19, 0xFF},
657 {WCD938X_DIGITAL_EFUSE_REG_20, 0x0E},
658 {WCD938X_DIGITAL_EFUSE_REG_21, 0x00},
659 {WCD938X_DIGITAL_EFUSE_REG_22, 0x00},
660 {WCD938X_DIGITAL_EFUSE_REG_23, 0xF8},
661 {WCD938X_DIGITAL_EFUSE_REG_24, 0x16},
662 {WCD938X_DIGITAL_EFUSE_REG_25, 0x00},
663 {WCD938X_DIGITAL_EFUSE_REG_26, 0x00},
664 {WCD938X_DIGITAL_EFUSE_REG_27, 0x00},
665 {WCD938X_DIGITAL_EFUSE_REG_28, 0x00},
666 {WCD938X_DIGITAL_EFUSE_REG_29, 0x00},
667 {WCD938X_DIGITAL_EFUSE_REG_30, 0x00},
668 {WCD938X_DIGITAL_EFUSE_REG_31, 0x00},
669 {WCD938X_DIGITAL_TX_REQ_FB_CTL_0, 0x88},
670 {WCD938X_DIGITAL_TX_REQ_FB_CTL_1, 0x88},
671 {WCD938X_DIGITAL_TX_REQ_FB_CTL_2, 0x88},
672 {WCD938X_DIGITAL_TX_REQ_FB_CTL_3, 0x88},
673 {WCD938X_DIGITAL_TX_REQ_FB_CTL_4, 0x88},
674 {WCD938X_DIGITAL_DEM_BYPASS_DATA0, 0x55},
675 {WCD938X_DIGITAL_DEM_BYPASS_DATA1, 0x55},
676 {WCD938X_DIGITAL_DEM_BYPASS_DATA2, 0x55},
677 {WCD938X_DIGITAL_DEM_BYPASS_DATA3, 0x01},
678};
679
680static bool wcd938x_rdwr_register(struct device *dev, unsigned int reg)
681{
682 switch (reg) {
683 case WCD938X_ANA_PAGE_REGISTER:
684 case WCD938X_ANA_BIAS:
685 case WCD938X_ANA_RX_SUPPLIES:
686 case WCD938X_ANA_HPH:
687 case WCD938X_ANA_EAR:
688 case WCD938X_ANA_EAR_COMPANDER_CTL:
689 case WCD938X_ANA_TX_CH1:
690 case WCD938X_ANA_TX_CH2:
691 case WCD938X_ANA_TX_CH3:
692 case WCD938X_ANA_TX_CH4:
693 case WCD938X_ANA_MICB1_MICB2_DSP_EN_LOGIC:
694 case WCD938X_ANA_MICB3_DSP_EN_LOGIC:
695 case WCD938X_ANA_MBHC_MECH:
696 case WCD938X_ANA_MBHC_ELECT:
697 case WCD938X_ANA_MBHC_ZDET:
698 case WCD938X_ANA_MBHC_BTN0:
699 case WCD938X_ANA_MBHC_BTN1:
700 case WCD938X_ANA_MBHC_BTN2:
701 case WCD938X_ANA_MBHC_BTN3:
702 case WCD938X_ANA_MBHC_BTN4:
703 case WCD938X_ANA_MBHC_BTN5:
704 case WCD938X_ANA_MBHC_BTN6:
705 case WCD938X_ANA_MBHC_BTN7:
706 case WCD938X_ANA_MICB1:
707 case WCD938X_ANA_MICB2:
708 case WCD938X_ANA_MICB2_RAMP:
709 case WCD938X_ANA_MICB3:
710 case WCD938X_ANA_MICB4:
711 case WCD938X_BIAS_CTL:
712 case WCD938X_BIAS_VBG_FINE_ADJ:
713 case WCD938X_LDOL_VDDCX_ADJUST:
714 case WCD938X_LDOL_DISABLE_LDOL:
715 case WCD938X_MBHC_CTL_CLK:
716 case WCD938X_MBHC_CTL_ANA:
717 case WCD938X_MBHC_CTL_SPARE_1:
718 case WCD938X_MBHC_CTL_SPARE_2:
719 case WCD938X_MBHC_CTL_BCS:
720 case WCD938X_MBHC_TEST_CTL:
721 case WCD938X_LDOH_MODE:
722 case WCD938X_LDOH_BIAS:
723 case WCD938X_LDOH_STB_LOADS:
724 case WCD938X_LDOH_SLOWRAMP:
725 case WCD938X_MICB1_TEST_CTL_1:
726 case WCD938X_MICB1_TEST_CTL_2:
727 case WCD938X_MICB1_TEST_CTL_3:
728 case WCD938X_MICB2_TEST_CTL_1:
729 case WCD938X_MICB2_TEST_CTL_2:
730 case WCD938X_MICB2_TEST_CTL_3:
731 case WCD938X_MICB3_TEST_CTL_1:
732 case WCD938X_MICB3_TEST_CTL_2:
733 case WCD938X_MICB3_TEST_CTL_3:
734 case WCD938X_MICB4_TEST_CTL_1:
735 case WCD938X_MICB4_TEST_CTL_2:
736 case WCD938X_MICB4_TEST_CTL_3:
737 case WCD938X_TX_COM_ADC_VCM:
738 case WCD938X_TX_COM_BIAS_ATEST:
739 case WCD938X_TX_COM_SPARE1:
740 case WCD938X_TX_COM_SPARE2:
741 case WCD938X_TX_COM_TXFE_DIV_CTL:
742 case WCD938X_TX_COM_TXFE_DIV_START:
743 case WCD938X_TX_COM_SPARE3:
744 case WCD938X_TX_COM_SPARE4:
745 case WCD938X_TX_1_2_TEST_EN:
746 case WCD938X_TX_1_2_ADC_IB:
747 case WCD938X_TX_1_2_ATEST_REFCTL:
748 case WCD938X_TX_1_2_TEST_CTL:
749 case WCD938X_TX_1_2_TEST_BLK_EN1:
750 case WCD938X_TX_1_2_TXFE1_CLKDIV:
751 case WCD938X_TX_3_4_TEST_EN:
752 case WCD938X_TX_3_4_ADC_IB:
753 case WCD938X_TX_3_4_ATEST_REFCTL:
754 case WCD938X_TX_3_4_TEST_CTL:
755 case WCD938X_TX_3_4_TEST_BLK_EN3:
756 case WCD938X_TX_3_4_TXFE3_CLKDIV:
757 case WCD938X_TX_3_4_TEST_BLK_EN2:
758 case WCD938X_TX_3_4_TXFE2_CLKDIV:
759 case WCD938X_TX_3_4_SPARE1:
760 case WCD938X_TX_3_4_TEST_BLK_EN4:
761 case WCD938X_TX_3_4_TXFE4_CLKDIV:
762 case WCD938X_TX_3_4_SPARE2:
763 case WCD938X_CLASSH_MODE_1:
764 case WCD938X_CLASSH_MODE_2:
765 case WCD938X_CLASSH_MODE_3:
766 case WCD938X_CLASSH_CTRL_VCL_1:
767 case WCD938X_CLASSH_CTRL_VCL_2:
768 case WCD938X_CLASSH_CTRL_CCL_1:
769 case WCD938X_CLASSH_CTRL_CCL_2:
770 case WCD938X_CLASSH_CTRL_CCL_3:
771 case WCD938X_CLASSH_CTRL_CCL_4:
772 case WCD938X_CLASSH_CTRL_CCL_5:
773 case WCD938X_CLASSH_BUCK_TMUX_A_D:
774 case WCD938X_CLASSH_BUCK_SW_DRV_CNTL:
775 case WCD938X_CLASSH_SPARE:
776 case WCD938X_FLYBACK_EN:
777 case WCD938X_FLYBACK_VNEG_CTRL_1:
778 case WCD938X_FLYBACK_VNEG_CTRL_2:
779 case WCD938X_FLYBACK_VNEG_CTRL_3:
780 case WCD938X_FLYBACK_VNEG_CTRL_4:
781 case WCD938X_FLYBACK_VNEG_CTRL_5:
782 case WCD938X_FLYBACK_VNEG_CTRL_6:
783 case WCD938X_FLYBACK_VNEG_CTRL_7:
784 case WCD938X_FLYBACK_VNEG_CTRL_8:
785 case WCD938X_FLYBACK_VNEG_CTRL_9:
786 case WCD938X_FLYBACK_VNEGDAC_CTRL_1:
787 case WCD938X_FLYBACK_VNEGDAC_CTRL_2:
788 case WCD938X_FLYBACK_VNEGDAC_CTRL_3:
789 case WCD938X_FLYBACK_CTRL_1:
790 case WCD938X_FLYBACK_TEST_CTL:
791 case WCD938X_RX_AUX_SW_CTL:
792 case WCD938X_RX_PA_AUX_IN_CONN:
793 case WCD938X_RX_TIMER_DIV:
794 case WCD938X_RX_OCP_CTL:
795 case WCD938X_RX_OCP_COUNT:
796 case WCD938X_RX_BIAS_EAR_DAC:
797 case WCD938X_RX_BIAS_EAR_AMP:
798 case WCD938X_RX_BIAS_HPH_LDO:
799 case WCD938X_RX_BIAS_HPH_PA:
800 case WCD938X_RX_BIAS_HPH_RDACBUFF_CNP2:
801 case WCD938X_RX_BIAS_HPH_RDAC_LDO:
802 case WCD938X_RX_BIAS_HPH_CNP1:
803 case WCD938X_RX_BIAS_HPH_LOWPOWER:
804 case WCD938X_RX_BIAS_AUX_DAC:
805 case WCD938X_RX_BIAS_AUX_AMP:
806 case WCD938X_RX_BIAS_VNEGDAC_BLEEDER:
807 case WCD938X_RX_BIAS_MISC:
808 case WCD938X_RX_BIAS_BUCK_RST:
809 case WCD938X_RX_BIAS_BUCK_VREF_ERRAMP:
810 case WCD938X_RX_BIAS_FLYB_ERRAMP:
811 case WCD938X_RX_BIAS_FLYB_BUFF:
812 case WCD938X_RX_BIAS_FLYB_MID_RST:
813 case WCD938X_HPH_CNP_EN:
814 case WCD938X_HPH_CNP_WG_CTL:
815 case WCD938X_HPH_CNP_WG_TIME:
816 case WCD938X_HPH_OCP_CTL:
817 case WCD938X_HPH_AUTO_CHOP:
818 case WCD938X_HPH_CHOP_CTL:
819 case WCD938X_HPH_PA_CTL1:
820 case WCD938X_HPH_PA_CTL2:
821 case WCD938X_HPH_L_EN:
822 case WCD938X_HPH_L_TEST:
823 case WCD938X_HPH_L_ATEST:
824 case WCD938X_HPH_R_EN:
825 case WCD938X_HPH_R_TEST:
826 case WCD938X_HPH_R_ATEST:
827 case WCD938X_HPH_RDAC_CLK_CTL1:
828 case WCD938X_HPH_RDAC_CLK_CTL2:
829 case WCD938X_HPH_RDAC_LDO_CTL:
830 case WCD938X_HPH_RDAC_CHOP_CLK_LP_CTL:
831 case WCD938X_HPH_REFBUFF_UHQA_CTL:
832 case WCD938X_HPH_REFBUFF_LP_CTL:
833 case WCD938X_HPH_L_DAC_CTL:
834 case WCD938X_HPH_R_DAC_CTL:
835 case WCD938X_HPH_SURGE_HPHLR_SURGE_COMP_SEL:
836 case WCD938X_HPH_SURGE_HPHLR_SURGE_EN:
837 case WCD938X_HPH_SURGE_HPHLR_SURGE_MISC1:
838 case WCD938X_EAR_EAR_EN_REG:
839 case WCD938X_EAR_EAR_PA_CON:
840 case WCD938X_EAR_EAR_SP_CON:
841 case WCD938X_EAR_EAR_DAC_CON:
842 case WCD938X_EAR_EAR_CNP_FSM_CON:
843 case WCD938X_EAR_TEST_CTL:
844 case WCD938X_ANA_NEW_PAGE_REGISTER:
845 case WCD938X_HPH_NEW_ANA_HPH2:
846 case WCD938X_HPH_NEW_ANA_HPH3:
847 case WCD938X_SLEEP_CTL:
848 case WCD938X_SLEEP_WATCHDOG_CTL:
849 case WCD938X_MBHC_NEW_ELECT_REM_CLAMP_CTL:
850 case WCD938X_MBHC_NEW_CTL_1:
851 case WCD938X_MBHC_NEW_CTL_2:
852 case WCD938X_MBHC_NEW_PLUG_DETECT_CTL:
853 case WCD938X_MBHC_NEW_ZDET_ANA_CTL:
854 case WCD938X_MBHC_NEW_ZDET_RAMP_CTL:
855 case WCD938X_TX_NEW_AMIC_MUX_CFG:
856 case WCD938X_AUX_AUXPA:
857 case WCD938X_LDORXTX_MODE:
858 case WCD938X_LDORXTX_CONFIG:
859 case WCD938X_DIE_CRACK_DIE_CRK_DET_EN:
860 case WCD938X_HPH_NEW_INT_RDAC_GAIN_CTL:
861 case WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_L:
862 case WCD938X_HPH_NEW_INT_RDAC_VREF_CTL:
863 case WCD938X_HPH_NEW_INT_RDAC_OVERRIDE_CTL:
864 case WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_R:
865 case WCD938X_HPH_NEW_INT_PA_MISC1:
866 case WCD938X_HPH_NEW_INT_PA_MISC2:
867 case WCD938X_HPH_NEW_INT_PA_RDAC_MISC:
868 case WCD938X_HPH_NEW_INT_HPH_TIMER1:
869 case WCD938X_HPH_NEW_INT_HPH_TIMER2:
870 case WCD938X_HPH_NEW_INT_HPH_TIMER3:
871 case WCD938X_HPH_NEW_INT_HPH_TIMER4:
872 case WCD938X_HPH_NEW_INT_PA_RDAC_MISC2:
873 case WCD938X_HPH_NEW_INT_PA_RDAC_MISC3:
874 case WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_L_NEW:
875 case WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_R_NEW:
876 case WCD938X_RX_NEW_INT_HPH_RDAC_BIAS_LOHIFI:
877 case WCD938X_RX_NEW_INT_HPH_RDAC_BIAS_ULP:
878 case WCD938X_RX_NEW_INT_HPH_RDAC_LDO_LP:
879 case WCD938X_MBHC_NEW_INT_MOISTURE_DET_DC_CTRL:
880 case WCD938X_MBHC_NEW_INT_MOISTURE_DET_POLLING_CTRL:
881 case WCD938X_MBHC_NEW_INT_MECH_DET_CURRENT:
882 case WCD938X_MBHC_NEW_INT_SPARE_2:
883 case WCD938X_EAR_INT_NEW_EAR_CHOPPER_CON:
884 case WCD938X_EAR_INT_NEW_CNP_VCM_CON1:
885 case WCD938X_EAR_INT_NEW_CNP_VCM_CON2:
886 case WCD938X_EAR_INT_NEW_EAR_DYNAMIC_BIAS:
887 case WCD938X_AUX_INT_EN_REG:
888 case WCD938X_AUX_INT_PA_CTRL:
889 case WCD938X_AUX_INT_SP_CTRL:
890 case WCD938X_AUX_INT_DAC_CTRL:
891 case WCD938X_AUX_INT_CLK_CTRL:
892 case WCD938X_AUX_INT_TEST_CTRL:
893 case WCD938X_AUX_INT_MISC:
894 case WCD938X_LDORXTX_INT_BIAS:
895 case WCD938X_LDORXTX_INT_STB_LOADS_DTEST:
896 case WCD938X_LDORXTX_INT_TEST0:
897 case WCD938X_LDORXTX_INT_STARTUP_TIMER:
898 case WCD938X_LDORXTX_INT_TEST1:
899 case WCD938X_SLEEP_INT_WATCHDOG_CTL_1:
900 case WCD938X_SLEEP_INT_WATCHDOG_CTL_2:
901 case WCD938X_DIE_CRACK_INT_DIE_CRK_DET_INT1:
902 case WCD938X_DIE_CRACK_INT_DIE_CRK_DET_INT2:
903 case WCD938X_TX_COM_NEW_INT_TXFE_DIVSTOP_L2:
904 case WCD938X_TX_COM_NEW_INT_TXFE_DIVSTOP_L1:
905 case WCD938X_TX_COM_NEW_INT_TXFE_DIVSTOP_L0:
906 case WCD938X_TX_COM_NEW_INT_TXFE_DIVSTOP_ULP1P2M:
907 case WCD938X_TX_COM_NEW_INT_TXFE_DIVSTOP_ULP0P6M:
908 case WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG1_L2L1:
909 case WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG1_L0:
910 case WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG1_ULP:
911 case WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG2MAIN_L2L1:
912 case WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG2MAIN_L0:
913 case WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG2MAIN_ULP:
914 case WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG2CASC_L2L1L0:
915 case WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG2CASC_ULP:
916 case WCD938X_TX_COM_NEW_INT_TXADC_SCBIAS_L2L1:
917 case WCD938X_TX_COM_NEW_INT_TXADC_SCBIAS_L0ULP:
918 case WCD938X_TX_COM_NEW_INT_TXADC_INT_L2:
919 case WCD938X_TX_COM_NEW_INT_TXADC_INT_L1:
920 case WCD938X_TX_COM_NEW_INT_TXADC_INT_L0:
921 case WCD938X_TX_COM_NEW_INT_TXADC_INT_ULP:
922 case WCD938X_DIGITAL_PAGE_REGISTER:
923 case WCD938X_DIGITAL_SWR_TX_CLK_RATE:
924 case WCD938X_DIGITAL_CDC_RST_CTL:
925 case WCD938X_DIGITAL_TOP_CLK_CFG:
926 case WCD938X_DIGITAL_CDC_ANA_CLK_CTL:
927 case WCD938X_DIGITAL_CDC_DIG_CLK_CTL:
928 case WCD938X_DIGITAL_SWR_RST_EN:
929 case WCD938X_DIGITAL_CDC_PATH_MODE:
930 case WCD938X_DIGITAL_CDC_RX_RST:
931 case WCD938X_DIGITAL_CDC_RX0_CTL:
932 case WCD938X_DIGITAL_CDC_RX1_CTL:
933 case WCD938X_DIGITAL_CDC_RX2_CTL:
934 case WCD938X_DIGITAL_CDC_TX_ANA_MODE_0_1:
935 case WCD938X_DIGITAL_CDC_TX_ANA_MODE_2_3:
936 case WCD938X_DIGITAL_CDC_COMP_CTL_0:
937 case WCD938X_DIGITAL_CDC_ANA_TX_CLK_CTL:
938 case WCD938X_DIGITAL_CDC_HPH_DSM_A1_0:
939 case WCD938X_DIGITAL_CDC_HPH_DSM_A1_1:
940 case WCD938X_DIGITAL_CDC_HPH_DSM_A2_0:
941 case WCD938X_DIGITAL_CDC_HPH_DSM_A2_1:
942 case WCD938X_DIGITAL_CDC_HPH_DSM_A3_0:
943 case WCD938X_DIGITAL_CDC_HPH_DSM_A3_1:
944 case WCD938X_DIGITAL_CDC_HPH_DSM_A4_0:
945 case WCD938X_DIGITAL_CDC_HPH_DSM_A4_1:
946 case WCD938X_DIGITAL_CDC_HPH_DSM_A5_0:
947 case WCD938X_DIGITAL_CDC_HPH_DSM_A5_1:
948 case WCD938X_DIGITAL_CDC_HPH_DSM_A6_0:
949 case WCD938X_DIGITAL_CDC_HPH_DSM_A7_0:
950 case WCD938X_DIGITAL_CDC_HPH_DSM_C_0:
951 case WCD938X_DIGITAL_CDC_HPH_DSM_C_1:
952 case WCD938X_DIGITAL_CDC_HPH_DSM_C_2:
953 case WCD938X_DIGITAL_CDC_HPH_DSM_C_3:
954 case WCD938X_DIGITAL_CDC_HPH_DSM_R1:
955 case WCD938X_DIGITAL_CDC_HPH_DSM_R2:
956 case WCD938X_DIGITAL_CDC_HPH_DSM_R3:
957 case WCD938X_DIGITAL_CDC_HPH_DSM_R4:
958 case WCD938X_DIGITAL_CDC_HPH_DSM_R5:
959 case WCD938X_DIGITAL_CDC_HPH_DSM_R6:
960 case WCD938X_DIGITAL_CDC_HPH_DSM_R7:
961 case WCD938X_DIGITAL_CDC_AUX_DSM_A1_0:
962 case WCD938X_DIGITAL_CDC_AUX_DSM_A1_1:
963 case WCD938X_DIGITAL_CDC_AUX_DSM_A2_0:
964 case WCD938X_DIGITAL_CDC_AUX_DSM_A2_1:
965 case WCD938X_DIGITAL_CDC_AUX_DSM_A3_0:
966 case WCD938X_DIGITAL_CDC_AUX_DSM_A3_1:
967 case WCD938X_DIGITAL_CDC_AUX_DSM_A4_0:
968 case WCD938X_DIGITAL_CDC_AUX_DSM_A4_1:
969 case WCD938X_DIGITAL_CDC_AUX_DSM_A5_0:
970 case WCD938X_DIGITAL_CDC_AUX_DSM_A5_1:
971 case WCD938X_DIGITAL_CDC_AUX_DSM_A6_0:
972 case WCD938X_DIGITAL_CDC_AUX_DSM_A7_0:
973 case WCD938X_DIGITAL_CDC_AUX_DSM_C_0:
974 case WCD938X_DIGITAL_CDC_AUX_DSM_C_1:
975 case WCD938X_DIGITAL_CDC_AUX_DSM_C_2:
976 case WCD938X_DIGITAL_CDC_AUX_DSM_C_3:
977 case WCD938X_DIGITAL_CDC_AUX_DSM_R1:
978 case WCD938X_DIGITAL_CDC_AUX_DSM_R2:
979 case WCD938X_DIGITAL_CDC_AUX_DSM_R3:
980 case WCD938X_DIGITAL_CDC_AUX_DSM_R4:
981 case WCD938X_DIGITAL_CDC_AUX_DSM_R5:
982 case WCD938X_DIGITAL_CDC_AUX_DSM_R6:
983 case WCD938X_DIGITAL_CDC_AUX_DSM_R7:
984 case WCD938X_DIGITAL_CDC_HPH_GAIN_RX_0:
985 case WCD938X_DIGITAL_CDC_HPH_GAIN_RX_1:
986 case WCD938X_DIGITAL_CDC_HPH_GAIN_DSD_0:
987 case WCD938X_DIGITAL_CDC_HPH_GAIN_DSD_1:
988 case WCD938X_DIGITAL_CDC_HPH_GAIN_DSD_2:
989 case WCD938X_DIGITAL_CDC_AUX_GAIN_DSD_0:
990 case WCD938X_DIGITAL_CDC_AUX_GAIN_DSD_1:
991 case WCD938X_DIGITAL_CDC_AUX_GAIN_DSD_2:
992 case WCD938X_DIGITAL_CDC_HPH_GAIN_CTL:
993 case WCD938X_DIGITAL_CDC_AUX_GAIN_CTL:
994 case WCD938X_DIGITAL_CDC_EAR_PATH_CTL:
995 case WCD938X_DIGITAL_CDC_SWR_CLH:
996 case WCD938X_DIGITAL_SWR_CLH_BYP:
997 case WCD938X_DIGITAL_CDC_TX0_CTL:
998 case WCD938X_DIGITAL_CDC_TX1_CTL:
999 case WCD938X_DIGITAL_CDC_TX2_CTL:
1000 case WCD938X_DIGITAL_CDC_TX_RST:
1001 case WCD938X_DIGITAL_CDC_REQ_CTL:
1002 case WCD938X_DIGITAL_CDC_RST:
1003 case WCD938X_DIGITAL_CDC_AMIC_CTL:
1004 case WCD938X_DIGITAL_CDC_DMIC_CTL:
1005 case WCD938X_DIGITAL_CDC_DMIC1_CTL:
1006 case WCD938X_DIGITAL_CDC_DMIC2_CTL:
1007 case WCD938X_DIGITAL_CDC_DMIC3_CTL:
1008 case WCD938X_DIGITAL_CDC_DMIC4_CTL:
1009 case WCD938X_DIGITAL_EFUSE_PRG_CTL:
1010 case WCD938X_DIGITAL_EFUSE_CTL:
1011 case WCD938X_DIGITAL_CDC_DMIC_RATE_1_2:
1012 case WCD938X_DIGITAL_CDC_DMIC_RATE_3_4:
1013 case WCD938X_DIGITAL_PDM_WD_CTL0:
1014 case WCD938X_DIGITAL_PDM_WD_CTL1:
1015 case WCD938X_DIGITAL_PDM_WD_CTL2:
1016 case WCD938X_DIGITAL_INTR_MODE:
1017 case WCD938X_DIGITAL_INTR_MASK_0:
1018 case WCD938X_DIGITAL_INTR_MASK_1:
1019 case WCD938X_DIGITAL_INTR_MASK_2:
1020 case WCD938X_DIGITAL_INTR_CLEAR_0:
1021 case WCD938X_DIGITAL_INTR_CLEAR_1:
1022 case WCD938X_DIGITAL_INTR_CLEAR_2:
1023 case WCD938X_DIGITAL_INTR_LEVEL_0:
1024 case WCD938X_DIGITAL_INTR_LEVEL_1:
1025 case WCD938X_DIGITAL_INTR_LEVEL_2:
1026 case WCD938X_DIGITAL_INTR_SET_0:
1027 case WCD938X_DIGITAL_INTR_SET_1:
1028 case WCD938X_DIGITAL_INTR_SET_2:
1029 case WCD938X_DIGITAL_INTR_TEST_0:
1030 case WCD938X_DIGITAL_INTR_TEST_1:
1031 case WCD938X_DIGITAL_INTR_TEST_2:
1032 case WCD938X_DIGITAL_TX_MODE_DBG_EN:
1033 case WCD938X_DIGITAL_TX_MODE_DBG_0_1:
1034 case WCD938X_DIGITAL_TX_MODE_DBG_2_3:
1035 case WCD938X_DIGITAL_LB_IN_SEL_CTL:
1036 case WCD938X_DIGITAL_LOOP_BACK_MODE:
1037 case WCD938X_DIGITAL_SWR_DAC_TEST:
1038 case WCD938X_DIGITAL_SWR_HM_TEST_RX_0:
1039 case WCD938X_DIGITAL_SWR_HM_TEST_TX_0:
1040 case WCD938X_DIGITAL_SWR_HM_TEST_RX_1:
1041 case WCD938X_DIGITAL_SWR_HM_TEST_TX_1:
1042 case WCD938X_DIGITAL_SWR_HM_TEST_TX_2:
1043 case WCD938X_DIGITAL_PAD_CTL_SWR_0:
1044 case WCD938X_DIGITAL_PAD_CTL_SWR_1:
1045 case WCD938X_DIGITAL_I2C_CTL:
1046 case WCD938X_DIGITAL_CDC_TX_TANGGU_SW_MODE:
1047 case WCD938X_DIGITAL_EFUSE_TEST_CTL_0:
1048 case WCD938X_DIGITAL_EFUSE_TEST_CTL_1:
1049 case WCD938X_DIGITAL_PAD_CTL_PDM_RX0:
1050 case WCD938X_DIGITAL_PAD_CTL_PDM_RX1:
1051 case WCD938X_DIGITAL_PAD_CTL_PDM_TX0:
1052 case WCD938X_DIGITAL_PAD_CTL_PDM_TX1:
1053 case WCD938X_DIGITAL_PAD_CTL_PDM_TX2:
1054 case WCD938X_DIGITAL_PAD_INP_DIS_0:
1055 case WCD938X_DIGITAL_PAD_INP_DIS_1:
1056 case WCD938X_DIGITAL_DRIVE_STRENGTH_0:
1057 case WCD938X_DIGITAL_DRIVE_STRENGTH_1:
1058 case WCD938X_DIGITAL_DRIVE_STRENGTH_2:
1059 case WCD938X_DIGITAL_RX_DATA_EDGE_CTL:
1060 case WCD938X_DIGITAL_TX_DATA_EDGE_CTL:
1061 case WCD938X_DIGITAL_GPIO_MODE:
1062 case WCD938X_DIGITAL_PIN_CTL_OE:
1063 case WCD938X_DIGITAL_PIN_CTL_DATA_0:
1064 case WCD938X_DIGITAL_PIN_CTL_DATA_1:
1065 case WCD938X_DIGITAL_DIG_DEBUG_CTL:
1066 case WCD938X_DIGITAL_DIG_DEBUG_EN:
1067 case WCD938X_DIGITAL_ANA_CSR_DBG_ADD:
1068 case WCD938X_DIGITAL_ANA_CSR_DBG_CTL:
1069 case WCD938X_DIGITAL_SSP_DBG:
1070 case WCD938X_DIGITAL_SPARE_0:
1071 case WCD938X_DIGITAL_SPARE_1:
1072 case WCD938X_DIGITAL_SPARE_2:
1073 case WCD938X_DIGITAL_TX_REQ_FB_CTL_0:
1074 case WCD938X_DIGITAL_TX_REQ_FB_CTL_1:
1075 case WCD938X_DIGITAL_TX_REQ_FB_CTL_2:
1076 case WCD938X_DIGITAL_TX_REQ_FB_CTL_3:
1077 case WCD938X_DIGITAL_TX_REQ_FB_CTL_4:
1078 case WCD938X_DIGITAL_DEM_BYPASS_DATA0:
1079 case WCD938X_DIGITAL_DEM_BYPASS_DATA1:
1080 case WCD938X_DIGITAL_DEM_BYPASS_DATA2:
1081 case WCD938X_DIGITAL_DEM_BYPASS_DATA3:
1082 return true;
1083 }
1084
1085 return false;
1086}
1087
1088static bool wcd938x_readonly_register(struct device *dev, unsigned int reg)
1089{
1090 switch (reg) {
1091 case WCD938X_ANA_MBHC_RESULT_1:
1092 case WCD938X_ANA_MBHC_RESULT_2:
1093 case WCD938X_ANA_MBHC_RESULT_3:
1094 case WCD938X_MBHC_MOISTURE_DET_FSM_STATUS:
1095 case WCD938X_TX_1_2_SAR2_ERR:
1096 case WCD938X_TX_1_2_SAR1_ERR:
1097 case WCD938X_TX_3_4_SAR4_ERR:
1098 case WCD938X_TX_3_4_SAR3_ERR:
1099 case WCD938X_HPH_L_STATUS:
1100 case WCD938X_HPH_R_STATUS:
1101 case WCD938X_HPH_SURGE_HPHLR_SURGE_STATUS:
1102 case WCD938X_EAR_STATUS_REG_1:
1103 case WCD938X_EAR_STATUS_REG_2:
1104 case WCD938X_MBHC_NEW_FSM_STATUS:
1105 case WCD938X_MBHC_NEW_ADC_RESULT:
1106 case WCD938X_DIE_CRACK_DIE_CRK_DET_OUT:
1107 case WCD938X_AUX_INT_STATUS_REG:
1108 case WCD938X_LDORXTX_INT_STATUS:
1109 case WCD938X_DIGITAL_CHIP_ID0:
1110 case WCD938X_DIGITAL_CHIP_ID1:
1111 case WCD938X_DIGITAL_CHIP_ID2:
1112 case WCD938X_DIGITAL_CHIP_ID3:
1113 case WCD938X_DIGITAL_INTR_STATUS_0:
1114 case WCD938X_DIGITAL_INTR_STATUS_1:
1115 case WCD938X_DIGITAL_INTR_STATUS_2:
1116 case WCD938X_DIGITAL_SWR_HM_TEST_0:
1117 case WCD938X_DIGITAL_SWR_HM_TEST_1:
1118 case WCD938X_DIGITAL_EFUSE_T_DATA_0:
1119 case WCD938X_DIGITAL_EFUSE_T_DATA_1:
1120 case WCD938X_DIGITAL_PIN_STATUS_0:
1121 case WCD938X_DIGITAL_PIN_STATUS_1:
1122 case WCD938X_DIGITAL_MODE_STATUS_0:
1123 case WCD938X_DIGITAL_MODE_STATUS_1:
1124 case WCD938X_DIGITAL_EFUSE_REG_0:
1125 case WCD938X_DIGITAL_EFUSE_REG_1:
1126 case WCD938X_DIGITAL_EFUSE_REG_2:
1127 case WCD938X_DIGITAL_EFUSE_REG_3:
1128 case WCD938X_DIGITAL_EFUSE_REG_4:
1129 case WCD938X_DIGITAL_EFUSE_REG_5:
1130 case WCD938X_DIGITAL_EFUSE_REG_6:
1131 case WCD938X_DIGITAL_EFUSE_REG_7:
1132 case WCD938X_DIGITAL_EFUSE_REG_8:
1133 case WCD938X_DIGITAL_EFUSE_REG_9:
1134 case WCD938X_DIGITAL_EFUSE_REG_10:
1135 case WCD938X_DIGITAL_EFUSE_REG_11:
1136 case WCD938X_DIGITAL_EFUSE_REG_12:
1137 case WCD938X_DIGITAL_EFUSE_REG_13:
1138 case WCD938X_DIGITAL_EFUSE_REG_14:
1139 case WCD938X_DIGITAL_EFUSE_REG_15:
1140 case WCD938X_DIGITAL_EFUSE_REG_16:
1141 case WCD938X_DIGITAL_EFUSE_REG_17:
1142 case WCD938X_DIGITAL_EFUSE_REG_18:
1143 case WCD938X_DIGITAL_EFUSE_REG_19:
1144 case WCD938X_DIGITAL_EFUSE_REG_20:
1145 case WCD938X_DIGITAL_EFUSE_REG_21:
1146 case WCD938X_DIGITAL_EFUSE_REG_22:
1147 case WCD938X_DIGITAL_EFUSE_REG_23:
1148 case WCD938X_DIGITAL_EFUSE_REG_24:
1149 case WCD938X_DIGITAL_EFUSE_REG_25:
1150 case WCD938X_DIGITAL_EFUSE_REG_26:
1151 case WCD938X_DIGITAL_EFUSE_REG_27:
1152 case WCD938X_DIGITAL_EFUSE_REG_28:
1153 case WCD938X_DIGITAL_EFUSE_REG_29:
1154 case WCD938X_DIGITAL_EFUSE_REG_30:
1155 case WCD938X_DIGITAL_EFUSE_REG_31:
1156 return true;
1157 }
1158 return false;
1159}
1160
1161static bool wcd938x_readable_register(struct device *dev, unsigned int reg)
1162{
1163 bool ret;
1164
1165 ret = wcd938x_readonly_register(dev, reg);
1166 if (!ret)
1167 return wcd938x_rdwr_register(dev, reg);
1168
1169 return ret;
1170}
1171
1172static bool wcd938x_writeable_register(struct device *dev, unsigned int reg)
1173{
1174 return wcd938x_rdwr_register(dev, reg);
1175}
1176
1177static bool wcd938x_volatile_register(struct device *dev, unsigned int reg)
1178{
1179 if (reg <= WCD938X_BASE_ADDRESS)
1180 return 0;
1181
1182 if (reg == WCD938X_DIGITAL_SWR_TX_CLK_RATE)
1183 return true;
1184
1185 if (wcd938x_readonly_register(dev, reg))
1186 return true;
1187
1188 return false;
1189}
1190
1191struct regmap_config wcd938x_regmap_config = {
1192 .name = "wcd938x_csr",
1193 .reg_bits = 32,
1194 .val_bits = 8,
1195 .cache_type = REGCACHE_RBTREE,
1196 .reg_defaults = wcd938x_defaults,
1197 .num_reg_defaults = ARRAY_SIZE(wcd938x_defaults),
1198 .max_register = WCD938X_MAX_REGISTER,
1199 .readable_reg = wcd938x_readable_register,
1200 .writeable_reg = wcd938x_writeable_register,
1201 .volatile_reg = wcd938x_volatile_register,
1202 .can_multi_write = true,
1203};
1204EXPORT_SYMBOL_GPL(wcd938x_regmap_config);
1205
1206static const struct regmap_irq wcd938x_irqs[WCD938X_NUM_IRQS] = {
1207 REGMAP_IRQ_REG(WCD938X_IRQ_MBHC_BUTTON_PRESS_DET, 0, 0x01),
1208 REGMAP_IRQ_REG(WCD938X_IRQ_MBHC_BUTTON_RELEASE_DET, 0, 0x02),
1209 REGMAP_IRQ_REG(WCD938X_IRQ_MBHC_ELECT_INS_REM_DET, 0, 0x04),
1210 REGMAP_IRQ_REG(WCD938X_IRQ_MBHC_ELECT_INS_REM_LEG_DET, 0, 0x08),
1211 REGMAP_IRQ_REG(WCD938X_IRQ_MBHC_SW_DET, 0, 0x10),
1212 REGMAP_IRQ_REG(WCD938X_IRQ_HPHR_OCP_INT, 0, 0x20),
1213 REGMAP_IRQ_REG(WCD938X_IRQ_HPHR_CNP_INT, 0, 0x40),
1214 REGMAP_IRQ_REG(WCD938X_IRQ_HPHL_OCP_INT, 0, 0x80),
1215 REGMAP_IRQ_REG(WCD938X_IRQ_HPHL_CNP_INT, 1, 0x01),
1216 REGMAP_IRQ_REG(WCD938X_IRQ_EAR_CNP_INT, 1, 0x02),
1217 REGMAP_IRQ_REG(WCD938X_IRQ_EAR_SCD_INT, 1, 0x04),
1218 REGMAP_IRQ_REG(WCD938X_IRQ_AUX_CNP_INT, 1, 0x08),
1219 REGMAP_IRQ_REG(WCD938X_IRQ_AUX_SCD_INT, 1, 0x10),
1220 REGMAP_IRQ_REG(WCD938X_IRQ_HPHL_PDM_WD_INT, 1, 0x20),
1221 REGMAP_IRQ_REG(WCD938X_IRQ_HPHR_PDM_WD_INT, 1, 0x40),
1222 REGMAP_IRQ_REG(WCD938X_IRQ_AUX_PDM_WD_INT, 1, 0x80),
1223 REGMAP_IRQ_REG(WCD938X_IRQ_LDORT_SCD_INT, 2, 0x01),
1224 REGMAP_IRQ_REG(WCD938X_IRQ_MBHC_MOISTURE_INT, 2, 0x02),
1225 REGMAP_IRQ_REG(WCD938X_IRQ_HPHL_SURGE_DET_INT, 2, 0x04),
1226 REGMAP_IRQ_REG(WCD938X_IRQ_HPHR_SURGE_DET_INT, 2, 0x08),
1227};
1228
1229static struct regmap_irq_chip wcd938x_regmap_irq_chip = {
1230 .name = "wcd938x",
1231 .irqs = wcd938x_irqs,
1232 .num_irqs = ARRAY_SIZE(wcd938x_irqs),
1233 .num_regs = 3,
1234 .status_base = WCD938X_DIGITAL_INTR_STATUS_0,
1235 .mask_base = WCD938X_DIGITAL_INTR_MASK_0,
1236 .type_base = WCD938X_DIGITAL_INTR_LEVEL_0,
1237 .ack_base = WCD938X_DIGITAL_INTR_CLEAR_0,
1238 .use_ack = 1,
1239 .runtime_pm = true,
1240 .irq_drv_data = NULL,
1241};
1242
1243static int wcd938x_io_init(struct wcd938x_priv *wcd938x)
1244{
1245 struct regmap *rm = wcd938x->regmap;
1246
1247 regmap_update_bits(rm, WCD938X_SLEEP_CTL, 0x0E, 0x0E);
1248 regmap_update_bits(rm, WCD938X_SLEEP_CTL, 0x80, 0x80);
1249 /* 1 msec delay as per HW requirement */
1250 usleep_range(1000, 1010);
1251 regmap_update_bits(rm, WCD938X_SLEEP_CTL, 0x40, 0x40);
1252 /* 1 msec delay as per HW requirement */
1253 usleep_range(1000, 1010);
1254 regmap_update_bits(rm, WCD938X_LDORXTX_CONFIG, 0x10, 0x00);
1255 regmap_update_bits(rm, WCD938X_BIAS_VBG_FINE_ADJ,
1256 0xF0, 0x80);
1257 regmap_update_bits(rm, WCD938X_ANA_BIAS, 0x80, 0x80);
1258 regmap_update_bits(rm, WCD938X_ANA_BIAS, 0x40, 0x40);
1259 /* 10 msec delay as per HW requirement */
1260 usleep_range(10000, 10010);
1261
1262 regmap_update_bits(rm, WCD938X_ANA_BIAS, 0x40, 0x00);
1263 regmap_update_bits(rm, WCD938X_HPH_NEW_INT_RDAC_GAIN_CTL,
1264 0xF0, 0x00);
1265 regmap_update_bits(rm, WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_L_NEW,
1266 0x1F, 0x15);
1267 regmap_update_bits(rm, WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_R_NEW,
1268 0x1F, 0x15);
1269 regmap_update_bits(rm, WCD938X_HPH_REFBUFF_UHQA_CTL,
1270 0xC0, 0x80);
1271 regmap_update_bits(rm, WCD938X_DIGITAL_CDC_DMIC_CTL,
1272 0x02, 0x02);
1273
1274 regmap_update_bits(rm, WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG2CASC_ULP,
1275 0xFF, 0x14);
1276 regmap_update_bits(rm, WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG2MAIN_ULP,
1277 0x1F, 0x08);
1278
1279 regmap_update_bits(rm, WCD938X_DIGITAL_TX_REQ_FB_CTL_0, 0xFF, 0x55);
1280 regmap_update_bits(rm, WCD938X_DIGITAL_TX_REQ_FB_CTL_1, 0xFF, 0x44);
1281 regmap_update_bits(rm, WCD938X_DIGITAL_TX_REQ_FB_CTL_2, 0xFF, 0x11);
1282 regmap_update_bits(rm, WCD938X_DIGITAL_TX_REQ_FB_CTL_3, 0xFF, 0x00);
1283 regmap_update_bits(rm, WCD938X_DIGITAL_TX_REQ_FB_CTL_4, 0xFF, 0x00);
1284
1285 /* Set Noise Filter Resistor value */
1286 regmap_update_bits(rm, WCD938X_MICB1_TEST_CTL_1, 0xE0, 0xE0);
1287 regmap_update_bits(rm, WCD938X_MICB2_TEST_CTL_1, 0xE0, 0xE0);
1288 regmap_update_bits(rm, WCD938X_MICB3_TEST_CTL_1, 0xE0, 0xE0);
1289 regmap_update_bits(rm, WCD938X_MICB4_TEST_CTL_1, 0xE0, 0xE0);
1290
1291 regmap_update_bits(rm, WCD938X_TX_3_4_TEST_BLK_EN2, 0x01, 0x00);
1292 regmap_update_bits(rm, WCD938X_HPH_SURGE_HPHLR_SURGE_EN, 0xC0, 0xC0);
1293
1294 return 0;
1295
1296}
1297
Srinivas Kandagatlae8ba1e02021-06-09 10:09:40 +0100[diff] [blame]1298static int wcd938x_sdw_connect_port(struct wcd938x_sdw_ch_info *ch_info,
1299 struct sdw_port_config *port_config,
1300 u32 mstr_port_num,
1301 u8 enable)
1302{
1303 u8 ch_mask, port_num;
1304
1305 port_num = ch_info->port_num;
1306 ch_mask = ch_info->ch_mask;
1307
1308 port_config->num = port_num;
1309
1310 if (enable)
1311 port_config->ch_mask |= ch_mask;
1312 else
1313 port_config->ch_mask &= ~ch_mask;
1314
1315 return 0;
1316}
1317
1318static int wcd938x_connect_port(struct wcd938x_sdw_priv *wcd, u8 ch_id, u8 enable)
1319{
1320 u8 port_num, mstr_port_num;
1321
1322 port_num = wcd->ch_info[ch_id].port_num;
1323 mstr_port_num = wcd->port_map[port_num - 1];
1324
1325 return wcd938x_sdw_connect_port(&wcd->ch_info[ch_id],
1326 &wcd->port_config[port_num],
1327 mstr_port_num,
1328 enable);
1329}
1330
Srinivas Kandagatla8da9db02021-06-09 10:09:41 +0100[diff] [blame^]1331static int wcd938x_codec_enable_rxclk(struct snd_soc_dapm_widget *w,
1332 struct snd_kcontrol *kcontrol,
1333 int event)
1334{
1335 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
1336
1337 switch (event) {
1338 case SND_SOC_DAPM_PRE_PMU:
1339 snd_soc_component_write_field(component, WCD938X_DIGITAL_CDC_ANA_CLK_CTL,
1340 WCD938X_ANA_RX_CLK_EN_MASK, 1);
1341 snd_soc_component_write_field(component, WCD938X_ANA_RX_SUPPLIES,
1342 WCD938X_RX_BIAS_EN_MASK, 1);
1343 snd_soc_component_write_field(component, WCD938X_DIGITAL_CDC_RX0_CTL,
1344 WCD938X_DEM_DITHER_ENABLE_MASK, 0);
1345 snd_soc_component_write_field(component, WCD938X_DIGITAL_CDC_RX1_CTL,
1346 WCD938X_DEM_DITHER_ENABLE_MASK, 0);
1347 snd_soc_component_write_field(component, WCD938X_DIGITAL_CDC_RX2_CTL,
1348 WCD938X_DEM_DITHER_ENABLE_MASK, 0);
1349 snd_soc_component_write_field(component, WCD938X_DIGITAL_CDC_ANA_CLK_CTL,
1350 WCD938X_ANA_RX_DIV2_CLK_EN_MASK, 1);
1351 snd_soc_component_write_field(component, WCD938X_AUX_AUXPA,
1352 WCD938X_AUXPA_CLK_EN_MASK, 1);
1353 break;
1354 case SND_SOC_DAPM_POST_PMD:
1355 snd_soc_component_write_field(component, WCD938X_ANA_RX_SUPPLIES,
1356 WCD938X_VNEG_EN_MASK, 0);
1357 snd_soc_component_write_field(component, WCD938X_ANA_RX_SUPPLIES,
1358 WCD938X_VPOS_EN_MASK, 0);
1359 snd_soc_component_write_field(component, WCD938X_ANA_RX_SUPPLIES,
1360 WCD938X_RX_BIAS_EN_MASK, 0);
1361 snd_soc_component_write_field(component, WCD938X_DIGITAL_CDC_ANA_CLK_CTL,
1362 WCD938X_ANA_RX_DIV2_CLK_EN_MASK, 0);
1363 snd_soc_component_write_field(component, WCD938X_DIGITAL_CDC_ANA_CLK_CTL,
1364 WCD938X_ANA_RX_CLK_EN_MASK, 0);
1365 break;
1366 }
1367 return 0;
1368}
1369
1370static int wcd938x_codec_hphl_dac_event(struct snd_soc_dapm_widget *w,
1371 struct snd_kcontrol *kcontrol,
1372 int event)
1373{
1374 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
1375 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
1376
1377 switch (event) {
1378 case SND_SOC_DAPM_PRE_PMU:
1379 snd_soc_component_write_field(component,
1380 WCD938X_DIGITAL_CDC_DIG_CLK_CTL,
1381 WCD938X_RXD0_CLK_EN_MASK, 0x01);
1382 snd_soc_component_write_field(component,
1383 WCD938X_DIGITAL_CDC_HPH_GAIN_CTL,
1384 WCD938X_HPHL_RX_EN_MASK, 1);
1385 snd_soc_component_write_field(component,
1386 WCD938X_HPH_RDAC_CLK_CTL1,
1387 WCD938X_CHOP_CLK_EN_MASK, 0);
1388 break;
1389 case SND_SOC_DAPM_POST_PMU:
1390 snd_soc_component_write_field(component,
1391 WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_L,
1392 WCD938X_HPH_RES_DIV_MASK, 0x02);
1393 if (wcd938x->comp1_enable) {
1394 snd_soc_component_write_field(component,
1395 WCD938X_DIGITAL_CDC_COMP_CTL_0,
1396 WCD938X_HPHL_COMP_EN_MASK, 1);
1397 /* 5msec compander delay as per HW requirement */
1398 if (!wcd938x->comp2_enable || (snd_soc_component_read(component,
1399 WCD938X_DIGITAL_CDC_COMP_CTL_0) & 0x01))
1400 usleep_range(5000, 5010);
1401 snd_soc_component_write_field(component, WCD938X_HPH_NEW_INT_HPH_TIMER1,
1402 WCD938X_AUTOCHOP_TIMER_EN, 0);
1403 } else {
1404 snd_soc_component_write_field(component,
1405 WCD938X_DIGITAL_CDC_COMP_CTL_0,
1406 WCD938X_HPHL_COMP_EN_MASK, 0);
1407 snd_soc_component_write_field(component,
1408 WCD938X_HPH_L_EN,
1409 WCD938X_GAIN_SRC_SEL_MASK,
1410 WCD938X_GAIN_SRC_SEL_REGISTER);
1411
1412 }
1413 break;
1414 case SND_SOC_DAPM_POST_PMD:
1415 snd_soc_component_write_field(component,
1416 WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_R,
1417 WCD938X_HPH_RES_DIV_MASK, 0x1);
1418 break;
1419 }
1420
1421 return 0;
1422}
1423
1424static int wcd938x_codec_hphr_dac_event(struct snd_soc_dapm_widget *w,
1425 struct snd_kcontrol *kcontrol,
1426 int event)
1427{
1428 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
1429 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
1430
1431 switch (event) {
1432 case SND_SOC_DAPM_PRE_PMU:
1433 snd_soc_component_write_field(component,
1434 WCD938X_DIGITAL_CDC_DIG_CLK_CTL,
1435 WCD938X_RXD1_CLK_EN_MASK, 1);
1436 snd_soc_component_write_field(component,
1437 WCD938X_DIGITAL_CDC_HPH_GAIN_CTL,
1438 WCD938X_HPHR_RX_EN_MASK, 1);
1439 snd_soc_component_write_field(component,
1440 WCD938X_HPH_RDAC_CLK_CTL1,
1441 WCD938X_CHOP_CLK_EN_MASK, 0);
1442 break;
1443 case SND_SOC_DAPM_POST_PMU:
1444 snd_soc_component_write_field(component,
1445 WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_R,
1446 WCD938X_HPH_RES_DIV_MASK, 0x02);
1447 if (wcd938x->comp2_enable) {
1448 snd_soc_component_write_field(component,
1449 WCD938X_DIGITAL_CDC_COMP_CTL_0,
1450 WCD938X_HPHR_COMP_EN_MASK, 1);
1451 /* 5msec compander delay as per HW requirement */
1452 if (!wcd938x->comp1_enable ||
1453 (snd_soc_component_read(component,
1454 WCD938X_DIGITAL_CDC_COMP_CTL_0) & 0x02))
1455 usleep_range(5000, 5010);
1456 snd_soc_component_write_field(component, WCD938X_HPH_NEW_INT_HPH_TIMER1,
1457 WCD938X_AUTOCHOP_TIMER_EN, 0);
1458 } else {
1459 snd_soc_component_write_field(component,
1460 WCD938X_DIGITAL_CDC_COMP_CTL_0,
1461 WCD938X_HPHR_COMP_EN_MASK, 0);
1462 snd_soc_component_write_field(component,
1463 WCD938X_HPH_R_EN,
1464 WCD938X_GAIN_SRC_SEL_MASK,
1465 WCD938X_GAIN_SRC_SEL_REGISTER);
1466 }
1467 break;
1468 case SND_SOC_DAPM_POST_PMD:
1469 snd_soc_component_write_field(component,
1470 WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_R,
1471 WCD938X_HPH_RES_DIV_MASK, 0x01);
1472 break;
1473 }
1474
1475 return 0;
1476}
1477
1478static int wcd938x_codec_ear_dac_event(struct snd_soc_dapm_widget *w,
1479 struct snd_kcontrol *kcontrol,
1480 int event)
1481{
1482 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
1483 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
1484
1485 switch (event) {
1486 case SND_SOC_DAPM_PRE_PMU:
1487 wcd938x->ear_rx_path =
1488 snd_soc_component_read(
1489 component, WCD938X_DIGITAL_CDC_EAR_PATH_CTL);
1490 if (wcd938x->ear_rx_path & EAR_RX_PATH_AUX) {
1491 snd_soc_component_write_field(component,
1492 WCD938X_EAR_EAR_DAC_CON,
1493 WCD938X_DAC_SAMPLE_EDGE_SEL_MASK, 0);
1494 snd_soc_component_write_field(component,
1495 WCD938X_DIGITAL_CDC_AUX_GAIN_CTL,
1496 WCD938X_AUX_EN_MASK, 1);
1497 snd_soc_component_write_field(component,
1498 WCD938X_DIGITAL_CDC_DIG_CLK_CTL,
1499 WCD938X_RXD2_CLK_EN_MASK, 1);
1500 snd_soc_component_write_field(component,
1501 WCD938X_ANA_EAR_COMPANDER_CTL,
1502 WCD938X_GAIN_OVRD_REG_MASK, 1);
1503 } else {
1504 snd_soc_component_write_field(component,
1505 WCD938X_DIGITAL_CDC_HPH_GAIN_CTL,
1506 WCD938X_HPHL_RX_EN_MASK, 1);
1507 snd_soc_component_write_field(component,
1508 WCD938X_DIGITAL_CDC_DIG_CLK_CTL,
1509 WCD938X_RXD0_CLK_EN_MASK, 1);
1510 if (wcd938x->comp1_enable)
1511 snd_soc_component_write_field(component,
1512 WCD938X_DIGITAL_CDC_COMP_CTL_0,
1513 WCD938X_HPHL_COMP_EN_MASK, 1);
1514 }
1515 /* 5 msec delay as per HW requirement */
1516 usleep_range(5000, 5010);
1517 if (wcd938x->flyback_cur_det_disable == 0)
1518 snd_soc_component_write_field(component, WCD938X_FLYBACK_EN,
1519 WCD938X_EN_CUR_DET_MASK, 0);
1520 wcd938x->flyback_cur_det_disable++;
1521 wcd_clsh_ctrl_set_state(wcd938x->clsh_info,
1522 WCD_CLSH_EVENT_PRE_DAC,
1523 WCD_CLSH_STATE_EAR,
1524 wcd938x->hph_mode);
1525 break;
1526 case SND_SOC_DAPM_POST_PMD:
1527 if (wcd938x->ear_rx_path & EAR_RX_PATH_AUX) {
1528 snd_soc_component_write_field(component,
1529 WCD938X_DIGITAL_CDC_AUX_GAIN_CTL,
1530 WCD938X_AUX_EN_MASK, 0);
1531 snd_soc_component_write_field(component,
1532 WCD938X_DIGITAL_CDC_DIG_CLK_CTL,
1533 WCD938X_RXD2_CLK_EN_MASK, 0);
1534 } else {
1535 snd_soc_component_write_field(component,
1536 WCD938X_DIGITAL_CDC_HPH_GAIN_CTL,
1537 WCD938X_HPHL_RX_EN_MASK, 0);
1538 snd_soc_component_write_field(component,
1539 WCD938X_DIGITAL_CDC_DIG_CLK_CTL,
1540 WCD938X_RXD0_CLK_EN_MASK, 0);
1541 if (wcd938x->comp1_enable)
1542 snd_soc_component_write_field(component,
1543 WCD938X_DIGITAL_CDC_COMP_CTL_0,
1544 WCD938X_HPHL_COMP_EN_MASK, 0);
1545 }
1546 snd_soc_component_write_field(component, WCD938X_ANA_EAR_COMPANDER_CTL,
1547 WCD938X_GAIN_OVRD_REG_MASK, 0);
1548 snd_soc_component_write_field(component,
1549 WCD938X_EAR_EAR_DAC_CON,
1550 WCD938X_DAC_SAMPLE_EDGE_SEL_MASK, 1);
1551 break;
1552 }
1553 return 0;
1554
1555}
1556
1557static int wcd938x_codec_aux_dac_event(struct snd_soc_dapm_widget *w,
1558 struct snd_kcontrol *kcontrol,
1559 int event)
1560{
1561 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
1562 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
1563 int ret = 0;
1564
1565 switch (event) {
1566 case SND_SOC_DAPM_PRE_PMU:
1567 snd_soc_component_write_field(component,
1568 WCD938X_DIGITAL_CDC_ANA_CLK_CTL,
1569 WCD938X_ANA_RX_DIV4_CLK_EN_MASK, 1);
1570 snd_soc_component_write_field(component,
1571 WCD938X_DIGITAL_CDC_DIG_CLK_CTL,
1572 WCD938X_RXD2_CLK_EN_MASK, 1);
1573 snd_soc_component_write_field(component,
1574 WCD938X_DIGITAL_CDC_AUX_GAIN_CTL,
1575 WCD938X_AUX_EN_MASK, 1);
1576 if (wcd938x->flyback_cur_det_disable == 0)
1577 snd_soc_component_write_field(component, WCD938X_FLYBACK_EN,
1578 WCD938X_EN_CUR_DET_MASK, 0);
1579 wcd938x->flyback_cur_det_disable++;
1580 wcd_clsh_ctrl_set_state(wcd938x->clsh_info,
1581 WCD_CLSH_EVENT_PRE_DAC,
1582 WCD_CLSH_STATE_AUX,
1583 wcd938x->hph_mode);
1584 break;
1585 case SND_SOC_DAPM_POST_PMD:
1586 snd_soc_component_write_field(component,
1587 WCD938X_DIGITAL_CDC_ANA_CLK_CTL,
1588 WCD938X_ANA_RX_DIV4_CLK_EN_MASK, 0);
1589 break;
1590 }
1591 return ret;
1592
1593}
1594
1595static int wcd938x_codec_enable_hphr_pa(struct snd_soc_dapm_widget *w,
1596 struct snd_kcontrol *kcontrol, int event)
1597{
1598 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
1599 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
1600 int hph_mode = wcd938x->hph_mode;
1601
1602 switch (event) {
1603 case SND_SOC_DAPM_PRE_PMU:
1604 if (wcd938x->ldoh)
1605 snd_soc_component_write_field(component, WCD938X_LDOH_MODE,
1606 WCD938X_LDOH_EN_MASK, 1);
1607 wcd_clsh_ctrl_set_state(wcd938x->clsh_info, WCD_CLSH_EVENT_PRE_DAC,
1608 WCD_CLSH_STATE_HPHR, hph_mode);
1609 wcd_clsh_set_hph_mode(wcd938x->clsh_info, CLS_H_HIFI);
1610
1611 if (hph_mode == CLS_H_LP || hph_mode == CLS_H_LOHIFI ||
1612 hph_mode == CLS_H_ULP) {
1613 snd_soc_component_write_field(component,
1614 WCD938X_HPH_REFBUFF_LP_CTL,
1615 WCD938X_PREREF_FLIT_BYPASS_MASK, 1);
1616 }
1617 snd_soc_component_write_field(component, WCD938X_ANA_HPH,
1618 WCD938X_HPHR_REF_EN_MASK, 1);
1619 wcd_clsh_set_hph_mode(wcd938x->clsh_info, hph_mode);
1620 /* 100 usec delay as per HW requirement */
1621 usleep_range(100, 110);
1622 set_bit(HPH_PA_DELAY, &wcd938x->status_mask);
1623 snd_soc_component_write_field(component,
1624 WCD938X_DIGITAL_PDM_WD_CTL1,
1625 WCD938X_PDM_WD_EN_MASK, 0x3);
1626 break;
1627 case SND_SOC_DAPM_POST_PMU:
1628 /*
1629 * 7ms sleep is required if compander is enabled as per
1630 * HW requirement. If compander is disabled, then
1631 * 20ms delay is required.
1632 */
1633 if (test_bit(HPH_PA_DELAY, &wcd938x->status_mask)) {
1634 if (!wcd938x->comp2_enable)
1635 usleep_range(20000, 20100);
1636 else
1637 usleep_range(7000, 7100);
1638
1639 if (hph_mode == CLS_H_LP || hph_mode == CLS_H_LOHIFI ||
1640 hph_mode == CLS_H_ULP)
1641 snd_soc_component_write_field(component,
1642 WCD938X_HPH_REFBUFF_LP_CTL,
1643 WCD938X_PREREF_FLIT_BYPASS_MASK, 0);
1644 clear_bit(HPH_PA_DELAY, &wcd938x->status_mask);
1645 }
1646 snd_soc_component_write_field(component, WCD938X_HPH_NEW_INT_HPH_TIMER1,
1647 WCD938X_AUTOCHOP_TIMER_EN, 1);
1648 if (hph_mode == CLS_AB || hph_mode == CLS_AB_HIFI ||
1649 hph_mode == CLS_AB_LP || hph_mode == CLS_AB_LOHIFI)
1650 snd_soc_component_write_field(component, WCD938X_ANA_RX_SUPPLIES,
1651 WCD938X_REGULATOR_MODE_MASK,
1652 WCD938X_REGULATOR_MODE_CLASS_AB);
1653 enable_irq(wcd938x->hphr_pdm_wd_int);
1654 break;
1655 case SND_SOC_DAPM_PRE_PMD:
1656 disable_irq_nosync(wcd938x->hphr_pdm_wd_int);
1657 /*
1658 * 7ms sleep is required if compander is enabled as per
1659 * HW requirement. If compander is disabled, then
1660 * 20ms delay is required.
1661 */
1662 if (!wcd938x->comp2_enable)
1663 usleep_range(20000, 20100);
1664 else
1665 usleep_range(7000, 7100);
1666 snd_soc_component_write_field(component, WCD938X_ANA_HPH,
1667 WCD938X_HPHR_EN_MASK, 0);
1668 set_bit(HPH_PA_DELAY, &wcd938x->status_mask);
1669 break;
1670 case SND_SOC_DAPM_POST_PMD:
1671 /*
1672 * 7ms sleep is required if compander is enabled as per
1673 * HW requirement. If compander is disabled, then
1674 * 20ms delay is required.
1675 */
1676 if (test_bit(HPH_PA_DELAY, &wcd938x->status_mask)) {
1677 if (!wcd938x->comp2_enable)
1678 usleep_range(20000, 20100);
1679 else
1680 usleep_range(7000, 7100);
1681 clear_bit(HPH_PA_DELAY, &wcd938x->status_mask);
1682 }
1683 snd_soc_component_write_field(component, WCD938X_ANA_HPH,
1684 WCD938X_HPHR_REF_EN_MASK, 0);
1685 snd_soc_component_write_field(component, WCD938X_DIGITAL_PDM_WD_CTL1,
1686 WCD938X_PDM_WD_EN_MASK, 0);
1687 wcd_clsh_ctrl_set_state(wcd938x->clsh_info, WCD_CLSH_EVENT_POST_PA,
1688 WCD_CLSH_STATE_HPHR, hph_mode);
1689 if (wcd938x->ldoh)
1690 snd_soc_component_write_field(component, WCD938X_LDOH_MODE,
1691 WCD938X_LDOH_EN_MASK, 0);
1692 break;
1693 }
1694
1695 return 0;
1696}
1697
1698static int wcd938x_codec_enable_hphl_pa(struct snd_soc_dapm_widget *w,
1699 struct snd_kcontrol *kcontrol, int event)
1700{
1701 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
1702 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
1703 int hph_mode = wcd938x->hph_mode;
1704
1705 switch (event) {
1706 case SND_SOC_DAPM_PRE_PMU:
1707 if (wcd938x->ldoh)
1708 snd_soc_component_write_field(component, WCD938X_LDOH_MODE,
1709 WCD938X_LDOH_EN_MASK, 1);
1710 wcd_clsh_ctrl_set_state(wcd938x->clsh_info, WCD_CLSH_EVENT_PRE_DAC,
1711 WCD_CLSH_STATE_HPHL, hph_mode);
1712 wcd_clsh_set_hph_mode(wcd938x->clsh_info, CLS_H_HIFI);
1713 if (hph_mode == CLS_H_LP || hph_mode == CLS_H_LOHIFI ||
1714 hph_mode == CLS_H_ULP) {
1715 snd_soc_component_write_field(component,
1716 WCD938X_HPH_REFBUFF_LP_CTL,
1717 WCD938X_PREREF_FLIT_BYPASS_MASK, 1);
1718 }
1719 snd_soc_component_write_field(component, WCD938X_ANA_HPH,
1720 WCD938X_HPHL_REF_EN_MASK, 1);
1721 wcd_clsh_set_hph_mode(wcd938x->clsh_info, hph_mode);
1722 /* 100 usec delay as per HW requirement */
1723 usleep_range(100, 110);
1724 set_bit(HPH_PA_DELAY, &wcd938x->status_mask);
1725 snd_soc_component_write_field(component,
1726 WCD938X_DIGITAL_PDM_WD_CTL0,
1727 WCD938X_PDM_WD_EN_MASK, 0x3);
1728 break;
1729 case SND_SOC_DAPM_POST_PMU:
1730 /*
1731 * 7ms sleep is required if compander is enabled as per
1732 * HW requirement. If compander is disabled, then
1733 * 20ms delay is required.
1734 */
1735 if (test_bit(HPH_PA_DELAY, &wcd938x->status_mask)) {
1736 if (!wcd938x->comp1_enable)
1737 usleep_range(20000, 20100);
1738 else
1739 usleep_range(7000, 7100);
1740 if (hph_mode == CLS_H_LP || hph_mode == CLS_H_LOHIFI ||
1741 hph_mode == CLS_H_ULP)
1742 snd_soc_component_write_field(component,
1743 WCD938X_HPH_REFBUFF_LP_CTL,
1744 WCD938X_PREREF_FLIT_BYPASS_MASK, 0);
1745 clear_bit(HPH_PA_DELAY, &wcd938x->status_mask);
1746 }
1747
1748 snd_soc_component_write_field(component, WCD938X_HPH_NEW_INT_HPH_TIMER1,
1749 WCD938X_AUTOCHOP_TIMER_EN, 1);
1750 if (hph_mode == CLS_AB || hph_mode == CLS_AB_HIFI ||
1751 hph_mode == CLS_AB_LP || hph_mode == CLS_AB_LOHIFI)
1752 snd_soc_component_write_field(component, WCD938X_ANA_RX_SUPPLIES,
1753 WCD938X_REGULATOR_MODE_MASK,
1754 WCD938X_REGULATOR_MODE_CLASS_AB);
1755 enable_irq(wcd938x->hphl_pdm_wd_int);
1756 break;
1757 case SND_SOC_DAPM_PRE_PMD:
1758 disable_irq_nosync(wcd938x->hphl_pdm_wd_int);
1759 /*
1760 * 7ms sleep is required if compander is enabled as per
1761 * HW requirement. If compander is disabled, then
1762 * 20ms delay is required.
1763 */
1764 if (!wcd938x->comp1_enable)
1765 usleep_range(20000, 20100);
1766 else
1767 usleep_range(7000, 7100);
1768 snd_soc_component_write_field(component, WCD938X_ANA_HPH,
1769 WCD938X_HPHL_EN_MASK, 0);
1770 set_bit(HPH_PA_DELAY, &wcd938x->status_mask);
1771 break;
1772 case SND_SOC_DAPM_POST_PMD:
1773 /*
1774 * 7ms sleep is required if compander is enabled as per
1775 * HW requirement. If compander is disabled, then
1776 * 20ms delay is required.
1777 */
1778 if (test_bit(HPH_PA_DELAY, &wcd938x->status_mask)) {
1779 if (!wcd938x->comp1_enable)
1780 usleep_range(21000, 21100);
1781 else
1782 usleep_range(7000, 7100);
1783 clear_bit(HPH_PA_DELAY, &wcd938x->status_mask);
1784 }
1785 snd_soc_component_write_field(component, WCD938X_ANA_HPH,
1786 WCD938X_HPHL_REF_EN_MASK, 0);
1787 snd_soc_component_write_field(component, WCD938X_DIGITAL_PDM_WD_CTL0,
1788 WCD938X_PDM_WD_EN_MASK, 0);
1789 wcd_clsh_ctrl_set_state(wcd938x->clsh_info, WCD_CLSH_EVENT_POST_PA,
1790 WCD_CLSH_STATE_HPHL, hph_mode);
1791 if (wcd938x->ldoh)
1792 snd_soc_component_write_field(component, WCD938X_LDOH_MODE,
1793 WCD938X_LDOH_EN_MASK, 0);
1794 break;
1795 }
1796
1797 return 0;
1798}
1799
1800static int wcd938x_codec_enable_aux_pa(struct snd_soc_dapm_widget *w,
1801 struct snd_kcontrol *kcontrol, int event)
1802{
1803 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
1804 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
1805 int hph_mode = wcd938x->hph_mode;
1806 int ret = 0;
1807
1808 switch (event) {
1809 case SND_SOC_DAPM_PRE_PMU:
1810 snd_soc_component_write_field(component, WCD938X_DIGITAL_PDM_WD_CTL2,
1811 WCD938X_AUX_PDM_WD_EN_MASK, 1);
1812 break;
1813 case SND_SOC_DAPM_POST_PMU:
1814 /* 1 msec delay as per HW requirement */
1815 usleep_range(1000, 1010);
1816 if (hph_mode == CLS_AB || hph_mode == CLS_AB_HIFI ||
1817 hph_mode == CLS_AB_LP || hph_mode == CLS_AB_LOHIFI)
1818 snd_soc_component_write_field(component, WCD938X_ANA_RX_SUPPLIES,
1819 WCD938X_REGULATOR_MODE_MASK,
1820 WCD938X_REGULATOR_MODE_CLASS_AB);
1821 enable_irq(wcd938x->aux_pdm_wd_int);
1822 break;
1823 case SND_SOC_DAPM_PRE_PMD:
1824 disable_irq_nosync(wcd938x->aux_pdm_wd_int);
1825 break;
1826 case SND_SOC_DAPM_POST_PMD:
1827 /* 1 msec delay as per HW requirement */
1828 usleep_range(1000, 1010);
1829 snd_soc_component_write_field(component, WCD938X_DIGITAL_PDM_WD_CTL2,
1830 WCD938X_AUX_PDM_WD_EN_MASK, 0);
1831 wcd_clsh_ctrl_set_state(wcd938x->clsh_info,
1832 WCD_CLSH_EVENT_POST_PA,
1833 WCD_CLSH_STATE_AUX,
1834 hph_mode);
1835
1836 wcd938x->flyback_cur_det_disable--;
1837 if (wcd938x->flyback_cur_det_disable == 0)
1838 snd_soc_component_write_field(component, WCD938X_FLYBACK_EN,
1839 WCD938X_EN_CUR_DET_MASK, 1);
1840 break;
1841 }
1842 return ret;
1843}
1844
1845static int wcd938x_codec_enable_ear_pa(struct snd_soc_dapm_widget *w,
1846 struct snd_kcontrol *kcontrol, int event)
1847{
1848 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
1849 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
1850 int hph_mode = wcd938x->hph_mode;
1851
1852 switch (event) {
1853 case SND_SOC_DAPM_PRE_PMU:
1854 /*
1855 * Enable watchdog interrupt for HPHL or AUX
1856 * depending on mux value
1857 */
1858 wcd938x->ear_rx_path = snd_soc_component_read(component,
1859 WCD938X_DIGITAL_CDC_EAR_PATH_CTL);
1860 if (wcd938x->ear_rx_path & EAR_RX_PATH_AUX)
1861 snd_soc_component_write_field(component, WCD938X_DIGITAL_PDM_WD_CTL2,
1862 WCD938X_AUX_PDM_WD_EN_MASK, 1);
1863 else
1864 snd_soc_component_write_field(component,
1865 WCD938X_DIGITAL_PDM_WD_CTL0,
1866 WCD938X_PDM_WD_EN_MASK, 0x3);
1867 if (!wcd938x->comp1_enable)
1868 snd_soc_component_write_field(component,
1869 WCD938X_ANA_EAR_COMPANDER_CTL,
1870 WCD938X_GAIN_OVRD_REG_MASK, 1);
1871
1872 break;
1873 case SND_SOC_DAPM_POST_PMU:
1874 /* 6 msec delay as per HW requirement */
1875 usleep_range(6000, 6010);
1876 if (hph_mode == CLS_AB || hph_mode == CLS_AB_HIFI ||
1877 hph_mode == CLS_AB_LP || hph_mode == CLS_AB_LOHIFI)
1878 snd_soc_component_write_field(component, WCD938X_ANA_RX_SUPPLIES,
1879 WCD938X_REGULATOR_MODE_MASK,
1880 WCD938X_REGULATOR_MODE_CLASS_AB);
1881 if (wcd938x->ear_rx_path & EAR_RX_PATH_AUX)
1882 enable_irq(wcd938x->aux_pdm_wd_int);
1883 else
1884 enable_irq(wcd938x->hphl_pdm_wd_int);
1885 break;
1886 case SND_SOC_DAPM_PRE_PMD:
1887 if (wcd938x->ear_rx_path & EAR_RX_PATH_AUX)
1888 disable_irq_nosync(wcd938x->aux_pdm_wd_int);
1889 else
1890 disable_irq_nosync(wcd938x->hphl_pdm_wd_int);
1891 break;
1892 case SND_SOC_DAPM_POST_PMD:
1893 if (!wcd938x->comp1_enable)
1894 snd_soc_component_write_field(component, WCD938X_ANA_EAR_COMPANDER_CTL,
1895 WCD938X_GAIN_OVRD_REG_MASK, 0);
1896 /* 7 msec delay as per HW requirement */
1897 usleep_range(7000, 7010);
1898 if (wcd938x->ear_rx_path & EAR_RX_PATH_AUX)
1899 snd_soc_component_write_field(component, WCD938X_DIGITAL_PDM_WD_CTL2,
1900 WCD938X_AUX_PDM_WD_EN_MASK, 0);
1901 else
1902 snd_soc_component_write_field(component, WCD938X_DIGITAL_PDM_WD_CTL0,
1903 WCD938X_PDM_WD_EN_MASK, 0);
1904
1905 wcd_clsh_ctrl_set_state(wcd938x->clsh_info, WCD_CLSH_EVENT_POST_PA,
1906 WCD_CLSH_STATE_EAR, hph_mode);
1907
1908 wcd938x->flyback_cur_det_disable--;
1909 if (wcd938x->flyback_cur_det_disable == 0)
1910 snd_soc_component_write_field(component, WCD938X_FLYBACK_EN,
1911 WCD938X_EN_CUR_DET_MASK, 1);
1912 break;
1913 }
1914
1915 return 0;
1916}
1917
Srinivas Kandagatlae8ba1e02021-06-09 10:09:40 +0100[diff] [blame]1918static int wcd938x_tx_mode_get(struct snd_kcontrol *kcontrol,
1919 struct snd_ctl_elem_value *ucontrol)
1920{
1921 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
1922 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
1923 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
1924 int path = e->shift_l;
1925
1926 ucontrol->value.integer.value[0] = wcd938x->tx_mode[path];
1927
1928 return 0;
1929}
1930
1931static int wcd938x_tx_mode_put(struct snd_kcontrol *kcontrol,
1932 struct snd_ctl_elem_value *ucontrol)
1933{
1934 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
1935 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
1936 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
1937 int path = e->shift_l;
1938
1939 wcd938x->tx_mode[path] = ucontrol->value.enumerated.item[0];
1940
1941 return 1;
1942}
1943
1944static int wcd938x_rx_hph_mode_get(struct snd_kcontrol *kcontrol,
1945 struct snd_ctl_elem_value *ucontrol)
1946{
1947 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
1948 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
1949
1950 ucontrol->value.integer.value[0] = wcd938x->hph_mode;
1951
1952 return 0;
1953}
1954
1955static int wcd938x_rx_hph_mode_put(struct snd_kcontrol *kcontrol,
1956 struct snd_ctl_elem_value *ucontrol)
1957{
1958 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
1959 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
1960
1961 wcd938x->hph_mode = ucontrol->value.enumerated.item[0];
1962
1963 return 1;
1964}
1965
1966static int wcd938x_ear_pa_put_gain(struct snd_kcontrol *kcontrol,
1967 struct snd_ctl_elem_value *ucontrol)
1968{
1969 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
1970 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
1971
1972 if (wcd938x->comp1_enable) {
1973 dev_err(component->dev, "Can not set EAR PA Gain, compander1 is enabled\n");
1974 return -EINVAL;
1975 }
1976
1977 snd_soc_component_write_field(component, WCD938X_ANA_EAR_COMPANDER_CTL,
1978 WCD938X_EAR_GAIN_MASK,
1979 ucontrol->value.integer.value[0]);
1980
1981 return 0;
1982}
1983
1984static int wcd938x_get_compander(struct snd_kcontrol *kcontrol,
1985 struct snd_ctl_elem_value *ucontrol)
1986{
1987
1988 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
1989 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
1990 struct soc_mixer_control *mc;
1991 bool hphr;
1992
1993 mc = (struct soc_mixer_control *)(kcontrol->private_value);
1994 hphr = mc->shift;
1995
1996 if (hphr)
1997 ucontrol->value.integer.value[0] = wcd938x->comp2_enable;
1998 else
1999 ucontrol->value.integer.value[0] = wcd938x->comp1_enable;
2000
2001 return 0;
2002}
2003
2004static int wcd938x_set_compander(struct snd_kcontrol *kcontrol,
2005 struct snd_ctl_elem_value *ucontrol)
2006{
2007 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
2008 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
2009 struct wcd938x_sdw_priv *wcd;
2010 int value = ucontrol->value.integer.value[0];
2011 struct soc_mixer_control *mc;
2012 bool hphr;
2013
2014 mc = (struct soc_mixer_control *)(kcontrol->private_value);
2015 hphr = mc->shift;
2016
2017 wcd = wcd938x->sdw_priv[AIF1_PB];
2018
2019 if (hphr)
2020 wcd938x->comp2_enable = value;
2021 else
2022 wcd938x->comp1_enable = value;
2023
2024 if (value)
2025 wcd938x_connect_port(wcd, mc->reg, true);
2026 else
2027 wcd938x_connect_port(wcd, mc->reg, false);
2028
2029 return 0;
2030}
2031
2032static int wcd938x_ldoh_get(struct snd_kcontrol *kcontrol,
2033 struct snd_ctl_elem_value *ucontrol)
2034{
2035 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
2036 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
2037
2038 ucontrol->value.integer.value[0] = wcd938x->ldoh;
2039
2040 return 0;
2041}
2042
2043static int wcd938x_ldoh_put(struct snd_kcontrol *kcontrol,
2044 struct snd_ctl_elem_value *ucontrol)
2045{
2046 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
2047 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
2048
2049 wcd938x->ldoh = ucontrol->value.integer.value[0];
2050
2051 return 1;
2052}
2053
2054static int wcd938x_bcs_get(struct snd_kcontrol *kcontrol,
2055 struct snd_ctl_elem_value *ucontrol)
2056{
2057 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
2058 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
2059
2060 ucontrol->value.integer.value[0] = wcd938x->bcs_dis;
2061
2062 return 0;
2063}
2064
2065static int wcd938x_bcs_put(struct snd_kcontrol *kcontrol,
2066 struct snd_ctl_elem_value *ucontrol)
2067{
2068 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
2069 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
2070
2071 wcd938x->bcs_dis = ucontrol->value.integer.value[0];
2072
2073 return 1;
2074}
2075
2076static const char * const tx_mode_mux_text_wcd9380[] = {
2077 "ADC_INVALID", "ADC_HIFI", "ADC_LO_HIF", "ADC_NORMAL", "ADC_LP",
2078};
2079
2080static const char * const tx_mode_mux_text[] = {
2081 "ADC_INVALID", "ADC_HIFI", "ADC_LO_HIF", "ADC_NORMAL", "ADC_LP",
2082 "ADC_ULP1", "ADC_ULP2",
2083};
2084
2085static const char * const rx_hph_mode_mux_text_wcd9380[] = {
2086 "CLS_H_INVALID", "CLS_H_INVALID_1", "CLS_H_LP", "CLS_AB",
2087 "CLS_H_LOHIFI", "CLS_H_ULP", "CLS_H_INVALID_2", "CLS_AB_LP",
2088 "CLS_AB_LOHIFI",
2089};
2090
2091static const char * const rx_hph_mode_mux_text[] = {
2092 "CLS_H_INVALID", "CLS_H_HIFI", "CLS_H_LP", "CLS_AB", "CLS_H_LOHIFI",
2093 "CLS_H_ULP", "CLS_AB_HIFI", "CLS_AB_LP", "CLS_AB_LOHIFI",
2094};
2095
Srinivas Kandagatla8da9db02021-06-09 10:09:41 +0100[diff] [blame^]2096static const char * const adc2_mux_text[] = {
2097 "INP2", "INP3"
2098};
2099
2100static const char * const adc3_mux_text[] = {
2101 "INP4", "INP6"
2102};
2103
2104static const char * const adc4_mux_text[] = {
2105 "INP5", "INP7"
2106};
2107
2108static const char * const rdac3_mux_text[] = {
2109 "RX1", "RX3"
2110};
2111
2112static const char * const hdr12_mux_text[] = {
2113 "NO_HDR12", "HDR12"
2114};
2115
2116static const char * const hdr34_mux_text[] = {
2117 "NO_HDR34", "HDR34"
2118};
2119
Srinivas Kandagatlae8ba1e02021-06-09 10:09:40 +0100[diff] [blame]2120static const struct soc_enum tx0_mode_enum_wcd9380 =
2121 SOC_ENUM_SINGLE(SND_SOC_NOPM, 0, ARRAY_SIZE(tx_mode_mux_text_wcd9380),
2122 tx_mode_mux_text_wcd9380);
2123
2124static const struct soc_enum tx1_mode_enum_wcd9380 =
2125 SOC_ENUM_SINGLE(SND_SOC_NOPM, 1, ARRAY_SIZE(tx_mode_mux_text_wcd9380),
2126 tx_mode_mux_text_wcd9380);
2127
2128static const struct soc_enum tx2_mode_enum_wcd9380 =
2129 SOC_ENUM_SINGLE(SND_SOC_NOPM, 2, ARRAY_SIZE(tx_mode_mux_text_wcd9380),
2130 tx_mode_mux_text_wcd9380);
2131
2132static const struct soc_enum tx3_mode_enum_wcd9380 =
2133 SOC_ENUM_SINGLE(SND_SOC_NOPM, 3, ARRAY_SIZE(tx_mode_mux_text_wcd9380),
2134 tx_mode_mux_text_wcd9380);
2135
2136static const struct soc_enum tx0_mode_enum_wcd9385 =
2137 SOC_ENUM_SINGLE(SND_SOC_NOPM, 0, ARRAY_SIZE(tx_mode_mux_text),
2138 tx_mode_mux_text);
2139
2140static const struct soc_enum tx1_mode_enum_wcd9385 =
2141 SOC_ENUM_SINGLE(SND_SOC_NOPM, 1, ARRAY_SIZE(tx_mode_mux_text),
2142 tx_mode_mux_text);
2143
2144static const struct soc_enum tx2_mode_enum_wcd9385 =
2145 SOC_ENUM_SINGLE(SND_SOC_NOPM, 2, ARRAY_SIZE(tx_mode_mux_text),
2146 tx_mode_mux_text);
2147
2148static const struct soc_enum tx3_mode_enum_wcd9385 =
2149 SOC_ENUM_SINGLE(SND_SOC_NOPM, 3, ARRAY_SIZE(tx_mode_mux_text),
2150 tx_mode_mux_text);
2151
2152static const struct soc_enum rx_hph_mode_mux_enum_wcd9380 =
2153 SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(rx_hph_mode_mux_text_wcd9380),
2154 rx_hph_mode_mux_text_wcd9380);
2155
2156static const struct soc_enum rx_hph_mode_mux_enum =
2157 SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(rx_hph_mode_mux_text),
2158 rx_hph_mode_mux_text);
2159
Srinivas Kandagatla8da9db02021-06-09 10:09:41 +0100[diff] [blame^]2160static const struct soc_enum rdac3_enum =
2161 SOC_ENUM_SINGLE(WCD938X_DIGITAL_CDC_EAR_PATH_CTL, 0,
2162 ARRAY_SIZE(rdac3_mux_text), rdac3_mux_text);
2163
2164static const struct snd_kcontrol_new ear_rdac_switch[] = {
2165 SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
2166};
2167
2168static const struct snd_kcontrol_new aux_rdac_switch[] = {
2169 SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
2170};
2171
2172static const struct snd_kcontrol_new hphl_rdac_switch[] = {
2173 SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
2174};
2175
2176static const struct snd_kcontrol_new hphr_rdac_switch[] = {
2177 SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
2178};
2179
2180static const struct snd_kcontrol_new rx_rdac3_mux =
2181 SOC_DAPM_ENUM("RDAC3_MUX Mux", rdac3_enum);
2182
Srinivas Kandagatlae8ba1e02021-06-09 10:09:40 +0100[diff] [blame]2183static const struct snd_kcontrol_new wcd9380_snd_controls[] = {
2184 SOC_ENUM_EXT("RX HPH Mode", rx_hph_mode_mux_enum_wcd9380,
2185 wcd938x_rx_hph_mode_get, wcd938x_rx_hph_mode_put),
2186 SOC_ENUM_EXT("TX0 MODE", tx0_mode_enum_wcd9380,
2187 wcd938x_tx_mode_get, wcd938x_tx_mode_put),
2188 SOC_ENUM_EXT("TX1 MODE", tx1_mode_enum_wcd9380,
2189 wcd938x_tx_mode_get, wcd938x_tx_mode_put),
2190 SOC_ENUM_EXT("TX2 MODE", tx2_mode_enum_wcd9380,
2191 wcd938x_tx_mode_get, wcd938x_tx_mode_put),
2192 SOC_ENUM_EXT("TX3 MODE", tx3_mode_enum_wcd9380,
2193 wcd938x_tx_mode_get, wcd938x_tx_mode_put),
2194};
2195
2196static const struct snd_kcontrol_new wcd9385_snd_controls[] = {
2197 SOC_ENUM_EXT("RX HPH Mode", rx_hph_mode_mux_enum,
2198 wcd938x_rx_hph_mode_get, wcd938x_rx_hph_mode_put),
2199 SOC_ENUM_EXT("TX0 MODE", tx0_mode_enum_wcd9385,
2200 wcd938x_tx_mode_get, wcd938x_tx_mode_put),
2201 SOC_ENUM_EXT("TX1 MODE", tx1_mode_enum_wcd9385,
2202 wcd938x_tx_mode_get, wcd938x_tx_mode_put),
2203 SOC_ENUM_EXT("TX2 MODE", tx2_mode_enum_wcd9385,
2204 wcd938x_tx_mode_get, wcd938x_tx_mode_put),
2205 SOC_ENUM_EXT("TX3 MODE", tx3_mode_enum_wcd9385,
2206 wcd938x_tx_mode_get, wcd938x_tx_mode_put),
2207};
2208
2209static int wcd938x_get_swr_port(struct snd_kcontrol *kcontrol,
2210 struct snd_ctl_elem_value *ucontrol)
2211{
2212 struct snd_soc_component *comp = snd_soc_kcontrol_component(kcontrol);
2213 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(comp);
2214 struct wcd938x_sdw_priv *wcd;
2215 struct soc_mixer_control *mixer = (struct soc_mixer_control *)kcontrol->private_value;
2216 int dai_id = mixer->shift;
2217 int portidx = mixer->reg;
2218
2219 wcd = wcd938x->sdw_priv[dai_id];
2220
2221 ucontrol->value.integer.value[0] = wcd->port_enable[portidx];
2222
2223 return 0;
2224}
2225
2226static int wcd938x_set_swr_port(struct snd_kcontrol *kcontrol,
2227 struct snd_ctl_elem_value *ucontrol)
2228{
2229 struct snd_soc_component *comp = snd_soc_kcontrol_component(kcontrol);
2230 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(comp);
2231 struct wcd938x_sdw_priv *wcd;
2232 struct soc_mixer_control *mixer =
2233 (struct soc_mixer_control *)kcontrol->private_value;
2234 int portidx = mixer->reg;
2235 int dai_id = mixer->shift;
2236 bool enable;
2237
2238 wcd = wcd938x->sdw_priv[dai_id];
2239
2240 if (ucontrol->value.integer.value[0])
2241 enable = true;
2242 else
2243 enable = false;
2244
2245 wcd->port_enable[portidx] = enable;
2246
2247 wcd938x_connect_port(wcd, portidx, enable);
2248
2249 return 0;
2250
2251}
2252
2253static const struct snd_kcontrol_new wcd938x_snd_controls[] = {
2254 SOC_SINGLE_EXT("HPHL_COMP Switch", WCD938X_COMP_L, 0, 1, 0,
2255 wcd938x_get_compander, wcd938x_set_compander),
2256 SOC_SINGLE_EXT("HPHR_COMP Switch", WCD938X_COMP_R, 1, 1, 0,
2257 wcd938x_get_compander, wcd938x_set_compander),
2258 SOC_SINGLE_EXT("HPHL Switch", WCD938X_HPH_L, 0, 1, 0,
2259 wcd938x_get_swr_port, wcd938x_set_swr_port),
2260 SOC_SINGLE_EXT("HPHR Switch", WCD938X_HPH_R, 0, 1, 0,
2261 wcd938x_get_swr_port, wcd938x_set_swr_port),
2262 SOC_SINGLE_EXT("CLSH Switch", WCD938X_CLSH, 0, 1, 0,
2263 wcd938x_get_swr_port, wcd938x_set_swr_port),
2264 SOC_SINGLE_EXT("LO Switch", WCD938X_LO, 0, 1, 0,
2265 wcd938x_get_swr_port, wcd938x_set_swr_port),
2266 SOC_SINGLE_EXT("DSD_L Switch", WCD938X_DSD_L, 0, 1, 0,
2267 wcd938x_get_swr_port, wcd938x_set_swr_port),
2268 SOC_SINGLE_EXT("DSD_R Switch", WCD938X_DSD_R, 0, 1, 0,
2269 wcd938x_get_swr_port, wcd938x_set_swr_port),
2270 SOC_SINGLE_TLV("HPHL Volume", WCD938X_HPH_L_EN, 0, 0x18, 0, line_gain),
2271 SOC_SINGLE_TLV("HPHR Volume", WCD938X_HPH_R_EN, 0, 0x18, 0, line_gain),
2272 WCD938X_EAR_PA_GAIN_TLV("EAR_PA Volume", WCD938X_ANA_EAR_COMPANDER_CTL,
2273 2, 0x10, 0, ear_pa_gain),
2274 SOC_SINGLE_EXT("ADC1 Switch", WCD938X_ADC1, 1, 1, 0,
2275 wcd938x_get_swr_port, wcd938x_set_swr_port),
2276 SOC_SINGLE_EXT("ADC2 Switch", WCD938X_ADC2, 1, 1, 0,
2277 wcd938x_get_swr_port, wcd938x_set_swr_port),
2278 SOC_SINGLE_EXT("ADC3 Switch", WCD938X_ADC3, 1, 1, 0,
2279 wcd938x_get_swr_port, wcd938x_set_swr_port),
2280 SOC_SINGLE_EXT("ADC4 Switch", WCD938X_ADC4, 1, 1, 0,
2281 wcd938x_get_swr_port, wcd938x_set_swr_port),
2282 SOC_SINGLE_EXT("DMIC0 Switch", WCD938X_DMIC0, 1, 1, 0,
2283 wcd938x_get_swr_port, wcd938x_set_swr_port),
2284 SOC_SINGLE_EXT("DMIC1 Switch", WCD938X_DMIC1, 1, 1, 0,
2285 wcd938x_get_swr_port, wcd938x_set_swr_port),
2286 SOC_SINGLE_EXT("MBHC Switch", WCD938X_MBHC, 1, 1, 0,
2287 wcd938x_get_swr_port, wcd938x_set_swr_port),
2288 SOC_SINGLE_EXT("DMIC2 Switch", WCD938X_DMIC2, 1, 1, 0,
2289 wcd938x_get_swr_port, wcd938x_set_swr_port),
2290 SOC_SINGLE_EXT("DMIC3 Switch", WCD938X_DMIC3, 1, 1, 0,
2291 wcd938x_get_swr_port, wcd938x_set_swr_port),
2292 SOC_SINGLE_EXT("DMIC4 Switch", WCD938X_DMIC4, 1, 1, 0,
2293 wcd938x_get_swr_port, wcd938x_set_swr_port),
2294 SOC_SINGLE_EXT("DMIC5 Switch", WCD938X_DMIC5, 1, 1, 0,
2295 wcd938x_get_swr_port, wcd938x_set_swr_port),
2296 SOC_SINGLE_EXT("DMIC6 Switch", WCD938X_DMIC6, 1, 1, 0,
2297 wcd938x_get_swr_port, wcd938x_set_swr_port),
2298 SOC_SINGLE_EXT("DMIC7 Switch", WCD938X_DMIC7, 1, 1, 0,
2299 wcd938x_get_swr_port, wcd938x_set_swr_port),
2300 SOC_SINGLE_EXT("LDOH Enable Switch", SND_SOC_NOPM, 0, 1, 0,
2301 wcd938x_ldoh_get, wcd938x_ldoh_put),
2302 SOC_SINGLE_EXT("ADC2_BCS Disable Switch", SND_SOC_NOPM, 0, 1, 0,
2303 wcd938x_bcs_get, wcd938x_bcs_put),
2304
2305 SOC_SINGLE_TLV("ADC1 Volume", WCD938X_ANA_TX_CH1, 0, 20, 0, analog_gain),
2306 SOC_SINGLE_TLV("ADC2 Volume", WCD938X_ANA_TX_CH2, 0, 20, 0, analog_gain),
2307 SOC_SINGLE_TLV("ADC3 Volume", WCD938X_ANA_TX_CH3, 0, 20, 0, analog_gain),
2308 SOC_SINGLE_TLV("ADC4 Volume", WCD938X_ANA_TX_CH4, 0, 20, 0, analog_gain),
2309};
2310
Srinivas Kandagatla8da9db02021-06-09 10:09:41 +0100[diff] [blame^]2311static const struct snd_soc_dapm_widget wcd938x_dapm_widgets[] = {
2312 SND_SOC_DAPM_INPUT("IN1_HPHL"),
2313 SND_SOC_DAPM_INPUT("IN2_HPHR"),
2314 SND_SOC_DAPM_INPUT("IN3_AUX"),
2315
2316 /*rx widgets*/
2317 SND_SOC_DAPM_PGA_E("EAR PGA", WCD938X_ANA_EAR, 7, 0, NULL, 0,
2318 wcd938x_codec_enable_ear_pa,
2319 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
2320 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
2321 SND_SOC_DAPM_PGA_E("AUX PGA", WCD938X_AUX_AUXPA, 7, 0, NULL, 0,
2322 wcd938x_codec_enable_aux_pa,
2323 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
2324 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
2325 SND_SOC_DAPM_PGA_E("HPHL PGA", WCD938X_ANA_HPH, 7, 0, NULL, 0,
2326 wcd938x_codec_enable_hphl_pa,
2327 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
2328 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
2329 SND_SOC_DAPM_PGA_E("HPHR PGA", WCD938X_ANA_HPH, 6, 0, NULL, 0,
2330 wcd938x_codec_enable_hphr_pa,
2331 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
2332 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
2333
2334 SND_SOC_DAPM_DAC_E("RDAC1", NULL, SND_SOC_NOPM, 0, 0,
2335 wcd938x_codec_hphl_dac_event,
2336 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
2337 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
2338 SND_SOC_DAPM_DAC_E("RDAC2", NULL, SND_SOC_NOPM, 0, 0,
2339 wcd938x_codec_hphr_dac_event,
2340 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
2341 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
2342 SND_SOC_DAPM_DAC_E("RDAC3", NULL, SND_SOC_NOPM, 0, 0,
2343 wcd938x_codec_ear_dac_event,
2344 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
2345 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
2346 SND_SOC_DAPM_DAC_E("RDAC4", NULL, SND_SOC_NOPM, 0, 0,
2347 wcd938x_codec_aux_dac_event,
2348 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
2349 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
2350
2351 SND_SOC_DAPM_MUX("RDAC3_MUX", SND_SOC_NOPM, 0, 0, &rx_rdac3_mux),
2352
2353 SND_SOC_DAPM_SUPPLY("VDD_BUCK", SND_SOC_NOPM, 0, 0, NULL, 0),
2354 SND_SOC_DAPM_SUPPLY("RXCLK", SND_SOC_NOPM, 0, 0,
2355 wcd938x_codec_enable_rxclk,
2356 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
2357 SND_SOC_DAPM_POST_PMD),
2358
2359 SND_SOC_DAPM_SUPPLY_S("CLS_H_PORT", 1, SND_SOC_NOPM, 0, 0, NULL, 0),
2360
2361 SND_SOC_DAPM_MIXER_E("RX1", SND_SOC_NOPM, 0, 0, NULL, 0, NULL, 0),
2362 SND_SOC_DAPM_MIXER_E("RX2", SND_SOC_NOPM, 0, 0, NULL, 0, NULL, 0),
2363 SND_SOC_DAPM_MIXER_E("RX3", SND_SOC_NOPM, 0, 0, NULL, 0, NULL, 0),
2364
2365 /* rx mixer widgets*/
2366 SND_SOC_DAPM_MIXER("EAR_RDAC", SND_SOC_NOPM, 0, 0,
2367 ear_rdac_switch, ARRAY_SIZE(ear_rdac_switch)),
2368 SND_SOC_DAPM_MIXER("AUX_RDAC", SND_SOC_NOPM, 0, 0,
2369 aux_rdac_switch, ARRAY_SIZE(aux_rdac_switch)),
2370 SND_SOC_DAPM_MIXER("HPHL_RDAC", SND_SOC_NOPM, 0, 0,
2371 hphl_rdac_switch, ARRAY_SIZE(hphl_rdac_switch)),
2372 SND_SOC_DAPM_MIXER("HPHR_RDAC", SND_SOC_NOPM, 0, 0,
2373 hphr_rdac_switch, ARRAY_SIZE(hphr_rdac_switch)),
2374
2375 /*output widgets rx*/
2376 SND_SOC_DAPM_OUTPUT("EAR"),
2377 SND_SOC_DAPM_OUTPUT("AUX"),
2378 SND_SOC_DAPM_OUTPUT("HPHL"),
2379 SND_SOC_DAPM_OUTPUT("HPHR"),
2380};
2381
Srinivas Kandagatla8d786022021-06-09 10:09:37 +0100[diff] [blame]2382static int wcd938x_get_micb_vout_ctl_val(u32 micb_mv)
2383{
2384 /* min micbias voltage is 1V and maximum is 2.85V */
2385 if (micb_mv < 1000 || micb_mv > 2850)
2386 return -EINVAL;
2387
2388 return (micb_mv - 1000) / 50;
2389}
2390
2391static int wcd938x_set_micbias_data(struct wcd938x_priv *wcd938x)
2392{
2393 int vout_ctl_1, vout_ctl_2, vout_ctl_3, vout_ctl_4;
2394
2395 /* set micbias voltage */
2396 vout_ctl_1 = wcd938x_get_micb_vout_ctl_val(wcd938x->micb1_mv);
2397 vout_ctl_2 = wcd938x_get_micb_vout_ctl_val(wcd938x->micb2_mv);
2398 vout_ctl_3 = wcd938x_get_micb_vout_ctl_val(wcd938x->micb3_mv);
2399 vout_ctl_4 = wcd938x_get_micb_vout_ctl_val(wcd938x->micb4_mv);
2400 if (vout_ctl_1 < 0 || vout_ctl_2 < 0 || vout_ctl_3 < 0 || vout_ctl_4 < 0)
2401 return -EINVAL;
2402
2403 regmap_update_bits(wcd938x->regmap, WCD938X_ANA_MICB1,
2404 WCD938X_MICB_VOUT_MASK, vout_ctl_1);
2405 regmap_update_bits(wcd938x->regmap, WCD938X_ANA_MICB2,
2406 WCD938X_MICB_VOUT_MASK, vout_ctl_2);
2407 regmap_update_bits(wcd938x->regmap, WCD938X_ANA_MICB3,
2408 WCD938X_MICB_VOUT_MASK, vout_ctl_3);
2409 regmap_update_bits(wcd938x->regmap, WCD938X_ANA_MICB4,
2410 WCD938X_MICB_VOUT_MASK, vout_ctl_4);
2411
2412 return 0;
2413}
2414
2415static irqreturn_t wcd938x_wd_handle_irq(int irq, void *data)
2416{
2417 return IRQ_HANDLED;
2418}
2419
2420static struct irq_chip wcd_irq_chip = {
2421 .name = "WCD938x",
2422};
2423
2424static int wcd_irq_chip_map(struct irq_domain *irqd, unsigned int virq,
2425 irq_hw_number_t hw)
2426{
2427 irq_set_chip_and_handler(virq, &wcd_irq_chip, handle_simple_irq);
2428 irq_set_nested_thread(virq, 1);
2429 irq_set_noprobe(virq);
2430
2431 return 0;
2432}
2433
2434static const struct irq_domain_ops wcd_domain_ops = {
2435 .map = wcd_irq_chip_map,
2436};
2437
2438static int wcd938x_irq_init(struct wcd938x_priv *wcd, struct device *dev)
2439{
2440
2441 wcd->virq = irq_domain_add_linear(NULL, 1, &wcd_domain_ops, NULL);
2442 if (!(wcd->virq)) {
2443 dev_err(dev, "%s: Failed to add IRQ domain\n", __func__);
2444 return -EINVAL;
2445 }
2446
2447 return devm_regmap_add_irq_chip(dev, wcd->regmap,
2448 irq_create_mapping(wcd->virq, 0),
2449 IRQF_ONESHOT, 0, &wcd938x_regmap_irq_chip,
2450 &wcd->irq_chip);
2451}
2452
2453static int wcd938x_soc_codec_probe(struct snd_soc_component *component)
2454{
2455 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
2456 struct device *dev = component->dev;
2457 int ret, i;
2458
2459 snd_soc_component_init_regmap(component, wcd938x->regmap);
2460
2461 wcd938x->variant = snd_soc_component_read_field(component,
2462 WCD938X_DIGITAL_EFUSE_REG_0,
2463 WCD938X_ID_MASK);
2464
2465 wcd938x->clsh_info = wcd_clsh_ctrl_alloc(component, WCD938X);
2466
2467 wcd938x_io_init(wcd938x);
2468 /* Set all interrupts as edge triggered */
2469 for (i = 0; i < wcd938x_regmap_irq_chip.num_regs; i++) {
2470 regmap_write(wcd938x->regmap,
2471 (WCD938X_DIGITAL_INTR_LEVEL_0 + i), 0);
2472 }
2473
2474 ret = wcd938x_irq_init(wcd938x, component->dev);
2475 if (ret) {
2476 dev_err(component->dev, "%s: IRQ init failed: %d\n",
2477 __func__, ret);
2478 return ret;
2479 }
2480
2481 wcd938x->hphr_pdm_wd_int = regmap_irq_get_virq(wcd938x->irq_chip,
2482 WCD938X_IRQ_HPHR_PDM_WD_INT);
2483 wcd938x->hphl_pdm_wd_int = regmap_irq_get_virq(wcd938x->irq_chip,
2484 WCD938X_IRQ_HPHL_PDM_WD_INT);
2485 wcd938x->aux_pdm_wd_int = regmap_irq_get_virq(wcd938x->irq_chip,
2486 WCD938X_IRQ_AUX_PDM_WD_INT);
2487
2488 /* Request for watchdog interrupt */
2489 ret = request_threaded_irq(wcd938x->hphr_pdm_wd_int, NULL, wcd938x_wd_handle_irq,
2490 IRQF_ONESHOT | IRQF_TRIGGER_RISING,
2491 "HPHR PDM WD INT", wcd938x);
2492 if (ret)
2493 dev_err(dev, "Failed to request HPHR WD interrupt (%d)\n", ret);
2494
2495 ret = request_threaded_irq(wcd938x->hphl_pdm_wd_int, NULL, wcd938x_wd_handle_irq,
2496 IRQF_ONESHOT | IRQF_TRIGGER_RISING,
2497 "HPHL PDM WD INT", wcd938x);
2498 if (ret)
2499 dev_err(dev, "Failed to request HPHL WD interrupt (%d)\n", ret);
2500
2501 ret = request_threaded_irq(wcd938x->aux_pdm_wd_int, NULL, wcd938x_wd_handle_irq,
2502 IRQF_ONESHOT | IRQF_TRIGGER_RISING,
2503 "AUX PDM WD INT", wcd938x);
2504 if (ret)
2505 dev_err(dev, "Failed to request Aux WD interrupt (%d)\n", ret);
2506
2507 /* Disable watchdog interrupt for HPH and AUX */
2508 disable_irq_nosync(wcd938x->hphr_pdm_wd_int);
2509 disable_irq_nosync(wcd938x->hphl_pdm_wd_int);
2510 disable_irq_nosync(wcd938x->aux_pdm_wd_int);
2511
Srinivas Kandagatlae8ba1e02021-06-09 10:09:40 +0100[diff] [blame]2512 switch (wcd938x->variant) {
2513 case WCD9380:
2514 ret = snd_soc_add_component_controls(component, wcd9380_snd_controls,
2515 ARRAY_SIZE(wcd9380_snd_controls));
2516 if (ret < 0) {
2517 dev_err(component->dev,
2518 "%s: Failed to add snd ctrls for variant: %d\n",
2519 __func__, wcd938x->variant);
2520 goto err;
2521 }
2522 break;
2523 case WCD9385:
2524 ret = snd_soc_add_component_controls(component, wcd9385_snd_controls,
2525 ARRAY_SIZE(wcd9385_snd_controls));
2526 if (ret < 0) {
2527 dev_err(component->dev,
2528 "%s: Failed to add snd ctrls for variant: %d\n",
2529 __func__, wcd938x->variant);
2530 goto err;
2531 }
2532 break;
2533 default:
2534 break;
2535 }
2536err:
Srinivas Kandagatla8d786022021-06-09 10:09:37 +0100[diff] [blame]2537 return ret;
2538}
2539
2540static const struct snd_soc_component_driver soc_codec_dev_wcd938x = {
2541 .name = "wcd938x_codec",
2542 .probe = wcd938x_soc_codec_probe,
Srinivas Kandagatlae8ba1e02021-06-09 10:09:40 +0100[diff] [blame]2543 .controls = wcd938x_snd_controls,
2544 .num_controls = ARRAY_SIZE(wcd938x_snd_controls),
Srinivas Kandagatla8da9db02021-06-09 10:09:41 +0100[diff] [blame^]2545 .dapm_widgets = wcd938x_dapm_widgets,
2546 .num_dapm_widgets = ARRAY_SIZE(wcd938x_dapm_widgets),
Srinivas Kandagatla8d786022021-06-09 10:09:37 +0100[diff] [blame]2547};
2548
2549static void wcd938x_dt_parse_micbias_info(struct device *dev, struct wcd938x_priv *wcd)
2550{
2551 struct device_node *np = dev->of_node;
2552 u32 prop_val = 0;
2553 int rc = 0;
2554
2555 rc = of_property_read_u32(np, "qcom,micbias1-microvolt", &prop_val);
2556 if (!rc)
2557 wcd->micb1_mv = prop_val/1000;
2558 else
2559 dev_info(dev, "%s: Micbias1 DT property not found\n", __func__);
2560
2561 rc = of_property_read_u32(np, "qcom,micbias2-microvolt", &prop_val);
2562 if (!rc)
2563 wcd->micb2_mv = prop_val/1000;
2564 else
2565 dev_info(dev, "%s: Micbias2 DT property not found\n", __func__);
2566
2567 rc = of_property_read_u32(np, "qcom,micbias3-microvolt", &prop_val);
2568 if (!rc)
2569 wcd->micb3_mv = prop_val/1000;
2570 else
2571 dev_info(dev, "%s: Micbias3 DT property not found\n", __func__);
2572
2573 rc = of_property_read_u32(np, "qcom,micbias4-microvolt", &prop_val);
2574 if (!rc)
2575 wcd->micb4_mv = prop_val/1000;
2576 else
2577 dev_info(dev, "%s: Micbias4 DT property not found\n", __func__);
2578}
2579
2580static int wcd938x_populate_dt_data(struct wcd938x_priv *wcd938x, struct device *dev)
2581{
2582 int ret;
2583
2584 wcd938x->reset_gpio = of_get_named_gpio(dev->of_node, "reset-gpios", 0);
2585 if (wcd938x->reset_gpio < 0) {
2586 dev_err(dev, "Failed to get reset gpio: err = %d\n",
2587 wcd938x->reset_gpio);
2588 return wcd938x->reset_gpio;
2589 }
2590
2591 wcd938x->supplies[0].supply = "vdd-rxtx";
2592 wcd938x->supplies[1].supply = "vdd-io";
2593 wcd938x->supplies[2].supply = "vdd-buck";
2594 wcd938x->supplies[3].supply = "vdd-mic-bias";
2595
2596 ret = regulator_bulk_get(dev, WCD938X_MAX_SUPPLY, wcd938x->supplies);
2597 if (ret) {
2598 dev_err(dev, "Failed to get supplies: err = %d\n", ret);
2599 return ret;
2600 }
2601
2602 ret = regulator_bulk_enable(WCD938X_MAX_SUPPLY, wcd938x->supplies);
2603 if (ret) {
2604 dev_err(dev, "Failed to enable supplies: err = %d\n", ret);
2605 return ret;
2606 }
2607
2608 wcd938x_dt_parse_micbias_info(dev, wcd938x);
2609
2610 return 0;
2611}
2612
2613static int wcd938x_reset(struct wcd938x_priv *wcd938x)
2614{
2615 gpio_direction_output(wcd938x->reset_gpio, 0);
2616 /* 20us sleep required after pulling the reset gpio to LOW */
2617 usleep_range(20, 30);
2618 gpio_set_value(wcd938x->reset_gpio, 1);
2619 /* 20us sleep required after pulling the reset gpio to HIGH */
2620 usleep_range(20, 30);
2621
2622 return 0;
2623}
2624
2625int wcd938x_handle_sdw_irq(struct wcd938x_sdw_priv *wcd)
2626{
2627 struct wcd938x_priv *wcd938x = wcd->wcd938x;
2628 struct irq_domain *slave_irq = wcd938x->virq;
2629 u32 sts1, sts2, sts3;
2630
2631 do {
2632 handle_nested_irq(irq_find_mapping(slave_irq, 0));
2633 regmap_read(wcd938x->regmap, WCD938X_DIGITAL_INTR_STATUS_0, &sts1);
2634 regmap_read(wcd938x->regmap, WCD938X_DIGITAL_INTR_STATUS_1, &sts2);
2635 regmap_read(wcd938x->regmap, WCD938X_DIGITAL_INTR_STATUS_2, &sts3);
2636
2637 } while (sts1 || sts2 || sts3);
2638
2639 return IRQ_HANDLED;
2640}
2641EXPORT_SYMBOL_GPL(wcd938x_handle_sdw_irq);
2642
Srinivas Kandagatla16572522021-06-09 10:09:39 +0100[diff] [blame]2643static int wcd938x_codec_hw_params(struct snd_pcm_substream *substream,
2644 struct snd_pcm_hw_params *params,
2645 struct snd_soc_dai *dai)
2646{
2647 struct wcd938x_priv *wcd938x = dev_get_drvdata(dai->dev);
2648 struct wcd938x_sdw_priv *wcd = wcd938x->sdw_priv[dai->id];
2649
2650 return wcd938x_sdw_hw_params(wcd, substream, params, dai);
2651}
2652
2653static int wcd938x_codec_free(struct snd_pcm_substream *substream,
2654 struct snd_soc_dai *dai)
2655{
2656 struct wcd938x_priv *wcd938x = dev_get_drvdata(dai->dev);
2657 struct wcd938x_sdw_priv *wcd = wcd938x->sdw_priv[dai->id];
2658
2659 return wcd938x_sdw_free(wcd, substream, dai);
2660}
2661
2662static int wcd938x_codec_set_sdw_stream(struct snd_soc_dai *dai,
2663 void *stream, int direction)
2664{
2665 struct wcd938x_priv *wcd938x = dev_get_drvdata(dai->dev);
2666 struct wcd938x_sdw_priv *wcd = wcd938x->sdw_priv[dai->id];
2667
2668 return wcd938x_sdw_set_sdw_stream(wcd, dai, stream, direction);
2669
2670}
2671
Srinivas Kandagatla8d786022021-06-09 10:09:37 +0100[diff] [blame]2672static struct snd_soc_dai_ops wcd938x_sdw_dai_ops = {
Srinivas Kandagatla16572522021-06-09 10:09:39 +0100[diff] [blame]2673 .hw_params = wcd938x_codec_hw_params,
2674 .hw_free = wcd938x_codec_free,
2675 .set_sdw_stream = wcd938x_codec_set_sdw_stream,
Srinivas Kandagatla8d786022021-06-09 10:09:37 +0100[diff] [blame]2676};
2677
2678static struct snd_soc_dai_driver wcd938x_dais[] = {
2679 [0] = {
2680 .name = "wcd938x-sdw-rx",
2681 .playback = {
2682 .stream_name = "WCD AIF1 Playback",
2683 .rates = WCD938X_RATES_MASK | WCD938X_FRAC_RATES_MASK,
2684 .formats = WCD938X_FORMATS_S16_S24_LE,
2685 .rate_max = 192000,
2686 .rate_min = 8000,
2687 .channels_min = 1,
2688 .channels_max = 2,
2689 },
2690 .ops = &wcd938x_sdw_dai_ops,
2691 },
2692 [1] = {
2693 .name = "wcd938x-sdw-tx",
2694 .capture = {
2695 .stream_name = "WCD AIF1 Capture",
2696 .rates = WCD938X_RATES_MASK,
2697 .formats = SNDRV_PCM_FMTBIT_S16_LE,
2698 .rate_min = 8000,
2699 .rate_max = 192000,
2700 .channels_min = 1,
2701 .channels_max = 4,
2702 },
2703 .ops = &wcd938x_sdw_dai_ops,
2704 },
2705};
2706
2707static int wcd938x_bind(struct device *dev)
2708{
2709 struct wcd938x_priv *wcd938x = dev_get_drvdata(dev);
2710 int ret;
2711
2712 ret = component_bind_all(dev, wcd938x);
2713 if (ret) {
2714 dev_err(dev, "%s: Slave bind failed, ret = %d\n",
2715 __func__, ret);
2716 return ret;
2717 }
2718
Srinivas Kandagatla16572522021-06-09 10:09:39 +0100[diff] [blame]2719 wcd938x->rxdev = wcd938x_sdw_device_get(wcd938x->rxnode);
2720 if (!wcd938x->rxdev) {
2721 dev_err(dev, "could not find slave with matching of node\n");
2722 return -EINVAL;
2723 }
2724 wcd938x->sdw_priv[AIF1_PB] = dev_get_drvdata(wcd938x->rxdev);
2725 wcd938x->sdw_priv[AIF1_PB]->wcd938x = wcd938x;
2726
2727 wcd938x->txdev = wcd938x_sdw_device_get(wcd938x->txnode);
2728 if (!wcd938x->txdev) {
2729 dev_err(dev, "could not find txslave with matching of node\n");
2730 return -EINVAL;
2731 }
2732 wcd938x->sdw_priv[AIF1_CAP] = dev_get_drvdata(wcd938x->txdev);
2733 wcd938x->sdw_priv[AIF1_CAP]->wcd938x = wcd938x;
2734 wcd938x->tx_sdw_dev = dev_to_sdw_dev(wcd938x->txdev);
2735 if (!wcd938x->tx_sdw_dev) {
2736 dev_err(dev, "could not get txslave with matching of dev\n");
2737 return -EINVAL;
2738 }
2739
2740 /* As TX is main CSR reg interface, which should not be suspended first.
2741 * expicilty add the dependency link */
2742 if (!device_link_add(wcd938x->rxdev, wcd938x->txdev, DL_FLAG_STATELESS |
2743 DL_FLAG_PM_RUNTIME)) {
2744 dev_err(dev, "could not devlink tx and rx\n");
2745 return -EINVAL;
2746 }
2747
2748 if (!device_link_add(dev, wcd938x->txdev, DL_FLAG_STATELESS |
2749 DL_FLAG_PM_RUNTIME)) {
2750 dev_err(dev, "could not devlink wcd and tx\n");
2751 return -EINVAL;
2752 }
2753
2754 if (!device_link_add(dev, wcd938x->rxdev, DL_FLAG_STATELESS |
2755 DL_FLAG_PM_RUNTIME)) {
2756 dev_err(dev, "could not devlink wcd and rx\n");
2757 return -EINVAL;
2758 }
2759
2760 wcd938x->regmap = dev_get_regmap(wcd938x->txdev, NULL);
2761 if (!wcd938x->regmap) {
2762 dev_err(dev, "%s: tx csr regmap not found\n", __func__);
2763 return PTR_ERR(wcd938x->regmap);
2764 }
2765
Srinivas Kandagatla8d786022021-06-09 10:09:37 +0100[diff] [blame]2766 ret = wcd938x_set_micbias_data(wcd938x);
2767 if (ret < 0) {
2768 dev_err(dev, "%s: bad micbias pdata\n", __func__);
2769 return ret;
2770 }
2771
2772 ret = snd_soc_register_component(dev, &soc_codec_dev_wcd938x,
2773 wcd938x_dais, ARRAY_SIZE(wcd938x_dais));
2774 if (ret)
2775 dev_err(dev, "%s: Codec registration failed\n",
2776 __func__);
2777
2778 return ret;
2779
2780}
2781
2782static void wcd938x_unbind(struct device *dev)
2783{
2784 struct wcd938x_priv *wcd938x = dev_get_drvdata(dev);
2785
Srinivas Kandagatla16572522021-06-09 10:09:39 +0100[diff] [blame]2786 device_link_remove(dev, wcd938x->txdev);
2787 device_link_remove(dev, wcd938x->rxdev);
2788 device_link_remove(wcd938x->rxdev, wcd938x->txdev);
Srinivas Kandagatla8d786022021-06-09 10:09:37 +0100[diff] [blame]2789 snd_soc_unregister_component(dev);
2790 component_unbind_all(dev, wcd938x);
2791}
2792
2793static const struct component_master_ops wcd938x_comp_ops = {
2794 .bind = wcd938x_bind,
2795 .unbind = wcd938x_unbind,
2796};
2797
2798static int wcd938x_compare_of(struct device *dev, void *data)
2799{
2800 return dev->of_node == data;
2801}
2802
2803static void wcd938x_release_of(struct device *dev, void *data)
2804{
2805 of_node_put(data);
2806}
2807
2808static int wcd938x_add_slave_components(struct wcd938x_priv *wcd938x,
2809 struct device *dev,
2810 struct component_match **matchptr)
2811{
2812 struct device_node *np;
2813
2814 np = dev->of_node;
2815
2816 wcd938x->rxnode = of_parse_phandle(np, "qcom,rx-device", 0);
2817 if (!wcd938x->rxnode) {
2818 dev_err(dev, "%s: Rx-device node not defined\n", __func__);
2819 return -ENODEV;
2820 }
2821
2822 of_node_get(wcd938x->rxnode);
2823 component_match_add_release(dev, matchptr, wcd938x_release_of,
2824 wcd938x_compare_of, wcd938x->rxnode);
2825
2826 wcd938x->txnode = of_parse_phandle(np, "qcom,tx-device", 0);
2827 if (!wcd938x->txnode) {
2828 dev_err(dev, "%s: Tx-device node not defined\n", __func__);
2829 return -ENODEV;
2830 }
2831 of_node_get(wcd938x->txnode);
2832 component_match_add_release(dev, matchptr, wcd938x_release_of,
2833 wcd938x_compare_of, wcd938x->txnode);
2834 return 0;
2835}
2836
2837static int wcd938x_probe(struct platform_device *pdev)
2838{
2839 struct component_match *match = NULL;
2840 struct wcd938x_priv *wcd938x = NULL;
2841 struct device *dev = &pdev->dev;
2842 int ret;
2843
2844 wcd938x = devm_kzalloc(dev, sizeof(struct wcd938x_priv),
2845 GFP_KERNEL);
2846 if (!wcd938x)
2847 return -ENOMEM;
2848
2849 dev_set_drvdata(dev, wcd938x);
2850
2851 ret = wcd938x_populate_dt_data(wcd938x, dev);
2852 if (ret) {
2853 dev_err(dev, "%s: Fail to obtain platform data\n", __func__);
2854 return -EINVAL;
2855 }
2856
2857 ret = wcd938x_add_slave_components(wcd938x, dev, &match);
2858 if (ret)
2859 return ret;
2860
2861 wcd938x_reset(wcd938x);
2862
2863 ret = component_master_add_with_match(dev, &wcd938x_comp_ops, match);
2864 if (ret)
2865 return ret;
2866
2867 pm_runtime_set_autosuspend_delay(dev, 1000);
2868 pm_runtime_use_autosuspend(dev);
2869 pm_runtime_mark_last_busy(dev);
2870 pm_runtime_set_active(dev);
2871 pm_runtime_enable(dev);
2872 pm_runtime_idle(dev);
2873
2874 return ret;
2875}
2876
2877static int wcd938x_remove(struct platform_device *pdev)
2878{
2879 component_master_del(&pdev->dev, &wcd938x_comp_ops);
2880
2881 return 0;
2882}
2883
2884static const struct of_device_id wcd938x_dt_match[] = {
2885 { .compatible = "qcom,wcd9380-codec" },
2886 { .compatible = "qcom,wcd9385-codec" },
2887 {}
2888};
2889MODULE_DEVICE_TABLE(of, wcd938x_dt_match);
2890
2891static struct platform_driver wcd938x_codec_driver = {
2892 .probe = wcd938x_probe,
2893 .remove = wcd938x_remove,
2894 .driver = {
2895 .name = "wcd938x_codec",
2896 .of_match_table = of_match_ptr(wcd938x_dt_match),
2897 .suppress_bind_attrs = true,
2898 },
2899};
2900
2901module_platform_driver(wcd938x_codec_driver);
2902MODULE_DESCRIPTION("WCD938X Codec driver");
2903MODULE_LICENSE("GPL");