Carlos O'Donell | 342a049 | 2006-09-07 13:05:17 -0400 | [diff] [blame] | 1 | #ifndef _ASM_PARISC_FUTEX_H |
| 2 | #define _ASM_PARISC_FUTEX_H |
Jakub Jelinek | 4732efbe | 2005-09-06 15:16:25 -0700 | [diff] [blame] | 3 | |
Carlos O'Donell | 342a049 | 2006-09-07 13:05:17 -0400 | [diff] [blame] | 4 | #ifdef __KERNEL__ |
Jakub Jelinek | 4732efbe | 2005-09-06 15:16:25 -0700 | [diff] [blame] | 5 | |
Carlos O'Donell | 342a049 | 2006-09-07 13:05:17 -0400 | [diff] [blame] | 6 | #include <linux/futex.h> |
Jeff Dike | 730f412 | 2008-04-30 00:54:49 -0700 | [diff] [blame] | 7 | #include <linux/uaccess.h> |
Carlos O'Donell | d9ba5fe | 2011-07-08 17:27:00 -0400 | [diff] [blame^] | 8 | #include <asm/atomic.h> |
Carlos O'Donell | 342a049 | 2006-09-07 13:05:17 -0400 | [diff] [blame] | 9 | #include <asm/errno.h> |
Carlos O'Donell | 342a049 | 2006-09-07 13:05:17 -0400 | [diff] [blame] | 10 | |
| 11 | static inline int |
Michel Lespinasse | 8d7718a | 2011-03-10 18:50:58 -0800 | [diff] [blame] | 12 | futex_atomic_op_inuser (int encoded_op, u32 __user *uaddr) |
Carlos O'Donell | 342a049 | 2006-09-07 13:05:17 -0400 | [diff] [blame] | 13 | { |
Carlos O'Donell | d9ba5fe | 2011-07-08 17:27:00 -0400 | [diff] [blame^] | 14 | unsigned long int flags; |
| 15 | u32 val; |
Carlos O'Donell | 342a049 | 2006-09-07 13:05:17 -0400 | [diff] [blame] | 16 | int op = (encoded_op >> 28) & 7; |
| 17 | int cmp = (encoded_op >> 24) & 15; |
| 18 | int oparg = (encoded_op << 8) >> 20; |
| 19 | int cmparg = (encoded_op << 20) >> 20; |
| 20 | int oldval = 0, ret; |
| 21 | if (encoded_op & (FUTEX_OP_OPARG_SHIFT << 28)) |
| 22 | oparg = 1 << oparg; |
| 23 | |
Carlos O'Donell | d9ba5fe | 2011-07-08 17:27:00 -0400 | [diff] [blame^] | 24 | if (!access_ok(VERIFY_WRITE, uaddr, sizeof(*uaddr))) |
Carlos O'Donell | 342a049 | 2006-09-07 13:05:17 -0400 | [diff] [blame] | 25 | return -EFAULT; |
| 26 | |
Peter Zijlstra | a866374 | 2006-12-06 20:32:20 -0800 | [diff] [blame] | 27 | pagefault_disable(); |
Carlos O'Donell | 342a049 | 2006-09-07 13:05:17 -0400 | [diff] [blame] | 28 | |
Carlos O'Donell | d9ba5fe | 2011-07-08 17:27:00 -0400 | [diff] [blame^] | 29 | _atomic_spin_lock_irqsave(uaddr, flags); |
| 30 | |
Carlos O'Donell | 342a049 | 2006-09-07 13:05:17 -0400 | [diff] [blame] | 31 | switch (op) { |
| 32 | case FUTEX_OP_SET: |
Carlos O'Donell | d9ba5fe | 2011-07-08 17:27:00 -0400 | [diff] [blame^] | 33 | /* *(int *)UADDR2 = OPARG; */ |
| 34 | ret = get_user(oldval, uaddr); |
| 35 | if (!ret) |
| 36 | ret = put_user(oparg, uaddr); |
| 37 | break; |
Carlos O'Donell | 342a049 | 2006-09-07 13:05:17 -0400 | [diff] [blame] | 38 | case FUTEX_OP_ADD: |
Carlos O'Donell | d9ba5fe | 2011-07-08 17:27:00 -0400 | [diff] [blame^] | 39 | /* *(int *)UADDR2 += OPARG; */ |
| 40 | ret = get_user(oldval, uaddr); |
| 41 | if (!ret) { |
| 42 | val = oldval + oparg; |
| 43 | ret = put_user(val, uaddr); |
| 44 | } |
| 45 | break; |
Carlos O'Donell | 342a049 | 2006-09-07 13:05:17 -0400 | [diff] [blame] | 46 | case FUTEX_OP_OR: |
Carlos O'Donell | d9ba5fe | 2011-07-08 17:27:00 -0400 | [diff] [blame^] | 47 | /* *(int *)UADDR2 |= OPARG; */ |
| 48 | ret = get_user(oldval, uaddr); |
| 49 | if (!ret) { |
| 50 | val = oldval | oparg; |
| 51 | ret = put_user(val, uaddr); |
| 52 | } |
| 53 | break; |
Carlos O'Donell | 342a049 | 2006-09-07 13:05:17 -0400 | [diff] [blame] | 54 | case FUTEX_OP_ANDN: |
Carlos O'Donell | d9ba5fe | 2011-07-08 17:27:00 -0400 | [diff] [blame^] | 55 | /* *(int *)UADDR2 &= ~OPARG; */ |
| 56 | ret = get_user(oldval, uaddr); |
| 57 | if (!ret) { |
| 58 | val = oldval & ~oparg; |
| 59 | ret = put_user(val, uaddr); |
| 60 | } |
| 61 | break; |
Carlos O'Donell | 342a049 | 2006-09-07 13:05:17 -0400 | [diff] [blame] | 62 | case FUTEX_OP_XOR: |
Carlos O'Donell | d9ba5fe | 2011-07-08 17:27:00 -0400 | [diff] [blame^] | 63 | /* *(int *)UADDR2 ^= OPARG; */ |
| 64 | ret = get_user(oldval, uaddr); |
| 65 | if (!ret) { |
| 66 | val = oldval ^ oparg; |
| 67 | ret = put_user(val, uaddr); |
| 68 | } |
| 69 | break; |
Carlos O'Donell | 342a049 | 2006-09-07 13:05:17 -0400 | [diff] [blame] | 70 | default: |
| 71 | ret = -ENOSYS; |
| 72 | } |
| 73 | |
Carlos O'Donell | d9ba5fe | 2011-07-08 17:27:00 -0400 | [diff] [blame^] | 74 | _atomic_spin_unlock_irqrestore(uaddr, flags); |
| 75 | |
Peter Zijlstra | a866374 | 2006-12-06 20:32:20 -0800 | [diff] [blame] | 76 | pagefault_enable(); |
Carlos O'Donell | 342a049 | 2006-09-07 13:05:17 -0400 | [diff] [blame] | 77 | |
| 78 | if (!ret) { |
| 79 | switch (cmp) { |
| 80 | case FUTEX_OP_CMP_EQ: ret = (oldval == cmparg); break; |
| 81 | case FUTEX_OP_CMP_NE: ret = (oldval != cmparg); break; |
| 82 | case FUTEX_OP_CMP_LT: ret = (oldval < cmparg); break; |
| 83 | case FUTEX_OP_CMP_GE: ret = (oldval >= cmparg); break; |
| 84 | case FUTEX_OP_CMP_LE: ret = (oldval <= cmparg); break; |
| 85 | case FUTEX_OP_CMP_GT: ret = (oldval > cmparg); break; |
| 86 | default: ret = -ENOSYS; |
| 87 | } |
| 88 | } |
| 89 | return ret; |
| 90 | } |
| 91 | |
| 92 | /* Non-atomic version */ |
| 93 | static inline int |
Michel Lespinasse | 8d7718a | 2011-03-10 18:50:58 -0800 | [diff] [blame] | 94 | futex_atomic_cmpxchg_inatomic(u32 *uval, u32 __user *uaddr, |
| 95 | u32 oldval, u32 newval) |
Carlos O'Donell | 342a049 | 2006-09-07 13:05:17 -0400 | [diff] [blame] | 96 | { |
Carlos O'Donell | d9ba5fe | 2011-07-08 17:27:00 -0400 | [diff] [blame^] | 97 | int ret; |
Michel Lespinasse | 8d7718a | 2011-03-10 18:50:58 -0800 | [diff] [blame] | 98 | u32 val; |
Carlos O'Donell | d9ba5fe | 2011-07-08 17:27:00 -0400 | [diff] [blame^] | 99 | unsigned long flags; |
Carlos O'Donell | 342a049 | 2006-09-07 13:05:17 -0400 | [diff] [blame] | 100 | |
Kyle McMartin | c20a84c | 2008-03-01 10:25:52 -0800 | [diff] [blame] | 101 | /* futex.c wants to do a cmpxchg_inatomic on kernel NULL, which is |
| 102 | * our gateway page, and causes no end of trouble... |
| 103 | */ |
| 104 | if (segment_eq(KERNEL_DS, get_fs()) && !uaddr) |
| 105 | return -EFAULT; |
| 106 | |
Michel Lespinasse | 8d7718a | 2011-03-10 18:50:58 -0800 | [diff] [blame] | 107 | if (!access_ok(VERIFY_WRITE, uaddr, sizeof(u32))) |
Carlos O'Donell | 342a049 | 2006-09-07 13:05:17 -0400 | [diff] [blame] | 108 | return -EFAULT; |
| 109 | |
Carlos O'Donell | d9ba5fe | 2011-07-08 17:27:00 -0400 | [diff] [blame^] | 110 | /* HPPA has no cmpxchg in hardware and therefore the |
| 111 | * best we can do here is use an array of locks. The |
| 112 | * lock selected is based on a hash of the userspace |
| 113 | * address. This should scale to a couple of CPUs. |
| 114 | */ |
| 115 | |
| 116 | _atomic_spin_lock_irqsave(uaddr, flags); |
| 117 | |
| 118 | ret = get_user(val, uaddr); |
| 119 | |
| 120 | if (!ret && val == oldval) |
| 121 | ret = put_user(newval, uaddr); |
| 122 | |
Michel Lespinasse | 37a9d91 | 2011-03-10 18:48:51 -0800 | [diff] [blame] | 123 | *uval = val; |
Carlos O'Donell | d9ba5fe | 2011-07-08 17:27:00 -0400 | [diff] [blame^] | 124 | |
| 125 | _atomic_spin_unlock_irqrestore(uaddr, flags); |
| 126 | |
| 127 | return ret; |
Carlos O'Donell | 342a049 | 2006-09-07 13:05:17 -0400 | [diff] [blame] | 128 | } |
| 129 | |
Kyle McMartin | c20a84c | 2008-03-01 10:25:52 -0800 | [diff] [blame] | 130 | #endif /*__KERNEL__*/ |
| 131 | #endif /*_ASM_PARISC_FUTEX_H*/ |