Priyanka Jain | 0d748ec | 2015-07-30 10:33:55 +0530 | [diff] [blame] | 1 | /* |
| 2 | * T1040D4RDB/T1042D4RDB Device Tree Source |
| 3 | * |
| 4 | * Copyright 2015 Freescale Semiconductor Inc. |
| 5 | * |
| 6 | * Redistribution and use in source and binary forms, with or without |
| 7 | * modification, are permitted provided that the following conditions are met: |
| 8 | * * Redistributions of source code must retain the above copyright |
| 9 | * notice, this list of conditions and the following disclaimer. |
| 10 | * * Redistributions in binary form must reproduce the above copyright |
| 11 | * notice, this list of conditions and the following disclaimer in the |
| 12 | * documentation and/or other materials provided with the distribution. |
| 13 | * * Neither the name of Freescale Semiconductor nor the |
| 14 | * names of its contributors may be used to endorse or promote products |
| 15 | * derived from this software without specific prior written permission. |
| 16 | * |
| 17 | * |
| 18 | * ALTERNATIVELY, this software may be distributed under the terms of the |
| 19 | * GNU General Public License ("GPL") as published by the Free Software |
| 20 | * Foundation, either version 2 of that License or (at your option) any |
| 21 | * later version. |
| 22 | * |
| 23 | * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor "AS IS" AND ANY |
| 24 | * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED |
| 25 | * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
| 26 | * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY |
| 27 | * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES |
| 28 | * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; |
| 29 | * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND |
| 30 | * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
| 31 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS |
| 32 | * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| 33 | */ |
| 34 | |
| 35 | / { |
| 36 | reserved-memory { |
| 37 | #address-cells = <2>; |
| 38 | #size-cells = <2>; |
| 39 | ranges; |
| 40 | |
| 41 | bman_fbpr: bman-fbpr { |
| 42 | size = <0 0x1000000>; |
| 43 | alignment = <0 0x1000000>; |
| 44 | }; |
| 45 | qman_fqd: qman-fqd { |
| 46 | size = <0 0x400000>; |
| 47 | alignment = <0 0x400000>; |
| 48 | }; |
| 49 | qman_pfdr: qman-pfdr { |
| 50 | size = <0 0x2000000>; |
| 51 | alignment = <0 0x2000000>; |
| 52 | }; |
| 53 | }; |
| 54 | |
| 55 | ifc: localbus@ffe124000 { |
| 56 | reg = <0xf 0xfe124000 0 0x2000>; |
| 57 | ranges = <0 0 0xf 0xe8000000 0x08000000 |
| 58 | 2 0 0xf 0xff800000 0x00010000 |
| 59 | 3 0 0xf 0xffdf0000 0x00008000>; |
| 60 | |
| 61 | nor@0,0 { |
| 62 | #address-cells = <1>; |
| 63 | #size-cells = <1>; |
| 64 | compatible = "cfi-flash"; |
| 65 | reg = <0x0 0x0 0x8000000>; |
| 66 | bank-width = <2>; |
| 67 | device-width = <1>; |
| 68 | }; |
| 69 | |
| 70 | nand@2,0 { |
| 71 | #address-cells = <1>; |
| 72 | #size-cells = <1>; |
| 73 | compatible = "fsl,ifc-nand"; |
| 74 | reg = <0x2 0x0 0x10000>; |
| 75 | }; |
| 76 | |
| 77 | cpld@3,0 { |
| 78 | compatible = "fsl,t1040d4rdb-cpld"; |
| 79 | reg = <3 0 0x300>; |
| 80 | }; |
| 81 | }; |
| 82 | |
| 83 | memory { |
| 84 | device_type = "memory"; |
| 85 | }; |
| 86 | |
| 87 | dcsr: dcsr@f00000000 { |
| 88 | ranges = <0x00000000 0xf 0x00000000 0x01072000>; |
| 89 | }; |
| 90 | |
| 91 | bportals: bman-portals@ff4000000 { |
| 92 | ranges = <0x0 0xf 0xf4000000 0x2000000>; |
| 93 | }; |
| 94 | |
| 95 | qportals: qman-portals@ff6000000 { |
| 96 | ranges = <0x0 0xf 0xf6000000 0x2000000>; |
| 97 | }; |
| 98 | |
| 99 | soc: soc@ffe000000 { |
| 100 | ranges = <0x00000000 0xf 0xfe000000 0x1000000>; |
| 101 | reg = <0xf 0xfe000000 0 0x00001000>; |
| 102 | |
| 103 | spi@110000 { |
| 104 | flash@0 { |
| 105 | #address-cells = <1>; |
| 106 | #size-cells = <1>; |
| 107 | compatible = "micron,n25q512ax3"; |
| 108 | reg = <0>; |
| 109 | /* input clock */ |
| 110 | spi-max-frequency = <10000000>; |
| 111 | }; |
Zhao Qiang | a109752 | 2015-08-21 10:48:56 +0800 | [diff] [blame] | 112 | slic@1 { |
| 113 | compatible = "maxim,ds26522"; |
| 114 | reg = <1>; |
| 115 | spi-max-frequency = <2000000>; /* input clock */ |
| 116 | }; |
| 117 | slic@2 { |
| 118 | compatible = "maxim,ds26522"; |
| 119 | reg = <2>; |
| 120 | spi-max-frequency = <2000000>; /* input clock */ |
| 121 | }; |
Priyanka Jain | 0d748ec | 2015-07-30 10:33:55 +0530 | [diff] [blame] | 122 | }; |
| 123 | i2c@118000 { |
| 124 | hwmon@4c { |
| 125 | compatible = "adi,adt7461"; |
| 126 | reg = <0x4c>; |
| 127 | }; |
| 128 | |
| 129 | rtc@68 { |
| 130 | compatible = "dallas,ds1337"; |
| 131 | reg = <0x68>; |
| 132 | interrupts = <0x2 0x1 0 0>; |
| 133 | }; |
| 134 | }; |
| 135 | |
| 136 | i2c@118100 { |
| 137 | mux@77 { |
| 138 | /* |
| 139 | * Child nodes of mux depend on which i2c |
| 140 | * devices are connected via the mini PCI |
| 141 | * connector slot1, the mini PCI connector |
| 142 | * slot2, the HDMI connector, and the PEX |
| 143 | * slot. Systems with such devices attached |
| 144 | * should provide a wrapper .dts file that |
| 145 | * includes this one, and adds those nodes |
| 146 | */ |
| 147 | compatible = "nxp,pca9546"; |
| 148 | reg = <0x77>; |
| 149 | #address-cells = <1>; |
| 150 | #size-cells = <0>; |
| 151 | }; |
| 152 | }; |
| 153 | |
| 154 | }; |
| 155 | |
| 156 | pci0: pcie@ffe240000 { |
| 157 | reg = <0xf 0xfe240000 0 0x10000>; |
| 158 | ranges = <0x02000000 0 0xe0000000 0xc 0x0 0x0 0x10000000 |
| 159 | 0x01000000 0 0x0 0xf 0xf8000000 0x0 0x00010000>; |
| 160 | pcie@0 { |
| 161 | ranges = <0x02000000 0 0xe0000000 |
| 162 | 0x02000000 0 0xe0000000 |
| 163 | 0 0x10000000 |
| 164 | |
| 165 | 0x01000000 0 0x00000000 |
| 166 | 0x01000000 0 0x00000000 |
| 167 | 0 0x00010000>; |
| 168 | }; |
| 169 | }; |
| 170 | |
| 171 | pci1: pcie@ffe250000 { |
| 172 | reg = <0xf 0xfe250000 0 0x10000>; |
| 173 | ranges = <0x02000000 0 0xe0000000 0xc 0x10000000 0 0x10000000 |
| 174 | 0x01000000 0 0 0xf 0xf8010000 0 0x00010000>; |
| 175 | pcie@0 { |
| 176 | ranges = <0x02000000 0 0xe0000000 |
| 177 | 0x02000000 0 0xe0000000 |
| 178 | 0 0x10000000 |
| 179 | |
| 180 | 0x01000000 0 0x00000000 |
| 181 | 0x01000000 0 0x00000000 |
| 182 | 0 0x00010000>; |
| 183 | }; |
| 184 | }; |
| 185 | |
| 186 | pci2: pcie@ffe260000 { |
| 187 | reg = <0xf 0xfe260000 0 0x10000>; |
| 188 | ranges = <0x02000000 0 0xe0000000 0xc 0x20000000 0 0x10000000 |
| 189 | 0x01000000 0 0x00000000 0xf 0xf8020000 0 0x00010000>; |
| 190 | pcie@0 { |
| 191 | ranges = <0x02000000 0 0xe0000000 |
| 192 | 0x02000000 0 0xe0000000 |
| 193 | 0 0x10000000 |
| 194 | |
| 195 | 0x01000000 0 0x00000000 |
| 196 | 0x01000000 0 0x00000000 |
| 197 | 0 0x00010000>; |
| 198 | }; |
| 199 | }; |
| 200 | |
| 201 | pci3: pcie@ffe270000 { |
| 202 | reg = <0xf 0xfe270000 0 0x10000>; |
| 203 | ranges = <0x02000000 0 0xe0000000 0xc 0x30000000 0 0x10000000 |
| 204 | 0x01000000 0 0x00000000 0xf 0xf8030000 0 0x00010000>; |
| 205 | pcie@0 { |
| 206 | ranges = <0x02000000 0 0xe0000000 |
| 207 | 0x02000000 0 0xe0000000 |
| 208 | 0 0x10000000 |
| 209 | |
| 210 | 0x01000000 0 0x00000000 |
| 211 | 0x01000000 0 0x00000000 |
| 212 | 0 0x00010000>; |
| 213 | }; |
| 214 | }; |
| 215 | }; |