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review.shift-gmbh.com / SHIFTPHONES / mainline / linux / d7a58decc7049e8ca9707b63fcc2556cde3d26c5 / . / drivers / regulator / mt6359-regulator.c
blob: 994d3f67f73dc0b911267b7a214ee77e44e0ad6c [file] [log] [blame]
Wen Sud7a58de2021-05-26 14:52:05 +0800[diff] [blame^]1// SPDX-License-Identifier: GPL-2.0
2//
3// Copyright (c) 2021 MediaTek Inc.
4
5#include <linux/platform_device.h>
6#include <linux/mfd/mt6359/registers.h>
7#include <linux/mfd/mt6397/core.h>
8#include <linux/module.h>
9#include <linux/of_device.h>
10#include <linux/regmap.h>
11#include <linux/regulator/driver.h>
12#include <linux/regulator/machine.h>
13#include <linux/regulator/mt6359-regulator.h>
14#include <linux/regulator/of_regulator.h>
15
16#define MT6359_BUCK_MODE_AUTO 0
17#define MT6359_BUCK_MODE_FORCE_PWM 1
18#define MT6359_BUCK_MODE_NORMAL 0
19#define MT6359_BUCK_MODE_LP 2
20
21/*
22 * MT6359 regulators' information
23 *
24 * @desc: standard fields of regulator description.
25 * @status_reg: for query status of regulators.
26 * @qi: Mask for query enable signal status of regulators.
27 * @modeset_reg: for operating AUTO/PWM mode register.
28 * @modeset_mask: MASK for operating modeset register.
29 * @modeset_shift: SHIFT for operating modeset register.
30 */
31struct mt6359_regulator_info {
32 struct regulator_desc desc;
33 u32 status_reg;
34 u32 qi;
35 u32 modeset_reg;
36 u32 modeset_mask;
37 u32 modeset_shift;
38 u32 lp_mode_reg;
39 u32 lp_mode_mask;
40 u32 lp_mode_shift;
41};
42
43#define MT6359_BUCK(match, _name, min, max, step, min_sel, \
44 volt_ranges, _enable_reg, _status_reg, \
45 _vsel_reg, _vsel_mask, \
46 _lp_mode_reg, _lp_mode_shift, \
47 _modeset_reg, _modeset_shift) \
48[MT6359_ID_##_name] = { \
49 .desc = { \
50 .name = #_name, \
51 .of_match = of_match_ptr(match), \
52 .regulators_node = of_match_ptr("regulators"), \
53 .ops = &mt6359_volt_range_ops, \
54 .type = REGULATOR_VOLTAGE, \
55 .id = MT6359_ID_##_name, \
56 .owner = THIS_MODULE, \
57 .uV_step = (step), \
58 .linear_min_sel = (min_sel), \
59 .n_voltages = ((max) - (min)) / (step) + 1, \
60 .min_uV = (min), \
61 .linear_ranges = volt_ranges, \
62 .n_linear_ranges = ARRAY_SIZE(volt_ranges), \
63 .vsel_reg = _vsel_reg, \
64 .vsel_mask = _vsel_mask, \
65 .enable_reg = _enable_reg, \
66 .enable_mask = BIT(0), \
67 .of_map_mode = mt6359_map_mode, \
68 }, \
69 .status_reg = _status_reg, \
70 .qi = BIT(0), \
71 .lp_mode_reg = _lp_mode_reg, \
72 .lp_mode_mask = BIT(_lp_mode_shift), \
73 .lp_mode_shift = _lp_mode_shift, \
74 .modeset_reg = _modeset_reg, \
75 .modeset_mask = BIT(_modeset_shift), \
76 .modeset_shift = _modeset_shift \
77}
78
79#define MT6359_LDO_LINEAR(match, _name, min, max, step, min_sel,\
80 volt_ranges, _enable_reg, _status_reg, \
81 _vsel_reg, _vsel_mask) \
82[MT6359_ID_##_name] = { \
83 .desc = { \
84 .name = #_name, \
85 .of_match = of_match_ptr(match), \
86 .regulators_node = of_match_ptr("regulators"), \
87 .ops = &mt6359_volt_range_ops, \
88 .type = REGULATOR_VOLTAGE, \
89 .id = MT6359_ID_##_name, \
90 .owner = THIS_MODULE, \
91 .uV_step = (step), \
92 .linear_min_sel = (min_sel), \
93 .n_voltages = ((max) - (min)) / (step) + 1, \
94 .min_uV = (min), \
95 .linear_ranges = volt_ranges, \
96 .n_linear_ranges = ARRAY_SIZE(volt_ranges), \
97 .vsel_reg = _vsel_reg, \
98 .vsel_mask = _vsel_mask, \
99 .enable_reg = _enable_reg, \
100 .enable_mask = BIT(0), \
101 }, \
102 .status_reg = _status_reg, \
103 .qi = BIT(0), \
104}
105
106#define MT6359_LDO(match, _name, _volt_table, \
107 _enable_reg, _enable_mask, _status_reg, \
108 _vsel_reg, _vsel_mask, _en_delay) \
109[MT6359_ID_##_name] = { \
110 .desc = { \
111 .name = #_name, \
112 .of_match = of_match_ptr(match), \
113 .regulators_node = of_match_ptr("regulators"), \
114 .ops = &mt6359_volt_table_ops, \
115 .type = REGULATOR_VOLTAGE, \
116 .id = MT6359_ID_##_name, \
117 .owner = THIS_MODULE, \
118 .n_voltages = ARRAY_SIZE(_volt_table), \
119 .volt_table = _volt_table, \
120 .vsel_reg = _vsel_reg, \
121 .vsel_mask = _vsel_mask, \
122 .enable_reg = _enable_reg, \
123 .enable_mask = BIT(_enable_mask), \
124 .enable_time = _en_delay, \
125 }, \
126 .status_reg = _status_reg, \
127 .qi = BIT(0), \
128}
129
130#define MT6359_REG_FIXED(match, _name, _enable_reg, \
131 _status_reg, _fixed_volt) \
132[MT6359_ID_##_name] = { \
133 .desc = { \
134 .name = #_name, \
135 .of_match = of_match_ptr(match), \
136 .regulators_node = of_match_ptr("regulators"), \
137 .ops = &mt6359_volt_fixed_ops, \
138 .type = REGULATOR_VOLTAGE, \
139 .id = MT6359_ID_##_name, \
140 .owner = THIS_MODULE, \
141 .n_voltages = 1, \
142 .enable_reg = _enable_reg, \
143 .enable_mask = BIT(0), \
144 .fixed_uV = (_fixed_volt), \
145 }, \
146 .status_reg = _status_reg, \
147 .qi = BIT(0), \
148}
149
150static const struct linear_range mt_volt_range1[] = {
151 REGULATOR_LINEAR_RANGE(800000, 0, 0x70, 12500),
152};
153
154static const struct linear_range mt_volt_range2[] = {
155 REGULATOR_LINEAR_RANGE(400000, 0, 0x7f, 6250),
156};
157
158static const struct linear_range mt_volt_range3[] = {
159 REGULATOR_LINEAR_RANGE(400000, 0, 0x70, 6250),
160};
161
162static const struct linear_range mt_volt_range4[] = {
163 REGULATOR_LINEAR_RANGE(800000, 0, 0x40, 12500),
164};
165
166static const struct linear_range mt_volt_range5[] = {
167 REGULATOR_LINEAR_RANGE(500000, 0, 0x3F, 50000),
168};
169
170static const struct linear_range mt_volt_range6[] = {
171 REGULATOR_LINEAR_RANGE(500000, 0, 0x7f, 6250),
172};
173
174static const struct linear_range mt_volt_range7[] = {
175 REGULATOR_LINEAR_RANGE(500000, 0, 0x7f, 6250),
176};
177
178static const u32 vsim1_voltages[] = {
179 0, 0, 0, 1700000, 1800000, 0, 0, 0, 2700000, 0, 0, 3000000, 3100000,
180};
181
182static const u32 vibr_voltages[] = {
183 1200000, 1300000, 1500000, 0, 1800000, 2000000, 0, 0, 2700000, 2800000,
184 0, 3000000, 0, 3300000,
185};
186
187static const u32 vrf12_voltages[] = {
188 0, 0, 1100000, 1200000, 1300000,
189};
190
191static const u32 volt18_voltages[] = {
192 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1700000, 1800000, 1900000,
193};
194
195static const u32 vcn13_voltages[] = {
196 900000, 1000000, 0, 1200000, 1300000,
197};
198
199static const u32 vcn33_voltages[] = {
200 0, 0, 0, 0, 0, 0, 0, 0, 0, 2800000, 0, 0, 0, 3300000, 3400000, 3500000,
201};
202
203static const u32 vefuse_voltages[] = {
204 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1700000, 1800000, 1900000, 2000000,
205};
206
207static const u32 vxo22_voltages[] = {
208 1800000, 0, 0, 0, 2200000,
209};
210
211static const u32 vrfck_voltages[] = {
212 0, 0, 1500000, 0, 0, 0, 0, 1600000, 0, 0, 0, 0, 1700000,
213};
214
215static const u32 vio28_voltages[] = {
216 0, 0, 0, 0, 0, 0, 0, 0, 0, 2800000, 2900000, 3000000, 3100000, 3300000,
217};
218
219static const u32 vemc_voltages[] = {
220 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2900000, 3000000, 0, 3300000,
221};
222
223static const u32 va12_voltages[] = {
224 0, 0, 0, 0, 0, 0, 1200000, 1300000,
225};
226
227static const u32 va09_voltages[] = {
228 0, 0, 800000, 900000, 0, 0, 1200000,
229};
230
231static const u32 vrf18_voltages[] = {
232 0, 0, 0, 0, 0, 1700000, 1800000, 1810000,
233};
234
235static const u32 vbbck_voltages[] = {
236 0, 0, 0, 0, 1100000, 0, 0, 0, 1150000, 0, 0, 0, 1200000,
237};
238
239static const u32 vsim2_voltages[] = {
240 0, 0, 0, 1700000, 1800000, 0, 0, 0, 2700000, 0, 0, 3000000, 3100000,
241};
242
243static inline unsigned int mt6359_map_mode(unsigned int mode)
244{
245 switch (mode) {
246 case MT6359_BUCK_MODE_NORMAL:
247 return REGULATOR_MODE_NORMAL;
248 case MT6359_BUCK_MODE_FORCE_PWM:
249 return REGULATOR_MODE_FAST;
250 case MT6359_BUCK_MODE_LP:
251 return REGULATOR_MODE_IDLE;
252 default:
253 return REGULATOR_MODE_INVALID;
254 }
255}
256
257static int mt6359_get_status(struct regulator_dev *rdev)
258{
259 int ret;
260 u32 regval;
261 struct mt6359_regulator_info *info = rdev_get_drvdata(rdev);
262
263 ret = regmap_read(rdev->regmap, info->status_reg, &regval);
264 if (ret != 0) {
265 dev_err(&rdev->dev, "Failed to get enable reg: %d\n", ret);
266 return ret;
267 }
268
269 if (regval & info->qi)
270 return REGULATOR_STATUS_ON;
271 else
272 return REGULATOR_STATUS_OFF;
273}
274
275static unsigned int mt6359_regulator_get_mode(struct regulator_dev *rdev)
276{
277 struct mt6359_regulator_info *info = rdev_get_drvdata(rdev);
278 int ret, regval;
279
280 ret = regmap_read(rdev->regmap, info->modeset_reg, &regval);
281 if (ret != 0) {
282 dev_err(&rdev->dev,
283 "Failed to get mt6359 buck mode: %d\n", ret);
284 return ret;
285 }
286
287 if ((regval & info->modeset_mask) >> info->modeset_shift ==
288 MT6359_BUCK_MODE_FORCE_PWM)
289 return REGULATOR_MODE_FAST;
290
291 ret = regmap_read(rdev->regmap, info->lp_mode_reg, &regval);
292 if (ret != 0) {
293 dev_err(&rdev->dev,
294 "Failed to get mt6359 buck lp mode: %d\n", ret);
295 return ret;
296 }
297
298 if (regval & info->lp_mode_mask)
299 return REGULATOR_MODE_IDLE;
300 else
301 return REGULATOR_MODE_NORMAL;
302}
303
304static int mt6359_regulator_set_mode(struct regulator_dev *rdev,
305 unsigned int mode)
306{
307 struct mt6359_regulator_info *info = rdev_get_drvdata(rdev);
308 int ret = 0, val;
309 int curr_mode;
310
311 curr_mode = mt6359_regulator_get_mode(rdev);
312 switch (mode) {
313 case REGULATOR_MODE_FAST:
314 val = MT6359_BUCK_MODE_FORCE_PWM;
315 val <<= info->modeset_shift;
316 ret = regmap_update_bits(rdev->regmap,
317 info->modeset_reg,
318 info->modeset_mask,
319 val);
320 break;
321 case REGULATOR_MODE_NORMAL:
322 if (curr_mode == REGULATOR_MODE_FAST) {
323 val = MT6359_BUCK_MODE_AUTO;
324 val <<= info->modeset_shift;
325 ret = regmap_update_bits(rdev->regmap,
326 info->modeset_reg,
327 info->modeset_mask,
328 val);
329 } else if (curr_mode == REGULATOR_MODE_IDLE) {
330 val = MT6359_BUCK_MODE_NORMAL;
331 val <<= info->lp_mode_shift;
332 ret = regmap_update_bits(rdev->regmap,
333 info->lp_mode_reg,
334 info->lp_mode_mask,
335 val);
336 udelay(100);
337 }
338 break;
339 case REGULATOR_MODE_IDLE:
340 val = MT6359_BUCK_MODE_LP >> 1;
341 val <<= info->lp_mode_shift;
342 ret = regmap_update_bits(rdev->regmap,
343 info->lp_mode_reg,
344 info->lp_mode_mask,
345 val);
346 break;
347 default:
348 return -EINVAL;
349 }
350
351 if (ret != 0) {
352 dev_err(&rdev->dev,
353 "Failed to set mt6359 buck mode: %d\n", ret);
354 }
355
356 return ret;
357}
358
359static const struct regulator_ops mt6359_volt_range_ops = {
360 .list_voltage = regulator_list_voltage_linear_range,
361 .map_voltage = regulator_map_voltage_linear_range,
362 .set_voltage_sel = regulator_set_voltage_sel_regmap,
363 .get_voltage_sel = regulator_get_voltage_sel_regmap,
364 .set_voltage_time_sel = regulator_set_voltage_time_sel,
365 .enable = regulator_enable_regmap,
366 .disable = regulator_disable_regmap,
367 .is_enabled = regulator_is_enabled_regmap,
368 .get_status = mt6359_get_status,
369 .set_mode = mt6359_regulator_set_mode,
370 .get_mode = mt6359_regulator_get_mode,
371};
372
373static const struct regulator_ops mt6359_volt_table_ops = {
374 .list_voltage = regulator_list_voltage_table,
375 .map_voltage = regulator_map_voltage_iterate,
376 .set_voltage_sel = regulator_set_voltage_sel_regmap,
377 .get_voltage_sel = regulator_get_voltage_sel_regmap,
378 .set_voltage_time_sel = regulator_set_voltage_time_sel,
379 .enable = regulator_enable_regmap,
380 .disable = regulator_disable_regmap,
381 .is_enabled = regulator_is_enabled_regmap,
382 .get_status = mt6359_get_status,
383};
384
385static const struct regulator_ops mt6359_volt_fixed_ops = {
386 .enable = regulator_enable_regmap,
387 .disable = regulator_disable_regmap,
388 .is_enabled = regulator_is_enabled_regmap,
389 .get_status = mt6359_get_status,
390};
391
392/* The array is indexed by id(MT6359_ID_XXX) */
393static struct mt6359_regulator_info mt6359_regulators[] = {
394 MT6359_BUCK("buck_vs1", VS1, 800000, 2200000, 12500, 0,
395 mt_volt_range1, MT6359_RG_BUCK_VS1_EN_ADDR,
396 MT6359_DA_VS1_EN_ADDR, MT6359_RG_BUCK_VS1_VOSEL_ADDR,
397 MT6359_RG_BUCK_VS1_VOSEL_MASK <<
398 MT6359_RG_BUCK_VS1_VOSEL_SHIFT,
399 MT6359_RG_BUCK_VS1_LP_ADDR, MT6359_RG_BUCK_VS1_LP_SHIFT,
400 MT6359_RG_VS1_FPWM_ADDR, MT6359_RG_VS1_FPWM_SHIFT),
401 MT6359_BUCK("buck_vgpu11", VGPU11, 400000, 1193750, 6250, 0,
402 mt_volt_range2, MT6359_RG_BUCK_VGPU11_EN_ADDR,
403 MT6359_DA_VGPU11_EN_ADDR, MT6359_RG_BUCK_VGPU11_VOSEL_ADDR,
404 MT6359_RG_BUCK_VGPU11_VOSEL_MASK <<
405 MT6359_RG_BUCK_VGPU11_VOSEL_SHIFT,
406 MT6359_RG_BUCK_VGPU11_LP_ADDR,
407 MT6359_RG_BUCK_VGPU11_LP_SHIFT,
408 MT6359_RG_VGPU11_FCCM_ADDR, MT6359_RG_VGPU11_FCCM_SHIFT),
409 MT6359_BUCK("buck_vmodem", VMODEM, 400000, 1100000, 6250, 0,
410 mt_volt_range3, MT6359_RG_BUCK_VMODEM_EN_ADDR,
411 MT6359_DA_VMODEM_EN_ADDR, MT6359_RG_BUCK_VMODEM_VOSEL_ADDR,
412 MT6359_RG_BUCK_VMODEM_VOSEL_MASK <<
413 MT6359_RG_BUCK_VMODEM_VOSEL_SHIFT,
414 MT6359_RG_BUCK_VMODEM_LP_ADDR,
415 MT6359_RG_BUCK_VMODEM_LP_SHIFT,
416 MT6359_RG_VMODEM_FCCM_ADDR, MT6359_RG_VMODEM_FCCM_SHIFT),
417 MT6359_BUCK("buck_vpu", VPU, 400000, 1193750, 6250, 0,
418 mt_volt_range2, MT6359_RG_BUCK_VPU_EN_ADDR,
419 MT6359_DA_VPU_EN_ADDR, MT6359_RG_BUCK_VPU_VOSEL_ADDR,
420 MT6359_RG_BUCK_VPU_VOSEL_MASK <<
421 MT6359_RG_BUCK_VPU_VOSEL_SHIFT,
422 MT6359_RG_BUCK_VPU_LP_ADDR, MT6359_RG_BUCK_VPU_LP_SHIFT,
423 MT6359_RG_VPU_FCCM_ADDR, MT6359_RG_VPU_FCCM_SHIFT),
424 MT6359_BUCK("buck_vcore", VCORE, 400000, 1193750, 6250, 0,
425 mt_volt_range2, MT6359_RG_BUCK_VCORE_EN_ADDR,
426 MT6359_DA_VCORE_EN_ADDR, MT6359_RG_BUCK_VCORE_VOSEL_ADDR,
427 MT6359_RG_BUCK_VCORE_VOSEL_MASK <<
428 MT6359_RG_BUCK_VCORE_VOSEL_SHIFT,
429 MT6359_RG_BUCK_VCORE_LP_ADDR, MT6359_RG_BUCK_VCORE_LP_SHIFT,
430 MT6359_RG_VCORE_FCCM_ADDR, MT6359_RG_VCORE_FCCM_SHIFT),
431 MT6359_BUCK("buck_vs2", VS2, 800000, 1600000, 12500, 0,
432 mt_volt_range4, MT6359_RG_BUCK_VS2_EN_ADDR,
433 MT6359_DA_VS2_EN_ADDR, MT6359_RG_BUCK_VS2_VOSEL_ADDR,
434 MT6359_RG_BUCK_VS2_VOSEL_MASK <<
435 MT6359_RG_BUCK_VS2_VOSEL_SHIFT,
436 MT6359_RG_BUCK_VS2_LP_ADDR, MT6359_RG_BUCK_VS2_LP_SHIFT,
437 MT6359_RG_VS2_FPWM_ADDR, MT6359_RG_VS2_FPWM_SHIFT),
438 MT6359_BUCK("buck_vpa", VPA, 500000, 3650000, 50000, 0,
439 mt_volt_range5, MT6359_RG_BUCK_VPA_EN_ADDR,
440 MT6359_DA_VPA_EN_ADDR, MT6359_RG_BUCK_VPA_VOSEL_ADDR,
441 MT6359_RG_BUCK_VPA_VOSEL_MASK <<
442 MT6359_RG_BUCK_VPA_VOSEL_SHIFT,
443 MT6359_RG_BUCK_VPA_LP_ADDR, MT6359_RG_BUCK_VPA_LP_SHIFT,
444 MT6359_RG_VPA_MODESET_ADDR, MT6359_RG_VPA_MODESET_SHIFT),
445 MT6359_BUCK("buck_vproc2", VPROC2, 400000, 1193750, 6250, 0,
446 mt_volt_range2, MT6359_RG_BUCK_VPROC2_EN_ADDR,
447 MT6359_DA_VPROC2_EN_ADDR, MT6359_RG_BUCK_VPROC2_VOSEL_ADDR,
448 MT6359_RG_BUCK_VPROC2_VOSEL_MASK <<
449 MT6359_RG_BUCK_VPROC2_VOSEL_SHIFT,
450 MT6359_RG_BUCK_VPROC2_LP_ADDR,
451 MT6359_RG_BUCK_VPROC2_LP_SHIFT,
452 MT6359_RG_VPROC2_FCCM_ADDR, MT6359_RG_VPROC2_FCCM_SHIFT),
453 MT6359_BUCK("buck_vproc1", VPROC1, 400000, 1193750, 6250, 0,
454 mt_volt_range2, MT6359_RG_BUCK_VPROC1_EN_ADDR,
455 MT6359_DA_VPROC1_EN_ADDR, MT6359_RG_BUCK_VPROC1_VOSEL_ADDR,
456 MT6359_RG_BUCK_VPROC1_VOSEL_MASK <<
457 MT6359_RG_BUCK_VPROC1_VOSEL_SHIFT,
458 MT6359_RG_BUCK_VPROC1_LP_ADDR,
459 MT6359_RG_BUCK_VPROC1_LP_SHIFT,
460 MT6359_RG_VPROC1_FCCM_ADDR, MT6359_RG_VPROC1_FCCM_SHIFT),
461 MT6359_BUCK("buck_vcore_sshub", VCORE_SSHUB, 400000, 1193750, 6250, 0,
462 mt_volt_range2, MT6359_RG_BUCK_VCORE_SSHUB_EN_ADDR,
463 MT6359_DA_VCORE_EN_ADDR,
464 MT6359_RG_BUCK_VCORE_SSHUB_VOSEL_ADDR,
465 MT6359_RG_BUCK_VCORE_SSHUB_VOSEL_MASK <<
466 MT6359_RG_BUCK_VCORE_SSHUB_VOSEL_SHIFT,
467 MT6359_RG_BUCK_VCORE_LP_ADDR, MT6359_RG_BUCK_VCORE_LP_SHIFT,
468 MT6359_RG_VCORE_FCCM_ADDR, MT6359_RG_VCORE_FCCM_SHIFT),
469 MT6359_REG_FIXED("ldo_vaud18", VAUD18, MT6359_RG_LDO_VAUD18_EN_ADDR,
470 MT6359_DA_VAUD18_B_EN_ADDR, 1800000),
471 MT6359_LDO("ldo_vsim1", VSIM1, vsim1_voltages,
472 MT6359_RG_LDO_VSIM1_EN_ADDR, MT6359_RG_LDO_VSIM1_EN_SHIFT,
473 MT6359_DA_VSIM1_B_EN_ADDR, MT6359_RG_VSIM1_VOSEL_ADDR,
474 MT6359_RG_VSIM1_VOSEL_MASK << MT6359_RG_VSIM1_VOSEL_SHIFT,
475 480),
476 MT6359_LDO("ldo_vibr", VIBR, vibr_voltages,
477 MT6359_RG_LDO_VIBR_EN_ADDR, MT6359_RG_LDO_VIBR_EN_SHIFT,
478 MT6359_DA_VIBR_B_EN_ADDR, MT6359_RG_VIBR_VOSEL_ADDR,
479 MT6359_RG_VIBR_VOSEL_MASK << MT6359_RG_VIBR_VOSEL_SHIFT,
480 240),
481 MT6359_LDO("ldo_vrf12", VRF12, vrf12_voltages,
482 MT6359_RG_LDO_VRF12_EN_ADDR, MT6359_RG_LDO_VRF12_EN_SHIFT,
483 MT6359_DA_VRF12_B_EN_ADDR, MT6359_RG_VRF12_VOSEL_ADDR,
484 MT6359_RG_VRF12_VOSEL_MASK << MT6359_RG_VRF12_VOSEL_SHIFT,
485 120),
486 MT6359_REG_FIXED("ldo_vusb", VUSB, MT6359_RG_LDO_VUSB_EN_0_ADDR,
487 MT6359_DA_VUSB_B_EN_ADDR, 3000000),
488 MT6359_LDO_LINEAR("ldo_vsram_proc2", VSRAM_PROC2, 500000, 1293750, 6250,
489 0, mt_volt_range6, MT6359_RG_LDO_VSRAM_PROC2_EN_ADDR,
490 MT6359_DA_VSRAM_PROC2_B_EN_ADDR,
491 MT6359_RG_LDO_VSRAM_PROC2_VOSEL_ADDR,
492 MT6359_RG_LDO_VSRAM_PROC2_VOSEL_MASK <<
493 MT6359_RG_LDO_VSRAM_PROC2_VOSEL_SHIFT),
494 MT6359_LDO("ldo_vio18", VIO18, volt18_voltages,
495 MT6359_RG_LDO_VIO18_EN_ADDR, MT6359_RG_LDO_VIO18_EN_SHIFT,
496 MT6359_DA_VIO18_B_EN_ADDR, MT6359_RG_VIO18_VOSEL_ADDR,
497 MT6359_RG_VIO18_VOSEL_MASK << MT6359_RG_VIO18_VOSEL_SHIFT,
498 960),
499 MT6359_LDO("ldo_vcamio", VCAMIO, volt18_voltages,
500 MT6359_RG_LDO_VCAMIO_EN_ADDR, MT6359_RG_LDO_VCAMIO_EN_SHIFT,
501 MT6359_DA_VCAMIO_B_EN_ADDR, MT6359_RG_VCAMIO_VOSEL_ADDR,
502 MT6359_RG_VCAMIO_VOSEL_MASK << MT6359_RG_VCAMIO_VOSEL_SHIFT,
503 1290),
504 MT6359_REG_FIXED("ldo_vcn18", VCN18, MT6359_RG_LDO_VCN18_EN_ADDR,
505 MT6359_DA_VCN18_B_EN_ADDR, 1800000),
506 MT6359_REG_FIXED("ldo_vfe28", VFE28, MT6359_RG_LDO_VFE28_EN_ADDR,
507 MT6359_DA_VFE28_B_EN_ADDR, 2800000),
508 MT6359_LDO("ldo_vcn13", VCN13, vcn13_voltages,
509 MT6359_RG_LDO_VCN13_EN_ADDR, MT6359_RG_LDO_VCN13_EN_SHIFT,
510 MT6359_DA_VCN13_B_EN_ADDR, MT6359_RG_VCN13_VOSEL_ADDR,
511 MT6359_RG_VCN13_VOSEL_MASK << MT6359_RG_VCN13_VOSEL_SHIFT,
512 240),
513 MT6359_LDO("ldo_vcn33_1_bt", VCN33_1_BT, vcn33_voltages,
514 MT6359_RG_LDO_VCN33_1_EN_0_ADDR,
515 MT6359_RG_LDO_VCN33_1_EN_0_SHIFT,
516 MT6359_DA_VCN33_1_B_EN_ADDR, MT6359_RG_VCN33_1_VOSEL_ADDR,
517 MT6359_RG_VCN33_1_VOSEL_MASK <<
518 MT6359_RG_VCN33_1_VOSEL_SHIFT, 240),
519 MT6359_LDO("ldo_vcn33_1_wifi", VCN33_1_WIFI, vcn33_voltages,
520 MT6359_RG_LDO_VCN33_1_EN_1_ADDR,
521 MT6359_RG_LDO_VCN33_1_EN_1_SHIFT,
522 MT6359_DA_VCN33_1_B_EN_ADDR, MT6359_RG_VCN33_1_VOSEL_ADDR,
523 MT6359_RG_VCN33_1_VOSEL_MASK <<
524 MT6359_RG_VCN33_1_VOSEL_SHIFT, 240),
525 MT6359_REG_FIXED("ldo_vaux18", VAUX18, MT6359_RG_LDO_VAUX18_EN_ADDR,
526 MT6359_DA_VAUX18_B_EN_ADDR, 1800000),
527 MT6359_LDO_LINEAR("ldo_vsram_others", VSRAM_OTHERS, 500000, 1293750,
528 6250, 0, mt_volt_range6,
529 MT6359_RG_LDO_VSRAM_OTHERS_EN_ADDR,
530 MT6359_DA_VSRAM_OTHERS_B_EN_ADDR,
531 MT6359_RG_LDO_VSRAM_OTHERS_VOSEL_ADDR,
532 MT6359_RG_LDO_VSRAM_OTHERS_VOSEL_MASK <<
533 MT6359_RG_LDO_VSRAM_OTHERS_VOSEL_SHIFT),
534 MT6359_LDO("ldo_vefuse", VEFUSE, vefuse_voltages,
535 MT6359_RG_LDO_VEFUSE_EN_ADDR, MT6359_RG_LDO_VEFUSE_EN_SHIFT,
536 MT6359_DA_VEFUSE_B_EN_ADDR, MT6359_RG_VEFUSE_VOSEL_ADDR,
537 MT6359_RG_VEFUSE_VOSEL_MASK << MT6359_RG_VEFUSE_VOSEL_SHIFT,
538 240),
539 MT6359_LDO("ldo_vxo22", VXO22, vxo22_voltages,
540 MT6359_RG_LDO_VXO22_EN_ADDR, MT6359_RG_LDO_VXO22_EN_SHIFT,
541 MT6359_DA_VXO22_B_EN_ADDR, MT6359_RG_VXO22_VOSEL_ADDR,
542 MT6359_RG_VXO22_VOSEL_MASK << MT6359_RG_VXO22_VOSEL_SHIFT,
543 120),
544 MT6359_LDO("ldo_vrfck", VRFCK, vrfck_voltages,
545 MT6359_RG_LDO_VRFCK_EN_ADDR, MT6359_RG_LDO_VRFCK_EN_SHIFT,
546 MT6359_DA_VRFCK_B_EN_ADDR, MT6359_RG_VRFCK_VOSEL_ADDR,
547 MT6359_RG_VRFCK_VOSEL_MASK << MT6359_RG_VRFCK_VOSEL_SHIFT,
548 480),
549 MT6359_REG_FIXED("ldo_vbif28", VBIF28, MT6359_RG_LDO_VBIF28_EN_ADDR,
550 MT6359_DA_VBIF28_B_EN_ADDR, 2800000),
551 MT6359_LDO("ldo_vio28", VIO28, vio28_voltages,
552 MT6359_RG_LDO_VIO28_EN_ADDR, MT6359_RG_LDO_VIO28_EN_SHIFT,
553 MT6359_DA_VIO28_B_EN_ADDR, MT6359_RG_VIO28_VOSEL_ADDR,
554 MT6359_RG_VIO28_VOSEL_MASK << MT6359_RG_VIO28_VOSEL_SHIFT,
555 240),
556 MT6359_LDO("ldo_vemc", VEMC, vemc_voltages,
557 MT6359_RG_LDO_VEMC_EN_ADDR, MT6359_RG_LDO_VEMC_EN_SHIFT,
558 MT6359_DA_VEMC_B_EN_ADDR, MT6359_RG_VEMC_VOSEL_ADDR,
559 MT6359_RG_VEMC_VOSEL_MASK << MT6359_RG_VEMC_VOSEL_SHIFT,
560 240),
561 MT6359_LDO("ldo_vcn33_2_bt", VCN33_2_BT, vcn33_voltages,
562 MT6359_RG_LDO_VCN33_2_EN_0_ADDR,
563 MT6359_RG_LDO_VCN33_2_EN_0_SHIFT,
564 MT6359_DA_VCN33_2_B_EN_ADDR, MT6359_RG_VCN33_2_VOSEL_ADDR,
565 MT6359_RG_VCN33_2_VOSEL_MASK <<
566 MT6359_RG_VCN33_2_VOSEL_SHIFT, 240),
567 MT6359_LDO("ldo_vcn33_2_wifi", VCN33_2_WIFI, vcn33_voltages,
568 MT6359_RG_LDO_VCN33_2_EN_1_ADDR,
569 MT6359_RG_LDO_VCN33_2_EN_1_SHIFT,
570 MT6359_DA_VCN33_2_B_EN_ADDR, MT6359_RG_VCN33_2_VOSEL_ADDR,
571 MT6359_RG_VCN33_2_VOSEL_MASK <<
572 MT6359_RG_VCN33_2_VOSEL_SHIFT, 240),
573 MT6359_LDO("ldo_va12", VA12, va12_voltages,
574 MT6359_RG_LDO_VA12_EN_ADDR, MT6359_RG_LDO_VA12_EN_SHIFT,
575 MT6359_DA_VA12_B_EN_ADDR, MT6359_RG_VA12_VOSEL_ADDR,
576 MT6359_RG_VA12_VOSEL_MASK << MT6359_RG_VA12_VOSEL_SHIFT,
577 240),
578 MT6359_LDO("ldo_va09", VA09, va09_voltages,
579 MT6359_RG_LDO_VA09_EN_ADDR, MT6359_RG_LDO_VA09_EN_SHIFT,
580 MT6359_DA_VA09_B_EN_ADDR, MT6359_RG_VA09_VOSEL_ADDR,
581 MT6359_RG_VA09_VOSEL_MASK << MT6359_RG_VA09_VOSEL_SHIFT,
582 240),
583 MT6359_LDO("ldo_vrf18", VRF18, vrf18_voltages,
584 MT6359_RG_LDO_VRF18_EN_ADDR, MT6359_RG_LDO_VRF18_EN_SHIFT,
585 MT6359_DA_VRF18_B_EN_ADDR, MT6359_RG_VRF18_VOSEL_ADDR,
586 MT6359_RG_VRF18_VOSEL_MASK << MT6359_RG_VRF18_VOSEL_SHIFT,
587 120),
588 MT6359_LDO_LINEAR("ldo_vsram_md", VSRAM_MD, 500000, 1100000, 6250,
589 0, mt_volt_range7, MT6359_RG_LDO_VSRAM_MD_EN_ADDR,
590 MT6359_DA_VSRAM_MD_B_EN_ADDR,
591 MT6359_RG_LDO_VSRAM_MD_VOSEL_ADDR,
592 MT6359_RG_LDO_VSRAM_MD_VOSEL_MASK <<
593 MT6359_RG_LDO_VSRAM_MD_VOSEL_SHIFT),
594 MT6359_LDO("ldo_vufs", VUFS, volt18_voltages,
595 MT6359_RG_LDO_VUFS_EN_ADDR, MT6359_RG_LDO_VUFS_EN_SHIFT,
596 MT6359_DA_VUFS_B_EN_ADDR, MT6359_RG_VUFS_VOSEL_ADDR,
597 MT6359_RG_VUFS_VOSEL_MASK << MT6359_RG_VUFS_VOSEL_SHIFT,
598 1920),
599 MT6359_LDO("ldo_vm18", VM18, volt18_voltages,
600 MT6359_RG_LDO_VM18_EN_ADDR, MT6359_RG_LDO_VM18_EN_SHIFT,
601 MT6359_DA_VM18_B_EN_ADDR, MT6359_RG_VM18_VOSEL_ADDR,
602 MT6359_RG_VM18_VOSEL_MASK << MT6359_RG_VM18_VOSEL_SHIFT,
603 1920),
604 MT6359_LDO("ldo_vbbck", VBBCK, vbbck_voltages,
605 MT6359_RG_LDO_VBBCK_EN_ADDR, MT6359_RG_LDO_VBBCK_EN_SHIFT,
606 MT6359_DA_VBBCK_B_EN_ADDR, MT6359_RG_VBBCK_VOSEL_ADDR,
607 MT6359_RG_VBBCK_VOSEL_MASK << MT6359_RG_VBBCK_VOSEL_SHIFT,
608 240),
609 MT6359_LDO_LINEAR("ldo_vsram_proc1", VSRAM_PROC1, 500000, 1293750, 6250,
610 0, mt_volt_range6, MT6359_RG_LDO_VSRAM_PROC1_EN_ADDR,
611 MT6359_DA_VSRAM_PROC1_B_EN_ADDR,
612 MT6359_RG_LDO_VSRAM_PROC1_VOSEL_ADDR,
613 MT6359_RG_LDO_VSRAM_PROC1_VOSEL_MASK <<
614 MT6359_RG_LDO_VSRAM_PROC1_VOSEL_SHIFT),
615 MT6359_LDO("ldo_vsim2", VSIM2, vsim2_voltages,
616 MT6359_RG_LDO_VSIM2_EN_ADDR, MT6359_RG_LDO_VSIM2_EN_SHIFT,
617 MT6359_DA_VSIM2_B_EN_ADDR, MT6359_RG_VSIM2_VOSEL_ADDR,
618 MT6359_RG_VSIM2_VOSEL_MASK << MT6359_RG_VSIM2_VOSEL_SHIFT,
619 480),
620 MT6359_LDO_LINEAR("ldo_vsram_others_sshub", VSRAM_OTHERS_SSHUB,
621 500000, 1293750, 6250, 0, mt_volt_range6,
622 MT6359_RG_LDO_VSRAM_OTHERS_SSHUB_EN_ADDR,
623 MT6359_DA_VSRAM_OTHERS_B_EN_ADDR,
624 MT6359_RG_LDO_VSRAM_OTHERS_SSHUB_VOSEL_ADDR,
625 MT6359_RG_LDO_VSRAM_OTHERS_SSHUB_VOSEL_MASK <<
626 MT6359_RG_LDO_VSRAM_OTHERS_SSHUB_VOSEL_SHIFT),
627};
628
629static int mt6359_regulator_probe(struct platform_device *pdev)
630{
631 struct mt6397_chip *mt6397 = dev_get_drvdata(pdev->dev.parent);
632 struct regulator_config config = {};
633 struct regulator_dev *rdev;
634 int i;
635
636 config.dev = mt6397->dev;
637 config.regmap = mt6397->regmap;
638 for (i = 0; i < MT6359_MAX_REGULATOR; i++) {
639 config.driver_data = &mt6359_regulators[i];
640 rdev = devm_regulator_register(&pdev->dev, &mt6359_regulators[i].desc, &config);
641 if (IS_ERR(rdev)) {
642 dev_err(&pdev->dev, "failed to register %s\n",
643 mt6359_regulators[i].desc.name);
644 return PTR_ERR(rdev);
645 }
646 }
647
648 return 0;
649}
650
651static const struct platform_device_id mt6359_platform_ids[] = {
652 {"mt6359-regulator", 0},
653 { /* sentinel */ },
654};
655MODULE_DEVICE_TABLE(platform, mt6359_platform_ids);
656
657static struct platform_driver mt6359_regulator_driver = {
658 .driver = {
659 .name = "mt6359-regulator",
660 },
661 .probe = mt6359_regulator_probe,
662 .id_table = mt6359_platform_ids,
663};
664
665module_platform_driver(mt6359_regulator_driver);
666
667MODULE_AUTHOR("Wen Su <wen.su@mediatek.com>");
668MODULE_DESCRIPTION("Regulator Driver for MediaTek MT6359 PMIC");
669MODULE_LICENSE("GPL");