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Benjamin Gaignardd7a131d2017-12-05 15:57:21 +01001// SPDX-License-Identifier: GPL-2.0
Benjamin Gaignard7edf7362017-01-20 10:15:05 +01002/*
3 * Copyright (C) STMicroelectronics 2016
4 *
5 * Author: Gerald Baeza <gerald.baeza@st.com>
6 *
Benjamin Gaignard7edf7362017-01-20 10:15:05 +01007 * Inspired by timer-stm32.c from Maxime Coquelin
8 * pwm-atmel.c from Bo Shen
9 */
10
11#include <linux/mfd/stm32-timers.h>
12#include <linux/module.h>
13#include <linux/of.h>
14#include <linux/platform_device.h>
15#include <linux/pwm.h>
16
17#define CCMR_CHANNEL_SHIFT 8
18#define CCMR_CHANNEL_MASK 0xFF
19#define MAX_BREAKINPUT 2
20
21struct stm32_pwm {
22 struct pwm_chip chip;
23 struct device *dev;
24 struct clk *clk;
25 struct regmap *regmap;
26 u32 max_arr;
27 bool have_complementary_output;
28};
29
30struct stm32_breakinput {
31 u32 index;
32 u32 level;
33 u32 filter;
34};
35
36static inline struct stm32_pwm *to_stm32_pwm_dev(struct pwm_chip *chip)
37{
38 return container_of(chip, struct stm32_pwm, chip);
39}
40
41static u32 active_channels(struct stm32_pwm *dev)
42{
43 u32 ccer;
44
45 regmap_read(dev->regmap, TIM_CCER, &ccer);
46
47 return ccer & TIM_CCER_CCXE;
48}
49
50static int write_ccrx(struct stm32_pwm *dev, int ch, u32 value)
51{
52 switch (ch) {
53 case 0:
54 return regmap_write(dev->regmap, TIM_CCR1, value);
55 case 1:
56 return regmap_write(dev->regmap, TIM_CCR2, value);
57 case 2:
58 return regmap_write(dev->regmap, TIM_CCR3, value);
59 case 3:
60 return regmap_write(dev->regmap, TIM_CCR4, value);
61 }
62 return -EINVAL;
63}
64
65static int stm32_pwm_config(struct stm32_pwm *priv, int ch,
66 int duty_ns, int period_ns)
67{
68 unsigned long long prd, div, dty;
69 unsigned int prescaler = 0;
70 u32 ccmr, mask, shift;
71
72 /* Period and prescaler values depends on clock rate */
73 div = (unsigned long long)clk_get_rate(priv->clk) * period_ns;
74
75 do_div(div, NSEC_PER_SEC);
76 prd = div;
77
78 while (div > priv->max_arr) {
79 prescaler++;
80 div = prd;
81 do_div(div, prescaler + 1);
82 }
83
84 prd = div;
85
86 if (prescaler > MAX_TIM_PSC)
87 return -EINVAL;
88
89 /*
90 * All channels share the same prescaler and counter so when two
91 * channels are active at the same time we can't change them
92 */
93 if (active_channels(priv) & ~(1 << ch * 4)) {
94 u32 psc, arr;
95
96 regmap_read(priv->regmap, TIM_PSC, &psc);
97 regmap_read(priv->regmap, TIM_ARR, &arr);
98
99 if ((psc != prescaler) || (arr != prd - 1))
100 return -EBUSY;
101 }
102
103 regmap_write(priv->regmap, TIM_PSC, prescaler);
104 regmap_write(priv->regmap, TIM_ARR, prd - 1);
105 regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_ARPE, TIM_CR1_ARPE);
106
107 /* Calculate the duty cycles */
108 dty = prd * duty_ns;
109 do_div(dty, period_ns);
110
111 write_ccrx(priv, ch, dty);
112
113 /* Configure output mode */
114 shift = (ch & 0x1) * CCMR_CHANNEL_SHIFT;
115 ccmr = (TIM_CCMR_PE | TIM_CCMR_M1) << shift;
116 mask = CCMR_CHANNEL_MASK << shift;
117
118 if (ch < 2)
119 regmap_update_bits(priv->regmap, TIM_CCMR1, mask, ccmr);
120 else
121 regmap_update_bits(priv->regmap, TIM_CCMR2, mask, ccmr);
122
123 regmap_update_bits(priv->regmap, TIM_BDTR,
124 TIM_BDTR_MOE | TIM_BDTR_AOE,
125 TIM_BDTR_MOE | TIM_BDTR_AOE);
126
127 return 0;
128}
129
130static int stm32_pwm_set_polarity(struct stm32_pwm *priv, int ch,
131 enum pwm_polarity polarity)
132{
133 u32 mask;
134
135 mask = TIM_CCER_CC1P << (ch * 4);
136 if (priv->have_complementary_output)
137 mask |= TIM_CCER_CC1NP << (ch * 4);
138
139 regmap_update_bits(priv->regmap, TIM_CCER, mask,
140 polarity == PWM_POLARITY_NORMAL ? 0 : mask);
141
142 return 0;
143}
144
145static int stm32_pwm_enable(struct stm32_pwm *priv, int ch)
146{
147 u32 mask;
148 int ret;
149
150 ret = clk_enable(priv->clk);
151 if (ret)
152 return ret;
153
154 /* Enable channel */
155 mask = TIM_CCER_CC1E << (ch * 4);
156 if (priv->have_complementary_output)
157 mask |= TIM_CCER_CC1NE << (ch * 4);
158
159 regmap_update_bits(priv->regmap, TIM_CCER, mask, mask);
160
161 /* Make sure that registers are updated */
162 regmap_update_bits(priv->regmap, TIM_EGR, TIM_EGR_UG, TIM_EGR_UG);
163
164 /* Enable controller */
165 regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN, TIM_CR1_CEN);
166
167 return 0;
168}
169
170static void stm32_pwm_disable(struct stm32_pwm *priv, int ch)
171{
172 u32 mask;
173
174 /* Disable channel */
175 mask = TIM_CCER_CC1E << (ch * 4);
176 if (priv->have_complementary_output)
177 mask |= TIM_CCER_CC1NE << (ch * 4);
178
179 regmap_update_bits(priv->regmap, TIM_CCER, mask, 0);
180
181 /* When all channels are disabled, we can disable the controller */
182 if (!active_channels(priv))
183 regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN, 0);
184
185 clk_disable(priv->clk);
186}
187
188static int stm32_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
189 struct pwm_state *state)
190{
191 bool enabled;
192 struct stm32_pwm *priv = to_stm32_pwm_dev(chip);
193 int ret;
194
195 enabled = pwm->state.enabled;
196
197 if (enabled && !state->enabled) {
198 stm32_pwm_disable(priv, pwm->hwpwm);
199 return 0;
200 }
201
202 if (state->polarity != pwm->state.polarity)
203 stm32_pwm_set_polarity(priv, pwm->hwpwm, state->polarity);
204
205 ret = stm32_pwm_config(priv, pwm->hwpwm,
206 state->duty_cycle, state->period);
207 if (ret)
208 return ret;
209
210 if (!enabled && state->enabled)
211 ret = stm32_pwm_enable(priv, pwm->hwpwm);
212
213 return ret;
214}
215
216static const struct pwm_ops stm32pwm_ops = {
217 .owner = THIS_MODULE,
218 .apply = stm32_pwm_apply,
219};
220
221static int stm32_pwm_set_breakinput(struct stm32_pwm *priv,
222 int index, int level, int filter)
223{
224 u32 bke = (index == 0) ? TIM_BDTR_BKE : TIM_BDTR_BK2E;
225 int shift = (index == 0) ? TIM_BDTR_BKF_SHIFT : TIM_BDTR_BK2F_SHIFT;
226 u32 mask = (index == 0) ? TIM_BDTR_BKE | TIM_BDTR_BKP | TIM_BDTR_BKF
227 : TIM_BDTR_BK2E | TIM_BDTR_BK2P | TIM_BDTR_BK2F;
228 u32 bdtr = bke;
229
230 /*
231 * The both bits could be set since only one will be wrote
232 * due to mask value.
233 */
234 if (level)
235 bdtr |= TIM_BDTR_BKP | TIM_BDTR_BK2P;
236
237 bdtr |= (filter & TIM_BDTR_BKF_MASK) << shift;
238
239 regmap_update_bits(priv->regmap, TIM_BDTR, mask, bdtr);
240
241 regmap_read(priv->regmap, TIM_BDTR, &bdtr);
242
243 return (bdtr & bke) ? 0 : -EINVAL;
244}
245
246static int stm32_pwm_apply_breakinputs(struct stm32_pwm *priv,
247 struct device_node *np)
248{
249 struct stm32_breakinput breakinput[MAX_BREAKINPUT];
250 int nb, ret, i, array_size;
251
252 nb = of_property_count_elems_of_size(np, "st,breakinput",
253 sizeof(struct stm32_breakinput));
254
255 /*
256 * Because "st,breakinput" parameter is optional do not make probe
257 * failed if it doesn't exist.
258 */
259 if (nb <= 0)
260 return 0;
261
262 if (nb > MAX_BREAKINPUT)
263 return -EINVAL;
264
265 array_size = nb * sizeof(struct stm32_breakinput) / sizeof(u32);
266 ret = of_property_read_u32_array(np, "st,breakinput",
267 (u32 *)breakinput, array_size);
268 if (ret)
269 return ret;
270
271 for (i = 0; i < nb && !ret; i++) {
272 ret = stm32_pwm_set_breakinput(priv,
273 breakinput[i].index,
274 breakinput[i].level,
275 breakinput[i].filter);
276 }
277
278 return ret;
279}
280
281static void stm32_pwm_detect_complementary(struct stm32_pwm *priv)
282{
283 u32 ccer;
284
285 /*
286 * If complementary bit doesn't exist writing 1 will have no
287 * effect so we can detect it.
288 */
289 regmap_update_bits(priv->regmap,
290 TIM_CCER, TIM_CCER_CC1NE, TIM_CCER_CC1NE);
291 regmap_read(priv->regmap, TIM_CCER, &ccer);
292 regmap_update_bits(priv->regmap, TIM_CCER, TIM_CCER_CC1NE, 0);
293
294 priv->have_complementary_output = (ccer != 0);
295}
296
297static int stm32_pwm_detect_channels(struct stm32_pwm *priv)
298{
299 u32 ccer;
300 int npwm = 0;
301
302 /*
303 * If channels enable bits don't exist writing 1 will have no
304 * effect so we can detect and count them.
305 */
306 regmap_update_bits(priv->regmap,
307 TIM_CCER, TIM_CCER_CCXE, TIM_CCER_CCXE);
308 regmap_read(priv->regmap, TIM_CCER, &ccer);
309 regmap_update_bits(priv->regmap, TIM_CCER, TIM_CCER_CCXE, 0);
310
311 if (ccer & TIM_CCER_CC1E)
312 npwm++;
313
314 if (ccer & TIM_CCER_CC2E)
315 npwm++;
316
317 if (ccer & TIM_CCER_CC3E)
318 npwm++;
319
320 if (ccer & TIM_CCER_CC4E)
321 npwm++;
322
323 return npwm;
324}
325
326static int stm32_pwm_probe(struct platform_device *pdev)
327{
328 struct device *dev = &pdev->dev;
329 struct device_node *np = dev->of_node;
330 struct stm32_timers *ddata = dev_get_drvdata(pdev->dev.parent);
331 struct stm32_pwm *priv;
332 int ret;
333
334 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
335 if (!priv)
336 return -ENOMEM;
337
338 priv->regmap = ddata->regmap;
339 priv->clk = ddata->clk;
340 priv->max_arr = ddata->max_arr;
341
342 if (!priv->regmap || !priv->clk)
343 return -EINVAL;
344
345 ret = stm32_pwm_apply_breakinputs(priv, np);
346 if (ret)
347 return ret;
348
349 stm32_pwm_detect_complementary(priv);
350
351 priv->chip.base = -1;
352 priv->chip.dev = dev;
353 priv->chip.ops = &stm32pwm_ops;
354 priv->chip.npwm = stm32_pwm_detect_channels(priv);
355
356 ret = pwmchip_add(&priv->chip);
357 if (ret < 0)
358 return ret;
359
360 platform_set_drvdata(pdev, priv);
361
362 return 0;
363}
364
365static int stm32_pwm_remove(struct platform_device *pdev)
366{
367 struct stm32_pwm *priv = platform_get_drvdata(pdev);
368 unsigned int i;
369
370 for (i = 0; i < priv->chip.npwm; i++)
371 pwm_disable(&priv->chip.pwms[i]);
372
373 pwmchip_remove(&priv->chip);
374
375 return 0;
376}
377
378static const struct of_device_id stm32_pwm_of_match[] = {
379 { .compatible = "st,stm32-pwm", },
380 { /* end node */ },
381};
382MODULE_DEVICE_TABLE(of, stm32_pwm_of_match);
383
384static struct platform_driver stm32_pwm_driver = {
385 .probe = stm32_pwm_probe,
386 .remove = stm32_pwm_remove,
387 .driver = {
388 .name = "stm32-pwm",
389 .of_match_table = stm32_pwm_of_match,
390 },
391};
392module_platform_driver(stm32_pwm_driver);
393
394MODULE_ALIAS("platform:stm32-pwm");
395MODULE_DESCRIPTION("STMicroelectronics STM32 PWM driver");
396MODULE_LICENSE("GPL v2");