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Eli Cohene126ba92013-07-07 17:25:49 +03001/*
Saeed Mahameed6cf0a152015-04-02 17:07:30 +03002 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
Eli Cohene126ba92013-07-07 17:25:49 +03003 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33#include <linux/module.h>
34#include <rdma/ib_umem.h>
Achiad Shochat2811ba52015-12-23 18:47:24 +020035#include <rdma/ib_cache.h>
Haggai Abramovskycfb5e082016-01-14 19:12:57 +020036#include <rdma/ib_user_verbs.h>
Yishai Hadasc2e53b22017-06-08 16:15:08 +030037#include <linux/mlx5/fs.h>
Eli Cohene126ba92013-07-07 17:25:49 +030038#include "mlx5_ib.h"
Mark Blochb96c9dd2018-01-29 10:40:37 +000039#include "ib_rep.h"
Yishai Hadas443c1cf2018-09-20 21:39:26 +030040#include "cmd.h"
Eli Cohene126ba92013-07-07 17:25:49 +030041
42/* not supported currently */
43static int wq_signature;
44
45enum {
46 MLX5_IB_ACK_REQ_FREQ = 8,
47};
48
49enum {
50 MLX5_IB_DEFAULT_SCHED_QUEUE = 0x83,
51 MLX5_IB_DEFAULT_QP0_SCHED_QUEUE = 0x3f,
52 MLX5_IB_LINK_TYPE_IB = 0,
53 MLX5_IB_LINK_TYPE_ETH = 1
54};
55
56enum {
57 MLX5_IB_SQ_STRIDE = 6,
Idan Burstein064e5262018-05-02 13:16:39 +030058 MLX5_IB_SQ_UMR_INLINE_THRESHOLD = 64,
Eli Cohene126ba92013-07-07 17:25:49 +030059};
60
61static const u32 mlx5_ib_opcode[] = {
62 [IB_WR_SEND] = MLX5_OPCODE_SEND,
Erez Shitritf0313962016-02-21 16:27:17 +020063 [IB_WR_LSO] = MLX5_OPCODE_LSO,
Eli Cohene126ba92013-07-07 17:25:49 +030064 [IB_WR_SEND_WITH_IMM] = MLX5_OPCODE_SEND_IMM,
65 [IB_WR_RDMA_WRITE] = MLX5_OPCODE_RDMA_WRITE,
66 [IB_WR_RDMA_WRITE_WITH_IMM] = MLX5_OPCODE_RDMA_WRITE_IMM,
67 [IB_WR_RDMA_READ] = MLX5_OPCODE_RDMA_READ,
68 [IB_WR_ATOMIC_CMP_AND_SWP] = MLX5_OPCODE_ATOMIC_CS,
69 [IB_WR_ATOMIC_FETCH_AND_ADD] = MLX5_OPCODE_ATOMIC_FA,
70 [IB_WR_SEND_WITH_INV] = MLX5_OPCODE_SEND_INVAL,
71 [IB_WR_LOCAL_INV] = MLX5_OPCODE_UMR,
Sagi Grimberg8a187ee2015-10-13 19:11:26 +030072 [IB_WR_REG_MR] = MLX5_OPCODE_UMR,
Eli Cohene126ba92013-07-07 17:25:49 +030073 [IB_WR_MASKED_ATOMIC_CMP_AND_SWP] = MLX5_OPCODE_ATOMIC_MASKED_CS,
74 [IB_WR_MASKED_ATOMIC_FETCH_AND_ADD] = MLX5_OPCODE_ATOMIC_MASKED_FA,
75 [MLX5_IB_WR_UMR] = MLX5_OPCODE_UMR,
76};
77
Erez Shitritf0313962016-02-21 16:27:17 +020078struct mlx5_wqe_eth_pad {
79 u8 rsvd0[16];
80};
Eli Cohene126ba92013-07-07 17:25:49 +030081
Alex Veskereb49ab02016-08-28 12:25:53 +030082enum raw_qp_set_mask_map {
83 MLX5_RAW_QP_MOD_SET_RQ_Q_CTR_ID = 1UL << 0,
Bodong Wang7d29f342016-12-01 13:43:16 +020084 MLX5_RAW_QP_RATE_LIMIT = 1UL << 1,
Alex Veskereb49ab02016-08-28 12:25:53 +030085};
86
Alex Vesker0680efa2016-08-28 12:25:52 +030087struct mlx5_modify_raw_qp_param {
88 u16 operation;
Alex Veskereb49ab02016-08-28 12:25:53 +030089
90 u32 set_mask; /* raw_qp_set_mask_map */
Bodong Wang61147f32018-03-19 15:10:30 +020091
92 struct mlx5_rate_limit rl;
93
Alex Veskereb49ab02016-08-28 12:25:53 +030094 u8 rq_q_ctr_id;
Mark Blochd5ed8ac2019-03-28 15:27:38 +020095 u16 port;
Alex Vesker0680efa2016-08-28 12:25:52 +030096};
97
Maor Gottlieb89ea94a72016-06-17 15:01:38 +030098static void get_cqs(enum ib_qp_type qp_type,
99 struct ib_cq *ib_send_cq, struct ib_cq *ib_recv_cq,
100 struct mlx5_ib_cq **send_cq, struct mlx5_ib_cq **recv_cq);
101
Eli Cohene126ba92013-07-07 17:25:49 +0300102static int is_qp0(enum ib_qp_type qp_type)
103{
104 return qp_type == IB_QPT_SMI;
105}
106
Eli Cohene126ba92013-07-07 17:25:49 +0300107static int is_sqp(enum ib_qp_type qp_type)
108{
109 return is_qp0(qp_type) || is_qp1(qp_type);
110}
111
Haggai Eranc1395a22014-12-11 17:04:14 +0200112/**
Moni Shouafbeb4072019-01-22 08:48:46 +0200113 * mlx5_ib_read_user_wqe_common() - Copy a WQE (or part of) from user WQ
114 * to kernel buffer
Haggai Eranc1395a22014-12-11 17:04:14 +0200115 *
Moni Shouafbeb4072019-01-22 08:48:46 +0200116 * @umem: User space memory where the WQ is
117 * @buffer: buffer to copy to
118 * @buflen: buffer length
119 * @wqe_index: index of WQE to copy from
120 * @wq_offset: offset to start of WQ
121 * @wq_wqe_cnt: number of WQEs in WQ
122 * @wq_wqe_shift: log2 of WQE size
123 * @bcnt: number of bytes to copy
124 * @bytes_copied: number of bytes to copy (return value)
Haggai Eranc1395a22014-12-11 17:04:14 +0200125 *
Moni Shouafbeb4072019-01-22 08:48:46 +0200126 * Copies from start of WQE bcnt or less bytes.
127 * Does not gurantee to copy the entire WQE.
Haggai Eranc1395a22014-12-11 17:04:14 +0200128 *
Moni Shouafbeb4072019-01-22 08:48:46 +0200129 * Return: zero on success, or an error code.
Haggai Eranc1395a22014-12-11 17:04:14 +0200130 */
Moni Shouafbeb4072019-01-22 08:48:46 +0200131static int mlx5_ib_read_user_wqe_common(struct ib_umem *umem,
132 void *buffer,
133 u32 buflen,
134 int wqe_index,
135 int wq_offset,
136 int wq_wqe_cnt,
137 int wq_wqe_shift,
138 int bcnt,
139 size_t *bytes_copied)
Haggai Eranc1395a22014-12-11 17:04:14 +0200140{
Moni Shouafbeb4072019-01-22 08:48:46 +0200141 size_t offset = wq_offset + ((wqe_index % wq_wqe_cnt) << wq_wqe_shift);
142 size_t wq_end = wq_offset + (wq_wqe_cnt << wq_wqe_shift);
143 size_t copy_length;
Haggai Eranc1395a22014-12-11 17:04:14 +0200144 int ret;
145
Moni Shouafbeb4072019-01-22 08:48:46 +0200146 /* don't copy more than requested, more than buffer length or
147 * beyond WQ end
148 */
149 copy_length = min_t(u32, buflen, wq_end - offset);
150 copy_length = min_t(u32, copy_length, bcnt);
Haggai Eranc1395a22014-12-11 17:04:14 +0200151
Moni Shouafbeb4072019-01-22 08:48:46 +0200152 ret = ib_umem_copy_from(buffer, umem, offset, copy_length);
Haggai Eranc1395a22014-12-11 17:04:14 +0200153 if (ret)
154 return ret;
155
Moni Shouafbeb4072019-01-22 08:48:46 +0200156 if (!ret && bytes_copied)
157 *bytes_copied = copy_length;
Haggai Eranc1395a22014-12-11 17:04:14 +0200158
Moni Shouafbeb4072019-01-22 08:48:46 +0200159 return 0;
160}
Haggai Eranc1395a22014-12-11 17:04:14 +0200161
Moni Shouafbeb4072019-01-22 08:48:46 +0200162int mlx5_ib_read_user_wqe_sq(struct mlx5_ib_qp *qp,
163 int wqe_index,
164 void *buffer,
165 int buflen,
166 size_t *bc)
167{
168 struct mlx5_ib_qp_base *base = &qp->trans_qp.base;
169 struct ib_umem *umem = base->ubuffer.umem;
170 struct mlx5_ib_wq *wq = &qp->sq;
171 struct mlx5_wqe_ctrl_seg *ctrl;
172 size_t bytes_copied;
173 size_t bytes_copied2;
174 size_t wqe_length;
175 int ret;
176 int ds;
Haggai Eranc1395a22014-12-11 17:04:14 +0200177
Moni Shouafbeb4072019-01-22 08:48:46 +0200178 if (buflen < sizeof(*ctrl))
179 return -EINVAL;
180
181 /* at first read as much as possible */
182 ret = mlx5_ib_read_user_wqe_common(umem,
183 buffer,
184 buflen,
185 wqe_index,
186 wq->offset,
187 wq->wqe_cnt,
188 wq->wqe_shift,
189 buflen,
190 &bytes_copied);
Haggai Eranc1395a22014-12-11 17:04:14 +0200191 if (ret)
192 return ret;
193
Moni Shouafbeb4072019-01-22 08:48:46 +0200194 /* we need at least control segment size to proceed */
195 if (bytes_copied < sizeof(*ctrl))
196 return -EINVAL;
197
198 ctrl = buffer;
199 ds = be32_to_cpu(ctrl->qpn_ds) & MLX5_WQE_CTRL_DS_MASK;
200 wqe_length = ds * MLX5_WQE_DS_UNITS;
201
202 /* if we copied enough then we are done */
203 if (bytes_copied >= wqe_length) {
204 *bc = bytes_copied;
205 return 0;
206 }
207
208 /* otherwise this a wrapped around wqe
209 * so read the remaining bytes starting
210 * from wqe_index 0
211 */
212 ret = mlx5_ib_read_user_wqe_common(umem,
213 buffer + bytes_copied,
214 buflen - bytes_copied,
215 0,
216 wq->offset,
217 wq->wqe_cnt,
218 wq->wqe_shift,
219 wqe_length - bytes_copied,
220 &bytes_copied2);
221
222 if (ret)
223 return ret;
224 *bc = bytes_copied + bytes_copied2;
225 return 0;
226}
227
228int mlx5_ib_read_user_wqe_rq(struct mlx5_ib_qp *qp,
229 int wqe_index,
230 void *buffer,
231 int buflen,
232 size_t *bc)
233{
234 struct mlx5_ib_qp_base *base = &qp->trans_qp.base;
235 struct ib_umem *umem = base->ubuffer.umem;
236 struct mlx5_ib_wq *wq = &qp->rq;
237 size_t bytes_copied;
238 int ret;
239
240 ret = mlx5_ib_read_user_wqe_common(umem,
241 buffer,
242 buflen,
243 wqe_index,
244 wq->offset,
245 wq->wqe_cnt,
246 wq->wqe_shift,
247 buflen,
248 &bytes_copied);
249
250 if (ret)
251 return ret;
252 *bc = bytes_copied;
253 return 0;
254}
255
256int mlx5_ib_read_user_wqe_srq(struct mlx5_ib_srq *srq,
257 int wqe_index,
258 void *buffer,
259 int buflen,
260 size_t *bc)
261{
262 struct ib_umem *umem = srq->umem;
263 size_t bytes_copied;
264 int ret;
265
266 ret = mlx5_ib_read_user_wqe_common(umem,
267 buffer,
268 buflen,
269 wqe_index,
270 0,
271 srq->msrq.max,
272 srq->msrq.wqe_shift,
273 buflen,
274 &bytes_copied);
275
276 if (ret)
277 return ret;
278 *bc = bytes_copied;
279 return 0;
Haggai Eranc1395a22014-12-11 17:04:14 +0200280}
281
Eli Cohene126ba92013-07-07 17:25:49 +0300282static void mlx5_ib_qp_event(struct mlx5_core_qp *qp, int type)
283{
284 struct ib_qp *ibqp = &to_mibqp(qp)->ibqp;
285 struct ib_event event;
286
majd@mellanox.com19098df2016-01-14 19:13:03 +0200287 if (type == MLX5_EVENT_TYPE_PATH_MIG) {
288 /* This event is only valid for trans_qps */
289 to_mibqp(qp)->port = to_mibqp(qp)->trans_qp.alt_port;
290 }
Eli Cohene126ba92013-07-07 17:25:49 +0300291
292 if (ibqp->event_handler) {
293 event.device = ibqp->device;
294 event.element.qp = ibqp;
295 switch (type) {
296 case MLX5_EVENT_TYPE_PATH_MIG:
297 event.event = IB_EVENT_PATH_MIG;
298 break;
299 case MLX5_EVENT_TYPE_COMM_EST:
300 event.event = IB_EVENT_COMM_EST;
301 break;
302 case MLX5_EVENT_TYPE_SQ_DRAINED:
303 event.event = IB_EVENT_SQ_DRAINED;
304 break;
305 case MLX5_EVENT_TYPE_SRQ_LAST_WQE:
306 event.event = IB_EVENT_QP_LAST_WQE_REACHED;
307 break;
308 case MLX5_EVENT_TYPE_WQ_CATAS_ERROR:
309 event.event = IB_EVENT_QP_FATAL;
310 break;
311 case MLX5_EVENT_TYPE_PATH_MIG_FAILED:
312 event.event = IB_EVENT_PATH_MIG_ERR;
313 break;
314 case MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR:
315 event.event = IB_EVENT_QP_REQ_ERR;
316 break;
317 case MLX5_EVENT_TYPE_WQ_ACCESS_ERROR:
318 event.event = IB_EVENT_QP_ACCESS_ERR;
319 break;
320 default:
321 pr_warn("mlx5_ib: Unexpected event type %d on QP %06x\n", type, qp->qpn);
322 return;
323 }
324
325 ibqp->event_handler(&event, ibqp->qp_context);
326 }
327}
328
329static int set_rq_size(struct mlx5_ib_dev *dev, struct ib_qp_cap *cap,
330 int has_rq, struct mlx5_ib_qp *qp, struct mlx5_ib_create_qp *ucmd)
331{
332 int wqe_size;
333 int wq_size;
334
335 /* Sanity check RQ size before proceeding */
Saeed Mahameed938fe832015-05-28 22:28:41 +0300336 if (cap->max_recv_wr > (1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz)))
Eli Cohene126ba92013-07-07 17:25:49 +0300337 return -EINVAL;
338
339 if (!has_rq) {
340 qp->rq.max_gs = 0;
341 qp->rq.wqe_cnt = 0;
342 qp->rq.wqe_shift = 0;
Noa Osherovich0540d812016-06-04 15:15:32 +0300343 cap->max_recv_wr = 0;
344 cap->max_recv_sge = 0;
Eli Cohene126ba92013-07-07 17:25:49 +0300345 } else {
346 if (ucmd) {
347 qp->rq.wqe_cnt = ucmd->rq_wqe_count;
Leon Romanovsky002bf222018-04-23 17:01:53 +0300348 if (ucmd->rq_wqe_shift > BITS_PER_BYTE * sizeof(ucmd->rq_wqe_shift))
349 return -EINVAL;
Eli Cohene126ba92013-07-07 17:25:49 +0300350 qp->rq.wqe_shift = ucmd->rq_wqe_shift;
Leon Romanovsky002bf222018-04-23 17:01:53 +0300351 if ((1 << qp->rq.wqe_shift) / sizeof(struct mlx5_wqe_data_seg) < qp->wq_sig)
352 return -EINVAL;
Eli Cohene126ba92013-07-07 17:25:49 +0300353 qp->rq.max_gs = (1 << qp->rq.wqe_shift) / sizeof(struct mlx5_wqe_data_seg) - qp->wq_sig;
354 qp->rq.max_post = qp->rq.wqe_cnt;
355 } else {
356 wqe_size = qp->wq_sig ? sizeof(struct mlx5_wqe_signature_seg) : 0;
357 wqe_size += cap->max_recv_sge * sizeof(struct mlx5_wqe_data_seg);
358 wqe_size = roundup_pow_of_two(wqe_size);
359 wq_size = roundup_pow_of_two(cap->max_recv_wr) * wqe_size;
360 wq_size = max_t(int, wq_size, MLX5_SEND_WQE_BB);
361 qp->rq.wqe_cnt = wq_size / wqe_size;
Saeed Mahameed938fe832015-05-28 22:28:41 +0300362 if (wqe_size > MLX5_CAP_GEN(dev->mdev, max_wqe_sz_rq)) {
Eli Cohene126ba92013-07-07 17:25:49 +0300363 mlx5_ib_dbg(dev, "wqe_size %d, max %d\n",
364 wqe_size,
Saeed Mahameed938fe832015-05-28 22:28:41 +0300365 MLX5_CAP_GEN(dev->mdev,
366 max_wqe_sz_rq));
Eli Cohene126ba92013-07-07 17:25:49 +0300367 return -EINVAL;
368 }
369 qp->rq.wqe_shift = ilog2(wqe_size);
370 qp->rq.max_gs = (1 << qp->rq.wqe_shift) / sizeof(struct mlx5_wqe_data_seg) - qp->wq_sig;
371 qp->rq.max_post = qp->rq.wqe_cnt;
372 }
373 }
374
375 return 0;
376}
377
Erez Shitritf0313962016-02-21 16:27:17 +0200378static int sq_overhead(struct ib_qp_init_attr *attr)
Eli Cohene126ba92013-07-07 17:25:49 +0300379{
Andi Shyti618af382013-07-16 15:35:01 +0200380 int size = 0;
Eli Cohene126ba92013-07-07 17:25:49 +0300381
Erez Shitritf0313962016-02-21 16:27:17 +0200382 switch (attr->qp_type) {
Eli Cohene126ba92013-07-07 17:25:49 +0300383 case IB_QPT_XRC_INI:
Eli Cohenb125a542013-09-11 16:35:22 +0300384 size += sizeof(struct mlx5_wqe_xrc_seg);
Eli Cohene126ba92013-07-07 17:25:49 +0300385 /* fall through */
386 case IB_QPT_RC:
387 size += sizeof(struct mlx5_wqe_ctrl_seg) +
Leon Romanovsky75c1657e2016-02-11 21:09:57 +0200388 max(sizeof(struct mlx5_wqe_atomic_seg) +
389 sizeof(struct mlx5_wqe_raddr_seg),
390 sizeof(struct mlx5_wqe_umr_ctrl_seg) +
Idan Burstein064e5262018-05-02 13:16:39 +0300391 sizeof(struct mlx5_mkey_seg) +
392 MLX5_IB_SQ_UMR_INLINE_THRESHOLD /
393 MLX5_IB_UMR_OCTOWORD);
Eli Cohene126ba92013-07-07 17:25:49 +0300394 break;
395
Eli Cohenb125a542013-09-11 16:35:22 +0300396 case IB_QPT_XRC_TGT:
397 return 0;
398
Eli Cohene126ba92013-07-07 17:25:49 +0300399 case IB_QPT_UC:
Eli Cohenb125a542013-09-11 16:35:22 +0300400 size += sizeof(struct mlx5_wqe_ctrl_seg) +
Leon Romanovsky75c1657e2016-02-11 21:09:57 +0200401 max(sizeof(struct mlx5_wqe_raddr_seg),
402 sizeof(struct mlx5_wqe_umr_ctrl_seg) +
403 sizeof(struct mlx5_mkey_seg));
Eli Cohene126ba92013-07-07 17:25:49 +0300404 break;
405
406 case IB_QPT_UD:
Erez Shitritf0313962016-02-21 16:27:17 +0200407 if (attr->create_flags & IB_QP_CREATE_IPOIB_UD_LSO)
408 size += sizeof(struct mlx5_wqe_eth_pad) +
409 sizeof(struct mlx5_wqe_eth_seg);
410 /* fall through */
Eli Cohene126ba92013-07-07 17:25:49 +0300411 case IB_QPT_SMI:
Haggai Erand16e91d2016-02-29 15:45:05 +0200412 case MLX5_IB_QPT_HW_GSI:
Eli Cohenb125a542013-09-11 16:35:22 +0300413 size += sizeof(struct mlx5_wqe_ctrl_seg) +
Eli Cohene126ba92013-07-07 17:25:49 +0300414 sizeof(struct mlx5_wqe_datagram_seg);
415 break;
416
417 case MLX5_IB_QPT_REG_UMR:
Eli Cohenb125a542013-09-11 16:35:22 +0300418 size += sizeof(struct mlx5_wqe_ctrl_seg) +
Eli Cohene126ba92013-07-07 17:25:49 +0300419 sizeof(struct mlx5_wqe_umr_ctrl_seg) +
420 sizeof(struct mlx5_mkey_seg);
421 break;
422
423 default:
424 return -EINVAL;
425 }
426
427 return size;
428}
429
430static int calc_send_wqe(struct ib_qp_init_attr *attr)
431{
432 int inl_size = 0;
433 int size;
434
Erez Shitritf0313962016-02-21 16:27:17 +0200435 size = sq_overhead(attr);
Eli Cohene126ba92013-07-07 17:25:49 +0300436 if (size < 0)
437 return size;
438
439 if (attr->cap.max_inline_data) {
440 inl_size = size + sizeof(struct mlx5_wqe_inline_seg) +
441 attr->cap.max_inline_data;
442 }
443
444 size += attr->cap.max_send_sge * sizeof(struct mlx5_wqe_data_seg);
Sagi Grimberge1e66cc2014-02-23 14:19:07 +0200445 if (attr->create_flags & IB_QP_CREATE_SIGNATURE_EN &&
446 ALIGN(max_t(int, inl_size, size), MLX5_SEND_WQE_BB) < MLX5_SIG_WQE_SIZE)
447 return MLX5_SIG_WQE_SIZE;
448 else
449 return ALIGN(max_t(int, inl_size, size), MLX5_SEND_WQE_BB);
Eli Cohene126ba92013-07-07 17:25:49 +0300450}
451
Eli Cohen288c01b2016-10-27 16:36:45 +0300452static int get_send_sge(struct ib_qp_init_attr *attr, int wqe_size)
453{
454 int max_sge;
455
456 if (attr->qp_type == IB_QPT_RC)
457 max_sge = (min_t(int, wqe_size, 512) -
458 sizeof(struct mlx5_wqe_ctrl_seg) -
459 sizeof(struct mlx5_wqe_raddr_seg)) /
460 sizeof(struct mlx5_wqe_data_seg);
461 else if (attr->qp_type == IB_QPT_XRC_INI)
462 max_sge = (min_t(int, wqe_size, 512) -
463 sizeof(struct mlx5_wqe_ctrl_seg) -
464 sizeof(struct mlx5_wqe_xrc_seg) -
465 sizeof(struct mlx5_wqe_raddr_seg)) /
466 sizeof(struct mlx5_wqe_data_seg);
467 else
468 max_sge = (wqe_size - sq_overhead(attr)) /
469 sizeof(struct mlx5_wqe_data_seg);
470
471 return min_t(int, max_sge, wqe_size - sq_overhead(attr) /
472 sizeof(struct mlx5_wqe_data_seg));
473}
474
Eli Cohene126ba92013-07-07 17:25:49 +0300475static int calc_sq_size(struct mlx5_ib_dev *dev, struct ib_qp_init_attr *attr,
476 struct mlx5_ib_qp *qp)
477{
478 int wqe_size;
479 int wq_size;
480
481 if (!attr->cap.max_send_wr)
482 return 0;
483
484 wqe_size = calc_send_wqe(attr);
485 mlx5_ib_dbg(dev, "wqe_size %d\n", wqe_size);
486 if (wqe_size < 0)
487 return wqe_size;
488
Saeed Mahameed938fe832015-05-28 22:28:41 +0300489 if (wqe_size > MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq)) {
Eli Cohenb125a542013-09-11 16:35:22 +0300490 mlx5_ib_dbg(dev, "wqe_size(%d) > max_sq_desc_sz(%d)\n",
Saeed Mahameed938fe832015-05-28 22:28:41 +0300491 wqe_size, MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq));
Eli Cohene126ba92013-07-07 17:25:49 +0300492 return -EINVAL;
493 }
494
Erez Shitritf0313962016-02-21 16:27:17 +0200495 qp->max_inline_data = wqe_size - sq_overhead(attr) -
496 sizeof(struct mlx5_wqe_inline_seg);
Eli Cohene126ba92013-07-07 17:25:49 +0300497 attr->cap.max_inline_data = qp->max_inline_data;
498
Sagi Grimberge1e66cc2014-02-23 14:19:07 +0200499 if (attr->create_flags & IB_QP_CREATE_SIGNATURE_EN)
500 qp->signature_en = true;
501
Eli Cohene126ba92013-07-07 17:25:49 +0300502 wq_size = roundup_pow_of_two(attr->cap.max_send_wr * wqe_size);
503 qp->sq.wqe_cnt = wq_size / MLX5_SEND_WQE_BB;
Saeed Mahameed938fe832015-05-28 22:28:41 +0300504 if (qp->sq.wqe_cnt > (1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz))) {
Bart Van Assche1974ab92016-12-05 17:19:52 -0800505 mlx5_ib_dbg(dev, "send queue size (%d * %d / %d -> %d) exceeds limits(%d)\n",
506 attr->cap.max_send_wr, wqe_size, MLX5_SEND_WQE_BB,
Saeed Mahameed938fe832015-05-28 22:28:41 +0300507 qp->sq.wqe_cnt,
508 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz));
Eli Cohenb125a542013-09-11 16:35:22 +0300509 return -ENOMEM;
510 }
Eli Cohene126ba92013-07-07 17:25:49 +0300511 qp->sq.wqe_shift = ilog2(MLX5_SEND_WQE_BB);
Eli Cohen288c01b2016-10-27 16:36:45 +0300512 qp->sq.max_gs = get_send_sge(attr, wqe_size);
513 if (qp->sq.max_gs < attr->cap.max_send_sge)
514 return -ENOMEM;
515
516 attr->cap.max_send_sge = qp->sq.max_gs;
Eli Cohenb125a542013-09-11 16:35:22 +0300517 qp->sq.max_post = wq_size / wqe_size;
518 attr->cap.max_send_wr = qp->sq.max_post;
Eli Cohene126ba92013-07-07 17:25:49 +0300519
520 return wq_size;
521}
522
523static int set_user_buf_size(struct mlx5_ib_dev *dev,
524 struct mlx5_ib_qp *qp,
majd@mellanox.com19098df2016-01-14 19:13:03 +0200525 struct mlx5_ib_create_qp *ucmd,
majd@mellanox.com0fb2ed62016-01-14 19:13:04 +0200526 struct mlx5_ib_qp_base *base,
527 struct ib_qp_init_attr *attr)
Eli Cohene126ba92013-07-07 17:25:49 +0300528{
529 int desc_sz = 1 << qp->sq.wqe_shift;
530
Saeed Mahameed938fe832015-05-28 22:28:41 +0300531 if (desc_sz > MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq)) {
Eli Cohene126ba92013-07-07 17:25:49 +0300532 mlx5_ib_warn(dev, "desc_sz %d, max_sq_desc_sz %d\n",
Saeed Mahameed938fe832015-05-28 22:28:41 +0300533 desc_sz, MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq));
Eli Cohene126ba92013-07-07 17:25:49 +0300534 return -EINVAL;
535 }
536
Gal Pressmanaf8b38e2019-02-06 15:45:35 +0200537 if (ucmd->sq_wqe_count && !is_power_of_2(ucmd->sq_wqe_count)) {
538 mlx5_ib_warn(dev, "sq_wqe_count %d is not a power of two\n",
539 ucmd->sq_wqe_count);
Eli Cohene126ba92013-07-07 17:25:49 +0300540 return -EINVAL;
541 }
542
543 qp->sq.wqe_cnt = ucmd->sq_wqe_count;
544
Saeed Mahameed938fe832015-05-28 22:28:41 +0300545 if (qp->sq.wqe_cnt > (1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz))) {
Eli Cohene126ba92013-07-07 17:25:49 +0300546 mlx5_ib_warn(dev, "wqe_cnt %d, max_wqes %d\n",
Saeed Mahameed938fe832015-05-28 22:28:41 +0300547 qp->sq.wqe_cnt,
548 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz));
Eli Cohene126ba92013-07-07 17:25:49 +0300549 return -EINVAL;
550 }
551
Yishai Hadasc2e53b22017-06-08 16:15:08 +0300552 if (attr->qp_type == IB_QPT_RAW_PACKET ||
553 qp->flags & MLX5_IB_QP_UNDERLAY) {
majd@mellanox.com0fb2ed62016-01-14 19:13:04 +0200554 base->ubuffer.buf_size = qp->rq.wqe_cnt << qp->rq.wqe_shift;
555 qp->raw_packet_qp.sq.ubuffer.buf_size = qp->sq.wqe_cnt << 6;
556 } else {
557 base->ubuffer.buf_size = (qp->rq.wqe_cnt << qp->rq.wqe_shift) +
558 (qp->sq.wqe_cnt << 6);
559 }
Eli Cohene126ba92013-07-07 17:25:49 +0300560
561 return 0;
562}
563
564static int qp_has_rq(struct ib_qp_init_attr *attr)
565{
566 if (attr->qp_type == IB_QPT_XRC_INI ||
567 attr->qp_type == IB_QPT_XRC_TGT || attr->srq ||
568 attr->qp_type == MLX5_IB_QPT_REG_UMR ||
569 !attr->cap.max_recv_wr)
570 return 0;
571
572 return 1;
573}
574
Eli Cohen0b80c14f02017-01-03 23:55:22 +0200575enum {
576 /* this is the first blue flame register in the array of bfregs assigned
577 * to a processes. Since we do not use it for blue flame but rather
578 * regular 64 bit doorbells, we do not need a lock for maintaiing
579 * "odd/even" order
580 */
581 NUM_NON_BLUE_FLAME_BFREGS = 1,
582};
583
Eli Cohenb037c292017-01-03 23:55:26 +0200584static int max_bfregs(struct mlx5_ib_dev *dev, struct mlx5_bfreg_info *bfregi)
585{
Yishai Hadas31a78a52017-12-24 16:31:34 +0200586 return get_num_static_uars(dev, bfregi) * MLX5_NON_FP_BFREGS_PER_UAR;
Eli Cohenb037c292017-01-03 23:55:26 +0200587}
588
589static int num_med_bfreg(struct mlx5_ib_dev *dev,
590 struct mlx5_bfreg_info *bfregi)
Eli Cohenc1be5232014-01-14 17:45:12 +0200591{
592 int n;
593
Eli Cohenb037c292017-01-03 23:55:26 +0200594 n = max_bfregs(dev, bfregi) - bfregi->num_low_latency_bfregs -
595 NUM_NON_BLUE_FLAME_BFREGS;
Eli Cohenc1be5232014-01-14 17:45:12 +0200596
597 return n >= 0 ? n : 0;
598}
599
Yishai Hadas18b03622018-05-07 10:20:01 +0300600static int first_med_bfreg(struct mlx5_ib_dev *dev,
601 struct mlx5_bfreg_info *bfregi)
602{
603 return num_med_bfreg(dev, bfregi) ? 1 : -ENOMEM;
604}
605
Eli Cohenb037c292017-01-03 23:55:26 +0200606static int first_hi_bfreg(struct mlx5_ib_dev *dev,
607 struct mlx5_bfreg_info *bfregi)
Eli Cohenc1be5232014-01-14 17:45:12 +0200608{
609 int med;
Eli Cohenc1be5232014-01-14 17:45:12 +0200610
Eli Cohenb037c292017-01-03 23:55:26 +0200611 med = num_med_bfreg(dev, bfregi);
612 return ++med;
Eli Cohenc1be5232014-01-14 17:45:12 +0200613}
614
Eli Cohenb037c292017-01-03 23:55:26 +0200615static int alloc_high_class_bfreg(struct mlx5_ib_dev *dev,
616 struct mlx5_bfreg_info *bfregi)
Eli Cohene126ba92013-07-07 17:25:49 +0300617{
Eli Cohene126ba92013-07-07 17:25:49 +0300618 int i;
619
Eli Cohenb037c292017-01-03 23:55:26 +0200620 for (i = first_hi_bfreg(dev, bfregi); i < max_bfregs(dev, bfregi); i++) {
621 if (!bfregi->count[i]) {
Eli Cohen2f5ff262017-01-03 23:55:21 +0200622 bfregi->count[i]++;
Eli Cohene126ba92013-07-07 17:25:49 +0300623 return i;
624 }
625 }
626
627 return -ENOMEM;
628}
629
Eli Cohenb037c292017-01-03 23:55:26 +0200630static int alloc_med_class_bfreg(struct mlx5_ib_dev *dev,
631 struct mlx5_bfreg_info *bfregi)
Eli Cohene126ba92013-07-07 17:25:49 +0300632{
Yishai Hadas18b03622018-05-07 10:20:01 +0300633 int minidx = first_med_bfreg(dev, bfregi);
Eli Cohene126ba92013-07-07 17:25:49 +0300634 int i;
635
Yishai Hadas18b03622018-05-07 10:20:01 +0300636 if (minidx < 0)
637 return minidx;
638
639 for (i = minidx; i < first_hi_bfreg(dev, bfregi); i++) {
Eli Cohen2f5ff262017-01-03 23:55:21 +0200640 if (bfregi->count[i] < bfregi->count[minidx])
Eli Cohene126ba92013-07-07 17:25:49 +0300641 minidx = i;
Eli Cohen0b80c14f02017-01-03 23:55:22 +0200642 if (!bfregi->count[minidx])
643 break;
Eli Cohene126ba92013-07-07 17:25:49 +0300644 }
645
Eli Cohen2f5ff262017-01-03 23:55:21 +0200646 bfregi->count[minidx]++;
Eli Cohene126ba92013-07-07 17:25:49 +0300647 return minidx;
648}
649
Eli Cohenb037c292017-01-03 23:55:26 +0200650static int alloc_bfreg(struct mlx5_ib_dev *dev,
Leon Romanovskyffaf58d2018-07-08 13:50:20 +0300651 struct mlx5_bfreg_info *bfregi)
Eli Cohene126ba92013-07-07 17:25:49 +0300652{
Leon Romanovskyffaf58d2018-07-08 13:50:20 +0300653 int bfregn = -ENOMEM;
Eli Cohene126ba92013-07-07 17:25:49 +0300654
Eli Cohen2f5ff262017-01-03 23:55:21 +0200655 mutex_lock(&bfregi->lock);
Leon Romanovskyffaf58d2018-07-08 13:50:20 +0300656 if (bfregi->ver >= 2) {
657 bfregn = alloc_high_class_bfreg(dev, bfregi);
658 if (bfregn < 0)
659 bfregn = alloc_med_class_bfreg(dev, bfregi);
660 }
661
662 if (bfregn < 0) {
Eli Cohen0b80c14f02017-01-03 23:55:22 +0200663 BUILD_BUG_ON(NUM_NON_BLUE_FLAME_BFREGS != 1);
Eli Cohen2f5ff262017-01-03 23:55:21 +0200664 bfregn = 0;
665 bfregi->count[bfregn]++;
Eli Cohene126ba92013-07-07 17:25:49 +0300666 }
Eli Cohen2f5ff262017-01-03 23:55:21 +0200667 mutex_unlock(&bfregi->lock);
Eli Cohene126ba92013-07-07 17:25:49 +0300668
Eli Cohen2f5ff262017-01-03 23:55:21 +0200669 return bfregn;
Eli Cohene126ba92013-07-07 17:25:49 +0300670}
671
Yishai Hadas4ed131d2017-12-24 16:31:35 +0200672void mlx5_ib_free_bfreg(struct mlx5_ib_dev *dev, struct mlx5_bfreg_info *bfregi, int bfregn)
Eli Cohene126ba92013-07-07 17:25:49 +0300673{
Eli Cohen2f5ff262017-01-03 23:55:21 +0200674 mutex_lock(&bfregi->lock);
Eli Cohenb037c292017-01-03 23:55:26 +0200675 bfregi->count[bfregn]--;
Eli Cohen2f5ff262017-01-03 23:55:21 +0200676 mutex_unlock(&bfregi->lock);
Eli Cohene126ba92013-07-07 17:25:49 +0300677}
678
679static enum mlx5_qp_state to_mlx5_state(enum ib_qp_state state)
680{
681 switch (state) {
682 case IB_QPS_RESET: return MLX5_QP_STATE_RST;
683 case IB_QPS_INIT: return MLX5_QP_STATE_INIT;
684 case IB_QPS_RTR: return MLX5_QP_STATE_RTR;
685 case IB_QPS_RTS: return MLX5_QP_STATE_RTS;
686 case IB_QPS_SQD: return MLX5_QP_STATE_SQD;
687 case IB_QPS_SQE: return MLX5_QP_STATE_SQER;
688 case IB_QPS_ERR: return MLX5_QP_STATE_ERR;
689 default: return -1;
690 }
691}
692
693static int to_mlx5_st(enum ib_qp_type type)
694{
695 switch (type) {
696 case IB_QPT_RC: return MLX5_QP_ST_RC;
697 case IB_QPT_UC: return MLX5_QP_ST_UC;
698 case IB_QPT_UD: return MLX5_QP_ST_UD;
699 case MLX5_IB_QPT_REG_UMR: return MLX5_QP_ST_REG_UMR;
700 case IB_QPT_XRC_INI:
701 case IB_QPT_XRC_TGT: return MLX5_QP_ST_XRC;
702 case IB_QPT_SMI: return MLX5_QP_ST_QP0;
Haggai Erand16e91d2016-02-29 15:45:05 +0200703 case MLX5_IB_QPT_HW_GSI: return MLX5_QP_ST_QP1;
Moni Shouac32a4f22018-01-02 16:19:32 +0200704 case MLX5_IB_QPT_DCI: return MLX5_QP_ST_DCI;
Eli Cohene126ba92013-07-07 17:25:49 +0300705 case IB_QPT_RAW_IPV6: return MLX5_QP_ST_RAW_IPV6;
Eli Cohene126ba92013-07-07 17:25:49 +0300706 case IB_QPT_RAW_PACKET:
majd@mellanox.com0fb2ed62016-01-14 19:13:04 +0200707 case IB_QPT_RAW_ETHERTYPE: return MLX5_QP_ST_RAW_ETHERTYPE;
Eli Cohene126ba92013-07-07 17:25:49 +0300708 case IB_QPT_MAX:
709 default: return -EINVAL;
710 }
711}
712
Maor Gottlieb89ea94a72016-06-17 15:01:38 +0300713static void mlx5_ib_lock_cqs(struct mlx5_ib_cq *send_cq,
714 struct mlx5_ib_cq *recv_cq);
715static void mlx5_ib_unlock_cqs(struct mlx5_ib_cq *send_cq,
716 struct mlx5_ib_cq *recv_cq);
717
Yishai Hadas7c043e92018-06-17 13:00:03 +0300718int bfregn_to_uar_index(struct mlx5_ib_dev *dev,
Leon Romanovsky05f58ce2018-07-08 13:50:21 +0300719 struct mlx5_bfreg_info *bfregi, u32 bfregn,
Yishai Hadas7c043e92018-06-17 13:00:03 +0300720 bool dyn_bfreg)
Eli Cohene126ba92013-07-07 17:25:49 +0300721{
Leon Romanovsky05f58ce2018-07-08 13:50:21 +0300722 unsigned int bfregs_per_sys_page;
723 u32 index_of_sys_page;
724 u32 offset;
Eli Cohenb037c292017-01-03 23:55:26 +0200725
726 bfregs_per_sys_page = get_uars_per_sys_page(dev, bfregi->lib_uar_4k) *
727 MLX5_NON_FP_BFREGS_PER_UAR;
728 index_of_sys_page = bfregn / bfregs_per_sys_page;
729
Yishai Hadas1ee47ab2017-12-24 16:31:36 +0200730 if (dyn_bfreg) {
731 index_of_sys_page += bfregi->num_static_sys_pages;
Leon Romanovsky05f58ce2018-07-08 13:50:21 +0300732
733 if (index_of_sys_page >= bfregi->num_sys_pages)
734 return -EINVAL;
735
Yishai Hadas1ee47ab2017-12-24 16:31:36 +0200736 if (bfregn > bfregi->num_dyn_bfregs ||
737 bfregi->sys_pages[index_of_sys_page] == MLX5_IB_INVALID_UAR_INDEX) {
738 mlx5_ib_dbg(dev, "Invalid dynamic uar index\n");
739 return -EINVAL;
740 }
741 }
Eli Cohenb037c292017-01-03 23:55:26 +0200742
Yishai Hadas1ee47ab2017-12-24 16:31:36 +0200743 offset = bfregn % bfregs_per_sys_page / MLX5_NON_FP_BFREGS_PER_UAR;
Eli Cohenb037c292017-01-03 23:55:26 +0200744 return bfregi->sys_pages[index_of_sys_page] + offset;
Eli Cohene126ba92013-07-07 17:25:49 +0300745}
746
Jason Gunthorpeb0ea0fa2019-01-09 11:15:16 +0200747static int mlx5_ib_umem_get(struct mlx5_ib_dev *dev, struct ib_udata *udata,
majd@mellanox.com19098df2016-01-14 19:13:03 +0200748 unsigned long addr, size_t size,
Jason Gunthorpeb0ea0fa2019-01-09 11:15:16 +0200749 struct ib_umem **umem, int *npages, int *page_shift,
750 int *ncont, u32 *offset)
majd@mellanox.com19098df2016-01-14 19:13:03 +0200751{
752 int err;
753
Jason Gunthorpeb0ea0fa2019-01-09 11:15:16 +0200754 *umem = ib_umem_get(udata, addr, size, 0, 0);
majd@mellanox.com19098df2016-01-14 19:13:03 +0200755 if (IS_ERR(*umem)) {
756 mlx5_ib_dbg(dev, "umem_get failed\n");
757 return PTR_ERR(*umem);
758 }
759
Majd Dibbiny762f8992016-10-27 16:36:47 +0300760 mlx5_ib_cont_pages(*umem, addr, 0, npages, page_shift, ncont, NULL);
majd@mellanox.com19098df2016-01-14 19:13:03 +0200761
762 err = mlx5_ib_get_buf_offset(addr, *page_shift, offset);
763 if (err) {
764 mlx5_ib_warn(dev, "bad offset\n");
765 goto err_umem;
766 }
767
768 mlx5_ib_dbg(dev, "addr 0x%lx, size %zu, npages %d, page_shift %d, ncont %d, offset %d\n",
769 addr, size, *npages, *page_shift, *ncont, *offset);
770
771 return 0;
772
773err_umem:
774 ib_umem_release(*umem);
775 *umem = NULL;
776
777 return err;
778}
779
Maor Gottliebfe248c32017-05-30 10:29:14 +0300780static void destroy_user_rq(struct mlx5_ib_dev *dev, struct ib_pd *pd,
Shamir Rabinovitchbdeacab2019-03-31 19:10:06 +0300781 struct mlx5_ib_rwq *rwq, struct ib_udata *udata)
Yishai Hadas79b20a62016-05-23 15:20:50 +0300782{
Shamir Rabinovitchbdeacab2019-03-31 19:10:06 +0300783 struct mlx5_ib_ucontext *context =
784 rdma_udata_to_drv_context(
785 udata,
786 struct mlx5_ib_ucontext,
787 ibucontext);
Yishai Hadas79b20a62016-05-23 15:20:50 +0300788
Maor Gottliebfe248c32017-05-30 10:29:14 +0300789 if (rwq->create_flags & MLX5_IB_WQ_FLAGS_DELAY_DROP)
790 atomic_dec(&dev->delay_drop.rqs_cnt);
791
Yishai Hadas79b20a62016-05-23 15:20:50 +0300792 mlx5_ib_db_unmap_user(context, &rwq->db);
793 if (rwq->umem)
794 ib_umem_release(rwq->umem);
795}
796
797static int create_user_rq(struct mlx5_ib_dev *dev, struct ib_pd *pd,
Jason Gunthorpeb0ea0fa2019-01-09 11:15:16 +0200798 struct ib_udata *udata, struct mlx5_ib_rwq *rwq,
Yishai Hadas79b20a62016-05-23 15:20:50 +0300799 struct mlx5_ib_create_wq *ucmd)
800{
Shamir Rabinovitch89944452019-02-07 18:44:49 +0200801 struct mlx5_ib_ucontext *ucontext = rdma_udata_to_drv_context(
802 udata, struct mlx5_ib_ucontext, ibucontext);
Yishai Hadas79b20a62016-05-23 15:20:50 +0300803 int page_shift = 0;
804 int npages;
805 u32 offset = 0;
806 int ncont = 0;
807 int err;
808
809 if (!ucmd->buf_addr)
810 return -EINVAL;
811
Jason Gunthorpeb0ea0fa2019-01-09 11:15:16 +0200812 rwq->umem = ib_umem_get(udata, ucmd->buf_addr, rwq->buf_size, 0, 0);
Yishai Hadas79b20a62016-05-23 15:20:50 +0300813 if (IS_ERR(rwq->umem)) {
814 mlx5_ib_dbg(dev, "umem_get failed\n");
815 err = PTR_ERR(rwq->umem);
816 return err;
817 }
818
Majd Dibbiny762f8992016-10-27 16:36:47 +0300819 mlx5_ib_cont_pages(rwq->umem, ucmd->buf_addr, 0, &npages, &page_shift,
Yishai Hadas79b20a62016-05-23 15:20:50 +0300820 &ncont, NULL);
821 err = mlx5_ib_get_buf_offset(ucmd->buf_addr, page_shift,
822 &rwq->rq_page_offset);
823 if (err) {
824 mlx5_ib_warn(dev, "bad offset\n");
825 goto err_umem;
826 }
827
828 rwq->rq_num_pas = ncont;
829 rwq->page_shift = page_shift;
830 rwq->log_page_size = page_shift - MLX5_ADAPTER_PAGE_SHIFT;
831 rwq->wq_sig = !!(ucmd->flags & MLX5_WQ_FLAG_SIGNATURE);
832
833 mlx5_ib_dbg(dev, "addr 0x%llx, size %zd, npages %d, page_shift %d, ncont %d, offset %d\n",
834 (unsigned long long)ucmd->buf_addr, rwq->buf_size,
835 npages, page_shift, ncont, offset);
836
Shamir Rabinovitch89944452019-02-07 18:44:49 +0200837 err = mlx5_ib_db_map_user(ucontext, udata, ucmd->db_addr, &rwq->db);
Yishai Hadas79b20a62016-05-23 15:20:50 +0300838 if (err) {
839 mlx5_ib_dbg(dev, "map failed\n");
840 goto err_umem;
841 }
842
843 rwq->create_type = MLX5_WQ_USER;
844 return 0;
845
846err_umem:
847 ib_umem_release(rwq->umem);
848 return err;
849}
850
Eli Cohenb037c292017-01-03 23:55:26 +0200851static int adjust_bfregn(struct mlx5_ib_dev *dev,
852 struct mlx5_bfreg_info *bfregi, int bfregn)
853{
854 return bfregn / MLX5_NON_FP_BFREGS_PER_UAR * MLX5_BFREGS_PER_UAR +
855 bfregn % MLX5_NON_FP_BFREGS_PER_UAR;
856}
857
Eli Cohene126ba92013-07-07 17:25:49 +0300858static int create_user_qp(struct mlx5_ib_dev *dev, struct ib_pd *pd,
859 struct mlx5_ib_qp *qp, struct ib_udata *udata,
majd@mellanox.com0fb2ed62016-01-14 19:13:04 +0200860 struct ib_qp_init_attr *attr,
Saeed Mahameed09a7d9e2016-07-19 01:17:59 +0300861 u32 **in,
majd@mellanox.com19098df2016-01-14 19:13:03 +0200862 struct mlx5_ib_create_qp_resp *resp, int *inlen,
863 struct mlx5_ib_qp_base *base)
Eli Cohene126ba92013-07-07 17:25:49 +0300864{
865 struct mlx5_ib_ucontext *context;
866 struct mlx5_ib_create_qp ucmd;
majd@mellanox.com19098df2016-01-14 19:13:03 +0200867 struct mlx5_ib_ubuffer *ubuffer = &base->ubuffer;
Eli Cohen9e9c47d2014-01-14 17:45:21 +0200868 int page_shift = 0;
Yishai Hadas1ee47ab2017-12-24 16:31:36 +0200869 int uar_index = 0;
Eli Cohene126ba92013-07-07 17:25:49 +0300870 int npages;
Eli Cohen9e9c47d2014-01-14 17:45:21 +0200871 u32 offset = 0;
Eli Cohen2f5ff262017-01-03 23:55:21 +0200872 int bfregn;
Eli Cohen9e9c47d2014-01-14 17:45:21 +0200873 int ncont = 0;
Saeed Mahameed09a7d9e2016-07-19 01:17:59 +0300874 __be64 *pas;
875 void *qpc;
Eli Cohene126ba92013-07-07 17:25:49 +0300876 int err;
Yishai Hadas5aa37712018-11-26 08:28:38 +0200877 u16 uid;
Eli Cohene126ba92013-07-07 17:25:49 +0300878
879 err = ib_copy_from_udata(&ucmd, udata, sizeof(ucmd));
880 if (err) {
881 mlx5_ib_dbg(dev, "copy failed\n");
882 return err;
883 }
884
Shamir Rabinovitch89944452019-02-07 18:44:49 +0200885 context = rdma_udata_to_drv_context(udata, struct mlx5_ib_ucontext,
886 ibucontext);
Yishai Hadas1ee47ab2017-12-24 16:31:36 +0200887 if (ucmd.flags & MLX5_QP_FLAG_BFREG_INDEX) {
888 uar_index = bfregn_to_uar_index(dev, &context->bfregi,
889 ucmd.bfreg_index, true);
890 if (uar_index < 0)
891 return uar_index;
892
893 bfregn = MLX5_IB_INVALID_BFREG;
894 } else if (qp->flags & MLX5_IB_QP_CROSS_CHANNEL) {
895 /*
896 * TBD: should come from the verbs when we have the API
897 */
Leon Romanovsky051f2632015-12-20 12:16:11 +0200898 /* In CROSS_CHANNEL CQ and QP must use the same UAR */
Eli Cohen2f5ff262017-01-03 23:55:21 +0200899 bfregn = MLX5_CROSS_CHANNEL_BFREG;
Yishai Hadas1ee47ab2017-12-24 16:31:36 +0200900 }
Leon Romanovsky051f2632015-12-20 12:16:11 +0200901 else {
Leon Romanovskyffaf58d2018-07-08 13:50:20 +0300902 bfregn = alloc_bfreg(dev, &context->bfregi);
903 if (bfregn < 0)
904 return bfregn;
Eli Cohene126ba92013-07-07 17:25:49 +0300905 }
906
Eli Cohen2f5ff262017-01-03 23:55:21 +0200907 mlx5_ib_dbg(dev, "bfregn 0x%x, uar_index 0x%x\n", bfregn, uar_index);
Yishai Hadas1ee47ab2017-12-24 16:31:36 +0200908 if (bfregn != MLX5_IB_INVALID_BFREG)
909 uar_index = bfregn_to_uar_index(dev, &context->bfregi, bfregn,
910 false);
Eli Cohene126ba92013-07-07 17:25:49 +0300911
Haggai Eran48fea832014-05-22 14:50:11 +0300912 qp->rq.offset = 0;
913 qp->sq.wqe_shift = ilog2(MLX5_SEND_WQE_BB);
914 qp->sq.offset = qp->rq.wqe_cnt << qp->rq.wqe_shift;
915
majd@mellanox.com0fb2ed62016-01-14 19:13:04 +0200916 err = set_user_buf_size(dev, qp, &ucmd, base, attr);
Eli Cohene126ba92013-07-07 17:25:49 +0300917 if (err)
Eli Cohen2f5ff262017-01-03 23:55:21 +0200918 goto err_bfreg;
Eli Cohene126ba92013-07-07 17:25:49 +0300919
majd@mellanox.com19098df2016-01-14 19:13:03 +0200920 if (ucmd.buf_addr && ubuffer->buf_size) {
921 ubuffer->buf_addr = ucmd.buf_addr;
Jason Gunthorpeb0ea0fa2019-01-09 11:15:16 +0200922 err = mlx5_ib_umem_get(dev, udata, ubuffer->buf_addr,
923 ubuffer->buf_size, &ubuffer->umem,
924 &npages, &page_shift, &ncont, &offset);
majd@mellanox.com19098df2016-01-14 19:13:03 +0200925 if (err)
Eli Cohen2f5ff262017-01-03 23:55:21 +0200926 goto err_bfreg;
Eli Cohen9e9c47d2014-01-14 17:45:21 +0200927 } else {
majd@mellanox.com19098df2016-01-14 19:13:03 +0200928 ubuffer->umem = NULL;
Eli Cohene126ba92013-07-07 17:25:49 +0300929 }
Eli Cohene126ba92013-07-07 17:25:49 +0300930
Saeed Mahameed09a7d9e2016-07-19 01:17:59 +0300931 *inlen = MLX5_ST_SZ_BYTES(create_qp_in) +
932 MLX5_FLD_SZ_BYTES(create_qp_in, pas[0]) * ncont;
Leon Romanovsky1b9a07e2017-05-10 21:32:18 +0300933 *in = kvzalloc(*inlen, GFP_KERNEL);
Eli Cohene126ba92013-07-07 17:25:49 +0300934 if (!*in) {
935 err = -ENOMEM;
936 goto err_umem;
937 }
Eli Cohene126ba92013-07-07 17:25:49 +0300938
Yishai Hadas7422edc2018-12-23 13:12:21 +0200939 uid = (attr->qp_type != IB_QPT_XRC_TGT &&
940 attr->qp_type != IB_QPT_XRC_INI) ? to_mpd(pd)->uid : 0;
Yishai Hadas5aa37712018-11-26 08:28:38 +0200941 MLX5_SET(create_qp_in, *in, uid, uid);
Saeed Mahameed09a7d9e2016-07-19 01:17:59 +0300942 pas = (__be64 *)MLX5_ADDR_OF(create_qp_in, *in, pas);
943 if (ubuffer->umem)
944 mlx5_ib_populate_pas(dev, ubuffer->umem, page_shift, pas, 0);
945
946 qpc = MLX5_ADDR_OF(create_qp_in, *in, qpc);
947
948 MLX5_SET(qpc, qpc, log_page_size, page_shift - MLX5_ADAPTER_PAGE_SHIFT);
949 MLX5_SET(qpc, qpc, page_offset, offset);
950
951 MLX5_SET(qpc, qpc, uar_page, uar_index);
Yishai Hadas1ee47ab2017-12-24 16:31:36 +0200952 if (bfregn != MLX5_IB_INVALID_BFREG)
953 resp->bfreg_index = adjust_bfregn(dev, &context->bfregi, bfregn);
954 else
955 resp->bfreg_index = MLX5_IB_INVALID_BFREG;
Eli Cohen2f5ff262017-01-03 23:55:21 +0200956 qp->bfregn = bfregn;
Eli Cohene126ba92013-07-07 17:25:49 +0300957
Jason Gunthorpeb0ea0fa2019-01-09 11:15:16 +0200958 err = mlx5_ib_db_map_user(context, udata, ucmd.db_addr, &qp->db);
Eli Cohene126ba92013-07-07 17:25:49 +0300959 if (err) {
960 mlx5_ib_dbg(dev, "map failed\n");
961 goto err_free;
962 }
963
Jason Gunthorpe41d902c2018-04-03 10:00:53 +0300964 err = ib_copy_to_udata(udata, resp, min(udata->outlen, sizeof(*resp)));
Eli Cohene126ba92013-07-07 17:25:49 +0300965 if (err) {
966 mlx5_ib_dbg(dev, "copy failed\n");
967 goto err_unmap;
968 }
969 qp->create_type = MLX5_QP_USER;
970
971 return 0;
972
973err_unmap:
974 mlx5_ib_db_unmap_user(context, &qp->db);
975
976err_free:
Al Viro479163f2014-11-20 08:13:57 +0000977 kvfree(*in);
Eli Cohene126ba92013-07-07 17:25:49 +0300978
979err_umem:
majd@mellanox.com19098df2016-01-14 19:13:03 +0200980 if (ubuffer->umem)
981 ib_umem_release(ubuffer->umem);
Eli Cohene126ba92013-07-07 17:25:49 +0300982
Eli Cohen2f5ff262017-01-03 23:55:21 +0200983err_bfreg:
Yishai Hadas1ee47ab2017-12-24 16:31:36 +0200984 if (bfregn != MLX5_IB_INVALID_BFREG)
985 mlx5_ib_free_bfreg(dev, &context->bfregi, bfregn);
Eli Cohene126ba92013-07-07 17:25:49 +0300986 return err;
987}
988
Eli Cohenb037c292017-01-03 23:55:26 +0200989static void destroy_qp_user(struct mlx5_ib_dev *dev, struct ib_pd *pd,
Shamir Rabinovitchbdeacab2019-03-31 19:10:06 +0300990 struct mlx5_ib_qp *qp, struct mlx5_ib_qp_base *base,
991 struct ib_udata *udata)
Eli Cohene126ba92013-07-07 17:25:49 +0300992{
Shamir Rabinovitchbdeacab2019-03-31 19:10:06 +0300993 struct mlx5_ib_ucontext *context =
994 rdma_udata_to_drv_context(
995 udata,
996 struct mlx5_ib_ucontext,
997 ibucontext);
Eli Cohene126ba92013-07-07 17:25:49 +0300998
Eli Cohene126ba92013-07-07 17:25:49 +0300999 mlx5_ib_db_unmap_user(context, &qp->db);
majd@mellanox.com19098df2016-01-14 19:13:03 +02001000 if (base->ubuffer.umem)
1001 ib_umem_release(base->ubuffer.umem);
Yishai Hadas1ee47ab2017-12-24 16:31:36 +02001002
1003 /*
1004 * Free only the BFREGs which are handled by the kernel.
1005 * BFREGs of UARs allocated dynamically are handled by user.
1006 */
1007 if (qp->bfregn != MLX5_IB_INVALID_BFREG)
1008 mlx5_ib_free_bfreg(dev, &context->bfregi, qp->bfregn);
Eli Cohene126ba92013-07-07 17:25:49 +03001009}
1010
Guy Levi34f4c952018-11-26 08:15:50 +02001011/* get_sq_edge - Get the next nearby edge.
1012 *
1013 * An 'edge' is defined as the first following address after the end
1014 * of the fragment or the SQ. Accordingly, during the WQE construction
1015 * which repetitively increases the pointer to write the next data, it
1016 * simply should check if it gets to an edge.
1017 *
1018 * @sq - SQ buffer.
1019 * @idx - Stride index in the SQ buffer.
1020 *
1021 * Return:
1022 * The new edge.
1023 */
1024static void *get_sq_edge(struct mlx5_ib_wq *sq, u32 idx)
1025{
1026 void *fragment_end;
1027
1028 fragment_end = mlx5_frag_buf_get_wqe
1029 (&sq->fbc,
1030 mlx5_frag_buf_get_idx_last_contig_stride(&sq->fbc, idx));
1031
1032 return fragment_end + MLX5_SEND_WQE_BB;
1033}
1034
Eli Cohene126ba92013-07-07 17:25:49 +03001035static int create_kernel_qp(struct mlx5_ib_dev *dev,
1036 struct ib_qp_init_attr *init_attr,
1037 struct mlx5_ib_qp *qp,
Saeed Mahameed09a7d9e2016-07-19 01:17:59 +03001038 u32 **in, int *inlen,
majd@mellanox.com19098df2016-01-14 19:13:03 +02001039 struct mlx5_ib_qp_base *base)
Eli Cohene126ba92013-07-07 17:25:49 +03001040{
Eli Cohene126ba92013-07-07 17:25:49 +03001041 int uar_index;
Saeed Mahameed09a7d9e2016-07-19 01:17:59 +03001042 void *qpc;
Eli Cohene126ba92013-07-07 17:25:49 +03001043 int err;
1044
Erez Shitritf0313962016-02-21 16:27:17 +02001045 if (init_attr->create_flags & ~(IB_QP_CREATE_SIGNATURE_EN |
1046 IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK |
Haggai Eranb11a4f92016-02-29 15:45:03 +02001047 IB_QP_CREATE_IPOIB_UD_LSO |
Erez Shitrit93d576a2017-04-13 06:37:06 +03001048 IB_QP_CREATE_NETIF_QP |
Haggai Eranb11a4f92016-02-29 15:45:03 +02001049 mlx5_ib_create_qp_sqpn_qp1()))
Eli Cohen1a4c3a32014-02-06 17:41:25 +02001050 return -EINVAL;
Eli Cohene126ba92013-07-07 17:25:49 +03001051
1052 if (init_attr->qp_type == MLX5_IB_QPT_REG_UMR)
Eli Cohen5fe9dec2017-01-03 23:55:25 +02001053 qp->bf.bfreg = &dev->fp_bfreg;
1054 else
1055 qp->bf.bfreg = &dev->bfreg;
Eli Cohene126ba92013-07-07 17:25:49 +03001056
Eli Cohend8030b02017-02-09 19:31:47 +02001057 /* We need to divide by two since each register is comprised of
1058 * two buffers of identical size, namely odd and even
1059 */
1060 qp->bf.buf_size = (1 << MLX5_CAP_GEN(dev->mdev, log_bf_reg_size)) / 2;
Eli Cohen5fe9dec2017-01-03 23:55:25 +02001061 uar_index = qp->bf.bfreg->index;
Eli Cohene126ba92013-07-07 17:25:49 +03001062
1063 err = calc_sq_size(dev, init_attr, qp);
1064 if (err < 0) {
1065 mlx5_ib_dbg(dev, "err %d\n", err);
Eli Cohen5fe9dec2017-01-03 23:55:25 +02001066 return err;
Eli Cohene126ba92013-07-07 17:25:49 +03001067 }
1068
1069 qp->rq.offset = 0;
1070 qp->sq.offset = qp->rq.wqe_cnt << qp->rq.wqe_shift;
majd@mellanox.com19098df2016-01-14 19:13:03 +02001071 base->ubuffer.buf_size = err + (qp->rq.wqe_cnt << qp->rq.wqe_shift);
Eli Cohene126ba92013-07-07 17:25:49 +03001072
Guy Levi34f4c952018-11-26 08:15:50 +02001073 err = mlx5_frag_buf_alloc_node(dev->mdev, base->ubuffer.buf_size,
1074 &qp->buf, dev->mdev->priv.numa_node);
Eli Cohene126ba92013-07-07 17:25:49 +03001075 if (err) {
1076 mlx5_ib_dbg(dev, "err %d\n", err);
Eli Cohen5fe9dec2017-01-03 23:55:25 +02001077 return err;
Eli Cohene126ba92013-07-07 17:25:49 +03001078 }
1079
Guy Levi34f4c952018-11-26 08:15:50 +02001080 if (qp->rq.wqe_cnt)
1081 mlx5_init_fbc(qp->buf.frags, qp->rq.wqe_shift,
1082 ilog2(qp->rq.wqe_cnt), &qp->rq.fbc);
1083
1084 if (qp->sq.wqe_cnt) {
1085 int sq_strides_offset = (qp->sq.offset & (PAGE_SIZE - 1)) /
1086 MLX5_SEND_WQE_BB;
1087 mlx5_init_fbc_offset(qp->buf.frags +
1088 (qp->sq.offset / PAGE_SIZE),
1089 ilog2(MLX5_SEND_WQE_BB),
1090 ilog2(qp->sq.wqe_cnt),
1091 sq_strides_offset, &qp->sq.fbc);
1092
1093 qp->sq.cur_edge = get_sq_edge(&qp->sq, 0);
1094 }
1095
Saeed Mahameed09a7d9e2016-07-19 01:17:59 +03001096 *inlen = MLX5_ST_SZ_BYTES(create_qp_in) +
1097 MLX5_FLD_SZ_BYTES(create_qp_in, pas[0]) * qp->buf.npages;
Leon Romanovsky1b9a07e2017-05-10 21:32:18 +03001098 *in = kvzalloc(*inlen, GFP_KERNEL);
Eli Cohene126ba92013-07-07 17:25:49 +03001099 if (!*in) {
1100 err = -ENOMEM;
1101 goto err_buf;
1102 }
Saeed Mahameed09a7d9e2016-07-19 01:17:59 +03001103
1104 qpc = MLX5_ADDR_OF(create_qp_in, *in, qpc);
1105 MLX5_SET(qpc, qpc, uar_page, uar_index);
1106 MLX5_SET(qpc, qpc, log_page_size, qp->buf.page_shift - MLX5_ADAPTER_PAGE_SHIFT);
1107
Eli Cohene126ba92013-07-07 17:25:49 +03001108 /* Set "fast registration enabled" for all kernel QPs */
Saeed Mahameed09a7d9e2016-07-19 01:17:59 +03001109 MLX5_SET(qpc, qpc, fre, 1);
1110 MLX5_SET(qpc, qpc, rlky, 1);
Eli Cohene126ba92013-07-07 17:25:49 +03001111
Haggai Eranb11a4f92016-02-29 15:45:03 +02001112 if (init_attr->create_flags & mlx5_ib_create_qp_sqpn_qp1()) {
Saeed Mahameed09a7d9e2016-07-19 01:17:59 +03001113 MLX5_SET(qpc, qpc, deth_sqpn, 1);
Haggai Eranb11a4f92016-02-29 15:45:03 +02001114 qp->flags |= MLX5_IB_QP_SQPN_QP1;
1115 }
1116
Guy Levi34f4c952018-11-26 08:15:50 +02001117 mlx5_fill_page_frag_array(&qp->buf,
1118 (__be64 *)MLX5_ADDR_OF(create_qp_in,
1119 *in, pas));
Eli Cohene126ba92013-07-07 17:25:49 +03001120
Jack Morgenstein9603b612014-07-28 23:30:22 +03001121 err = mlx5_db_alloc(dev->mdev, &qp->db);
Eli Cohene126ba92013-07-07 17:25:49 +03001122 if (err) {
1123 mlx5_ib_dbg(dev, "err %d\n", err);
1124 goto err_free;
1125 }
1126
Li Dongyangb5883002017-08-16 23:31:22 +10001127 qp->sq.wrid = kvmalloc_array(qp->sq.wqe_cnt,
1128 sizeof(*qp->sq.wrid), GFP_KERNEL);
1129 qp->sq.wr_data = kvmalloc_array(qp->sq.wqe_cnt,
1130 sizeof(*qp->sq.wr_data), GFP_KERNEL);
1131 qp->rq.wrid = kvmalloc_array(qp->rq.wqe_cnt,
1132 sizeof(*qp->rq.wrid), GFP_KERNEL);
1133 qp->sq.w_list = kvmalloc_array(qp->sq.wqe_cnt,
1134 sizeof(*qp->sq.w_list), GFP_KERNEL);
1135 qp->sq.wqe_head = kvmalloc_array(qp->sq.wqe_cnt,
1136 sizeof(*qp->sq.wqe_head), GFP_KERNEL);
Eli Cohene126ba92013-07-07 17:25:49 +03001137
1138 if (!qp->sq.wrid || !qp->sq.wr_data || !qp->rq.wrid ||
1139 !qp->sq.w_list || !qp->sq.wqe_head) {
1140 err = -ENOMEM;
1141 goto err_wrid;
1142 }
1143 qp->create_type = MLX5_QP_KERNEL;
1144
1145 return 0;
1146
1147err_wrid:
Li Dongyangb5883002017-08-16 23:31:22 +10001148 kvfree(qp->sq.wqe_head);
1149 kvfree(qp->sq.w_list);
1150 kvfree(qp->sq.wrid);
1151 kvfree(qp->sq.wr_data);
1152 kvfree(qp->rq.wrid);
Eli Cohenf4044da2017-01-03 23:55:20 +02001153 mlx5_db_free(dev->mdev, &qp->db);
Eli Cohene126ba92013-07-07 17:25:49 +03001154
1155err_free:
Al Viro479163f2014-11-20 08:13:57 +00001156 kvfree(*in);
Eli Cohene126ba92013-07-07 17:25:49 +03001157
1158err_buf:
Guy Levi34f4c952018-11-26 08:15:50 +02001159 mlx5_frag_buf_free(dev->mdev, &qp->buf);
Eli Cohene126ba92013-07-07 17:25:49 +03001160 return err;
1161}
1162
1163static void destroy_qp_kernel(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp)
1164{
Li Dongyangb5883002017-08-16 23:31:22 +10001165 kvfree(qp->sq.wqe_head);
1166 kvfree(qp->sq.w_list);
1167 kvfree(qp->sq.wrid);
1168 kvfree(qp->sq.wr_data);
1169 kvfree(qp->rq.wrid);
Eli Cohenf4044da2017-01-03 23:55:20 +02001170 mlx5_db_free(dev->mdev, &qp->db);
Guy Levi34f4c952018-11-26 08:15:50 +02001171 mlx5_frag_buf_free(dev->mdev, &qp->buf);
Eli Cohene126ba92013-07-07 17:25:49 +03001172}
1173
Saeed Mahameed09a7d9e2016-07-19 01:17:59 +03001174static u32 get_rx_type(struct mlx5_ib_qp *qp, struct ib_qp_init_attr *attr)
Eli Cohene126ba92013-07-07 17:25:49 +03001175{
1176 if (attr->srq || (attr->qp_type == IB_QPT_XRC_TGT) ||
Moni Shouac32a4f22018-01-02 16:19:32 +02001177 (attr->qp_type == MLX5_IB_QPT_DCI) ||
Eli Cohene126ba92013-07-07 17:25:49 +03001178 (attr->qp_type == IB_QPT_XRC_INI))
Saeed Mahameed09a7d9e2016-07-19 01:17:59 +03001179 return MLX5_SRQ_RQ;
Eli Cohene126ba92013-07-07 17:25:49 +03001180 else if (!qp->has_rq)
Saeed Mahameed09a7d9e2016-07-19 01:17:59 +03001181 return MLX5_ZERO_LEN_RQ;
Eli Cohene126ba92013-07-07 17:25:49 +03001182 else
Saeed Mahameed09a7d9e2016-07-19 01:17:59 +03001183 return MLX5_NON_ZERO_RQ;
Eli Cohene126ba92013-07-07 17:25:49 +03001184}
1185
1186static int is_connected(enum ib_qp_type qp_type)
1187{
Yonatan Cohen5d6ff1b2018-10-09 12:05:13 +03001188 if (qp_type == IB_QPT_RC || qp_type == IB_QPT_UC ||
1189 qp_type == MLX5_IB_QPT_DCI)
Eli Cohene126ba92013-07-07 17:25:49 +03001190 return 1;
1191
1192 return 0;
1193}
1194
majd@mellanox.com0fb2ed62016-01-14 19:13:04 +02001195static int create_raw_packet_qp_tis(struct mlx5_ib_dev *dev,
Yishai Hadasc2e53b22017-06-08 16:15:08 +03001196 struct mlx5_ib_qp *qp,
Yishai Hadas1cd6dbd2018-09-20 21:39:27 +03001197 struct mlx5_ib_sq *sq, u32 tdn,
1198 struct ib_pd *pd)
majd@mellanox.com0fb2ed62016-01-14 19:13:04 +02001199{
Saeed Mahameedc4f287c2016-07-19 20:17:12 +03001200 u32 in[MLX5_ST_SZ_DW(create_tis_in)] = {0};
majd@mellanox.com0fb2ed62016-01-14 19:13:04 +02001201 void *tisc = MLX5_ADDR_OF(create_tis_in, in, ctx);
1202
Yishai Hadas1cd6dbd2018-09-20 21:39:27 +03001203 MLX5_SET(create_tis_in, in, uid, to_mpd(pd)->uid);
majd@mellanox.com0fb2ed62016-01-14 19:13:04 +02001204 MLX5_SET(tisc, tisc, transport_domain, tdn);
Yishai Hadasc2e53b22017-06-08 16:15:08 +03001205 if (qp->flags & MLX5_IB_QP_UNDERLAY)
1206 MLX5_SET(tisc, tisc, underlay_qpn, qp->underlay_qpn);
1207
majd@mellanox.com0fb2ed62016-01-14 19:13:04 +02001208 return mlx5_core_create_tis(dev->mdev, in, sizeof(in), &sq->tisn);
1209}
1210
1211static void destroy_raw_packet_qp_tis(struct mlx5_ib_dev *dev,
Yishai Hadas1cd6dbd2018-09-20 21:39:27 +03001212 struct mlx5_ib_sq *sq, struct ib_pd *pd)
majd@mellanox.com0fb2ed62016-01-14 19:13:04 +02001213{
Yishai Hadas1cd6dbd2018-09-20 21:39:27 +03001214 mlx5_cmd_destroy_tis(dev->mdev, sq->tisn, to_mpd(pd)->uid);
majd@mellanox.com0fb2ed62016-01-14 19:13:04 +02001215}
1216
Mark Blochd5ed8ac2019-03-28 15:27:38 +02001217static void destroy_flow_rule_vport_sq(struct mlx5_ib_sq *sq)
Mark Blochb96c9dd2018-01-29 10:40:37 +00001218{
1219 if (sq->flow_rule)
1220 mlx5_del_flow_rules(sq->flow_rule);
Mark Blochd5ed8ac2019-03-28 15:27:38 +02001221 sq->flow_rule = NULL;
Mark Blochb96c9dd2018-01-29 10:40:37 +00001222}
1223
majd@mellanox.com0fb2ed62016-01-14 19:13:04 +02001224static int create_raw_packet_qp_sq(struct mlx5_ib_dev *dev,
Jason Gunthorpeb0ea0fa2019-01-09 11:15:16 +02001225 struct ib_udata *udata,
majd@mellanox.com0fb2ed62016-01-14 19:13:04 +02001226 struct mlx5_ib_sq *sq, void *qpin,
1227 struct ib_pd *pd)
1228{
1229 struct mlx5_ib_ubuffer *ubuffer = &sq->ubuffer;
1230 __be64 *pas;
1231 void *in;
1232 void *sqc;
1233 void *qpc = MLX5_ADDR_OF(create_qp_in, qpin, qpc);
1234 void *wq;
1235 int inlen;
1236 int err;
1237 int page_shift = 0;
1238 int npages;
1239 int ncont = 0;
1240 u32 offset = 0;
1241
Jason Gunthorpeb0ea0fa2019-01-09 11:15:16 +02001242 err = mlx5_ib_umem_get(dev, udata, ubuffer->buf_addr, ubuffer->buf_size,
1243 &sq->ubuffer.umem, &npages, &page_shift, &ncont,
1244 &offset);
majd@mellanox.com0fb2ed62016-01-14 19:13:04 +02001245 if (err)
1246 return err;
1247
1248 inlen = MLX5_ST_SZ_BYTES(create_sq_in) + sizeof(u64) * ncont;
Leon Romanovsky1b9a07e2017-05-10 21:32:18 +03001249 in = kvzalloc(inlen, GFP_KERNEL);
majd@mellanox.com0fb2ed62016-01-14 19:13:04 +02001250 if (!in) {
1251 err = -ENOMEM;
1252 goto err_umem;
1253 }
1254
Yishai Hadasc14003f2018-09-20 21:39:22 +03001255 MLX5_SET(create_sq_in, in, uid, to_mpd(pd)->uid);
majd@mellanox.com0fb2ed62016-01-14 19:13:04 +02001256 sqc = MLX5_ADDR_OF(create_sq_in, in, ctx);
1257 MLX5_SET(sqc, sqc, flush_in_error_en, 1);
Bodong Wang795b6092017-08-17 15:52:34 +03001258 if (MLX5_CAP_ETH(dev->mdev, multi_pkt_send_wqe))
1259 MLX5_SET(sqc, sqc, allow_multi_pkt_send_wqe, 1);
majd@mellanox.com0fb2ed62016-01-14 19:13:04 +02001260 MLX5_SET(sqc, sqc, state, MLX5_SQC_STATE_RST);
1261 MLX5_SET(sqc, sqc, user_index, MLX5_GET(qpc, qpc, user_index));
1262 MLX5_SET(sqc, sqc, cqn, MLX5_GET(qpc, qpc, cqn_snd));
1263 MLX5_SET(sqc, sqc, tis_lst_sz, 1);
1264 MLX5_SET(sqc, sqc, tis_num_0, sq->tisn);
Noa Osherovich96dc3fc2017-08-17 15:52:28 +03001265 if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads) &&
1266 MLX5_CAP_ETH(dev->mdev, swp))
1267 MLX5_SET(sqc, sqc, allow_swp, 1);
majd@mellanox.com0fb2ed62016-01-14 19:13:04 +02001268
1269 wq = MLX5_ADDR_OF(sqc, sqc, wq);
1270 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC);
1271 MLX5_SET(wq, wq, pd, MLX5_GET(qpc, qpc, pd));
1272 MLX5_SET(wq, wq, uar_page, MLX5_GET(qpc, qpc, uar_page));
1273 MLX5_SET64(wq, wq, dbr_addr, MLX5_GET64(qpc, qpc, dbr_addr));
1274 MLX5_SET(wq, wq, log_wq_stride, ilog2(MLX5_SEND_WQE_BB));
1275 MLX5_SET(wq, wq, log_wq_sz, MLX5_GET(qpc, qpc, log_sq_size));
1276 MLX5_SET(wq, wq, log_wq_pg_sz, page_shift - MLX5_ADAPTER_PAGE_SHIFT);
1277 MLX5_SET(wq, wq, page_offset, offset);
1278
1279 pas = (__be64 *)MLX5_ADDR_OF(wq, wq, pas);
1280 mlx5_ib_populate_pas(dev, sq->ubuffer.umem, page_shift, pas, 0);
1281
1282 err = mlx5_core_create_sq_tracked(dev->mdev, in, inlen, &sq->base.mqp);
1283
1284 kvfree(in);
1285
1286 if (err)
1287 goto err_umem;
1288
1289 return 0;
1290
1291err_umem:
1292 ib_umem_release(sq->ubuffer.umem);
1293 sq->ubuffer.umem = NULL;
1294
1295 return err;
1296}
1297
1298static void destroy_raw_packet_qp_sq(struct mlx5_ib_dev *dev,
1299 struct mlx5_ib_sq *sq)
1300{
Mark Blochd5ed8ac2019-03-28 15:27:38 +02001301 destroy_flow_rule_vport_sq(sq);
majd@mellanox.com0fb2ed62016-01-14 19:13:04 +02001302 mlx5_core_destroy_sq_tracked(dev->mdev, &sq->base.mqp);
1303 ib_umem_release(sq->ubuffer.umem);
1304}
1305
Boris Pismenny2c292db2018-03-08 15:51:40 +02001306static size_t get_rq_pas_size(void *qpc)
majd@mellanox.com0fb2ed62016-01-14 19:13:04 +02001307{
1308 u32 log_page_size = MLX5_GET(qpc, qpc, log_page_size) + 12;
1309 u32 log_rq_stride = MLX5_GET(qpc, qpc, log_rq_stride);
1310 u32 log_rq_size = MLX5_GET(qpc, qpc, log_rq_size);
1311 u32 page_offset = MLX5_GET(qpc, qpc, page_offset);
1312 u32 po_quanta = 1 << (log_page_size - 6);
1313 u32 rq_sz = 1 << (log_rq_size + 4 + log_rq_stride);
1314 u32 page_size = 1 << log_page_size;
1315 u32 rq_sz_po = rq_sz + (page_offset * po_quanta);
1316 u32 rq_num_pas = (rq_sz_po + page_size - 1) / page_size;
1317
1318 return rq_num_pas * sizeof(u64);
1319}
1320
1321static int create_raw_packet_qp_rq(struct mlx5_ib_dev *dev,
Boris Pismenny2c292db2018-03-08 15:51:40 +02001322 struct mlx5_ib_rq *rq, void *qpin,
Yishai Hadas34d57582018-09-20 21:39:21 +03001323 size_t qpinlen, struct ib_pd *pd)
majd@mellanox.com0fb2ed62016-01-14 19:13:04 +02001324{
Majd Dibbiny358e42e2016-04-17 17:19:37 +03001325 struct mlx5_ib_qp *mqp = rq->base.container_mibqp;
majd@mellanox.com0fb2ed62016-01-14 19:13:04 +02001326 __be64 *pas;
1327 __be64 *qp_pas;
1328 void *in;
1329 void *rqc;
1330 void *wq;
1331 void *qpc = MLX5_ADDR_OF(create_qp_in, qpin, qpc);
Boris Pismenny2c292db2018-03-08 15:51:40 +02001332 size_t rq_pas_size = get_rq_pas_size(qpc);
1333 size_t inlen;
majd@mellanox.com0fb2ed62016-01-14 19:13:04 +02001334 int err;
Boris Pismenny2c292db2018-03-08 15:51:40 +02001335
1336 if (qpinlen < rq_pas_size + MLX5_BYTE_OFF(create_qp_in, pas))
1337 return -EINVAL;
majd@mellanox.com0fb2ed62016-01-14 19:13:04 +02001338
1339 inlen = MLX5_ST_SZ_BYTES(create_rq_in) + rq_pas_size;
Leon Romanovsky1b9a07e2017-05-10 21:32:18 +03001340 in = kvzalloc(inlen, GFP_KERNEL);
majd@mellanox.com0fb2ed62016-01-14 19:13:04 +02001341 if (!in)
1342 return -ENOMEM;
1343
Yishai Hadas34d57582018-09-20 21:39:21 +03001344 MLX5_SET(create_rq_in, in, uid, to_mpd(pd)->uid);
majd@mellanox.com0fb2ed62016-01-14 19:13:04 +02001345 rqc = MLX5_ADDR_OF(create_rq_in, in, ctx);
Noa Osheroviche4cc4fa2017-01-18 15:40:03 +02001346 if (!(rq->flags & MLX5_IB_RQ_CVLAN_STRIPPING))
1347 MLX5_SET(rqc, rqc, vsd, 1);
majd@mellanox.com0fb2ed62016-01-14 19:13:04 +02001348 MLX5_SET(rqc, rqc, mem_rq_type, MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE);
1349 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RST);
1350 MLX5_SET(rqc, rqc, flush_in_error_en, 1);
1351 MLX5_SET(rqc, rqc, user_index, MLX5_GET(qpc, qpc, user_index));
1352 MLX5_SET(rqc, rqc, cqn, MLX5_GET(qpc, qpc, cqn_rcv));
1353
Majd Dibbiny358e42e2016-04-17 17:19:37 +03001354 if (mqp->flags & MLX5_IB_QP_CAP_SCATTER_FCS)
1355 MLX5_SET(rqc, rqc, scatter_fcs, 1);
1356
majd@mellanox.com0fb2ed62016-01-14 19:13:04 +02001357 wq = MLX5_ADDR_OF(rqc, rqc, wq);
1358 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC);
Noa Osherovichb1383aa2017-10-29 13:59:45 +02001359 if (rq->flags & MLX5_IB_RQ_PCI_WRITE_END_PADDING)
1360 MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN);
majd@mellanox.com0fb2ed62016-01-14 19:13:04 +02001361 MLX5_SET(wq, wq, page_offset, MLX5_GET(qpc, qpc, page_offset));
1362 MLX5_SET(wq, wq, pd, MLX5_GET(qpc, qpc, pd));
1363 MLX5_SET64(wq, wq, dbr_addr, MLX5_GET64(qpc, qpc, dbr_addr));
1364 MLX5_SET(wq, wq, log_wq_stride, MLX5_GET(qpc, qpc, log_rq_stride) + 4);
1365 MLX5_SET(wq, wq, log_wq_pg_sz, MLX5_GET(qpc, qpc, log_page_size));
1366 MLX5_SET(wq, wq, log_wq_sz, MLX5_GET(qpc, qpc, log_rq_size));
1367
1368 pas = (__be64 *)MLX5_ADDR_OF(wq, wq, pas);
1369 qp_pas = (__be64 *)MLX5_ADDR_OF(create_qp_in, qpin, pas);
1370 memcpy(pas, qp_pas, rq_pas_size);
1371
1372 err = mlx5_core_create_rq_tracked(dev->mdev, in, inlen, &rq->base.mqp);
1373
1374 kvfree(in);
1375
1376 return err;
1377}
1378
1379static void destroy_raw_packet_qp_rq(struct mlx5_ib_dev *dev,
1380 struct mlx5_ib_rq *rq)
1381{
1382 mlx5_core_destroy_rq_tracked(dev->mdev, &rq->base.mqp);
1383}
1384
Maor Gottliebf95ef6c2017-10-19 08:25:55 +03001385static bool tunnel_offload_supported(struct mlx5_core_dev *dev)
1386{
1387 return (MLX5_CAP_ETH(dev, tunnel_stateless_vxlan) ||
1388 MLX5_CAP_ETH(dev, tunnel_stateless_gre) ||
1389 MLX5_CAP_ETH(dev, tunnel_stateless_geneve_rx));
1390}
1391
Mark Bloch0042f9e2018-09-17 13:30:49 +03001392static void destroy_raw_packet_qp_tir(struct mlx5_ib_dev *dev,
1393 struct mlx5_ib_rq *rq,
Yishai Hadas443c1cf2018-09-20 21:39:26 +03001394 u32 qp_flags_en,
1395 struct ib_pd *pd)
Mark Bloch0042f9e2018-09-17 13:30:49 +03001396{
1397 if (qp_flags_en & (MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC |
1398 MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_MC))
1399 mlx5_ib_disable_lb(dev, false, true);
Yishai Hadas443c1cf2018-09-20 21:39:26 +03001400 mlx5_cmd_destroy_tir(dev->mdev, rq->tirn, to_mpd(pd)->uid);
Mark Bloch0042f9e2018-09-17 13:30:49 +03001401}
1402
majd@mellanox.com0fb2ed62016-01-14 19:13:04 +02001403static int create_raw_packet_qp_tir(struct mlx5_ib_dev *dev,
Maor Gottliebf95ef6c2017-10-19 08:25:55 +03001404 struct mlx5_ib_rq *rq, u32 tdn,
Yishai Hadas443c1cf2018-09-20 21:39:26 +03001405 u32 *qp_flags_en,
1406 struct ib_pd *pd)
majd@mellanox.com0fb2ed62016-01-14 19:13:04 +02001407{
Mark Bloch175edba2018-09-17 13:30:48 +03001408 u8 lb_flag = 0;
majd@mellanox.com0fb2ed62016-01-14 19:13:04 +02001409 u32 *in;
1410 void *tirc;
1411 int inlen;
1412 int err;
1413
1414 inlen = MLX5_ST_SZ_BYTES(create_tir_in);
Leon Romanovsky1b9a07e2017-05-10 21:32:18 +03001415 in = kvzalloc(inlen, GFP_KERNEL);
majd@mellanox.com0fb2ed62016-01-14 19:13:04 +02001416 if (!in)
1417 return -ENOMEM;
1418
Yishai Hadas443c1cf2018-09-20 21:39:26 +03001419 MLX5_SET(create_tir_in, in, uid, to_mpd(pd)->uid);
majd@mellanox.com0fb2ed62016-01-14 19:13:04 +02001420 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
1421 MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_DIRECT);
1422 MLX5_SET(tirc, tirc, inline_rqn, rq->base.mqp.qpn);
1423 MLX5_SET(tirc, tirc, transport_domain, tdn);
Mark Bloch175edba2018-09-17 13:30:48 +03001424 if (*qp_flags_en & MLX5_QP_FLAG_TUNNEL_OFFLOADS)
Maor Gottliebf95ef6c2017-10-19 08:25:55 +03001425 MLX5_SET(tirc, tirc, tunneled_offload_en, 1);
majd@mellanox.com0fb2ed62016-01-14 19:13:04 +02001426
Mark Bloch175edba2018-09-17 13:30:48 +03001427 if (*qp_flags_en & MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC)
1428 lb_flag |= MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST;
1429
1430 if (*qp_flags_en & MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_MC)
1431 lb_flag |= MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST;
1432
Mark Bloch6a4d00b2019-03-28 15:27:37 +02001433 if (dev->is_rep) {
Mark Bloch175edba2018-09-17 13:30:48 +03001434 lb_flag |= MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST;
1435 *qp_flags_en |= MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC;
1436 }
1437
1438 MLX5_SET(tirc, tirc, self_lb_block, lb_flag);
Mark Blochec9c2fb2018-01-15 13:11:37 +00001439
majd@mellanox.com0fb2ed62016-01-14 19:13:04 +02001440 err = mlx5_core_create_tir(dev->mdev, in, inlen, &rq->tirn);
1441
Mark Bloch0042f9e2018-09-17 13:30:49 +03001442 if (!err && MLX5_GET(tirc, tirc, self_lb_block)) {
1443 err = mlx5_ib_enable_lb(dev, false, true);
1444
1445 if (err)
Yishai Hadas443c1cf2018-09-20 21:39:26 +03001446 destroy_raw_packet_qp_tir(dev, rq, 0, pd);
Mark Bloch0042f9e2018-09-17 13:30:49 +03001447 }
majd@mellanox.com0fb2ed62016-01-14 19:13:04 +02001448 kvfree(in);
1449
1450 return err;
1451}
1452
majd@mellanox.com0fb2ed62016-01-14 19:13:04 +02001453static int create_raw_packet_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
Boris Pismenny2c292db2018-03-08 15:51:40 +02001454 u32 *in, size_t inlen,
Yishai Hadas7f720522018-09-20 21:45:18 +03001455 struct ib_pd *pd,
1456 struct ib_udata *udata,
1457 struct mlx5_ib_create_qp_resp *resp)
majd@mellanox.com0fb2ed62016-01-14 19:13:04 +02001458{
1459 struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp;
1460 struct mlx5_ib_sq *sq = &raw_packet_qp->sq;
1461 struct mlx5_ib_rq *rq = &raw_packet_qp->rq;
Shamir Rabinovitch89944452019-02-07 18:44:49 +02001462 struct mlx5_ib_ucontext *mucontext = rdma_udata_to_drv_context(
1463 udata, struct mlx5_ib_ucontext, ibucontext);
majd@mellanox.com0fb2ed62016-01-14 19:13:04 +02001464 int err;
1465 u32 tdn = mucontext->tdn;
Yishai Hadas7f720522018-09-20 21:45:18 +03001466 u16 uid = to_mpd(pd)->uid;
majd@mellanox.com0fb2ed62016-01-14 19:13:04 +02001467
1468 if (qp->sq.wqe_cnt) {
Yishai Hadas1cd6dbd2018-09-20 21:39:27 +03001469 err = create_raw_packet_qp_tis(dev, qp, sq, tdn, pd);
majd@mellanox.com0fb2ed62016-01-14 19:13:04 +02001470 if (err)
1471 return err;
1472
Jason Gunthorpeb0ea0fa2019-01-09 11:15:16 +02001473 err = create_raw_packet_qp_sq(dev, udata, sq, in, pd);
majd@mellanox.com0fb2ed62016-01-14 19:13:04 +02001474 if (err)
1475 goto err_destroy_tis;
1476
Yishai Hadas7f720522018-09-20 21:45:18 +03001477 if (uid) {
1478 resp->tisn = sq->tisn;
1479 resp->comp_mask |= MLX5_IB_CREATE_QP_RESP_MASK_TISN;
1480 resp->sqn = sq->base.mqp.qpn;
1481 resp->comp_mask |= MLX5_IB_CREATE_QP_RESP_MASK_SQN;
1482 }
1483
majd@mellanox.com0fb2ed62016-01-14 19:13:04 +02001484 sq->base.container_mibqp = qp;
Majd Dibbiny1d31e9c2017-08-23 08:35:41 +03001485 sq->base.mqp.event = mlx5_ib_qp_event;
majd@mellanox.com0fb2ed62016-01-14 19:13:04 +02001486 }
1487
1488 if (qp->rq.wqe_cnt) {
Majd Dibbiny358e42e2016-04-17 17:19:37 +03001489 rq->base.container_mibqp = qp;
1490
Noa Osheroviche4cc4fa2017-01-18 15:40:03 +02001491 if (qp->flags & MLX5_IB_QP_CVLAN_STRIPPING)
1492 rq->flags |= MLX5_IB_RQ_CVLAN_STRIPPING;
Noa Osherovichb1383aa2017-10-29 13:59:45 +02001493 if (qp->flags & MLX5_IB_QP_PCI_WRITE_END_PADDING)
1494 rq->flags |= MLX5_IB_RQ_PCI_WRITE_END_PADDING;
Yishai Hadas34d57582018-09-20 21:39:21 +03001495 err = create_raw_packet_qp_rq(dev, rq, in, inlen, pd);
majd@mellanox.com0fb2ed62016-01-14 19:13:04 +02001496 if (err)
1497 goto err_destroy_sq;
1498
Yishai Hadas443c1cf2018-09-20 21:39:26 +03001499 err = create_raw_packet_qp_tir(dev, rq, tdn, &qp->flags_en, pd);
majd@mellanox.com0fb2ed62016-01-14 19:13:04 +02001500 if (err)
1501 goto err_destroy_rq;
Yishai Hadas7f720522018-09-20 21:45:18 +03001502
1503 if (uid) {
1504 resp->rqn = rq->base.mqp.qpn;
1505 resp->comp_mask |= MLX5_IB_CREATE_QP_RESP_MASK_RQN;
1506 resp->tirn = rq->tirn;
1507 resp->comp_mask |= MLX5_IB_CREATE_QP_RESP_MASK_TIRN;
1508 }
majd@mellanox.com0fb2ed62016-01-14 19:13:04 +02001509 }
1510
1511 qp->trans_qp.base.mqp.qpn = qp->sq.wqe_cnt ? sq->base.mqp.qpn :
1512 rq->base.mqp.qpn;
Yishai Hadas7f720522018-09-20 21:45:18 +03001513 err = ib_copy_to_udata(udata, resp, min(udata->outlen, sizeof(*resp)));
1514 if (err)
1515 goto err_destroy_tir;
majd@mellanox.com0fb2ed62016-01-14 19:13:04 +02001516
1517 return 0;
1518
Yishai Hadas7f720522018-09-20 21:45:18 +03001519err_destroy_tir:
1520 destroy_raw_packet_qp_tir(dev, rq, qp->flags_en, pd);
majd@mellanox.com0fb2ed62016-01-14 19:13:04 +02001521err_destroy_rq:
1522 destroy_raw_packet_qp_rq(dev, rq);
1523err_destroy_sq:
1524 if (!qp->sq.wqe_cnt)
1525 return err;
1526 destroy_raw_packet_qp_sq(dev, sq);
1527err_destroy_tis:
Yishai Hadas1cd6dbd2018-09-20 21:39:27 +03001528 destroy_raw_packet_qp_tis(dev, sq, pd);
majd@mellanox.com0fb2ed62016-01-14 19:13:04 +02001529
1530 return err;
1531}
1532
1533static void destroy_raw_packet_qp(struct mlx5_ib_dev *dev,
1534 struct mlx5_ib_qp *qp)
1535{
1536 struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp;
1537 struct mlx5_ib_sq *sq = &raw_packet_qp->sq;
1538 struct mlx5_ib_rq *rq = &raw_packet_qp->rq;
1539
1540 if (qp->rq.wqe_cnt) {
Yishai Hadas443c1cf2018-09-20 21:39:26 +03001541 destroy_raw_packet_qp_tir(dev, rq, qp->flags_en, qp->ibqp.pd);
majd@mellanox.com0fb2ed62016-01-14 19:13:04 +02001542 destroy_raw_packet_qp_rq(dev, rq);
1543 }
1544
1545 if (qp->sq.wqe_cnt) {
1546 destroy_raw_packet_qp_sq(dev, sq);
Yishai Hadas1cd6dbd2018-09-20 21:39:27 +03001547 destroy_raw_packet_qp_tis(dev, sq, qp->ibqp.pd);
majd@mellanox.com0fb2ed62016-01-14 19:13:04 +02001548 }
1549}
1550
1551static void raw_packet_qp_copy_info(struct mlx5_ib_qp *qp,
1552 struct mlx5_ib_raw_packet_qp *raw_packet_qp)
1553{
1554 struct mlx5_ib_sq *sq = &raw_packet_qp->sq;
1555 struct mlx5_ib_rq *rq = &raw_packet_qp->rq;
1556
1557 sq->sq = &qp->sq;
1558 rq->rq = &qp->rq;
1559 sq->doorbell = &qp->db;
1560 rq->doorbell = &qp->db;
1561}
1562
Yishai Hadas28d61372016-05-23 15:20:56 +03001563static void destroy_rss_raw_qp_tir(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp)
1564{
Mark Bloch0042f9e2018-09-17 13:30:49 +03001565 if (qp->flags_en & (MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC |
1566 MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_MC))
1567 mlx5_ib_disable_lb(dev, false, true);
Yishai Hadas443c1cf2018-09-20 21:39:26 +03001568 mlx5_cmd_destroy_tir(dev->mdev, qp->rss_qp.tirn,
1569 to_mpd(qp->ibqp.pd)->uid);
Yishai Hadas28d61372016-05-23 15:20:56 +03001570}
1571
1572static int create_rss_raw_qp_tir(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
1573 struct ib_pd *pd,
1574 struct ib_qp_init_attr *init_attr,
1575 struct ib_udata *udata)
1576{
Shamir Rabinovitch89944452019-02-07 18:44:49 +02001577 struct mlx5_ib_ucontext *mucontext = rdma_udata_to_drv_context(
1578 udata, struct mlx5_ib_ucontext, ibucontext);
Yishai Hadas28d61372016-05-23 15:20:56 +03001579 struct mlx5_ib_create_qp_resp resp = {};
1580 int inlen;
1581 int err;
1582 u32 *in;
1583 void *tirc;
1584 void *hfso;
1585 u32 selected_fields = 0;
Matan Barak2d93fc82018-03-28 09:27:55 +03001586 u32 outer_l4;
Yishai Hadas28d61372016-05-23 15:20:56 +03001587 size_t min_resp_len;
1588 u32 tdn = mucontext->tdn;
1589 struct mlx5_ib_create_qp_rss ucmd = {};
1590 size_t required_cmd_sz;
Mark Bloch175edba2018-09-17 13:30:48 +03001591 u8 lb_flag = 0;
Yishai Hadas28d61372016-05-23 15:20:56 +03001592
1593 if (init_attr->qp_type != IB_QPT_RAW_PACKET)
1594 return -EOPNOTSUPP;
1595
1596 if (init_attr->create_flags || init_attr->send_cq)
1597 return -EINVAL;
1598
Eli Cohen2f5ff262017-01-03 23:55:21 +02001599 min_resp_len = offsetof(typeof(resp), bfreg_index) + sizeof(resp.bfreg_index);
Yishai Hadas28d61372016-05-23 15:20:56 +03001600 if (udata->outlen < min_resp_len)
1601 return -EINVAL;
1602
Maor Gottliebf95ef6c2017-10-19 08:25:55 +03001603 required_cmd_sz = offsetof(typeof(ucmd), flags) + sizeof(ucmd.flags);
Yishai Hadas28d61372016-05-23 15:20:56 +03001604 if (udata->inlen < required_cmd_sz) {
1605 mlx5_ib_dbg(dev, "invalid inlen\n");
1606 return -EINVAL;
1607 }
1608
1609 if (udata->inlen > sizeof(ucmd) &&
1610 !ib_is_udata_cleared(udata, sizeof(ucmd),
1611 udata->inlen - sizeof(ucmd))) {
1612 mlx5_ib_dbg(dev, "inlen is not supported\n");
1613 return -EOPNOTSUPP;
1614 }
1615
1616 if (ib_copy_from_udata(&ucmd, udata, min(sizeof(ucmd), udata->inlen))) {
1617 mlx5_ib_dbg(dev, "copy failed\n");
1618 return -EFAULT;
1619 }
1620
1621 if (ucmd.comp_mask) {
1622 mlx5_ib_dbg(dev, "invalid comp mask\n");
1623 return -EOPNOTSUPP;
1624 }
1625
Mark Bloch175edba2018-09-17 13:30:48 +03001626 if (ucmd.flags & ~(MLX5_QP_FLAG_TUNNEL_OFFLOADS |
1627 MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC |
1628 MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_MC)) {
Maor Gottliebf95ef6c2017-10-19 08:25:55 +03001629 mlx5_ib_dbg(dev, "invalid flags\n");
1630 return -EOPNOTSUPP;
1631 }
1632
1633 if (ucmd.flags & MLX5_QP_FLAG_TUNNEL_OFFLOADS &&
1634 !tunnel_offload_supported(dev->mdev)) {
1635 mlx5_ib_dbg(dev, "tunnel offloads isn't supported\n");
Yishai Hadas28d61372016-05-23 15:20:56 +03001636 return -EOPNOTSUPP;
1637 }
1638
Maor Gottlieb309fa342017-10-19 08:25:56 +03001639 if (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_INNER &&
1640 !(ucmd.flags & MLX5_QP_FLAG_TUNNEL_OFFLOADS)) {
1641 mlx5_ib_dbg(dev, "Tunnel offloads must be set for inner RSS\n");
1642 return -EOPNOTSUPP;
1643 }
1644
Mark Bloch6a4d00b2019-03-28 15:27:37 +02001645 if (ucmd.flags & MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC || dev->is_rep) {
Mark Bloch175edba2018-09-17 13:30:48 +03001646 lb_flag |= MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST;
1647 qp->flags_en |= MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC;
1648 }
1649
1650 if (ucmd.flags & MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_MC) {
1651 lb_flag |= MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST;
1652 qp->flags_en |= MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_MC;
1653 }
1654
Jason Gunthorpe41d902c2018-04-03 10:00:53 +03001655 err = ib_copy_to_udata(udata, &resp, min(udata->outlen, sizeof(resp)));
Yishai Hadas28d61372016-05-23 15:20:56 +03001656 if (err) {
1657 mlx5_ib_dbg(dev, "copy failed\n");
1658 return -EINVAL;
1659 }
1660
1661 inlen = MLX5_ST_SZ_BYTES(create_tir_in);
Leon Romanovsky1b9a07e2017-05-10 21:32:18 +03001662 in = kvzalloc(inlen, GFP_KERNEL);
Yishai Hadas28d61372016-05-23 15:20:56 +03001663 if (!in)
1664 return -ENOMEM;
1665
Yishai Hadas443c1cf2018-09-20 21:39:26 +03001666 MLX5_SET(create_tir_in, in, uid, to_mpd(pd)->uid);
Yishai Hadas28d61372016-05-23 15:20:56 +03001667 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
1668 MLX5_SET(tirc, tirc, disp_type,
1669 MLX5_TIRC_DISP_TYPE_INDIRECT);
1670 MLX5_SET(tirc, tirc, indirect_table,
1671 init_attr->rwq_ind_tbl->ind_tbl_num);
1672 MLX5_SET(tirc, tirc, transport_domain, tdn);
1673
1674 hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer);
Maor Gottliebf95ef6c2017-10-19 08:25:55 +03001675
1676 if (ucmd.flags & MLX5_QP_FLAG_TUNNEL_OFFLOADS)
1677 MLX5_SET(tirc, tirc, tunneled_offload_en, 1);
1678
Mark Bloch175edba2018-09-17 13:30:48 +03001679 MLX5_SET(tirc, tirc, self_lb_block, lb_flag);
1680
Maor Gottlieb309fa342017-10-19 08:25:56 +03001681 if (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_INNER)
1682 hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_inner);
1683 else
1684 hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer);
1685
Yishai Hadas28d61372016-05-23 15:20:56 +03001686 switch (ucmd.rx_hash_function) {
1687 case MLX5_RX_HASH_FUNC_TOEPLITZ:
1688 {
1689 void *rss_key = MLX5_ADDR_OF(tirc, tirc, rx_hash_toeplitz_key);
1690 size_t len = MLX5_FLD_SZ_BYTES(tirc, rx_hash_toeplitz_key);
1691
1692 if (len != ucmd.rx_key_len) {
1693 err = -EINVAL;
1694 goto err;
1695 }
1696
1697 MLX5_SET(tirc, tirc, rx_hash_fn, MLX5_RX_HASH_FN_TOEPLITZ);
1698 MLX5_SET(tirc, tirc, rx_hash_symmetric, 1);
1699 memcpy(rss_key, ucmd.rx_hash_key, len);
1700 break;
1701 }
1702 default:
1703 err = -EOPNOTSUPP;
1704 goto err;
1705 }
1706
1707 if (!ucmd.rx_hash_fields_mask) {
1708 /* special case when this TIR serves as steering entry without hashing */
1709 if (!init_attr->rwq_ind_tbl->log_ind_tbl_size)
1710 goto create_tir;
1711 err = -EINVAL;
1712 goto err;
1713 }
1714
1715 if (((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV4) ||
1716 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV4)) &&
1717 ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV6) ||
1718 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV6))) {
1719 err = -EINVAL;
1720 goto err;
1721 }
1722
1723 /* If none of IPV4 & IPV6 SRC/DST was set - this bit field is ignored */
1724 if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV4) ||
1725 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV4))
1726 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1727 MLX5_L3_PROT_TYPE_IPV4);
1728 else if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV6) ||
1729 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV6))
1730 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1731 MLX5_L3_PROT_TYPE_IPV6);
1732
Matan Barak2d93fc82018-03-28 09:27:55 +03001733 outer_l4 = ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_TCP) ||
1734 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_TCP)) << 0 |
1735 ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_UDP) ||
1736 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_UDP)) << 1 |
1737 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_IPSEC_SPI) << 2;
1738
1739 /* Check that only one l4 protocol is set */
1740 if (outer_l4 & (outer_l4 - 1)) {
Yishai Hadas28d61372016-05-23 15:20:56 +03001741 err = -EINVAL;
1742 goto err;
1743 }
1744
1745 /* If none of TCP & UDP SRC/DST was set - this bit field is ignored */
1746 if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_TCP) ||
1747 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_TCP))
1748 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
1749 MLX5_L4_PROT_TYPE_TCP);
1750 else if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_UDP) ||
1751 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_UDP))
1752 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
1753 MLX5_L4_PROT_TYPE_UDP);
1754
1755 if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV4) ||
1756 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV6))
1757 selected_fields |= MLX5_HASH_FIELD_SEL_SRC_IP;
1758
1759 if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV4) ||
1760 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV6))
1761 selected_fields |= MLX5_HASH_FIELD_SEL_DST_IP;
1762
1763 if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_TCP) ||
1764 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_UDP))
1765 selected_fields |= MLX5_HASH_FIELD_SEL_L4_SPORT;
1766
1767 if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_TCP) ||
1768 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_UDP))
1769 selected_fields |= MLX5_HASH_FIELD_SEL_L4_DPORT;
1770
Matan Barak2d93fc82018-03-28 09:27:55 +03001771 if (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_IPSEC_SPI)
1772 selected_fields |= MLX5_HASH_FIELD_SEL_IPSEC_SPI;
1773
Yishai Hadas28d61372016-05-23 15:20:56 +03001774 MLX5_SET(rx_hash_field_select, hfso, selected_fields, selected_fields);
1775
1776create_tir:
1777 err = mlx5_core_create_tir(dev->mdev, in, inlen, &qp->rss_qp.tirn);
1778
Mark Bloch0042f9e2018-09-17 13:30:49 +03001779 if (!err && MLX5_GET(tirc, tirc, self_lb_block)) {
1780 err = mlx5_ib_enable_lb(dev, false, true);
1781
1782 if (err)
Yishai Hadas443c1cf2018-09-20 21:39:26 +03001783 mlx5_cmd_destroy_tir(dev->mdev, qp->rss_qp.tirn,
1784 to_mpd(pd)->uid);
Mark Bloch0042f9e2018-09-17 13:30:49 +03001785 }
1786
Yishai Hadas28d61372016-05-23 15:20:56 +03001787 if (err)
1788 goto err;
1789
Yishai Hadas7f720522018-09-20 21:45:18 +03001790 if (mucontext->devx_uid) {
1791 resp.comp_mask |= MLX5_IB_CREATE_QP_RESP_MASK_TIRN;
1792 resp.tirn = qp->rss_qp.tirn;
1793 }
1794
1795 err = ib_copy_to_udata(udata, &resp, min(udata->outlen, sizeof(resp)));
1796 if (err)
1797 goto err_copy;
1798
Yishai Hadas28d61372016-05-23 15:20:56 +03001799 kvfree(in);
1800 /* qpn is reserved for that QP */
1801 qp->trans_qp.base.mqp.qpn = 0;
Yishai Hadasd9f88e52016-08-28 10:58:37 +03001802 qp->flags |= MLX5_IB_QP_RSS;
Yishai Hadas28d61372016-05-23 15:20:56 +03001803 return 0;
1804
Yishai Hadas7f720522018-09-20 21:45:18 +03001805err_copy:
1806 mlx5_cmd_destroy_tir(dev->mdev, qp->rss_qp.tirn, mucontext->devx_uid);
Yishai Hadas28d61372016-05-23 15:20:56 +03001807err:
1808 kvfree(in);
1809 return err;
1810}
1811
Yonatan Cohen5d6ff1b2018-10-09 12:05:13 +03001812static void configure_responder_scat_cqe(struct ib_qp_init_attr *init_attr,
1813 void *qpc)
1814{
1815 int rcqe_sz;
1816
1817 if (init_attr->qp_type == MLX5_IB_QPT_DCI)
1818 return;
1819
1820 rcqe_sz = mlx5_ib_get_cqe_size(init_attr->recv_cq);
1821
1822 if (rcqe_sz == 128) {
1823 MLX5_SET(qpc, qpc, cs_res, MLX5_RES_SCAT_DATA64_CQE);
1824 return;
1825 }
1826
1827 if (init_attr->qp_type != MLX5_IB_QPT_DCT)
1828 MLX5_SET(qpc, qpc, cs_res, MLX5_RES_SCAT_DATA32_CQE);
1829}
1830
1831static void configure_requester_scat_cqe(struct mlx5_ib_dev *dev,
1832 struct ib_qp_init_attr *init_attr,
Yonatan Cohen6f4bc0e2018-10-09 12:05:15 +03001833 struct mlx5_ib_create_qp *ucmd,
Yonatan Cohen5d6ff1b2018-10-09 12:05:13 +03001834 void *qpc)
1835{
1836 enum ib_qp_type qpt = init_attr->qp_type;
1837 int scqe_sz;
Yonatan Cohen6f4bc0e2018-10-09 12:05:15 +03001838 bool allow_scat_cqe = 0;
Yonatan Cohen5d6ff1b2018-10-09 12:05:13 +03001839
1840 if (qpt == IB_QPT_UC || qpt == IB_QPT_UD)
1841 return;
1842
Yonatan Cohen6f4bc0e2018-10-09 12:05:15 +03001843 if (ucmd)
1844 allow_scat_cqe = ucmd->flags & MLX5_QP_FLAG_ALLOW_SCATTER_CQE;
1845
1846 if (!allow_scat_cqe && init_attr->sq_sig_type != IB_SIGNAL_ALL_WR)
Yonatan Cohen5d6ff1b2018-10-09 12:05:13 +03001847 return;
1848
1849 scqe_sz = mlx5_ib_get_cqe_size(init_attr->send_cq);
1850 if (scqe_sz == 128) {
1851 MLX5_SET(qpc, qpc, cs_req, MLX5_REQ_SCAT_DATA64_CQE);
1852 return;
1853 }
1854
1855 if (init_attr->qp_type != MLX5_IB_QPT_DCI ||
1856 MLX5_CAP_GEN(dev->mdev, dc_req_scat_data_cqe))
1857 MLX5_SET(qpc, qpc, cs_req, MLX5_REQ_SCAT_DATA32_CQE);
1858}
1859
Yonatan Cohena60109d2018-10-10 09:25:16 +03001860static int atomic_size_to_mode(int size_mask)
1861{
1862 /* driver does not support atomic_size > 256B
1863 * and does not know how to translate bigger sizes
1864 */
1865 int supported_size_mask = size_mask & 0x1ff;
1866 int log_max_size;
1867
1868 if (!supported_size_mask)
1869 return -EOPNOTSUPP;
1870
1871 log_max_size = __fls(supported_size_mask);
1872
1873 if (log_max_size > 3)
1874 return log_max_size;
1875
1876 return MLX5_ATOMIC_MODE_8B;
1877}
1878
1879static int get_atomic_mode(struct mlx5_ib_dev *dev,
1880 enum ib_qp_type qp_type)
1881{
1882 u8 atomic_operations = MLX5_CAP_ATOMIC(dev->mdev, atomic_operations);
1883 u8 atomic = MLX5_CAP_GEN(dev->mdev, atomic);
1884 int atomic_mode = -EOPNOTSUPP;
1885 int atomic_size_mask;
1886
1887 if (!atomic)
1888 return -EOPNOTSUPP;
1889
1890 if (qp_type == MLX5_IB_QPT_DCT)
1891 atomic_size_mask = MLX5_CAP_ATOMIC(dev->mdev, atomic_size_dc);
1892 else
1893 atomic_size_mask = MLX5_CAP_ATOMIC(dev->mdev, atomic_size_qp);
1894
1895 if ((atomic_operations & MLX5_ATOMIC_OPS_EXTENDED_CMP_SWAP) ||
1896 (atomic_operations & MLX5_ATOMIC_OPS_EXTENDED_FETCH_ADD))
1897 atomic_mode = atomic_size_to_mode(atomic_size_mask);
1898
1899 if (atomic_mode <= 0 &&
1900 (atomic_operations & MLX5_ATOMIC_OPS_CMP_SWAP &&
1901 atomic_operations & MLX5_ATOMIC_OPS_FETCH_ADD))
1902 atomic_mode = MLX5_ATOMIC_MODE_IB_COMP;
1903
1904 return atomic_mode;
1905}
1906
Yonatan Cohen2e43bb32018-10-09 12:05:14 +03001907static inline bool check_flags_mask(uint64_t input, uint64_t supported)
1908{
1909 return (input & ~supported) == 0;
1910}
1911
Eli Cohene126ba92013-07-07 17:25:49 +03001912static int create_qp_common(struct mlx5_ib_dev *dev, struct ib_pd *pd,
1913 struct ib_qp_init_attr *init_attr,
1914 struct ib_udata *udata, struct mlx5_ib_qp *qp)
1915{
1916 struct mlx5_ib_resources *devr = &dev->devr;
Saeed Mahameed09a7d9e2016-07-19 01:17:59 +03001917 int inlen = MLX5_ST_SZ_BYTES(create_qp_in);
Saeed Mahameed938fe832015-05-28 22:28:41 +03001918 struct mlx5_core_dev *mdev = dev->mdev;
Jason Gunthorpe0625b4b2018-08-14 15:33:52 -06001919 struct mlx5_ib_create_qp_resp resp = {};
Shamir Rabinovitch89944452019-02-07 18:44:49 +02001920 struct mlx5_ib_ucontext *ucontext = rdma_udata_to_drv_context(
1921 udata, struct mlx5_ib_ucontext, ibucontext);
Maor Gottlieb89ea94a72016-06-17 15:01:38 +03001922 struct mlx5_ib_cq *send_cq;
1923 struct mlx5_ib_cq *recv_cq;
1924 unsigned long flags;
Haggai Abramovskycfb5e082016-01-14 19:12:57 +02001925 u32 uidx = MLX5_IB_DEFAULT_UIDX;
Saeed Mahameed09a7d9e2016-07-19 01:17:59 +03001926 struct mlx5_ib_create_qp ucmd;
1927 struct mlx5_ib_qp_base *base;
Noa Osheroviche7b169f2018-02-25 13:39:51 +02001928 int mlx5_st;
Haggai Abramovskycfb5e082016-01-14 19:12:57 +02001929 void *qpc;
Saeed Mahameed09a7d9e2016-07-19 01:17:59 +03001930 u32 *in;
1931 int err;
Eli Cohene126ba92013-07-07 17:25:49 +03001932
1933 mutex_init(&qp->mutex);
1934 spin_lock_init(&qp->sq.lock);
1935 spin_lock_init(&qp->rq.lock);
1936
Noa Osheroviche7b169f2018-02-25 13:39:51 +02001937 mlx5_st = to_mlx5_st(init_attr->qp_type);
1938 if (mlx5_st < 0)
1939 return -EINVAL;
1940
Yishai Hadas28d61372016-05-23 15:20:56 +03001941 if (init_attr->rwq_ind_tbl) {
1942 if (!udata)
1943 return -ENOSYS;
1944
1945 err = create_rss_raw_qp_tir(dev, qp, pd, init_attr, udata);
1946 return err;
1947 }
1948
Eli Cohenf360d882014-04-02 00:10:16 +03001949 if (init_attr->create_flags & IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK) {
Saeed Mahameed938fe832015-05-28 22:28:41 +03001950 if (!MLX5_CAP_GEN(mdev, block_lb_mc)) {
Eli Cohenf360d882014-04-02 00:10:16 +03001951 mlx5_ib_dbg(dev, "block multicast loopback isn't supported\n");
1952 return -EINVAL;
1953 } else {
1954 qp->flags |= MLX5_IB_QP_BLOCK_MULTICAST_LOOPBACK;
1955 }
1956 }
1957
Leon Romanovsky051f2632015-12-20 12:16:11 +02001958 if (init_attr->create_flags &
1959 (IB_QP_CREATE_CROSS_CHANNEL |
1960 IB_QP_CREATE_MANAGED_SEND |
1961 IB_QP_CREATE_MANAGED_RECV)) {
1962 if (!MLX5_CAP_GEN(mdev, cd)) {
1963 mlx5_ib_dbg(dev, "cross-channel isn't supported\n");
1964 return -EINVAL;
1965 }
1966 if (init_attr->create_flags & IB_QP_CREATE_CROSS_CHANNEL)
1967 qp->flags |= MLX5_IB_QP_CROSS_CHANNEL;
1968 if (init_attr->create_flags & IB_QP_CREATE_MANAGED_SEND)
1969 qp->flags |= MLX5_IB_QP_MANAGED_SEND;
1970 if (init_attr->create_flags & IB_QP_CREATE_MANAGED_RECV)
1971 qp->flags |= MLX5_IB_QP_MANAGED_RECV;
1972 }
Erez Shitritf0313962016-02-21 16:27:17 +02001973
1974 if (init_attr->qp_type == IB_QPT_UD &&
1975 (init_attr->create_flags & IB_QP_CREATE_IPOIB_UD_LSO))
1976 if (!MLX5_CAP_GEN(mdev, ipoib_basic_offloads)) {
1977 mlx5_ib_dbg(dev, "ipoib UD lso qp isn't supported\n");
1978 return -EOPNOTSUPP;
1979 }
1980
Majd Dibbiny358e42e2016-04-17 17:19:37 +03001981 if (init_attr->create_flags & IB_QP_CREATE_SCATTER_FCS) {
1982 if (init_attr->qp_type != IB_QPT_RAW_PACKET) {
1983 mlx5_ib_dbg(dev, "Scatter FCS is supported only for Raw Packet QPs");
1984 return -EOPNOTSUPP;
1985 }
1986 if (!MLX5_CAP_GEN(dev->mdev, eth_net_offloads) ||
1987 !MLX5_CAP_ETH(dev->mdev, scatter_fcs)) {
1988 mlx5_ib_dbg(dev, "Scatter FCS isn't supported\n");
1989 return -EOPNOTSUPP;
1990 }
1991 qp->flags |= MLX5_IB_QP_CAP_SCATTER_FCS;
1992 }
1993
Eli Cohene126ba92013-07-07 17:25:49 +03001994 if (init_attr->sq_sig_type == IB_SIGNAL_ALL_WR)
1995 qp->sq_signal_bits = MLX5_WQE_CTRL_CQ_UPDATE;
1996
Noa Osheroviche4cc4fa2017-01-18 15:40:03 +02001997 if (init_attr->create_flags & IB_QP_CREATE_CVLAN_STRIPPING) {
1998 if (!(MLX5_CAP_GEN(dev->mdev, eth_net_offloads) &&
1999 MLX5_CAP_ETH(dev->mdev, vlan_cap)) ||
2000 (init_attr->qp_type != IB_QPT_RAW_PACKET))
2001 return -EOPNOTSUPP;
2002 qp->flags |= MLX5_IB_QP_CVLAN_STRIPPING;
2003 }
2004
Shamir Rabinovitche00b64f2018-12-17 17:15:18 +02002005 if (udata) {
Eli Cohene126ba92013-07-07 17:25:49 +03002006 if (ib_copy_from_udata(&ucmd, udata, sizeof(ucmd))) {
2007 mlx5_ib_dbg(dev, "copy failed\n");
2008 return -EFAULT;
2009 }
2010
Yonatan Cohen2e43bb32018-10-09 12:05:14 +03002011 if (!check_flags_mask(ucmd.flags,
Mark Bloch8af526e2019-01-15 16:45:32 +02002012 MLX5_QP_FLAG_ALLOW_SCATTER_CQE |
2013 MLX5_QP_FLAG_BFREG_INDEX |
2014 MLX5_QP_FLAG_PACKET_BASED_CREDIT_MODE |
2015 MLX5_QP_FLAG_SCATTER_CQE |
Yonatan Cohen2e43bb32018-10-09 12:05:14 +03002016 MLX5_QP_FLAG_SIGNATURE |
Mark Bloch8af526e2019-01-15 16:45:32 +02002017 MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_MC |
2018 MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC |
2019 MLX5_QP_FLAG_TUNNEL_OFFLOADS |
2020 MLX5_QP_FLAG_TYPE_DCI |
2021 MLX5_QP_FLAG_TYPE_DCT))
Yonatan Cohen2e43bb32018-10-09 12:05:14 +03002022 return -EINVAL;
2023
Shamir Rabinovitch89944452019-02-07 18:44:49 +02002024 err = get_qp_user_index(ucontext, &ucmd, udata->inlen, &uidx);
Haggai Abramovskycfb5e082016-01-14 19:12:57 +02002025 if (err)
2026 return err;
2027
Eli Cohene126ba92013-07-07 17:25:49 +03002028 qp->wq_sig = !!(ucmd.flags & MLX5_QP_FLAG_SIGNATURE);
Yonatan Cohen5d6ff1b2018-10-09 12:05:13 +03002029 if (MLX5_CAP_GEN(dev->mdev, sctr_data_cqe))
2030 qp->scat_cqe = !!(ucmd.flags & MLX5_QP_FLAG_SCATTER_CQE);
Maor Gottliebf95ef6c2017-10-19 08:25:55 +03002031 if (ucmd.flags & MLX5_QP_FLAG_TUNNEL_OFFLOADS) {
2032 if (init_attr->qp_type != IB_QPT_RAW_PACKET ||
2033 !tunnel_offload_supported(mdev)) {
2034 mlx5_ib_dbg(dev, "Tunnel offload isn't supported\n");
2035 return -EOPNOTSUPP;
2036 }
Mark Bloch175edba2018-09-17 13:30:48 +03002037 qp->flags_en |= MLX5_QP_FLAG_TUNNEL_OFFLOADS;
2038 }
2039
2040 if (ucmd.flags & MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC) {
2041 if (init_attr->qp_type != IB_QPT_RAW_PACKET) {
2042 mlx5_ib_dbg(dev, "Self-LB UC isn't supported\n");
2043 return -EOPNOTSUPP;
2044 }
2045 qp->flags_en |= MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC;
2046 }
2047
2048 if (ucmd.flags & MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_MC) {
2049 if (init_attr->qp_type != IB_QPT_RAW_PACKET) {
2050 mlx5_ib_dbg(dev, "Self-LB UM isn't supported\n");
2051 return -EOPNOTSUPP;
2052 }
2053 qp->flags_en |= MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_MC;
Maor Gottliebf95ef6c2017-10-19 08:25:55 +03002054 }
Yishai Hadasc2e53b22017-06-08 16:15:08 +03002055
Danit Goldberg569c6652018-11-30 13:22:05 +02002056 if (ucmd.flags & MLX5_QP_FLAG_PACKET_BASED_CREDIT_MODE) {
2057 if (init_attr->qp_type != IB_QPT_RC ||
2058 !MLX5_CAP_GEN(dev->mdev, qp_packet_based)) {
2059 mlx5_ib_dbg(dev, "packet based credit mode isn't supported\n");
2060 return -EOPNOTSUPP;
2061 }
2062 qp->flags |= MLX5_IB_QP_PACKET_BASED_CREDIT;
2063 }
2064
Yishai Hadasc2e53b22017-06-08 16:15:08 +03002065 if (init_attr->create_flags & IB_QP_CREATE_SOURCE_QPN) {
2066 if (init_attr->qp_type != IB_QPT_UD ||
2067 (MLX5_CAP_GEN(dev->mdev, port_type) !=
2068 MLX5_CAP_PORT_TYPE_IB) ||
2069 !mlx5_get_flow_namespace(dev->mdev, MLX5_FLOW_NAMESPACE_BYPASS)) {
2070 mlx5_ib_dbg(dev, "Source QP option isn't supported\n");
2071 return -EOPNOTSUPP;
2072 }
2073
2074 qp->flags |= MLX5_IB_QP_UNDERLAY;
2075 qp->underlay_qpn = init_attr->source_qpn;
2076 }
Eli Cohene126ba92013-07-07 17:25:49 +03002077 } else {
2078 qp->wq_sig = !!wq_signature;
2079 }
2080
Yishai Hadasc2e53b22017-06-08 16:15:08 +03002081 base = (init_attr->qp_type == IB_QPT_RAW_PACKET ||
2082 qp->flags & MLX5_IB_QP_UNDERLAY) ?
2083 &qp->raw_packet_qp.rq.base :
2084 &qp->trans_qp.base;
2085
Eli Cohene126ba92013-07-07 17:25:49 +03002086 qp->has_rq = qp_has_rq(init_attr);
2087 err = set_rq_size(dev, &init_attr->cap, qp->has_rq,
Shamir Rabinovitche00b64f2018-12-17 17:15:18 +02002088 qp, udata ? &ucmd : NULL);
Eli Cohene126ba92013-07-07 17:25:49 +03002089 if (err) {
2090 mlx5_ib_dbg(dev, "err %d\n", err);
2091 return err;
2092 }
2093
2094 if (pd) {
Shamir Rabinovitche00b64f2018-12-17 17:15:18 +02002095 if (udata) {
Saeed Mahameed938fe832015-05-28 22:28:41 +03002096 __u32 max_wqes =
2097 1 << MLX5_CAP_GEN(mdev, log_max_qp_sz);
Eli Cohene126ba92013-07-07 17:25:49 +03002098 mlx5_ib_dbg(dev, "requested sq_wqe_count (%d)\n", ucmd.sq_wqe_count);
2099 if (ucmd.rq_wqe_shift != qp->rq.wqe_shift ||
2100 ucmd.rq_wqe_count != qp->rq.wqe_cnt) {
2101 mlx5_ib_dbg(dev, "invalid rq params\n");
2102 return -EINVAL;
2103 }
Saeed Mahameed938fe832015-05-28 22:28:41 +03002104 if (ucmd.sq_wqe_count > max_wqes) {
Eli Cohene126ba92013-07-07 17:25:49 +03002105 mlx5_ib_dbg(dev, "requested sq_wqe_count (%d) > max allowed (%d)\n",
Saeed Mahameed938fe832015-05-28 22:28:41 +03002106 ucmd.sq_wqe_count, max_wqes);
Eli Cohene126ba92013-07-07 17:25:49 +03002107 return -EINVAL;
2108 }
Haggai Eranb11a4f92016-02-29 15:45:03 +02002109 if (init_attr->create_flags &
2110 mlx5_ib_create_qp_sqpn_qp1()) {
2111 mlx5_ib_dbg(dev, "user-space is not allowed to create UD QPs spoofing as QP1\n");
2112 return -EINVAL;
2113 }
majd@mellanox.com0fb2ed62016-01-14 19:13:04 +02002114 err = create_user_qp(dev, pd, qp, udata, init_attr, &in,
2115 &resp, &inlen, base);
Eli Cohene126ba92013-07-07 17:25:49 +03002116 if (err)
2117 mlx5_ib_dbg(dev, "err %d\n", err);
2118 } else {
majd@mellanox.com19098df2016-01-14 19:13:03 +02002119 err = create_kernel_qp(dev, init_attr, qp, &in, &inlen,
2120 base);
Eli Cohene126ba92013-07-07 17:25:49 +03002121 if (err)
2122 mlx5_ib_dbg(dev, "err %d\n", err);
Eli Cohene126ba92013-07-07 17:25:49 +03002123 }
2124
2125 if (err)
2126 return err;
2127 } else {
Leon Romanovsky1b9a07e2017-05-10 21:32:18 +03002128 in = kvzalloc(inlen, GFP_KERNEL);
Eli Cohene126ba92013-07-07 17:25:49 +03002129 if (!in)
2130 return -ENOMEM;
2131
2132 qp->create_type = MLX5_QP_EMPTY;
2133 }
2134
2135 if (is_sqp(init_attr->qp_type))
2136 qp->port = init_attr->port_num;
2137
Saeed Mahameed09a7d9e2016-07-19 01:17:59 +03002138 qpc = MLX5_ADDR_OF(create_qp_in, in, qpc);
2139
Noa Osheroviche7b169f2018-02-25 13:39:51 +02002140 MLX5_SET(qpc, qpc, st, mlx5_st);
Saeed Mahameed09a7d9e2016-07-19 01:17:59 +03002141 MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_MIGRATED);
Eli Cohene126ba92013-07-07 17:25:49 +03002142
2143 if (init_attr->qp_type != MLX5_IB_QPT_REG_UMR)
Saeed Mahameed09a7d9e2016-07-19 01:17:59 +03002144 MLX5_SET(qpc, qpc, pd, to_mpd(pd ? pd : devr->p0)->pdn);
Eli Cohene126ba92013-07-07 17:25:49 +03002145 else
Saeed Mahameed09a7d9e2016-07-19 01:17:59 +03002146 MLX5_SET(qpc, qpc, latency_sensitive, 1);
2147
Eli Cohene126ba92013-07-07 17:25:49 +03002148
2149 if (qp->wq_sig)
Saeed Mahameed09a7d9e2016-07-19 01:17:59 +03002150 MLX5_SET(qpc, qpc, wq_signature, 1);
Eli Cohene126ba92013-07-07 17:25:49 +03002151
Eli Cohenf360d882014-04-02 00:10:16 +03002152 if (qp->flags & MLX5_IB_QP_BLOCK_MULTICAST_LOOPBACK)
Saeed Mahameed09a7d9e2016-07-19 01:17:59 +03002153 MLX5_SET(qpc, qpc, block_lb_mc, 1);
Eli Cohenf360d882014-04-02 00:10:16 +03002154
Leon Romanovsky051f2632015-12-20 12:16:11 +02002155 if (qp->flags & MLX5_IB_QP_CROSS_CHANNEL)
Saeed Mahameed09a7d9e2016-07-19 01:17:59 +03002156 MLX5_SET(qpc, qpc, cd_master, 1);
Leon Romanovsky051f2632015-12-20 12:16:11 +02002157 if (qp->flags & MLX5_IB_QP_MANAGED_SEND)
Saeed Mahameed09a7d9e2016-07-19 01:17:59 +03002158 MLX5_SET(qpc, qpc, cd_slave_send, 1);
Leon Romanovsky051f2632015-12-20 12:16:11 +02002159 if (qp->flags & MLX5_IB_QP_MANAGED_RECV)
Saeed Mahameed09a7d9e2016-07-19 01:17:59 +03002160 MLX5_SET(qpc, qpc, cd_slave_receive, 1);
Danit Goldberg569c6652018-11-30 13:22:05 +02002161 if (qp->flags & MLX5_IB_QP_PACKET_BASED_CREDIT)
2162 MLX5_SET(qpc, qpc, req_e2e_credit_mode, 1);
Eli Cohene126ba92013-07-07 17:25:49 +03002163 if (qp->scat_cqe && is_connected(init_attr->qp_type)) {
Yonatan Cohen5d6ff1b2018-10-09 12:05:13 +03002164 configure_responder_scat_cqe(init_attr, qpc);
Yonatan Cohen6f4bc0e2018-10-09 12:05:15 +03002165 configure_requester_scat_cqe(dev, init_attr,
Shamir Rabinovitche00b64f2018-12-17 17:15:18 +02002166 udata ? &ucmd : NULL,
Yonatan Cohen6f4bc0e2018-10-09 12:05:15 +03002167 qpc);
Eli Cohene126ba92013-07-07 17:25:49 +03002168 }
2169
2170 if (qp->rq.wqe_cnt) {
Saeed Mahameed09a7d9e2016-07-19 01:17:59 +03002171 MLX5_SET(qpc, qpc, log_rq_stride, qp->rq.wqe_shift - 4);
2172 MLX5_SET(qpc, qpc, log_rq_size, ilog2(qp->rq.wqe_cnt));
Eli Cohene126ba92013-07-07 17:25:49 +03002173 }
2174
Saeed Mahameed09a7d9e2016-07-19 01:17:59 +03002175 MLX5_SET(qpc, qpc, rq_type, get_rx_type(qp, init_attr));
Eli Cohene126ba92013-07-07 17:25:49 +03002176
Artemy Kovalyov3fd33072017-08-17 15:52:11 +03002177 if (qp->sq.wqe_cnt) {
Saeed Mahameed09a7d9e2016-07-19 01:17:59 +03002178 MLX5_SET(qpc, qpc, log_sq_size, ilog2(qp->sq.wqe_cnt));
Artemy Kovalyov3fd33072017-08-17 15:52:11 +03002179 } else {
Saeed Mahameed09a7d9e2016-07-19 01:17:59 +03002180 MLX5_SET(qpc, qpc, no_sq, 1);
Artemy Kovalyov3fd33072017-08-17 15:52:11 +03002181 if (init_attr->srq &&
2182 init_attr->srq->srq_type == IB_SRQT_TM)
2183 MLX5_SET(qpc, qpc, offload_type,
2184 MLX5_QPC_OFFLOAD_TYPE_RNDV);
2185 }
Eli Cohene126ba92013-07-07 17:25:49 +03002186
2187 /* Set default resources */
2188 switch (init_attr->qp_type) {
2189 case IB_QPT_XRC_TGT:
Saeed Mahameed09a7d9e2016-07-19 01:17:59 +03002190 MLX5_SET(qpc, qpc, cqn_rcv, to_mcq(devr->c0)->mcq.cqn);
2191 MLX5_SET(qpc, qpc, cqn_snd, to_mcq(devr->c0)->mcq.cqn);
2192 MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, to_msrq(devr->s0)->msrq.srqn);
2193 MLX5_SET(qpc, qpc, xrcd, to_mxrcd(init_attr->xrcd)->xrcdn);
Eli Cohene126ba92013-07-07 17:25:49 +03002194 break;
2195 case IB_QPT_XRC_INI:
Saeed Mahameed09a7d9e2016-07-19 01:17:59 +03002196 MLX5_SET(qpc, qpc, cqn_rcv, to_mcq(devr->c0)->mcq.cqn);
2197 MLX5_SET(qpc, qpc, xrcd, to_mxrcd(devr->x1)->xrcdn);
2198 MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, to_msrq(devr->s0)->msrq.srqn);
Eli Cohene126ba92013-07-07 17:25:49 +03002199 break;
2200 default:
2201 if (init_attr->srq) {
Saeed Mahameed09a7d9e2016-07-19 01:17:59 +03002202 MLX5_SET(qpc, qpc, xrcd, to_mxrcd(devr->x0)->xrcdn);
2203 MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, to_msrq(init_attr->srq)->msrq.srqn);
Eli Cohene126ba92013-07-07 17:25:49 +03002204 } else {
Saeed Mahameed09a7d9e2016-07-19 01:17:59 +03002205 MLX5_SET(qpc, qpc, xrcd, to_mxrcd(devr->x1)->xrcdn);
2206 MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, to_msrq(devr->s1)->msrq.srqn);
Eli Cohene126ba92013-07-07 17:25:49 +03002207 }
2208 }
2209
2210 if (init_attr->send_cq)
Saeed Mahameed09a7d9e2016-07-19 01:17:59 +03002211 MLX5_SET(qpc, qpc, cqn_snd, to_mcq(init_attr->send_cq)->mcq.cqn);
Eli Cohene126ba92013-07-07 17:25:49 +03002212
2213 if (init_attr->recv_cq)
Saeed Mahameed09a7d9e2016-07-19 01:17:59 +03002214 MLX5_SET(qpc, qpc, cqn_rcv, to_mcq(init_attr->recv_cq)->mcq.cqn);
Eli Cohene126ba92013-07-07 17:25:49 +03002215
Saeed Mahameed09a7d9e2016-07-19 01:17:59 +03002216 MLX5_SET64(qpc, qpc, dbr_addr, qp->db.dma);
Eli Cohene126ba92013-07-07 17:25:49 +03002217
Saeed Mahameed09a7d9e2016-07-19 01:17:59 +03002218 /* 0xffffff means we ask to work with cqe version 0 */
2219 if (MLX5_CAP_GEN(mdev, cqe_version) == MLX5_CQE_VERSION_V1)
Haggai Abramovskycfb5e082016-01-14 19:12:57 +02002220 MLX5_SET(qpc, qpc, user_index, uidx);
Saeed Mahameed09a7d9e2016-07-19 01:17:59 +03002221
Erez Shitritf0313962016-02-21 16:27:17 +02002222 /* we use IB_QP_CREATE_IPOIB_UD_LSO to indicates ipoib qp */
2223 if (init_attr->qp_type == IB_QPT_UD &&
2224 (init_attr->create_flags & IB_QP_CREATE_IPOIB_UD_LSO)) {
Erez Shitritf0313962016-02-21 16:27:17 +02002225 MLX5_SET(qpc, qpc, ulp_stateless_offload_mode, 1);
2226 qp->flags |= MLX5_IB_QP_LSO;
2227 }
Haggai Abramovskycfb5e082016-01-14 19:12:57 +02002228
Noa Osherovichb1383aa2017-10-29 13:59:45 +02002229 if (init_attr->create_flags & IB_QP_CREATE_PCI_WRITE_END_PADDING) {
2230 if (!MLX5_CAP_GEN(dev->mdev, end_pad)) {
2231 mlx5_ib_dbg(dev, "scatter end padding is not supported\n");
2232 err = -EOPNOTSUPP;
2233 goto err;
2234 } else if (init_attr->qp_type != IB_QPT_RAW_PACKET) {
2235 MLX5_SET(qpc, qpc, end_padding_mode,
2236 MLX5_WQ_END_PAD_MODE_ALIGN);
2237 } else {
2238 qp->flags |= MLX5_IB_QP_PCI_WRITE_END_PADDING;
2239 }
2240 }
2241
Boris Pismenny2c292db2018-03-08 15:51:40 +02002242 if (inlen < 0) {
2243 err = -EINVAL;
2244 goto err;
2245 }
2246
Yishai Hadasc2e53b22017-06-08 16:15:08 +03002247 if (init_attr->qp_type == IB_QPT_RAW_PACKET ||
2248 qp->flags & MLX5_IB_QP_UNDERLAY) {
majd@mellanox.com0fb2ed62016-01-14 19:13:04 +02002249 qp->raw_packet_qp.sq.ubuffer.buf_addr = ucmd.sq_buf_addr;
2250 raw_packet_qp_copy_info(qp, &qp->raw_packet_qp);
Yishai Hadas7f720522018-09-20 21:45:18 +03002251 err = create_raw_packet_qp(dev, qp, in, inlen, pd, udata,
2252 &resp);
majd@mellanox.com0fb2ed62016-01-14 19:13:04 +02002253 } else {
2254 err = mlx5_core_create_qp(dev->mdev, &base->mqp, in, inlen);
2255 }
2256
Eli Cohene126ba92013-07-07 17:25:49 +03002257 if (err) {
2258 mlx5_ib_dbg(dev, "create qp failed\n");
2259 goto err_create;
2260 }
2261
Al Viro479163f2014-11-20 08:13:57 +00002262 kvfree(in);
Eli Cohene126ba92013-07-07 17:25:49 +03002263
majd@mellanox.com19098df2016-01-14 19:13:03 +02002264 base->container_mibqp = qp;
2265 base->mqp.event = mlx5_ib_qp_event;
Eli Cohene126ba92013-07-07 17:25:49 +03002266
Maor Gottlieb89ea94a72016-06-17 15:01:38 +03002267 get_cqs(init_attr->qp_type, init_attr->send_cq, init_attr->recv_cq,
2268 &send_cq, &recv_cq);
2269 spin_lock_irqsave(&dev->reset_flow_resource_lock, flags);
2270 mlx5_ib_lock_cqs(send_cq, recv_cq);
2271 /* Maintain device to QPs access, needed for further handling via reset
2272 * flow
2273 */
2274 list_add_tail(&qp->qps_list, &dev->qp_list);
2275 /* Maintain CQ to QPs access, needed for further handling via reset flow
2276 */
2277 if (send_cq)
2278 list_add_tail(&qp->cq_send_list, &send_cq->list_send_qp);
2279 if (recv_cq)
2280 list_add_tail(&qp->cq_recv_list, &recv_cq->list_recv_qp);
2281 mlx5_ib_unlock_cqs(send_cq, recv_cq);
2282 spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags);
2283
Eli Cohene126ba92013-07-07 17:25:49 +03002284 return 0;
2285
2286err_create:
2287 if (qp->create_type == MLX5_QP_USER)
Shamir Rabinovitchbdeacab2019-03-31 19:10:06 +03002288 destroy_qp_user(dev, pd, qp, base, udata);
Eli Cohene126ba92013-07-07 17:25:49 +03002289 else if (qp->create_type == MLX5_QP_KERNEL)
2290 destroy_qp_kernel(dev, qp);
2291
Noa Osherovichb1383aa2017-10-29 13:59:45 +02002292err:
Al Viro479163f2014-11-20 08:13:57 +00002293 kvfree(in);
Eli Cohene126ba92013-07-07 17:25:49 +03002294 return err;
2295}
2296
2297static void mlx5_ib_lock_cqs(struct mlx5_ib_cq *send_cq, struct mlx5_ib_cq *recv_cq)
2298 __acquires(&send_cq->lock) __acquires(&recv_cq->lock)
2299{
2300 if (send_cq) {
2301 if (recv_cq) {
2302 if (send_cq->mcq.cqn < recv_cq->mcq.cqn) {
Maor Gottlieb89ea94a72016-06-17 15:01:38 +03002303 spin_lock(&send_cq->lock);
Eli Cohene126ba92013-07-07 17:25:49 +03002304 spin_lock_nested(&recv_cq->lock,
2305 SINGLE_DEPTH_NESTING);
2306 } else if (send_cq->mcq.cqn == recv_cq->mcq.cqn) {
Maor Gottlieb89ea94a72016-06-17 15:01:38 +03002307 spin_lock(&send_cq->lock);
Eli Cohene126ba92013-07-07 17:25:49 +03002308 __acquire(&recv_cq->lock);
2309 } else {
Maor Gottlieb89ea94a72016-06-17 15:01:38 +03002310 spin_lock(&recv_cq->lock);
Eli Cohene126ba92013-07-07 17:25:49 +03002311 spin_lock_nested(&send_cq->lock,
2312 SINGLE_DEPTH_NESTING);
2313 }
2314 } else {
Maor Gottlieb89ea94a72016-06-17 15:01:38 +03002315 spin_lock(&send_cq->lock);
Eli Cohen6a4f1392014-12-02 12:26:18 +02002316 __acquire(&recv_cq->lock);
Eli Cohene126ba92013-07-07 17:25:49 +03002317 }
2318 } else if (recv_cq) {
Maor Gottlieb89ea94a72016-06-17 15:01:38 +03002319 spin_lock(&recv_cq->lock);
Eli Cohen6a4f1392014-12-02 12:26:18 +02002320 __acquire(&send_cq->lock);
2321 } else {
2322 __acquire(&send_cq->lock);
2323 __acquire(&recv_cq->lock);
Eli Cohene126ba92013-07-07 17:25:49 +03002324 }
2325}
2326
2327static void mlx5_ib_unlock_cqs(struct mlx5_ib_cq *send_cq, struct mlx5_ib_cq *recv_cq)
2328 __releases(&send_cq->lock) __releases(&recv_cq->lock)
2329{
2330 if (send_cq) {
2331 if (recv_cq) {
2332 if (send_cq->mcq.cqn < recv_cq->mcq.cqn) {
2333 spin_unlock(&recv_cq->lock);
Maor Gottlieb89ea94a72016-06-17 15:01:38 +03002334 spin_unlock(&send_cq->lock);
Eli Cohene126ba92013-07-07 17:25:49 +03002335 } else if (send_cq->mcq.cqn == recv_cq->mcq.cqn) {
2336 __release(&recv_cq->lock);
Maor Gottlieb89ea94a72016-06-17 15:01:38 +03002337 spin_unlock(&send_cq->lock);
Eli Cohene126ba92013-07-07 17:25:49 +03002338 } else {
2339 spin_unlock(&send_cq->lock);
Maor Gottlieb89ea94a72016-06-17 15:01:38 +03002340 spin_unlock(&recv_cq->lock);
Eli Cohene126ba92013-07-07 17:25:49 +03002341 }
2342 } else {
Eli Cohen6a4f1392014-12-02 12:26:18 +02002343 __release(&recv_cq->lock);
Maor Gottlieb89ea94a72016-06-17 15:01:38 +03002344 spin_unlock(&send_cq->lock);
Eli Cohene126ba92013-07-07 17:25:49 +03002345 }
2346 } else if (recv_cq) {
Eli Cohen6a4f1392014-12-02 12:26:18 +02002347 __release(&send_cq->lock);
Maor Gottlieb89ea94a72016-06-17 15:01:38 +03002348 spin_unlock(&recv_cq->lock);
Eli Cohen6a4f1392014-12-02 12:26:18 +02002349 } else {
2350 __release(&recv_cq->lock);
2351 __release(&send_cq->lock);
Eli Cohene126ba92013-07-07 17:25:49 +03002352 }
2353}
2354
2355static struct mlx5_ib_pd *get_pd(struct mlx5_ib_qp *qp)
2356{
2357 return to_mpd(qp->ibqp.pd);
2358}
2359
Maor Gottlieb89ea94a72016-06-17 15:01:38 +03002360static void get_cqs(enum ib_qp_type qp_type,
2361 struct ib_cq *ib_send_cq, struct ib_cq *ib_recv_cq,
Eli Cohene126ba92013-07-07 17:25:49 +03002362 struct mlx5_ib_cq **send_cq, struct mlx5_ib_cq **recv_cq)
2363{
Maor Gottlieb89ea94a72016-06-17 15:01:38 +03002364 switch (qp_type) {
Eli Cohene126ba92013-07-07 17:25:49 +03002365 case IB_QPT_XRC_TGT:
2366 *send_cq = NULL;
2367 *recv_cq = NULL;
2368 break;
2369 case MLX5_IB_QPT_REG_UMR:
2370 case IB_QPT_XRC_INI:
Maor Gottlieb89ea94a72016-06-17 15:01:38 +03002371 *send_cq = ib_send_cq ? to_mcq(ib_send_cq) : NULL;
Eli Cohene126ba92013-07-07 17:25:49 +03002372 *recv_cq = NULL;
2373 break;
2374
2375 case IB_QPT_SMI:
Haggai Erand16e91d2016-02-29 15:45:05 +02002376 case MLX5_IB_QPT_HW_GSI:
Eli Cohene126ba92013-07-07 17:25:49 +03002377 case IB_QPT_RC:
2378 case IB_QPT_UC:
2379 case IB_QPT_UD:
2380 case IB_QPT_RAW_IPV6:
2381 case IB_QPT_RAW_ETHERTYPE:
majd@mellanox.com0fb2ed62016-01-14 19:13:04 +02002382 case IB_QPT_RAW_PACKET:
Maor Gottlieb89ea94a72016-06-17 15:01:38 +03002383 *send_cq = ib_send_cq ? to_mcq(ib_send_cq) : NULL;
2384 *recv_cq = ib_recv_cq ? to_mcq(ib_recv_cq) : NULL;
Eli Cohene126ba92013-07-07 17:25:49 +03002385 break;
2386
Eli Cohene126ba92013-07-07 17:25:49 +03002387 case IB_QPT_MAX:
2388 default:
2389 *send_cq = NULL;
2390 *recv_cq = NULL;
2391 break;
2392 }
2393}
2394
majd@mellanox.comad5f8e92016-01-14 19:13:08 +02002395static int modify_raw_packet_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
Aviv Heller13eab212016-09-18 20:48:04 +03002396 const struct mlx5_modify_raw_qp_param *raw_qp_param,
2397 u8 lag_tx_affinity);
majd@mellanox.comad5f8e92016-01-14 19:13:08 +02002398
Shamir Rabinovitchbdeacab2019-03-31 19:10:06 +03002399static void destroy_qp_common(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
2400 struct ib_udata *udata)
Eli Cohene126ba92013-07-07 17:25:49 +03002401{
2402 struct mlx5_ib_cq *send_cq, *recv_cq;
Yishai Hadasc2e53b22017-06-08 16:15:08 +03002403 struct mlx5_ib_qp_base *base;
Maor Gottlieb89ea94a72016-06-17 15:01:38 +03002404 unsigned long flags;
Eli Cohene126ba92013-07-07 17:25:49 +03002405 int err;
2406
Yishai Hadas28d61372016-05-23 15:20:56 +03002407 if (qp->ibqp.rwq_ind_tbl) {
2408 destroy_rss_raw_qp_tir(dev, qp);
2409 return;
2410 }
2411
Yishai Hadasc2e53b22017-06-08 16:15:08 +03002412 base = (qp->ibqp.qp_type == IB_QPT_RAW_PACKET ||
2413 qp->flags & MLX5_IB_QP_UNDERLAY) ?
majd@mellanox.com0fb2ed62016-01-14 19:13:04 +02002414 &qp->raw_packet_qp.rq.base :
2415 &qp->trans_qp.base;
2416
Haggai Eran6aec21f2014-12-11 17:04:23 +02002417 if (qp->state != IB_QPS_RESET) {
Yishai Hadasc2e53b22017-06-08 16:15:08 +03002418 if (qp->ibqp.qp_type != IB_QPT_RAW_PACKET &&
2419 !(qp->flags & MLX5_IB_QP_UNDERLAY)) {
majd@mellanox.comad5f8e92016-01-14 19:13:08 +02002420 err = mlx5_core_qp_modify(dev->mdev,
Saeed Mahameed1a412fb2016-07-19 18:03:21 +03002421 MLX5_CMD_OP_2RST_QP, 0,
2422 NULL, &base->mqp);
majd@mellanox.comad5f8e92016-01-14 19:13:08 +02002423 } else {
Alex Vesker0680efa2016-08-28 12:25:52 +03002424 struct mlx5_modify_raw_qp_param raw_qp_param = {
2425 .operation = MLX5_CMD_OP_2RST_QP
2426 };
2427
Aviv Heller13eab212016-09-18 20:48:04 +03002428 err = modify_raw_packet_qp(dev, qp, &raw_qp_param, 0);
majd@mellanox.comad5f8e92016-01-14 19:13:08 +02002429 }
2430 if (err)
majd@mellanox.com427c1e72016-01-14 19:13:07 +02002431 mlx5_ib_warn(dev, "mlx5_ib: modify QP 0x%06x to RESET failed\n",
majd@mellanox.com19098df2016-01-14 19:13:03 +02002432 base->mqp.qpn);
Haggai Eran6aec21f2014-12-11 17:04:23 +02002433 }
Eli Cohene126ba92013-07-07 17:25:49 +03002434
Maor Gottlieb89ea94a72016-06-17 15:01:38 +03002435 get_cqs(qp->ibqp.qp_type, qp->ibqp.send_cq, qp->ibqp.recv_cq,
2436 &send_cq, &recv_cq);
2437
2438 spin_lock_irqsave(&dev->reset_flow_resource_lock, flags);
2439 mlx5_ib_lock_cqs(send_cq, recv_cq);
2440 /* del from lists under both locks above to protect reset flow paths */
2441 list_del(&qp->qps_list);
2442 if (send_cq)
2443 list_del(&qp->cq_send_list);
2444
2445 if (recv_cq)
2446 list_del(&qp->cq_recv_list);
Eli Cohene126ba92013-07-07 17:25:49 +03002447
2448 if (qp->create_type == MLX5_QP_KERNEL) {
majd@mellanox.com19098df2016-01-14 19:13:03 +02002449 __mlx5_ib_cq_clean(recv_cq, base->mqp.qpn,
Eli Cohene126ba92013-07-07 17:25:49 +03002450 qp->ibqp.srq ? to_msrq(qp->ibqp.srq) : NULL);
2451 if (send_cq != recv_cq)
majd@mellanox.com19098df2016-01-14 19:13:03 +02002452 __mlx5_ib_cq_clean(send_cq, base->mqp.qpn,
2453 NULL);
Eli Cohene126ba92013-07-07 17:25:49 +03002454 }
Maor Gottlieb89ea94a72016-06-17 15:01:38 +03002455 mlx5_ib_unlock_cqs(send_cq, recv_cq);
2456 spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags);
Eli Cohene126ba92013-07-07 17:25:49 +03002457
Yishai Hadasc2e53b22017-06-08 16:15:08 +03002458 if (qp->ibqp.qp_type == IB_QPT_RAW_PACKET ||
2459 qp->flags & MLX5_IB_QP_UNDERLAY) {
majd@mellanox.com0fb2ed62016-01-14 19:13:04 +02002460 destroy_raw_packet_qp(dev, qp);
2461 } else {
2462 err = mlx5_core_destroy_qp(dev->mdev, &base->mqp);
2463 if (err)
2464 mlx5_ib_warn(dev, "failed to destroy QP 0x%x\n",
2465 base->mqp.qpn);
2466 }
Eli Cohene126ba92013-07-07 17:25:49 +03002467
Eli Cohene126ba92013-07-07 17:25:49 +03002468 if (qp->create_type == MLX5_QP_KERNEL)
2469 destroy_qp_kernel(dev, qp);
2470 else if (qp->create_type == MLX5_QP_USER)
Shamir Rabinovitchbdeacab2019-03-31 19:10:06 +03002471 destroy_qp_user(dev, &get_pd(qp)->ibpd, qp, base, udata);
Eli Cohene126ba92013-07-07 17:25:49 +03002472}
2473
2474static const char *ib_qp_type_str(enum ib_qp_type type)
2475{
2476 switch (type) {
2477 case IB_QPT_SMI:
2478 return "IB_QPT_SMI";
2479 case IB_QPT_GSI:
2480 return "IB_QPT_GSI";
2481 case IB_QPT_RC:
2482 return "IB_QPT_RC";
2483 case IB_QPT_UC:
2484 return "IB_QPT_UC";
2485 case IB_QPT_UD:
2486 return "IB_QPT_UD";
2487 case IB_QPT_RAW_IPV6:
2488 return "IB_QPT_RAW_IPV6";
2489 case IB_QPT_RAW_ETHERTYPE:
2490 return "IB_QPT_RAW_ETHERTYPE";
2491 case IB_QPT_XRC_INI:
2492 return "IB_QPT_XRC_INI";
2493 case IB_QPT_XRC_TGT:
2494 return "IB_QPT_XRC_TGT";
2495 case IB_QPT_RAW_PACKET:
2496 return "IB_QPT_RAW_PACKET";
2497 case MLX5_IB_QPT_REG_UMR:
2498 return "MLX5_IB_QPT_REG_UMR";
Moni Shouab4aaa1f2018-01-02 16:19:31 +02002499 case IB_QPT_DRIVER:
2500 return "IB_QPT_DRIVER";
Eli Cohene126ba92013-07-07 17:25:49 +03002501 case IB_QPT_MAX:
2502 default:
2503 return "Invalid QP type";
2504 }
2505}
2506
Moni Shouab4aaa1f2018-01-02 16:19:31 +02002507static struct ib_qp *mlx5_ib_create_dct(struct ib_pd *pd,
2508 struct ib_qp_init_attr *attr,
Shamir Rabinovitch89944452019-02-07 18:44:49 +02002509 struct mlx5_ib_create_qp *ucmd,
2510 struct ib_udata *udata)
Moni Shouab4aaa1f2018-01-02 16:19:31 +02002511{
Shamir Rabinovitch89944452019-02-07 18:44:49 +02002512 struct mlx5_ib_ucontext *ucontext = rdma_udata_to_drv_context(
2513 udata, struct mlx5_ib_ucontext, ibucontext);
Moni Shouab4aaa1f2018-01-02 16:19:31 +02002514 struct mlx5_ib_qp *qp;
2515 int err = 0;
2516 u32 uidx = MLX5_IB_DEFAULT_UIDX;
2517 void *dctc;
2518
2519 if (!attr->srq || !attr->recv_cq)
2520 return ERR_PTR(-EINVAL);
2521
Shamir Rabinovitch89944452019-02-07 18:44:49 +02002522 err = get_qp_user_index(ucontext, ucmd, sizeof(*ucmd), &uidx);
Moni Shouab4aaa1f2018-01-02 16:19:31 +02002523 if (err)
2524 return ERR_PTR(err);
2525
2526 qp = kzalloc(sizeof(*qp), GFP_KERNEL);
2527 if (!qp)
2528 return ERR_PTR(-ENOMEM);
2529
2530 qp->dct.in = kzalloc(MLX5_ST_SZ_BYTES(create_dct_in), GFP_KERNEL);
2531 if (!qp->dct.in) {
2532 err = -ENOMEM;
2533 goto err_free;
2534 }
2535
Yishai Hadasa01a5862018-09-20 21:39:24 +03002536 MLX5_SET(create_dct_in, qp->dct.in, uid, to_mpd(pd)->uid);
Moni Shouab4aaa1f2018-01-02 16:19:31 +02002537 dctc = MLX5_ADDR_OF(create_dct_in, qp->dct.in, dct_context_entry);
Moni Shoua776a3902018-01-02 16:19:33 +02002538 qp->qp_sub_type = MLX5_IB_QPT_DCT;
Moni Shouab4aaa1f2018-01-02 16:19:31 +02002539 MLX5_SET(dctc, dctc, pd, to_mpd(pd)->pdn);
2540 MLX5_SET(dctc, dctc, srqn_xrqn, to_msrq(attr->srq)->msrq.srqn);
2541 MLX5_SET(dctc, dctc, cqn, to_mcq(attr->recv_cq)->mcq.cqn);
2542 MLX5_SET64(dctc, dctc, dc_access_key, ucmd->access_key);
2543 MLX5_SET(dctc, dctc, user_index, uidx);
2544
Yonatan Cohen5d6ff1b2018-10-09 12:05:13 +03002545 if (ucmd->flags & MLX5_QP_FLAG_SCATTER_CQE)
2546 configure_responder_scat_cqe(attr, dctc);
2547
Moni Shouab4aaa1f2018-01-02 16:19:31 +02002548 qp->state = IB_QPS_RESET;
2549
2550 return &qp->ibqp;
2551err_free:
2552 kfree(qp);
2553 return ERR_PTR(err);
2554}
2555
2556static int set_mlx_qp_type(struct mlx5_ib_dev *dev,
2557 struct ib_qp_init_attr *init_attr,
2558 struct mlx5_ib_create_qp *ucmd,
2559 struct ib_udata *udata)
2560{
2561 enum { MLX_QP_FLAGS = MLX5_QP_FLAG_TYPE_DCT | MLX5_QP_FLAG_TYPE_DCI };
2562 int err;
2563
2564 if (!udata)
2565 return -EINVAL;
2566
2567 if (udata->inlen < sizeof(*ucmd)) {
2568 mlx5_ib_dbg(dev, "create_qp user command is smaller than expected\n");
2569 return -EINVAL;
2570 }
2571 err = ib_copy_from_udata(ucmd, udata, sizeof(*ucmd));
2572 if (err)
2573 return err;
2574
2575 if ((ucmd->flags & MLX_QP_FLAGS) == MLX5_QP_FLAG_TYPE_DCI) {
2576 init_attr->qp_type = MLX5_IB_QPT_DCI;
2577 } else {
2578 if ((ucmd->flags & MLX_QP_FLAGS) == MLX5_QP_FLAG_TYPE_DCT) {
2579 init_attr->qp_type = MLX5_IB_QPT_DCT;
2580 } else {
2581 mlx5_ib_dbg(dev, "Invalid QP flags\n");
2582 return -EINVAL;
2583 }
2584 }
2585
2586 if (!MLX5_CAP_GEN(dev->mdev, dct)) {
2587 mlx5_ib_dbg(dev, "DC transport is not supported\n");
2588 return -EOPNOTSUPP;
2589 }
2590
2591 return 0;
2592}
2593
Eli Cohene126ba92013-07-07 17:25:49 +03002594struct ib_qp *mlx5_ib_create_qp(struct ib_pd *pd,
Moni Shouab4aaa1f2018-01-02 16:19:31 +02002595 struct ib_qp_init_attr *verbs_init_attr,
Eli Cohene126ba92013-07-07 17:25:49 +03002596 struct ib_udata *udata)
2597{
2598 struct mlx5_ib_dev *dev;
2599 struct mlx5_ib_qp *qp;
2600 u16 xrcdn = 0;
2601 int err;
Moni Shouab4aaa1f2018-01-02 16:19:31 +02002602 struct ib_qp_init_attr mlx_init_attr;
2603 struct ib_qp_init_attr *init_attr = verbs_init_attr;
Shamir Rabinovitch89944452019-02-07 18:44:49 +02002604 struct mlx5_ib_ucontext *ucontext = rdma_udata_to_drv_context(
2605 udata, struct mlx5_ib_ucontext, ibucontext);
Eli Cohene126ba92013-07-07 17:25:49 +03002606
2607 if (pd) {
2608 dev = to_mdev(pd->device);
majd@mellanox.com0fb2ed62016-01-14 19:13:04 +02002609
2610 if (init_attr->qp_type == IB_QPT_RAW_PACKET) {
Shamir Rabinovitch89944452019-02-07 18:44:49 +02002611 if (!ucontext) {
majd@mellanox.com0fb2ed62016-01-14 19:13:04 +02002612 mlx5_ib_dbg(dev, "Raw Packet QP is not supported for kernel consumers\n");
2613 return ERR_PTR(-EINVAL);
Shamir Rabinovitch89944452019-02-07 18:44:49 +02002614 } else if (!ucontext->cqe_version) {
majd@mellanox.com0fb2ed62016-01-14 19:13:04 +02002615 mlx5_ib_dbg(dev, "Raw Packet QP is only supported for CQE version > 0\n");
2616 return ERR_PTR(-EINVAL);
2617 }
2618 }
Majd Dibbiny09f16cf2016-01-28 17:51:48 +02002619 } else {
2620 /* being cautious here */
2621 if (init_attr->qp_type != IB_QPT_XRC_TGT &&
2622 init_attr->qp_type != MLX5_IB_QPT_REG_UMR) {
2623 pr_warn("%s: no PD for transport %s\n", __func__,
2624 ib_qp_type_str(init_attr->qp_type));
2625 return ERR_PTR(-EINVAL);
2626 }
2627 dev = to_mdev(to_mxrcd(init_attr->xrcd)->ibxrcd.device);
Eli Cohene126ba92013-07-07 17:25:49 +03002628 }
2629
Moni Shouab4aaa1f2018-01-02 16:19:31 +02002630 if (init_attr->qp_type == IB_QPT_DRIVER) {
2631 struct mlx5_ib_create_qp ucmd;
2632
2633 init_attr = &mlx_init_attr;
2634 memcpy(init_attr, verbs_init_attr, sizeof(*verbs_init_attr));
2635 err = set_mlx_qp_type(dev, init_attr, &ucmd, udata);
2636 if (err)
2637 return ERR_PTR(err);
Moni Shouac32a4f22018-01-02 16:19:32 +02002638
2639 if (init_attr->qp_type == MLX5_IB_QPT_DCI) {
2640 if (init_attr->cap.max_recv_wr ||
2641 init_attr->cap.max_recv_sge) {
2642 mlx5_ib_dbg(dev, "DCI QP requires zero size receive queue\n");
2643 return ERR_PTR(-EINVAL);
2644 }
Moni Shoua776a3902018-01-02 16:19:33 +02002645 } else {
Shamir Rabinovitch89944452019-02-07 18:44:49 +02002646 return mlx5_ib_create_dct(pd, init_attr, &ucmd, udata);
Moni Shouac32a4f22018-01-02 16:19:32 +02002647 }
Moni Shouab4aaa1f2018-01-02 16:19:31 +02002648 }
2649
Eli Cohene126ba92013-07-07 17:25:49 +03002650 switch (init_attr->qp_type) {
2651 case IB_QPT_XRC_TGT:
2652 case IB_QPT_XRC_INI:
Saeed Mahameed938fe832015-05-28 22:28:41 +03002653 if (!MLX5_CAP_GEN(dev->mdev, xrc)) {
Eli Cohene126ba92013-07-07 17:25:49 +03002654 mlx5_ib_dbg(dev, "XRC not supported\n");
2655 return ERR_PTR(-ENOSYS);
2656 }
2657 init_attr->recv_cq = NULL;
2658 if (init_attr->qp_type == IB_QPT_XRC_TGT) {
2659 xrcdn = to_mxrcd(init_attr->xrcd)->xrcdn;
2660 init_attr->send_cq = NULL;
2661 }
2662
2663 /* fall through */
majd@mellanox.com0fb2ed62016-01-14 19:13:04 +02002664 case IB_QPT_RAW_PACKET:
Eli Cohene126ba92013-07-07 17:25:49 +03002665 case IB_QPT_RC:
2666 case IB_QPT_UC:
2667 case IB_QPT_UD:
2668 case IB_QPT_SMI:
Haggai Erand16e91d2016-02-29 15:45:05 +02002669 case MLX5_IB_QPT_HW_GSI:
Eli Cohene126ba92013-07-07 17:25:49 +03002670 case MLX5_IB_QPT_REG_UMR:
Moni Shouac32a4f22018-01-02 16:19:32 +02002671 case MLX5_IB_QPT_DCI:
Eli Cohene126ba92013-07-07 17:25:49 +03002672 qp = kzalloc(sizeof(*qp), GFP_KERNEL);
2673 if (!qp)
2674 return ERR_PTR(-ENOMEM);
2675
2676 err = create_qp_common(dev, pd, init_attr, udata, qp);
2677 if (err) {
2678 mlx5_ib_dbg(dev, "create_qp_common failed\n");
2679 kfree(qp);
2680 return ERR_PTR(err);
2681 }
2682
2683 if (is_qp0(init_attr->qp_type))
2684 qp->ibqp.qp_num = 0;
2685 else if (is_qp1(init_attr->qp_type))
2686 qp->ibqp.qp_num = 1;
2687 else
majd@mellanox.com19098df2016-01-14 19:13:03 +02002688 qp->ibqp.qp_num = qp->trans_qp.base.mqp.qpn;
Eli Cohene126ba92013-07-07 17:25:49 +03002689
2690 mlx5_ib_dbg(dev, "ib qpnum 0x%x, mlx qpn 0x%x, rcqn 0x%x, scqn 0x%x\n",
majd@mellanox.com19098df2016-01-14 19:13:03 +02002691 qp->ibqp.qp_num, qp->trans_qp.base.mqp.qpn,
Eli Cohena1ab8402016-10-27 16:36:46 +03002692 init_attr->recv_cq ? to_mcq(init_attr->recv_cq)->mcq.cqn : -1,
2693 init_attr->send_cq ? to_mcq(init_attr->send_cq)->mcq.cqn : -1);
Eli Cohene126ba92013-07-07 17:25:49 +03002694
majd@mellanox.com19098df2016-01-14 19:13:03 +02002695 qp->trans_qp.xrcdn = xrcdn;
Eli Cohene126ba92013-07-07 17:25:49 +03002696
2697 break;
2698
Haggai Erand16e91d2016-02-29 15:45:05 +02002699 case IB_QPT_GSI:
2700 return mlx5_ib_gsi_create_qp(pd, init_attr);
2701
Eli Cohene126ba92013-07-07 17:25:49 +03002702 case IB_QPT_RAW_IPV6:
2703 case IB_QPT_RAW_ETHERTYPE:
Eli Cohene126ba92013-07-07 17:25:49 +03002704 case IB_QPT_MAX:
2705 default:
2706 mlx5_ib_dbg(dev, "unsupported qp type %d\n",
2707 init_attr->qp_type);
2708 /* Don't support raw QPs */
2709 return ERR_PTR(-EINVAL);
2710 }
2711
Moni Shouab4aaa1f2018-01-02 16:19:31 +02002712 if (verbs_init_attr->qp_type == IB_QPT_DRIVER)
2713 qp->qp_sub_type = init_attr->qp_type;
2714
Eli Cohene126ba92013-07-07 17:25:49 +03002715 return &qp->ibqp;
2716}
2717
Moni Shoua776a3902018-01-02 16:19:33 +02002718static int mlx5_ib_destroy_dct(struct mlx5_ib_qp *mqp)
2719{
2720 struct mlx5_ib_dev *dev = to_mdev(mqp->ibqp.device);
2721
2722 if (mqp->state == IB_QPS_RTR) {
2723 int err;
2724
2725 err = mlx5_core_destroy_dct(dev->mdev, &mqp->dct.mdct);
2726 if (err) {
2727 mlx5_ib_warn(dev, "failed to destroy DCT %d\n", err);
2728 return err;
2729 }
2730 }
2731
2732 kfree(mqp->dct.in);
2733 kfree(mqp);
2734 return 0;
2735}
2736
Shamir Rabinovitchc4367a22019-03-31 19:10:05 +03002737int mlx5_ib_destroy_qp(struct ib_qp *qp, struct ib_udata *udata)
Eli Cohene126ba92013-07-07 17:25:49 +03002738{
2739 struct mlx5_ib_dev *dev = to_mdev(qp->device);
2740 struct mlx5_ib_qp *mqp = to_mqp(qp);
2741
Haggai Erand16e91d2016-02-29 15:45:05 +02002742 if (unlikely(qp->qp_type == IB_QPT_GSI))
2743 return mlx5_ib_gsi_destroy_qp(qp);
2744
Moni Shoua776a3902018-01-02 16:19:33 +02002745 if (mqp->qp_sub_type == MLX5_IB_QPT_DCT)
2746 return mlx5_ib_destroy_dct(mqp);
2747
Shamir Rabinovitchbdeacab2019-03-31 19:10:06 +03002748 destroy_qp_common(dev, mqp, udata);
Eli Cohene126ba92013-07-07 17:25:49 +03002749
2750 kfree(mqp);
2751
2752 return 0;
2753}
2754
Yonatan Cohena60109d2018-10-10 09:25:16 +03002755static int to_mlx5_access_flags(struct mlx5_ib_qp *qp,
2756 const struct ib_qp_attr *attr,
Bart Van Asschebf3b4f02019-01-30 16:30:51 -08002757 int attr_mask, __be32 *hw_access_flags_be)
Eli Cohene126ba92013-07-07 17:25:49 +03002758{
Eli Cohene126ba92013-07-07 17:25:49 +03002759 u8 dest_rd_atomic;
Bart Van Asschebf3b4f02019-01-30 16:30:51 -08002760 u32 access_flags, hw_access_flags = 0;
Eli Cohene126ba92013-07-07 17:25:49 +03002761
Yonatan Cohena60109d2018-10-10 09:25:16 +03002762 struct mlx5_ib_dev *dev = to_mdev(qp->ibqp.device);
2763
Eli Cohene126ba92013-07-07 17:25:49 +03002764 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
2765 dest_rd_atomic = attr->max_dest_rd_atomic;
2766 else
majd@mellanox.com19098df2016-01-14 19:13:03 +02002767 dest_rd_atomic = qp->trans_qp.resp_depth;
Eli Cohene126ba92013-07-07 17:25:49 +03002768
2769 if (attr_mask & IB_QP_ACCESS_FLAGS)
2770 access_flags = attr->qp_access_flags;
2771 else
majd@mellanox.com19098df2016-01-14 19:13:03 +02002772 access_flags = qp->trans_qp.atomic_rd_en;
Eli Cohene126ba92013-07-07 17:25:49 +03002773
2774 if (!dest_rd_atomic)
2775 access_flags &= IB_ACCESS_REMOTE_WRITE;
2776
2777 if (access_flags & IB_ACCESS_REMOTE_READ)
Bart Van Asschebf3b4f02019-01-30 16:30:51 -08002778 hw_access_flags |= MLX5_QP_BIT_RRE;
Yonatan Cohen13f8d9c2018-11-21 13:48:39 +02002779 if (access_flags & IB_ACCESS_REMOTE_ATOMIC) {
Yonatan Cohena60109d2018-10-10 09:25:16 +03002780 int atomic_mode;
Eli Cohene126ba92013-07-07 17:25:49 +03002781
Yonatan Cohena60109d2018-10-10 09:25:16 +03002782 atomic_mode = get_atomic_mode(dev, qp->ibqp.qp_type);
2783 if (atomic_mode < 0)
2784 return -EOPNOTSUPP;
2785
Bart Van Asschebf3b4f02019-01-30 16:30:51 -08002786 hw_access_flags |= MLX5_QP_BIT_RAE;
2787 hw_access_flags |= atomic_mode << MLX5_ATOMIC_MODE_OFFSET;
Yonatan Cohena60109d2018-10-10 09:25:16 +03002788 }
2789
2790 if (access_flags & IB_ACCESS_REMOTE_WRITE)
Bart Van Asschebf3b4f02019-01-30 16:30:51 -08002791 hw_access_flags |= MLX5_QP_BIT_RWE;
Yonatan Cohena60109d2018-10-10 09:25:16 +03002792
Bart Van Asschebf3b4f02019-01-30 16:30:51 -08002793 *hw_access_flags_be = cpu_to_be32(hw_access_flags);
Yonatan Cohena60109d2018-10-10 09:25:16 +03002794
2795 return 0;
Eli Cohene126ba92013-07-07 17:25:49 +03002796}
2797
2798enum {
2799 MLX5_PATH_FLAG_FL = 1 << 0,
2800 MLX5_PATH_FLAG_FREE_AR = 1 << 1,
2801 MLX5_PATH_FLAG_COUNTER = 1 << 2,
2802};
2803
2804static int ib_rate_to_mlx5(struct mlx5_ib_dev *dev, u8 rate)
2805{
Danit Goldberg4f32ac22018-04-23 17:01:54 +03002806 if (rate == IB_RATE_PORT_CURRENT)
Eli Cohene126ba92013-07-07 17:25:49 +03002807 return 0;
Eli Cohene126ba92013-07-07 17:25:49 +03002808
Michael Guralnika5a5d192018-12-09 11:49:50 +02002809 if (rate < IB_RATE_2_5_GBPS || rate > IB_RATE_600_GBPS)
Danit Goldberg4f32ac22018-04-23 17:01:54 +03002810 return -EINVAL;
2811
2812 while (rate != IB_RATE_PORT_CURRENT &&
2813 !(1 << (rate + MLX5_STAT_RATE_OFFSET) &
2814 MLX5_CAP_GEN(dev->mdev, stat_rate_support)))
2815 --rate;
2816
2817 return rate ? rate + MLX5_STAT_RATE_OFFSET : rate;
Eli Cohene126ba92013-07-07 17:25:49 +03002818}
2819
majd@mellanox.com75850d02016-01-14 19:13:06 +02002820static int modify_raw_packet_eth_prio(struct mlx5_core_dev *dev,
Yishai Hadas1cd6dbd2018-09-20 21:39:27 +03002821 struct mlx5_ib_sq *sq, u8 sl,
2822 struct ib_pd *pd)
majd@mellanox.com75850d02016-01-14 19:13:06 +02002823{
2824 void *in;
2825 void *tisc;
2826 int inlen;
2827 int err;
2828
2829 inlen = MLX5_ST_SZ_BYTES(modify_tis_in);
Leon Romanovsky1b9a07e2017-05-10 21:32:18 +03002830 in = kvzalloc(inlen, GFP_KERNEL);
majd@mellanox.com75850d02016-01-14 19:13:06 +02002831 if (!in)
2832 return -ENOMEM;
2833
2834 MLX5_SET(modify_tis_in, in, bitmask.prio, 1);
Yishai Hadas1cd6dbd2018-09-20 21:39:27 +03002835 MLX5_SET(modify_tis_in, in, uid, to_mpd(pd)->uid);
majd@mellanox.com75850d02016-01-14 19:13:06 +02002836
2837 tisc = MLX5_ADDR_OF(modify_tis_in, in, ctx);
2838 MLX5_SET(tisc, tisc, prio, ((sl & 0x7) << 1));
2839
2840 err = mlx5_core_modify_tis(dev, sq->tisn, in, inlen);
2841
2842 kvfree(in);
2843
2844 return err;
2845}
2846
Aviv Heller13eab212016-09-18 20:48:04 +03002847static int modify_raw_packet_tx_affinity(struct mlx5_core_dev *dev,
Yishai Hadas1cd6dbd2018-09-20 21:39:27 +03002848 struct mlx5_ib_sq *sq, u8 tx_affinity,
2849 struct ib_pd *pd)
Aviv Heller13eab212016-09-18 20:48:04 +03002850{
2851 void *in;
2852 void *tisc;
2853 int inlen;
2854 int err;
2855
2856 inlen = MLX5_ST_SZ_BYTES(modify_tis_in);
Leon Romanovsky1b9a07e2017-05-10 21:32:18 +03002857 in = kvzalloc(inlen, GFP_KERNEL);
Aviv Heller13eab212016-09-18 20:48:04 +03002858 if (!in)
2859 return -ENOMEM;
2860
2861 MLX5_SET(modify_tis_in, in, bitmask.lag_tx_port_affinity, 1);
Yishai Hadas1cd6dbd2018-09-20 21:39:27 +03002862 MLX5_SET(modify_tis_in, in, uid, to_mpd(pd)->uid);
Aviv Heller13eab212016-09-18 20:48:04 +03002863
2864 tisc = MLX5_ADDR_OF(modify_tis_in, in, ctx);
2865 MLX5_SET(tisc, tisc, lag_tx_port_affinity, tx_affinity);
2866
2867 err = mlx5_core_modify_tis(dev, sq->tisn, in, inlen);
2868
2869 kvfree(in);
2870
2871 return err;
2872}
2873
majd@mellanox.com75850d02016-01-14 19:13:06 +02002874static int mlx5_set_path(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
Dasaratharaman Chandramouli90898852017-04-29 14:41:18 -04002875 const struct rdma_ah_attr *ah,
Eli Cohene126ba92013-07-07 17:25:49 +03002876 struct mlx5_qp_path *path, u8 port, int attr_mask,
Achiad Shochatf879ee82016-06-04 15:15:37 +03002877 u32 path_flags, const struct ib_qp_attr *attr,
2878 bool alt)
Eli Cohene126ba92013-07-07 17:25:49 +03002879{
Dasaratharaman Chandramoulid8966fc2017-04-29 14:41:28 -04002880 const struct ib_global_route *grh = rdma_ah_read_grh(ah);
Eli Cohene126ba92013-07-07 17:25:49 +03002881 int err;
Majd Dibbinyed884512017-01-18 14:10:35 +02002882 enum ib_gid_type gid_type;
Dasaratharaman Chandramoulid8966fc2017-04-29 14:41:28 -04002883 u8 ah_flags = rdma_ah_get_ah_flags(ah);
2884 u8 sl = rdma_ah_get_sl(ah);
Eli Cohene126ba92013-07-07 17:25:49 +03002885
Eli Cohene126ba92013-07-07 17:25:49 +03002886 if (attr_mask & IB_QP_PKEY_INDEX)
Achiad Shochatf879ee82016-06-04 15:15:37 +03002887 path->pkey_index = cpu_to_be16(alt ? attr->alt_pkey_index :
2888 attr->pkey_index);
Eli Cohene126ba92013-07-07 17:25:49 +03002889
Dasaratharaman Chandramoulid8966fc2017-04-29 14:41:28 -04002890 if (ah_flags & IB_AH_GRH) {
2891 if (grh->sgid_index >=
Saeed Mahameed938fe832015-05-28 22:28:41 +03002892 dev->mdev->port_caps[port - 1].gid_table_len) {
Joe Perchesf4f01b52015-05-08 15:58:07 -07002893 pr_err("sgid_index (%u) too large. max is %d\n",
Dasaratharaman Chandramoulid8966fc2017-04-29 14:41:28 -04002894 grh->sgid_index,
Saeed Mahameed938fe832015-05-28 22:28:41 +03002895 dev->mdev->port_caps[port - 1].gid_table_len);
Eli Cohenf83b4262014-09-14 16:47:54 +03002896 return -EINVAL;
2897 }
Achiad Shochat2811ba52015-12-23 18:47:24 +02002898 }
Dasaratharaman Chandramouli44c58482017-04-29 14:41:29 -04002899
2900 if (ah->type == RDMA_AH_ATTR_TYPE_ROCE) {
Dasaratharaman Chandramoulid8966fc2017-04-29 14:41:28 -04002901 if (!(ah_flags & IB_AH_GRH))
Achiad Shochat2811ba52015-12-23 18:47:24 +02002902 return -EINVAL;
Parav Pandit47ec3862018-06-13 10:22:06 +03002903
Dasaratharaman Chandramouli44c58482017-04-29 14:41:29 -04002904 memcpy(path->rmac, ah->roce.dmac, sizeof(ah->roce.dmac));
Majd Dibbiny2b621852017-10-30 14:23:14 +02002905 if (qp->ibqp.qp_type == IB_QPT_RC ||
2906 qp->ibqp.qp_type == IB_QPT_UC ||
2907 qp->ibqp.qp_type == IB_QPT_XRC_INI ||
2908 qp->ibqp.qp_type == IB_QPT_XRC_TGT)
Parav Pandit47ec3862018-06-13 10:22:06 +03002909 path->udp_sport =
2910 mlx5_get_roce_udp_sport(dev, ah->grh.sgid_attr);
Dasaratharaman Chandramoulid8966fc2017-04-29 14:41:28 -04002911 path->dci_cfi_prio_sl = (sl & 0x7) << 4;
Parav Pandit47ec3862018-06-13 10:22:06 +03002912 gid_type = ah->grh.sgid_attr->gid_type;
Majd Dibbinyed884512017-01-18 14:10:35 +02002913 if (gid_type == IB_GID_TYPE_ROCE_UDP_ENCAP)
Dasaratharaman Chandramoulid8966fc2017-04-29 14:41:28 -04002914 path->ecn_dscp = (grh->traffic_class >> 2) & 0x3f;
Achiad Shochat2811ba52015-12-23 18:47:24 +02002915 } else {
Noa Osherovichd3ae2bd2016-06-04 15:15:36 +03002916 path->fl_free_ar = (path_flags & MLX5_PATH_FLAG_FL) ? 0x80 : 0;
2917 path->fl_free_ar |=
2918 (path_flags & MLX5_PATH_FLAG_FREE_AR) ? 0x40 : 0;
Dasaratharaman Chandramoulid8966fc2017-04-29 14:41:28 -04002919 path->rlid = cpu_to_be16(rdma_ah_get_dlid(ah));
2920 path->grh_mlid = rdma_ah_get_path_bits(ah) & 0x7f;
2921 if (ah_flags & IB_AH_GRH)
Achiad Shochat2811ba52015-12-23 18:47:24 +02002922 path->grh_mlid |= 1 << 7;
Dasaratharaman Chandramoulid8966fc2017-04-29 14:41:28 -04002923 path->dci_cfi_prio_sl = sl & 0xf;
Achiad Shochat2811ba52015-12-23 18:47:24 +02002924 }
2925
Dasaratharaman Chandramoulid8966fc2017-04-29 14:41:28 -04002926 if (ah_flags & IB_AH_GRH) {
2927 path->mgid_index = grh->sgid_index;
2928 path->hop_limit = grh->hop_limit;
Eli Cohene126ba92013-07-07 17:25:49 +03002929 path->tclass_flowlabel =
Dasaratharaman Chandramoulid8966fc2017-04-29 14:41:28 -04002930 cpu_to_be32((grh->traffic_class << 20) |
2931 (grh->flow_label));
2932 memcpy(path->rgid, grh->dgid.raw, 16);
Eli Cohene126ba92013-07-07 17:25:49 +03002933 }
2934
Dasaratharaman Chandramoulid8966fc2017-04-29 14:41:28 -04002935 err = ib_rate_to_mlx5(dev, rdma_ah_get_static_rate(ah));
Eli Cohene126ba92013-07-07 17:25:49 +03002936 if (err < 0)
2937 return err;
2938 path->static_rate = err;
2939 path->port = port;
2940
Eli Cohene126ba92013-07-07 17:25:49 +03002941 if (attr_mask & IB_QP_TIMEOUT)
Achiad Shochatf879ee82016-06-04 15:15:37 +03002942 path->ackto_lt = (alt ? attr->alt_timeout : attr->timeout) << 3;
Eli Cohene126ba92013-07-07 17:25:49 +03002943
majd@mellanox.com75850d02016-01-14 19:13:06 +02002944 if ((qp->ibqp.qp_type == IB_QPT_RAW_PACKET) && qp->sq.wqe_cnt)
2945 return modify_raw_packet_eth_prio(dev->mdev,
2946 &qp->raw_packet_qp.sq,
Yishai Hadas1cd6dbd2018-09-20 21:39:27 +03002947 sl & 0xf, qp->ibqp.pd);
majd@mellanox.com75850d02016-01-14 19:13:06 +02002948
Eli Cohene126ba92013-07-07 17:25:49 +03002949 return 0;
2950}
2951
2952static enum mlx5_qp_optpar opt_mask[MLX5_QP_NUM_STATE][MLX5_QP_NUM_STATE][MLX5_QP_ST_MAX] = {
2953 [MLX5_QP_STATE_INIT] = {
2954 [MLX5_QP_STATE_INIT] = {
2955 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_RRE |
2956 MLX5_QP_OPTPAR_RAE |
2957 MLX5_QP_OPTPAR_RWE |
2958 MLX5_QP_OPTPAR_PKEY_INDEX |
2959 MLX5_QP_OPTPAR_PRI_PORT,
2960 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_RWE |
2961 MLX5_QP_OPTPAR_PKEY_INDEX |
2962 MLX5_QP_OPTPAR_PRI_PORT,
2963 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_PKEY_INDEX |
2964 MLX5_QP_OPTPAR_Q_KEY |
2965 MLX5_QP_OPTPAR_PRI_PORT,
2966 },
2967 [MLX5_QP_STATE_RTR] = {
2968 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH |
2969 MLX5_QP_OPTPAR_RRE |
2970 MLX5_QP_OPTPAR_RAE |
2971 MLX5_QP_OPTPAR_RWE |
2972 MLX5_QP_OPTPAR_PKEY_INDEX,
2973 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH |
2974 MLX5_QP_OPTPAR_RWE |
2975 MLX5_QP_OPTPAR_PKEY_INDEX,
2976 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_PKEY_INDEX |
2977 MLX5_QP_OPTPAR_Q_KEY,
2978 [MLX5_QP_ST_MLX] = MLX5_QP_OPTPAR_PKEY_INDEX |
2979 MLX5_QP_OPTPAR_Q_KEY,
Eli Cohena4774e92013-09-11 16:35:32 +03002980 [MLX5_QP_ST_XRC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH |
2981 MLX5_QP_OPTPAR_RRE |
2982 MLX5_QP_OPTPAR_RAE |
2983 MLX5_QP_OPTPAR_RWE |
2984 MLX5_QP_OPTPAR_PKEY_INDEX,
Eli Cohene126ba92013-07-07 17:25:49 +03002985 },
2986 },
2987 [MLX5_QP_STATE_RTR] = {
2988 [MLX5_QP_STATE_RTS] = {
2989 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH |
2990 MLX5_QP_OPTPAR_RRE |
2991 MLX5_QP_OPTPAR_RAE |
2992 MLX5_QP_OPTPAR_RWE |
2993 MLX5_QP_OPTPAR_PM_STATE |
2994 MLX5_QP_OPTPAR_RNR_TIMEOUT,
2995 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH |
2996 MLX5_QP_OPTPAR_RWE |
2997 MLX5_QP_OPTPAR_PM_STATE,
2998 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_Q_KEY,
2999 },
3000 },
3001 [MLX5_QP_STATE_RTS] = {
3002 [MLX5_QP_STATE_RTS] = {
3003 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_RRE |
3004 MLX5_QP_OPTPAR_RAE |
3005 MLX5_QP_OPTPAR_RWE |
3006 MLX5_QP_OPTPAR_RNR_TIMEOUT |
Eli Cohenc2a34312013-10-24 12:01:02 +03003007 MLX5_QP_OPTPAR_PM_STATE |
3008 MLX5_QP_OPTPAR_ALT_ADDR_PATH,
Eli Cohene126ba92013-07-07 17:25:49 +03003009 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_RWE |
Eli Cohenc2a34312013-10-24 12:01:02 +03003010 MLX5_QP_OPTPAR_PM_STATE |
3011 MLX5_QP_OPTPAR_ALT_ADDR_PATH,
Eli Cohene126ba92013-07-07 17:25:49 +03003012 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_Q_KEY |
3013 MLX5_QP_OPTPAR_SRQN |
3014 MLX5_QP_OPTPAR_CQN_RCV,
3015 },
3016 },
3017 [MLX5_QP_STATE_SQER] = {
3018 [MLX5_QP_STATE_RTS] = {
3019 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_Q_KEY,
3020 [MLX5_QP_ST_MLX] = MLX5_QP_OPTPAR_Q_KEY,
Eli Cohen75959f52013-09-11 16:35:31 +03003021 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_RWE,
Eli Cohena4774e92013-09-11 16:35:32 +03003022 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_RNR_TIMEOUT |
3023 MLX5_QP_OPTPAR_RWE |
3024 MLX5_QP_OPTPAR_RAE |
3025 MLX5_QP_OPTPAR_RRE,
Eli Cohene126ba92013-07-07 17:25:49 +03003026 },
3027 },
3028};
3029
3030static int ib_nr_to_mlx5_nr(int ib_mask)
3031{
3032 switch (ib_mask) {
3033 case IB_QP_STATE:
3034 return 0;
3035 case IB_QP_CUR_STATE:
3036 return 0;
3037 case IB_QP_EN_SQD_ASYNC_NOTIFY:
3038 return 0;
3039 case IB_QP_ACCESS_FLAGS:
3040 return MLX5_QP_OPTPAR_RWE | MLX5_QP_OPTPAR_RRE |
3041 MLX5_QP_OPTPAR_RAE;
3042 case IB_QP_PKEY_INDEX:
3043 return MLX5_QP_OPTPAR_PKEY_INDEX;
3044 case IB_QP_PORT:
3045 return MLX5_QP_OPTPAR_PRI_PORT;
3046 case IB_QP_QKEY:
3047 return MLX5_QP_OPTPAR_Q_KEY;
3048 case IB_QP_AV:
3049 return MLX5_QP_OPTPAR_PRIMARY_ADDR_PATH |
3050 MLX5_QP_OPTPAR_PRI_PORT;
3051 case IB_QP_PATH_MTU:
3052 return 0;
3053 case IB_QP_TIMEOUT:
3054 return MLX5_QP_OPTPAR_ACK_TIMEOUT;
3055 case IB_QP_RETRY_CNT:
3056 return MLX5_QP_OPTPAR_RETRY_COUNT;
3057 case IB_QP_RNR_RETRY:
3058 return MLX5_QP_OPTPAR_RNR_RETRY;
3059 case IB_QP_RQ_PSN:
3060 return 0;
3061 case IB_QP_MAX_QP_RD_ATOMIC:
3062 return MLX5_QP_OPTPAR_SRA_MAX;
3063 case IB_QP_ALT_PATH:
3064 return MLX5_QP_OPTPAR_ALT_ADDR_PATH;
3065 case IB_QP_MIN_RNR_TIMER:
3066 return MLX5_QP_OPTPAR_RNR_TIMEOUT;
3067 case IB_QP_SQ_PSN:
3068 return 0;
3069 case IB_QP_MAX_DEST_RD_ATOMIC:
3070 return MLX5_QP_OPTPAR_RRA_MAX | MLX5_QP_OPTPAR_RWE |
3071 MLX5_QP_OPTPAR_RRE | MLX5_QP_OPTPAR_RAE;
3072 case IB_QP_PATH_MIG_STATE:
3073 return MLX5_QP_OPTPAR_PM_STATE;
3074 case IB_QP_CAP:
3075 return 0;
3076 case IB_QP_DEST_QPN:
3077 return 0;
3078 }
3079 return 0;
3080}
3081
3082static int ib_mask_to_mlx5_opt(int ib_mask)
3083{
3084 int result = 0;
3085 int i;
3086
3087 for (i = 0; i < 8 * sizeof(int); i++) {
3088 if ((1 << i) & ib_mask)
3089 result |= ib_nr_to_mlx5_nr(1 << i);
3090 }
3091
3092 return result;
3093}
3094
Yishai Hadas34d57582018-09-20 21:39:21 +03003095static int modify_raw_packet_qp_rq(
3096 struct mlx5_ib_dev *dev, struct mlx5_ib_rq *rq, int new_state,
3097 const struct mlx5_modify_raw_qp_param *raw_qp_param, struct ib_pd *pd)
majd@mellanox.comad5f8e92016-01-14 19:13:08 +02003098{
3099 void *in;
3100 void *rqc;
3101 int inlen;
3102 int err;
3103
3104 inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
Leon Romanovsky1b9a07e2017-05-10 21:32:18 +03003105 in = kvzalloc(inlen, GFP_KERNEL);
majd@mellanox.comad5f8e92016-01-14 19:13:08 +02003106 if (!in)
3107 return -ENOMEM;
3108
3109 MLX5_SET(modify_rq_in, in, rq_state, rq->state);
Yishai Hadas34d57582018-09-20 21:39:21 +03003110 MLX5_SET(modify_rq_in, in, uid, to_mpd(pd)->uid);
majd@mellanox.comad5f8e92016-01-14 19:13:08 +02003111
3112 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
3113 MLX5_SET(rqc, rqc, state, new_state);
3114
Alex Veskereb49ab02016-08-28 12:25:53 +03003115 if (raw_qp_param->set_mask & MLX5_RAW_QP_MOD_SET_RQ_Q_CTR_ID) {
3116 if (MLX5_CAP_GEN(dev->mdev, modify_rq_counter_set_id)) {
3117 MLX5_SET64(modify_rq_in, in, modify_bitmask,
Majd Dibbiny23a69642017-01-18 15:25:10 +02003118 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID);
Alex Veskereb49ab02016-08-28 12:25:53 +03003119 MLX5_SET(rqc, rqc, counter_set_id, raw_qp_param->rq_q_ctr_id);
3120 } else
Jason Gunthorpe5a738b52018-09-20 16:42:24 -06003121 dev_info_once(
3122 &dev->ib_dev.dev,
3123 "RAW PACKET QP counters are not supported on current FW\n");
Alex Veskereb49ab02016-08-28 12:25:53 +03003124 }
3125
3126 err = mlx5_core_modify_rq(dev->mdev, rq->base.mqp.qpn, in, inlen);
majd@mellanox.comad5f8e92016-01-14 19:13:08 +02003127 if (err)
3128 goto out;
3129
3130 rq->state = new_state;
3131
3132out:
3133 kvfree(in);
3134 return err;
3135}
3136
Yishai Hadasc14003f2018-09-20 21:39:22 +03003137static int modify_raw_packet_qp_sq(
3138 struct mlx5_core_dev *dev, struct mlx5_ib_sq *sq, int new_state,
3139 const struct mlx5_modify_raw_qp_param *raw_qp_param, struct ib_pd *pd)
majd@mellanox.comad5f8e92016-01-14 19:13:08 +02003140{
Bodong Wang7d29f342016-12-01 13:43:16 +02003141 struct mlx5_ib_qp *ibqp = sq->base.container_mibqp;
Bodong Wang61147f32018-03-19 15:10:30 +02003142 struct mlx5_rate_limit old_rl = ibqp->rl;
3143 struct mlx5_rate_limit new_rl = old_rl;
3144 bool new_rate_added = false;
Bodong Wang7d29f342016-12-01 13:43:16 +02003145 u16 rl_index = 0;
majd@mellanox.comad5f8e92016-01-14 19:13:08 +02003146 void *in;
3147 void *sqc;
3148 int inlen;
3149 int err;
3150
3151 inlen = MLX5_ST_SZ_BYTES(modify_sq_in);
Leon Romanovsky1b9a07e2017-05-10 21:32:18 +03003152 in = kvzalloc(inlen, GFP_KERNEL);
majd@mellanox.comad5f8e92016-01-14 19:13:08 +02003153 if (!in)
3154 return -ENOMEM;
3155
Yishai Hadasc14003f2018-09-20 21:39:22 +03003156 MLX5_SET(modify_sq_in, in, uid, to_mpd(pd)->uid);
majd@mellanox.comad5f8e92016-01-14 19:13:08 +02003157 MLX5_SET(modify_sq_in, in, sq_state, sq->state);
3158
3159 sqc = MLX5_ADDR_OF(modify_sq_in, in, ctx);
3160 MLX5_SET(sqc, sqc, state, new_state);
3161
Bodong Wang7d29f342016-12-01 13:43:16 +02003162 if (raw_qp_param->set_mask & MLX5_RAW_QP_RATE_LIMIT) {
3163 if (new_state != MLX5_SQC_STATE_RDY)
3164 pr_warn("%s: Rate limit can only be changed when SQ is moving to RDY\n",
3165 __func__);
3166 else
Bodong Wang61147f32018-03-19 15:10:30 +02003167 new_rl = raw_qp_param->rl;
Bodong Wang7d29f342016-12-01 13:43:16 +02003168 }
majd@mellanox.comad5f8e92016-01-14 19:13:08 +02003169
Bodong Wang61147f32018-03-19 15:10:30 +02003170 if (!mlx5_rl_are_equal(&old_rl, &new_rl)) {
3171 if (new_rl.rate) {
3172 err = mlx5_rl_add_rate(dev, &rl_index, &new_rl);
Bodong Wang7d29f342016-12-01 13:43:16 +02003173 if (err) {
Bodong Wang61147f32018-03-19 15:10:30 +02003174 pr_err("Failed configuring rate limit(err %d): \
3175 rate %u, max_burst_sz %u, typical_pkt_sz %u\n",
3176 err, new_rl.rate, new_rl.max_burst_sz,
3177 new_rl.typical_pkt_sz);
3178
Bodong Wang7d29f342016-12-01 13:43:16 +02003179 goto out;
3180 }
Bodong Wang61147f32018-03-19 15:10:30 +02003181 new_rate_added = true;
Bodong Wang7d29f342016-12-01 13:43:16 +02003182 }
3183
3184 MLX5_SET64(modify_sq_in, in, modify_bitmask, 1);
Bodong Wang61147f32018-03-19 15:10:30 +02003185 /* index 0 means no limit */
Bodong Wang7d29f342016-12-01 13:43:16 +02003186 MLX5_SET(sqc, sqc, packet_pacing_rate_limit_index, rl_index);
3187 }
3188
3189 err = mlx5_core_modify_sq(dev, sq->base.mqp.qpn, in, inlen);
3190 if (err) {
3191 /* Remove new rate from table if failed */
Bodong Wang61147f32018-03-19 15:10:30 +02003192 if (new_rate_added)
3193 mlx5_rl_remove_rate(dev, &new_rl);
Bodong Wang7d29f342016-12-01 13:43:16 +02003194 goto out;
3195 }
3196
3197 /* Only remove the old rate after new rate was set */
Bodong Wang61147f32018-03-19 15:10:30 +02003198 if ((old_rl.rate &&
3199 !mlx5_rl_are_equal(&old_rl, &new_rl)) ||
Bodong Wang7d29f342016-12-01 13:43:16 +02003200 (new_state != MLX5_SQC_STATE_RDY))
Bodong Wang61147f32018-03-19 15:10:30 +02003201 mlx5_rl_remove_rate(dev, &old_rl);
Bodong Wang7d29f342016-12-01 13:43:16 +02003202
Bodong Wang61147f32018-03-19 15:10:30 +02003203 ibqp->rl = new_rl;
majd@mellanox.comad5f8e92016-01-14 19:13:08 +02003204 sq->state = new_state;
3205
3206out:
3207 kvfree(in);
3208 return err;
3209}
3210
3211static int modify_raw_packet_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
Aviv Heller13eab212016-09-18 20:48:04 +03003212 const struct mlx5_modify_raw_qp_param *raw_qp_param,
3213 u8 tx_affinity)
majd@mellanox.comad5f8e92016-01-14 19:13:08 +02003214{
3215 struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp;
3216 struct mlx5_ib_rq *rq = &raw_packet_qp->rq;
3217 struct mlx5_ib_sq *sq = &raw_packet_qp->sq;
Bodong Wang7d29f342016-12-01 13:43:16 +02003218 int modify_rq = !!qp->rq.wqe_cnt;
3219 int modify_sq = !!qp->sq.wqe_cnt;
majd@mellanox.comad5f8e92016-01-14 19:13:08 +02003220 int rq_state;
3221 int sq_state;
3222 int err;
3223
Alex Vesker0680efa2016-08-28 12:25:52 +03003224 switch (raw_qp_param->operation) {
majd@mellanox.comad5f8e92016-01-14 19:13:08 +02003225 case MLX5_CMD_OP_RST2INIT_QP:
3226 rq_state = MLX5_RQC_STATE_RDY;
3227 sq_state = MLX5_SQC_STATE_RDY;
3228 break;
3229 case MLX5_CMD_OP_2ERR_QP:
3230 rq_state = MLX5_RQC_STATE_ERR;
3231 sq_state = MLX5_SQC_STATE_ERR;
3232 break;
3233 case MLX5_CMD_OP_2RST_QP:
3234 rq_state = MLX5_RQC_STATE_RST;
3235 sq_state = MLX5_SQC_STATE_RST;
3236 break;
majd@mellanox.comad5f8e92016-01-14 19:13:08 +02003237 case MLX5_CMD_OP_RTR2RTS_QP:
3238 case MLX5_CMD_OP_RTS2RTS_QP:
Bodong Wang7d29f342016-12-01 13:43:16 +02003239 if (raw_qp_param->set_mask ==
3240 MLX5_RAW_QP_RATE_LIMIT) {
3241 modify_rq = 0;
3242 sq_state = sq->state;
3243 } else {
3244 return raw_qp_param->set_mask ? -EINVAL : 0;
3245 }
3246 break;
3247 case MLX5_CMD_OP_INIT2INIT_QP:
3248 case MLX5_CMD_OP_INIT2RTR_QP:
Alex Veskereb49ab02016-08-28 12:25:53 +03003249 if (raw_qp_param->set_mask)
3250 return -EINVAL;
3251 else
3252 return 0;
majd@mellanox.comad5f8e92016-01-14 19:13:08 +02003253 default:
3254 WARN_ON(1);
3255 return -EINVAL;
3256 }
3257
Bodong Wang7d29f342016-12-01 13:43:16 +02003258 if (modify_rq) {
Yishai Hadas34d57582018-09-20 21:39:21 +03003259 err = modify_raw_packet_qp_rq(dev, rq, rq_state, raw_qp_param,
3260 qp->ibqp.pd);
majd@mellanox.comad5f8e92016-01-14 19:13:08 +02003261 if (err)
3262 return err;
3263 }
3264
Bodong Wang7d29f342016-12-01 13:43:16 +02003265 if (modify_sq) {
Mark Blochd5ed8ac2019-03-28 15:27:38 +02003266 struct mlx5_flow_handle *flow_rule;
3267
Aviv Heller13eab212016-09-18 20:48:04 +03003268 if (tx_affinity) {
3269 err = modify_raw_packet_tx_affinity(dev->mdev, sq,
Yishai Hadas1cd6dbd2018-09-20 21:39:27 +03003270 tx_affinity,
3271 qp->ibqp.pd);
Aviv Heller13eab212016-09-18 20:48:04 +03003272 if (err)
3273 return err;
3274 }
3275
Mark Blochd5ed8ac2019-03-28 15:27:38 +02003276 flow_rule = create_flow_rule_vport_sq(dev, sq,
3277 raw_qp_param->port);
3278 if (IS_ERR(flow_rule))
3279 return err;
3280
3281 err = modify_raw_packet_qp_sq(dev->mdev, sq, sq_state,
3282 raw_qp_param, qp->ibqp.pd);
3283 if (err) {
3284 if (flow_rule)
3285 mlx5_del_flow_rules(flow_rule);
3286 return err;
3287 }
3288
3289 if (flow_rule) {
3290 destroy_flow_rule_vport_sq(sq);
3291 sq->flow_rule = flow_rule;
3292 }
3293
3294 return err;
Aviv Heller13eab212016-09-18 20:48:04 +03003295 }
majd@mellanox.comad5f8e92016-01-14 19:13:08 +02003296
3297 return 0;
3298}
3299
Majd Dibbinyc6a21c32018-08-28 14:29:05 +03003300static unsigned int get_tx_affinity(struct mlx5_ib_dev *dev,
3301 struct mlx5_ib_pd *pd,
3302 struct mlx5_ib_qp_base *qp_base,
Shamir Rabinovitch89944452019-02-07 18:44:49 +02003303 u8 port_num, struct ib_udata *udata)
Majd Dibbinyc6a21c32018-08-28 14:29:05 +03003304{
Shamir Rabinovitch89944452019-02-07 18:44:49 +02003305 struct mlx5_ib_ucontext *ucontext = rdma_udata_to_drv_context(
3306 udata, struct mlx5_ib_ucontext, ibucontext);
Majd Dibbinyc6a21c32018-08-28 14:29:05 +03003307 unsigned int tx_port_affinity;
3308
Majd Dibbinyc6a21c32018-08-28 14:29:05 +03003309 if (ucontext) {
3310 tx_port_affinity = (unsigned int)atomic_add_return(
3311 1, &ucontext->tx_port_affinity) %
3312 MLX5_MAX_PORTS +
3313 1;
3314 mlx5_ib_dbg(dev, "Set tx affinity 0x%x to qpn 0x%x ucontext %p\n",
3315 tx_port_affinity, qp_base->mqp.qpn, ucontext);
3316 } else {
3317 tx_port_affinity =
3318 (unsigned int)atomic_add_return(
Mark Bloch95579e72019-03-28 15:27:33 +02003319 1, &dev->port[port_num].roce.tx_port_affinity) %
Majd Dibbinyc6a21c32018-08-28 14:29:05 +03003320 MLX5_MAX_PORTS +
3321 1;
3322 mlx5_ib_dbg(dev, "Set tx affinity 0x%x to qpn 0x%x\n",
3323 tx_port_affinity, qp_base->mqp.qpn);
3324 }
3325
3326 return tx_port_affinity;
3327}
3328
Eli Cohene126ba92013-07-07 17:25:49 +03003329static int __mlx5_ib_modify_qp(struct ib_qp *ibqp,
3330 const struct ib_qp_attr *attr, int attr_mask,
Shamir Rabinovitch89944452019-02-07 18:44:49 +02003331 enum ib_qp_state cur_state,
3332 enum ib_qp_state new_state,
3333 const struct mlx5_ib_modify_qp *ucmd,
3334 struct ib_udata *udata)
Eli Cohene126ba92013-07-07 17:25:49 +03003335{
majd@mellanox.com427c1e72016-01-14 19:13:07 +02003336 static const u16 optab[MLX5_QP_NUM_STATE][MLX5_QP_NUM_STATE] = {
3337 [MLX5_QP_STATE_RST] = {
3338 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP,
3339 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP,
3340 [MLX5_QP_STATE_INIT] = MLX5_CMD_OP_RST2INIT_QP,
3341 },
3342 [MLX5_QP_STATE_INIT] = {
3343 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP,
3344 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP,
3345 [MLX5_QP_STATE_INIT] = MLX5_CMD_OP_INIT2INIT_QP,
3346 [MLX5_QP_STATE_RTR] = MLX5_CMD_OP_INIT2RTR_QP,
3347 },
3348 [MLX5_QP_STATE_RTR] = {
3349 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP,
3350 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP,
3351 [MLX5_QP_STATE_RTS] = MLX5_CMD_OP_RTR2RTS_QP,
3352 },
3353 [MLX5_QP_STATE_RTS] = {
3354 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP,
3355 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP,
3356 [MLX5_QP_STATE_RTS] = MLX5_CMD_OP_RTS2RTS_QP,
3357 },
3358 [MLX5_QP_STATE_SQD] = {
3359 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP,
3360 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP,
3361 },
3362 [MLX5_QP_STATE_SQER] = {
3363 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP,
3364 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP,
3365 [MLX5_QP_STATE_RTS] = MLX5_CMD_OP_SQERR2RTS_QP,
3366 },
3367 [MLX5_QP_STATE_ERR] = {
3368 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP,
3369 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP,
3370 }
3371 };
3372
Eli Cohene126ba92013-07-07 17:25:49 +03003373 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
3374 struct mlx5_ib_qp *qp = to_mqp(ibqp);
majd@mellanox.com19098df2016-01-14 19:13:03 +02003375 struct mlx5_ib_qp_base *base = &qp->trans_qp.base;
Eli Cohene126ba92013-07-07 17:25:49 +03003376 struct mlx5_ib_cq *send_cq, *recv_cq;
3377 struct mlx5_qp_context *context;
Eli Cohene126ba92013-07-07 17:25:49 +03003378 struct mlx5_ib_pd *pd;
Alex Veskereb49ab02016-08-28 12:25:53 +03003379 struct mlx5_ib_port *mibport = NULL;
Eli Cohene126ba92013-07-07 17:25:49 +03003380 enum mlx5_qp_state mlx5_cur, mlx5_new;
3381 enum mlx5_qp_optpar optpar;
Eli Cohene126ba92013-07-07 17:25:49 +03003382 int mlx5_st;
3383 int err;
majd@mellanox.com427c1e72016-01-14 19:13:07 +02003384 u16 op;
Aviv Heller13eab212016-09-18 20:48:04 +03003385 u8 tx_affinity = 0;
Eli Cohene126ba92013-07-07 17:25:49 +03003386
Leon Romanovsky55de9a72018-02-25 13:39:52 +02003387 mlx5_st = to_mlx5_st(ibqp->qp_type == IB_QPT_DRIVER ?
3388 qp->qp_sub_type : ibqp->qp_type);
3389 if (mlx5_st < 0)
3390 return -EINVAL;
3391
Saeed Mahameed1a412fb2016-07-19 18:03:21 +03003392 context = kzalloc(sizeof(*context), GFP_KERNEL);
3393 if (!context)
Eli Cohene126ba92013-07-07 17:25:49 +03003394 return -ENOMEM;
3395
Majd Dibbinyc6a21c32018-08-28 14:29:05 +03003396 pd = get_pd(qp);
Leon Romanovsky55de9a72018-02-25 13:39:52 +02003397 context->flags = cpu_to_be32(mlx5_st << 16);
Eli Cohene126ba92013-07-07 17:25:49 +03003398
3399 if (!(attr_mask & IB_QP_PATH_MIG_STATE)) {
3400 context->flags |= cpu_to_be32(MLX5_QP_PM_MIGRATED << 11);
3401 } else {
3402 switch (attr->path_mig_state) {
3403 case IB_MIG_MIGRATED:
3404 context->flags |= cpu_to_be32(MLX5_QP_PM_MIGRATED << 11);
3405 break;
3406 case IB_MIG_REARM:
3407 context->flags |= cpu_to_be32(MLX5_QP_PM_REARM << 11);
3408 break;
3409 case IB_MIG_ARMED:
3410 context->flags |= cpu_to_be32(MLX5_QP_PM_ARMED << 11);
3411 break;
3412 }
3413 }
3414
Aviv Heller13eab212016-09-18 20:48:04 +03003415 if ((cur_state == IB_QPS_RESET) && (new_state == IB_QPS_INIT)) {
3416 if ((ibqp->qp_type == IB_QPT_RC) ||
3417 (ibqp->qp_type == IB_QPT_UD &&
3418 !(qp->flags & MLX5_IB_QP_SQPN_QP1)) ||
3419 (ibqp->qp_type == IB_QPT_UC) ||
3420 (ibqp->qp_type == IB_QPT_RAW_PACKET) ||
3421 (ibqp->qp_type == IB_QPT_XRC_INI) ||
3422 (ibqp->qp_type == IB_QPT_XRC_TGT)) {
Aviv Heller7c34ec12018-08-23 13:47:53 +03003423 if (dev->lag_active) {
Mark Bloch95579e72019-03-28 15:27:33 +02003424 u8 p = mlx5_core_native_port_num(dev->mdev) - 1;
Shamir Rabinovitch89944452019-02-07 18:44:49 +02003425 tx_affinity = get_tx_affinity(dev, pd, base, p,
3426 udata);
Aviv Heller13eab212016-09-18 20:48:04 +03003427 context->flags |= cpu_to_be32(tx_affinity << 24);
3428 }
3429 }
3430 }
3431
Haggai Erand16e91d2016-02-29 15:45:05 +02003432 if (is_sqp(ibqp->qp_type)) {
Eli Cohene126ba92013-07-07 17:25:49 +03003433 context->mtu_msgmax = (IB_MTU_256 << 5) | 8;
Yishai Hadasc2e53b22017-06-08 16:15:08 +03003434 } else if ((ibqp->qp_type == IB_QPT_UD &&
3435 !(qp->flags & MLX5_IB_QP_UNDERLAY)) ||
Eli Cohene126ba92013-07-07 17:25:49 +03003436 ibqp->qp_type == MLX5_IB_QPT_REG_UMR) {
3437 context->mtu_msgmax = (IB_MTU_4096 << 5) | 12;
3438 } else if (attr_mask & IB_QP_PATH_MTU) {
3439 if (attr->path_mtu < IB_MTU_256 ||
3440 attr->path_mtu > IB_MTU_4096) {
3441 mlx5_ib_warn(dev, "invalid mtu %d\n", attr->path_mtu);
3442 err = -EINVAL;
3443 goto out;
3444 }
Saeed Mahameed938fe832015-05-28 22:28:41 +03003445 context->mtu_msgmax = (attr->path_mtu << 5) |
3446 (u8)MLX5_CAP_GEN(dev->mdev, log_max_msg);
Eli Cohene126ba92013-07-07 17:25:49 +03003447 }
3448
3449 if (attr_mask & IB_QP_DEST_QPN)
3450 context->log_pg_sz_remote_qpn = cpu_to_be32(attr->dest_qp_num);
3451
3452 if (attr_mask & IB_QP_PKEY_INDEX)
Noa Osherovichd3ae2bd2016-06-04 15:15:36 +03003453 context->pri_path.pkey_index = cpu_to_be16(attr->pkey_index);
Eli Cohene126ba92013-07-07 17:25:49 +03003454
3455 /* todo implement counter_index functionality */
3456
3457 if (is_sqp(ibqp->qp_type))
3458 context->pri_path.port = qp->port;
3459
3460 if (attr_mask & IB_QP_PORT)
3461 context->pri_path.port = attr->port_num;
3462
3463 if (attr_mask & IB_QP_AV) {
majd@mellanox.com75850d02016-01-14 19:13:06 +02003464 err = mlx5_set_path(dev, qp, &attr->ah_attr, &context->pri_path,
Eli Cohene126ba92013-07-07 17:25:49 +03003465 attr_mask & IB_QP_PORT ? attr->port_num : qp->port,
Achiad Shochatf879ee82016-06-04 15:15:37 +03003466 attr_mask, 0, attr, false);
Eli Cohene126ba92013-07-07 17:25:49 +03003467 if (err)
3468 goto out;
3469 }
3470
3471 if (attr_mask & IB_QP_TIMEOUT)
3472 context->pri_path.ackto_lt |= attr->timeout << 3;
3473
3474 if (attr_mask & IB_QP_ALT_PATH) {
majd@mellanox.com75850d02016-01-14 19:13:06 +02003475 err = mlx5_set_path(dev, qp, &attr->alt_ah_attr,
3476 &context->alt_path,
Achiad Shochatf879ee82016-06-04 15:15:37 +03003477 attr->alt_port_num,
3478 attr_mask | IB_QP_PKEY_INDEX | IB_QP_TIMEOUT,
3479 0, attr, true);
Eli Cohene126ba92013-07-07 17:25:49 +03003480 if (err)
3481 goto out;
3482 }
3483
Maor Gottlieb89ea94a72016-06-17 15:01:38 +03003484 get_cqs(qp->ibqp.qp_type, qp->ibqp.send_cq, qp->ibqp.recv_cq,
3485 &send_cq, &recv_cq);
Eli Cohene126ba92013-07-07 17:25:49 +03003486
3487 context->flags_pd = cpu_to_be32(pd ? pd->pdn : to_mpd(dev->devr.p0)->pdn);
3488 context->cqn_send = send_cq ? cpu_to_be32(send_cq->mcq.cqn) : 0;
3489 context->cqn_recv = recv_cq ? cpu_to_be32(recv_cq->mcq.cqn) : 0;
3490 context->params1 = cpu_to_be32(MLX5_IB_ACK_REQ_FREQ << 28);
3491
3492 if (attr_mask & IB_QP_RNR_RETRY)
3493 context->params1 |= cpu_to_be32(attr->rnr_retry << 13);
3494
3495 if (attr_mask & IB_QP_RETRY_CNT)
3496 context->params1 |= cpu_to_be32(attr->retry_cnt << 16);
3497
3498 if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC) {
3499 if (attr->max_rd_atomic)
3500 context->params1 |=
3501 cpu_to_be32(fls(attr->max_rd_atomic - 1) << 21);
3502 }
3503
3504 if (attr_mask & IB_QP_SQ_PSN)
3505 context->next_send_psn = cpu_to_be32(attr->sq_psn);
3506
3507 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) {
3508 if (attr->max_dest_rd_atomic)
3509 context->params2 |=
3510 cpu_to_be32(fls(attr->max_dest_rd_atomic - 1) << 21);
3511 }
3512
Yonatan Cohena60109d2018-10-10 09:25:16 +03003513 if (attr_mask & (IB_QP_ACCESS_FLAGS | IB_QP_MAX_DEST_RD_ATOMIC)) {
Bart Van Asschebf3b4f02019-01-30 16:30:51 -08003514 __be32 access_flags;
Yonatan Cohena60109d2018-10-10 09:25:16 +03003515
3516 err = to_mlx5_access_flags(qp, attr, attr_mask, &access_flags);
3517 if (err)
3518 goto out;
3519
3520 context->params2 |= access_flags;
3521 }
Eli Cohene126ba92013-07-07 17:25:49 +03003522
3523 if (attr_mask & IB_QP_MIN_RNR_TIMER)
3524 context->rnr_nextrecvpsn |= cpu_to_be32(attr->min_rnr_timer << 24);
3525
3526 if (attr_mask & IB_QP_RQ_PSN)
3527 context->rnr_nextrecvpsn |= cpu_to_be32(attr->rq_psn);
3528
3529 if (attr_mask & IB_QP_QKEY)
3530 context->qkey = cpu_to_be32(attr->qkey);
3531
3532 if (qp->rq.wqe_cnt && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT)
3533 context->db_rec_addr = cpu_to_be64(qp->db.dma);
3534
Mark Bloch0837e862016-06-17 15:10:55 +03003535 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
3536 u8 port_num = (attr_mask & IB_QP_PORT ? attr->port_num :
3537 qp->port) - 1;
Yishai Hadasc2e53b22017-06-08 16:15:08 +03003538
3539 /* Underlay port should be used - index 0 function per port */
3540 if (qp->flags & MLX5_IB_QP_UNDERLAY)
3541 port_num = 0;
3542
Alex Veskereb49ab02016-08-28 12:25:53 +03003543 mibport = &dev->port[port_num];
Mark Bloch0837e862016-06-17 15:10:55 +03003544 context->qp_counter_set_usr_page |=
Parav Pandite1f24a72017-04-16 07:29:29 +03003545 cpu_to_be32((u32)(mibport->cnts.set_id) << 24);
Mark Bloch0837e862016-06-17 15:10:55 +03003546 }
3547
Eli Cohene126ba92013-07-07 17:25:49 +03003548 if (!ibqp->uobject && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT)
3549 context->sq_crq_size |= cpu_to_be16(1 << 4);
3550
Haggai Eranb11a4f92016-02-29 15:45:03 +02003551 if (qp->flags & MLX5_IB_QP_SQPN_QP1)
3552 context->deth_sqpn = cpu_to_be32(1);
Eli Cohene126ba92013-07-07 17:25:49 +03003553
3554 mlx5_cur = to_mlx5_state(cur_state);
3555 mlx5_new = to_mlx5_state(new_state);
Eli Cohene126ba92013-07-07 17:25:49 +03003556
majd@mellanox.com427c1e72016-01-14 19:13:07 +02003557 if (mlx5_cur >= MLX5_QP_NUM_STATE || mlx5_new >= MLX5_QP_NUM_STATE ||
Dan Carpenter5d414b12018-03-06 13:00:31 +03003558 !optab[mlx5_cur][mlx5_new]) {
3559 err = -EINVAL;
majd@mellanox.com427c1e72016-01-14 19:13:07 +02003560 goto out;
Dan Carpenter5d414b12018-03-06 13:00:31 +03003561 }
majd@mellanox.com427c1e72016-01-14 19:13:07 +02003562
3563 op = optab[mlx5_cur][mlx5_new];
Eli Cohene126ba92013-07-07 17:25:49 +03003564 optpar = ib_mask_to_mlx5_opt(attr_mask);
3565 optpar &= opt_mask[mlx5_cur][mlx5_new][mlx5_st];
majd@mellanox.comad5f8e92016-01-14 19:13:08 +02003566
Yishai Hadasc2e53b22017-06-08 16:15:08 +03003567 if (qp->ibqp.qp_type == IB_QPT_RAW_PACKET ||
3568 qp->flags & MLX5_IB_QP_UNDERLAY) {
Alex Vesker0680efa2016-08-28 12:25:52 +03003569 struct mlx5_modify_raw_qp_param raw_qp_param = {};
3570
3571 raw_qp_param.operation = op;
Alex Veskereb49ab02016-08-28 12:25:53 +03003572 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
Parav Pandite1f24a72017-04-16 07:29:29 +03003573 raw_qp_param.rq_q_ctr_id = mibport->cnts.set_id;
Alex Veskereb49ab02016-08-28 12:25:53 +03003574 raw_qp_param.set_mask |= MLX5_RAW_QP_MOD_SET_RQ_Q_CTR_ID;
3575 }
Bodong Wang7d29f342016-12-01 13:43:16 +02003576
Mark Blochd5ed8ac2019-03-28 15:27:38 +02003577 if (attr_mask & IB_QP_PORT)
3578 raw_qp_param.port = attr->port_num;
3579
Bodong Wang7d29f342016-12-01 13:43:16 +02003580 if (attr_mask & IB_QP_RATE_LIMIT) {
Bodong Wang61147f32018-03-19 15:10:30 +02003581 raw_qp_param.rl.rate = attr->rate_limit;
3582
3583 if (ucmd->burst_info.max_burst_sz) {
3584 if (attr->rate_limit &&
3585 MLX5_CAP_QOS(dev->mdev, packet_pacing_burst_bound)) {
3586 raw_qp_param.rl.max_burst_sz =
3587 ucmd->burst_info.max_burst_sz;
3588 } else {
3589 err = -EINVAL;
3590 goto out;
3591 }
3592 }
3593
3594 if (ucmd->burst_info.typical_pkt_sz) {
3595 if (attr->rate_limit &&
3596 MLX5_CAP_QOS(dev->mdev, packet_pacing_typical_size)) {
3597 raw_qp_param.rl.typical_pkt_sz =
3598 ucmd->burst_info.typical_pkt_sz;
3599 } else {
3600 err = -EINVAL;
3601 goto out;
3602 }
3603 }
3604
Bodong Wang7d29f342016-12-01 13:43:16 +02003605 raw_qp_param.set_mask |= MLX5_RAW_QP_RATE_LIMIT;
3606 }
3607
Aviv Heller13eab212016-09-18 20:48:04 +03003608 err = modify_raw_packet_qp(dev, qp, &raw_qp_param, tx_affinity);
Alex Vesker0680efa2016-08-28 12:25:52 +03003609 } else {
Saeed Mahameed1a412fb2016-07-19 18:03:21 +03003610 err = mlx5_core_qp_modify(dev->mdev, op, optpar, context,
majd@mellanox.comad5f8e92016-01-14 19:13:08 +02003611 &base->mqp);
Alex Vesker0680efa2016-08-28 12:25:52 +03003612 }
3613
Eli Cohene126ba92013-07-07 17:25:49 +03003614 if (err)
3615 goto out;
3616
3617 qp->state = new_state;
3618
3619 if (attr_mask & IB_QP_ACCESS_FLAGS)
majd@mellanox.com19098df2016-01-14 19:13:03 +02003620 qp->trans_qp.atomic_rd_en = attr->qp_access_flags;
Eli Cohene126ba92013-07-07 17:25:49 +03003621 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
majd@mellanox.com19098df2016-01-14 19:13:03 +02003622 qp->trans_qp.resp_depth = attr->max_dest_rd_atomic;
Eli Cohene126ba92013-07-07 17:25:49 +03003623 if (attr_mask & IB_QP_PORT)
3624 qp->port = attr->port_num;
3625 if (attr_mask & IB_QP_ALT_PATH)
majd@mellanox.com19098df2016-01-14 19:13:03 +02003626 qp->trans_qp.alt_port = attr->alt_port_num;
Eli Cohene126ba92013-07-07 17:25:49 +03003627
3628 /*
3629 * If we moved a kernel QP to RESET, clean up all old CQ
3630 * entries and reinitialize the QP.
3631 */
Leon Romanovsky75a45982018-03-11 13:51:32 +02003632 if (new_state == IB_QPS_RESET &&
3633 !ibqp->uobject && ibqp->qp_type != IB_QPT_XRC_TGT) {
majd@mellanox.com19098df2016-01-14 19:13:03 +02003634 mlx5_ib_cq_clean(recv_cq, base->mqp.qpn,
Eli Cohene126ba92013-07-07 17:25:49 +03003635 ibqp->srq ? to_msrq(ibqp->srq) : NULL);
3636 if (send_cq != recv_cq)
majd@mellanox.com19098df2016-01-14 19:13:03 +02003637 mlx5_ib_cq_clean(send_cq, base->mqp.qpn, NULL);
Eli Cohene126ba92013-07-07 17:25:49 +03003638
3639 qp->rq.head = 0;
3640 qp->rq.tail = 0;
3641 qp->sq.head = 0;
3642 qp->sq.tail = 0;
3643 qp->sq.cur_post = 0;
Guy Levi34f4c952018-11-26 08:15:50 +02003644 if (qp->sq.wqe_cnt)
3645 qp->sq.cur_edge = get_sq_edge(&qp->sq, 0);
Eli Cohene126ba92013-07-07 17:25:49 +03003646 qp->db.db[MLX5_RCV_DBR] = 0;
3647 qp->db.db[MLX5_SND_DBR] = 0;
3648 }
3649
3650out:
Saeed Mahameed1a412fb2016-07-19 18:03:21 +03003651 kfree(context);
Eli Cohene126ba92013-07-07 17:25:49 +03003652 return err;
3653}
3654
Moni Shouac32a4f22018-01-02 16:19:32 +02003655static inline bool is_valid_mask(int mask, int req, int opt)
3656{
3657 if ((mask & req) != req)
3658 return false;
3659
3660 if (mask & ~(req | opt))
3661 return false;
3662
3663 return true;
3664}
3665
3666/* check valid transition for driver QP types
3667 * for now the only QP type that this function supports is DCI
3668 */
3669static bool modify_dci_qp_is_ok(enum ib_qp_state cur_state, enum ib_qp_state new_state,
3670 enum ib_qp_attr_mask attr_mask)
3671{
3672 int req = IB_QP_STATE;
3673 int opt = 0;
3674
Moni Shoua99ed7482018-09-12 09:33:55 +03003675 if (new_state == IB_QPS_RESET) {
3676 return is_valid_mask(attr_mask, req, opt);
3677 } else if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
Moni Shouac32a4f22018-01-02 16:19:32 +02003678 req |= IB_QP_PKEY_INDEX | IB_QP_PORT;
3679 return is_valid_mask(attr_mask, req, opt);
3680 } else if (cur_state == IB_QPS_INIT && new_state == IB_QPS_INIT) {
3681 opt = IB_QP_PKEY_INDEX | IB_QP_PORT;
3682 return is_valid_mask(attr_mask, req, opt);
3683 } else if (cur_state == IB_QPS_INIT && new_state == IB_QPS_RTR) {
3684 req |= IB_QP_PATH_MTU;
Artemy Kovalyov5ec03042018-11-05 08:12:07 +02003685 opt = IB_QP_PKEY_INDEX | IB_QP_AV;
Moni Shouac32a4f22018-01-02 16:19:32 +02003686 return is_valid_mask(attr_mask, req, opt);
3687 } else if (cur_state == IB_QPS_RTR && new_state == IB_QPS_RTS) {
3688 req |= IB_QP_TIMEOUT | IB_QP_RETRY_CNT | IB_QP_RNR_RETRY |
3689 IB_QP_MAX_QP_RD_ATOMIC | IB_QP_SQ_PSN;
3690 opt = IB_QP_MIN_RNR_TIMER;
3691 return is_valid_mask(attr_mask, req, opt);
3692 } else if (cur_state == IB_QPS_RTS && new_state == IB_QPS_RTS) {
3693 opt = IB_QP_MIN_RNR_TIMER;
3694 return is_valid_mask(attr_mask, req, opt);
3695 } else if (cur_state != IB_QPS_RESET && new_state == IB_QPS_ERR) {
3696 return is_valid_mask(attr_mask, req, opt);
3697 }
3698 return false;
3699}
3700
Moni Shoua776a3902018-01-02 16:19:33 +02003701/* mlx5_ib_modify_dct: modify a DCT QP
3702 * valid transitions are:
3703 * RESET to INIT: must set access_flags, pkey_index and port
3704 * INIT to RTR : must set min_rnr_timer, tclass, flow_label,
3705 * mtu, gid_index and hop_limit
3706 * Other transitions and attributes are illegal
3707 */
3708static int mlx5_ib_modify_dct(struct ib_qp *ibqp, struct ib_qp_attr *attr,
3709 int attr_mask, struct ib_udata *udata)
3710{
3711 struct mlx5_ib_qp *qp = to_mqp(ibqp);
3712 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
3713 enum ib_qp_state cur_state, new_state;
3714 int err = 0;
3715 int required = IB_QP_STATE;
3716 void *dctc;
3717
3718 if (!(attr_mask & IB_QP_STATE))
3719 return -EINVAL;
3720
3721 cur_state = qp->state;
3722 new_state = attr->qp_state;
3723
3724 dctc = MLX5_ADDR_OF(create_dct_in, qp->dct.in, dct_context_entry);
3725 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
3726 required |= IB_QP_ACCESS_FLAGS | IB_QP_PKEY_INDEX | IB_QP_PORT;
3727 if (!is_valid_mask(attr_mask, required, 0))
3728 return -EINVAL;
3729
3730 if (attr->port_num == 0 ||
3731 attr->port_num > MLX5_CAP_GEN(dev->mdev, num_ports)) {
3732 mlx5_ib_dbg(dev, "invalid port number %d. number of ports is %d\n",
3733 attr->port_num, dev->num_ports);
3734 return -EINVAL;
3735 }
3736 if (attr->qp_access_flags & IB_ACCESS_REMOTE_READ)
3737 MLX5_SET(dctc, dctc, rre, 1);
3738 if (attr->qp_access_flags & IB_ACCESS_REMOTE_WRITE)
3739 MLX5_SET(dctc, dctc, rwe, 1);
3740 if (attr->qp_access_flags & IB_ACCESS_REMOTE_ATOMIC) {
Yonatan Cohena60109d2018-10-10 09:25:16 +03003741 int atomic_mode;
3742
3743 atomic_mode = get_atomic_mode(dev, MLX5_IB_QPT_DCT);
3744 if (atomic_mode < 0)
Moni Shoua776a3902018-01-02 16:19:33 +02003745 return -EOPNOTSUPP;
Yonatan Cohena60109d2018-10-10 09:25:16 +03003746
3747 MLX5_SET(dctc, dctc, atomic_mode, atomic_mode);
Moni Shoua776a3902018-01-02 16:19:33 +02003748 MLX5_SET(dctc, dctc, rae, 1);
Moni Shoua776a3902018-01-02 16:19:33 +02003749 }
3750 MLX5_SET(dctc, dctc, pkey_index, attr->pkey_index);
3751 MLX5_SET(dctc, dctc, port, attr->port_num);
3752 MLX5_SET(dctc, dctc, counter_set_id, dev->port[attr->port_num - 1].cnts.set_id);
3753
3754 } else if (cur_state == IB_QPS_INIT && new_state == IB_QPS_RTR) {
3755 struct mlx5_ib_modify_qp_resp resp = {};
Yishai Hadasc5ae1952019-03-06 19:21:42 +02003756 u32 out[MLX5_ST_SZ_DW(create_dct_out)] = {0};
Moni Shoua776a3902018-01-02 16:19:33 +02003757 u32 min_resp_len = offsetof(typeof(resp), dctn) +
3758 sizeof(resp.dctn);
3759
3760 if (udata->outlen < min_resp_len)
3761 return -EINVAL;
3762 resp.response_length = min_resp_len;
3763
3764 required |= IB_QP_MIN_RNR_TIMER | IB_QP_AV | IB_QP_PATH_MTU;
3765 if (!is_valid_mask(attr_mask, required, 0))
3766 return -EINVAL;
3767 MLX5_SET(dctc, dctc, min_rnr_nak, attr->min_rnr_timer);
3768 MLX5_SET(dctc, dctc, tclass, attr->ah_attr.grh.traffic_class);
3769 MLX5_SET(dctc, dctc, flow_label, attr->ah_attr.grh.flow_label);
3770 MLX5_SET(dctc, dctc, mtu, attr->path_mtu);
3771 MLX5_SET(dctc, dctc, my_addr_index, attr->ah_attr.grh.sgid_index);
3772 MLX5_SET(dctc, dctc, hop_limit, attr->ah_attr.grh.hop_limit);
3773
3774 err = mlx5_core_create_dct(dev->mdev, &qp->dct.mdct, qp->dct.in,
Yishai Hadasc5ae1952019-03-06 19:21:42 +02003775 MLX5_ST_SZ_BYTES(create_dct_in), out,
3776 sizeof(out));
Moni Shoua776a3902018-01-02 16:19:33 +02003777 if (err)
3778 return err;
3779 resp.dctn = qp->dct.mdct.mqp.qpn;
3780 err = ib_copy_to_udata(udata, &resp, resp.response_length);
3781 if (err) {
3782 mlx5_core_destroy_dct(dev->mdev, &qp->dct.mdct);
3783 return err;
3784 }
3785 } else {
3786 mlx5_ib_warn(dev, "Modify DCT: Invalid transition from %d to %d\n", cur_state, new_state);
3787 return -EINVAL;
3788 }
3789 if (err)
3790 qp->state = IB_QPS_ERR;
3791 else
3792 qp->state = new_state;
3793 return err;
3794}
3795
Eli Cohene126ba92013-07-07 17:25:49 +03003796int mlx5_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
3797 int attr_mask, struct ib_udata *udata)
3798{
3799 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
3800 struct mlx5_ib_qp *qp = to_mqp(ibqp);
Bodong Wang61147f32018-03-19 15:10:30 +02003801 struct mlx5_ib_modify_qp ucmd = {};
Haggai Erand16e91d2016-02-29 15:45:05 +02003802 enum ib_qp_type qp_type;
Eli Cohene126ba92013-07-07 17:25:49 +03003803 enum ib_qp_state cur_state, new_state;
Bodong Wang61147f32018-03-19 15:10:30 +02003804 size_t required_cmd_sz;
Eli Cohene126ba92013-07-07 17:25:49 +03003805 int err = -EINVAL;
3806 int port;
3807
Yishai Hadas28d61372016-05-23 15:20:56 +03003808 if (ibqp->rwq_ind_tbl)
3809 return -ENOSYS;
3810
Bodong Wang61147f32018-03-19 15:10:30 +02003811 if (udata && udata->inlen) {
3812 required_cmd_sz = offsetof(typeof(ucmd), reserved) +
3813 sizeof(ucmd.reserved);
3814 if (udata->inlen < required_cmd_sz)
3815 return -EINVAL;
3816
3817 if (udata->inlen > sizeof(ucmd) &&
3818 !ib_is_udata_cleared(udata, sizeof(ucmd),
3819 udata->inlen - sizeof(ucmd)))
3820 return -EOPNOTSUPP;
3821
3822 if (ib_copy_from_udata(&ucmd, udata,
3823 min(udata->inlen, sizeof(ucmd))))
3824 return -EFAULT;
3825
3826 if (ucmd.comp_mask ||
3827 memchr_inv(&ucmd.reserved, 0, sizeof(ucmd.reserved)) ||
3828 memchr_inv(&ucmd.burst_info.reserved, 0,
3829 sizeof(ucmd.burst_info.reserved)))
3830 return -EOPNOTSUPP;
3831 }
3832
Haggai Erand16e91d2016-02-29 15:45:05 +02003833 if (unlikely(ibqp->qp_type == IB_QPT_GSI))
3834 return mlx5_ib_gsi_modify_qp(ibqp, attr, attr_mask);
3835
Moni Shouac32a4f22018-01-02 16:19:32 +02003836 if (ibqp->qp_type == IB_QPT_DRIVER)
3837 qp_type = qp->qp_sub_type;
3838 else
3839 qp_type = (unlikely(ibqp->qp_type == MLX5_IB_QPT_HW_GSI)) ?
3840 IB_QPT_GSI : ibqp->qp_type;
3841
Moni Shoua776a3902018-01-02 16:19:33 +02003842 if (qp_type == MLX5_IB_QPT_DCT)
3843 return mlx5_ib_modify_dct(ibqp, attr, attr_mask, udata);
Haggai Erand16e91d2016-02-29 15:45:05 +02003844
Eli Cohene126ba92013-07-07 17:25:49 +03003845 mutex_lock(&qp->mutex);
3846
3847 cur_state = attr_mask & IB_QP_CUR_STATE ? attr->cur_qp_state : qp->state;
3848 new_state = attr_mask & IB_QP_STATE ? attr->qp_state : cur_state;
3849
Achiad Shochat2811ba52015-12-23 18:47:24 +02003850 if (!(cur_state == new_state && cur_state == IB_QPS_RESET)) {
3851 port = attr_mask & IB_QP_PORT ? attr->port_num : qp->port;
Achiad Shochat2811ba52015-12-23 18:47:24 +02003852 }
3853
Yishai Hadasc2e53b22017-06-08 16:15:08 +03003854 if (qp->flags & MLX5_IB_QP_UNDERLAY) {
3855 if (attr_mask & ~(IB_QP_STATE | IB_QP_CUR_STATE)) {
3856 mlx5_ib_dbg(dev, "invalid attr_mask 0x%x when underlay QP is used\n",
3857 attr_mask);
3858 goto out;
3859 }
3860 } else if (qp_type != MLX5_IB_QPT_REG_UMR &&
Moni Shouac32a4f22018-01-02 16:19:32 +02003861 qp_type != MLX5_IB_QPT_DCI &&
Kamal Heibd31131b2018-10-02 16:11:21 +03003862 !ib_modify_qp_is_ok(cur_state, new_state, qp_type,
3863 attr_mask)) {
Haggai Eran158abf82016-02-29 15:45:04 +02003864 mlx5_ib_dbg(dev, "invalid QP state transition from %d to %d, qp_type %d, attr_mask 0x%x\n",
3865 cur_state, new_state, ibqp->qp_type, attr_mask);
Eli Cohene126ba92013-07-07 17:25:49 +03003866 goto out;
Moni Shouac32a4f22018-01-02 16:19:32 +02003867 } else if (qp_type == MLX5_IB_QPT_DCI &&
3868 !modify_dci_qp_is_ok(cur_state, new_state, attr_mask)) {
3869 mlx5_ib_dbg(dev, "invalid QP state transition from %d to %d, qp_type %d, attr_mask 0x%x\n",
3870 cur_state, new_state, qp_type, attr_mask);
3871 goto out;
Haggai Eran158abf82016-02-29 15:45:04 +02003872 }
Eli Cohene126ba92013-07-07 17:25:49 +03003873
3874 if ((attr_mask & IB_QP_PORT) &&
Saeed Mahameed938fe832015-05-28 22:28:41 +03003875 (attr->port_num == 0 ||
Daniel Jurgens508562d2018-01-04 17:25:34 +02003876 attr->port_num > dev->num_ports)) {
Haggai Eran158abf82016-02-29 15:45:04 +02003877 mlx5_ib_dbg(dev, "invalid port number %d. number of ports is %d\n",
3878 attr->port_num, dev->num_ports);
Eli Cohene126ba92013-07-07 17:25:49 +03003879 goto out;
Haggai Eran158abf82016-02-29 15:45:04 +02003880 }
Eli Cohene126ba92013-07-07 17:25:49 +03003881
3882 if (attr_mask & IB_QP_PKEY_INDEX) {
3883 port = attr_mask & IB_QP_PORT ? attr->port_num : qp->port;
Saeed Mahameed938fe832015-05-28 22:28:41 +03003884 if (attr->pkey_index >=
Haggai Eran158abf82016-02-29 15:45:04 +02003885 dev->mdev->port_caps[port - 1].pkey_table_len) {
3886 mlx5_ib_dbg(dev, "invalid pkey index %d\n",
3887 attr->pkey_index);
Eli Cohene126ba92013-07-07 17:25:49 +03003888 goto out;
Haggai Eran158abf82016-02-29 15:45:04 +02003889 }
Eli Cohene126ba92013-07-07 17:25:49 +03003890 }
3891
3892 if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC &&
Saeed Mahameed938fe832015-05-28 22:28:41 +03003893 attr->max_rd_atomic >
Haggai Eran158abf82016-02-29 15:45:04 +02003894 (1 << MLX5_CAP_GEN(dev->mdev, log_max_ra_res_qp))) {
3895 mlx5_ib_dbg(dev, "invalid max_rd_atomic value %d\n",
3896 attr->max_rd_atomic);
Eli Cohene126ba92013-07-07 17:25:49 +03003897 goto out;
Haggai Eran158abf82016-02-29 15:45:04 +02003898 }
Eli Cohene126ba92013-07-07 17:25:49 +03003899
3900 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC &&
Saeed Mahameed938fe832015-05-28 22:28:41 +03003901 attr->max_dest_rd_atomic >
Haggai Eran158abf82016-02-29 15:45:04 +02003902 (1 << MLX5_CAP_GEN(dev->mdev, log_max_ra_req_qp))) {
3903 mlx5_ib_dbg(dev, "invalid max_dest_rd_atomic value %d\n",
3904 attr->max_dest_rd_atomic);
Eli Cohene126ba92013-07-07 17:25:49 +03003905 goto out;
Haggai Eran158abf82016-02-29 15:45:04 +02003906 }
Eli Cohene126ba92013-07-07 17:25:49 +03003907
3908 if (cur_state == new_state && cur_state == IB_QPS_RESET) {
3909 err = 0;
3910 goto out;
3911 }
3912
Bodong Wang61147f32018-03-19 15:10:30 +02003913 err = __mlx5_ib_modify_qp(ibqp, attr, attr_mask, cur_state,
Shamir Rabinovitch89944452019-02-07 18:44:49 +02003914 new_state, &ucmd, udata);
Eli Cohene126ba92013-07-07 17:25:49 +03003915
3916out:
3917 mutex_unlock(&qp->mutex);
3918 return err;
3919}
3920
Guy Levi34f4c952018-11-26 08:15:50 +02003921static void _handle_post_send_edge(struct mlx5_ib_wq *sq, void **seg,
3922 u32 wqe_sz, void **cur_edge)
3923{
3924 u32 idx;
3925
3926 idx = (sq->cur_post + (wqe_sz >> 2)) & (sq->wqe_cnt - 1);
3927 *cur_edge = get_sq_edge(sq, idx);
3928
3929 *seg = mlx5_frag_buf_get_wqe(&sq->fbc, idx);
3930}
3931
3932/* handle_post_send_edge - Check if we get to SQ edge. If yes, update to the
3933 * next nearby edge and get new address translation for current WQE position.
3934 * @sq - SQ buffer.
3935 * @seg: Current WQE position (16B aligned).
3936 * @wqe_sz: Total current WQE size [16B].
3937 * @cur_edge: Updated current edge.
3938 */
3939static inline void handle_post_send_edge(struct mlx5_ib_wq *sq, void **seg,
3940 u32 wqe_sz, void **cur_edge)
3941{
3942 if (likely(*seg != *cur_edge))
3943 return;
3944
3945 _handle_post_send_edge(sq, seg, wqe_sz, cur_edge);
3946}
3947
3948/* memcpy_send_wqe - copy data from src to WQE and update the relevant WQ's
3949 * pointers. At the end @seg is aligned to 16B regardless the copied size.
3950 * @sq - SQ buffer.
3951 * @cur_edge: Updated current edge.
3952 * @seg: Current WQE position (16B aligned).
3953 * @wqe_sz: Total current WQE size [16B].
3954 * @src: Pointer to copy from.
3955 * @n: Number of bytes to copy.
3956 */
3957static inline void memcpy_send_wqe(struct mlx5_ib_wq *sq, void **cur_edge,
3958 void **seg, u32 *wqe_sz, const void *src,
3959 size_t n)
3960{
3961 while (likely(n)) {
3962 size_t leftlen = *cur_edge - *seg;
3963 size_t copysz = min_t(size_t, leftlen, n);
3964 size_t stride;
3965
3966 memcpy(*seg, src, copysz);
3967
3968 n -= copysz;
3969 src += copysz;
3970 stride = !n ? ALIGN(copysz, 16) : copysz;
3971 *seg += stride;
3972 *wqe_sz += stride >> 4;
3973 handle_post_send_edge(sq, seg, *wqe_sz, cur_edge);
3974 }
3975}
3976
Eli Cohene126ba92013-07-07 17:25:49 +03003977static int mlx5_wq_overflow(struct mlx5_ib_wq *wq, int nreq, struct ib_cq *ib_cq)
3978{
3979 struct mlx5_ib_cq *cq;
3980 unsigned cur;
3981
3982 cur = wq->head - wq->tail;
3983 if (likely(cur + nreq < wq->max_post))
3984 return 0;
3985
3986 cq = to_mcq(ib_cq);
3987 spin_lock(&cq->lock);
3988 cur = wq->head - wq->tail;
3989 spin_unlock(&cq->lock);
3990
3991 return cur + nreq >= wq->max_post;
3992}
3993
3994static __always_inline void set_raddr_seg(struct mlx5_wqe_raddr_seg *rseg,
3995 u64 remote_addr, u32 rkey)
3996{
3997 rseg->raddr = cpu_to_be64(remote_addr);
3998 rseg->rkey = cpu_to_be32(rkey);
3999 rseg->reserved = 0;
4000}
4001
Guy Levi34f4c952018-11-26 08:15:50 +02004002static void set_eth_seg(const struct ib_send_wr *wr, struct mlx5_ib_qp *qp,
4003 void **seg, int *size, void **cur_edge)
Erez Shitritf0313962016-02-21 16:27:17 +02004004{
Guy Levi34f4c952018-11-26 08:15:50 +02004005 struct mlx5_wqe_eth_seg *eseg = *seg;
Erez Shitritf0313962016-02-21 16:27:17 +02004006
4007 memset(eseg, 0, sizeof(struct mlx5_wqe_eth_seg));
4008
4009 if (wr->send_flags & IB_SEND_IP_CSUM)
4010 eseg->cs_flags = MLX5_ETH_WQE_L3_CSUM |
4011 MLX5_ETH_WQE_L4_CSUM;
4012
Erez Shitritf0313962016-02-21 16:27:17 +02004013 if (wr->opcode == IB_WR_LSO) {
4014 struct ib_ud_wr *ud_wr = container_of(wr, struct ib_ud_wr, wr);
Guy Levi34f4c952018-11-26 08:15:50 +02004015 size_t left, copysz;
Erez Shitritf0313962016-02-21 16:27:17 +02004016 void *pdata = ud_wr->header;
Guy Levi34f4c952018-11-26 08:15:50 +02004017 size_t stride;
Erez Shitritf0313962016-02-21 16:27:17 +02004018
4019 left = ud_wr->hlen;
4020 eseg->mss = cpu_to_be16(ud_wr->mss);
Saeed Mahameed2b31f7a2016-11-28 18:04:50 +02004021 eseg->inline_hdr.sz = cpu_to_be16(left);
Erez Shitritf0313962016-02-21 16:27:17 +02004022
Guy Levi34f4c952018-11-26 08:15:50 +02004023 /* memcpy_send_wqe should get a 16B align address. Hence, we
4024 * first copy up to the current edge and then, if needed,
4025 * fall-through to memcpy_send_wqe.
Erez Shitritf0313962016-02-21 16:27:17 +02004026 */
Guy Levi34f4c952018-11-26 08:15:50 +02004027 copysz = min_t(u64, *cur_edge - (void *)eseg->inline_hdr.start,
4028 left);
4029 memcpy(eseg->inline_hdr.start, pdata, copysz);
4030 stride = ALIGN(sizeof(struct mlx5_wqe_eth_seg) -
4031 sizeof(eseg->inline_hdr.start) + copysz, 16);
4032 *size += stride / 16;
4033 *seg += stride;
Erez Shitritf0313962016-02-21 16:27:17 +02004034
Guy Levi34f4c952018-11-26 08:15:50 +02004035 if (copysz < left) {
4036 handle_post_send_edge(&qp->sq, seg, *size, cur_edge);
Erez Shitritf0313962016-02-21 16:27:17 +02004037 left -= copysz;
4038 pdata += copysz;
Guy Levi34f4c952018-11-26 08:15:50 +02004039 memcpy_send_wqe(&qp->sq, cur_edge, seg, size, pdata,
4040 left);
Erez Shitritf0313962016-02-21 16:27:17 +02004041 }
Guy Levi34f4c952018-11-26 08:15:50 +02004042
4043 return;
Erez Shitritf0313962016-02-21 16:27:17 +02004044 }
4045
Guy Levi34f4c952018-11-26 08:15:50 +02004046 *seg += sizeof(struct mlx5_wqe_eth_seg);
4047 *size += sizeof(struct mlx5_wqe_eth_seg) / 16;
Erez Shitritf0313962016-02-21 16:27:17 +02004048}
4049
Eli Cohene126ba92013-07-07 17:25:49 +03004050static void set_datagram_seg(struct mlx5_wqe_datagram_seg *dseg,
Bart Van Asschef696bf62018-07-18 09:25:14 -07004051 const struct ib_send_wr *wr)
Eli Cohene126ba92013-07-07 17:25:49 +03004052{
Christoph Hellwige622f2f2015-10-08 09:16:33 +01004053 memcpy(&dseg->av, &to_mah(ud_wr(wr)->ah)->av, sizeof(struct mlx5_av));
4054 dseg->av.dqp_dct = cpu_to_be32(ud_wr(wr)->remote_qpn | MLX5_EXTENDED_UD_AV);
4055 dseg->av.key.qkey.qkey = cpu_to_be32(ud_wr(wr)->remote_qkey);
Eli Cohene126ba92013-07-07 17:25:49 +03004056}
4057
4058static void set_data_ptr_seg(struct mlx5_wqe_data_seg *dseg, struct ib_sge *sg)
4059{
4060 dseg->byte_count = cpu_to_be32(sg->length);
4061 dseg->lkey = cpu_to_be32(sg->lkey);
4062 dseg->addr = cpu_to_be64(sg->addr);
4063}
4064
Artemy Kovalyov31616252017-01-02 11:37:42 +02004065static u64 get_xlt_octo(u64 bytes)
Eli Cohene126ba92013-07-07 17:25:49 +03004066{
Artemy Kovalyov31616252017-01-02 11:37:42 +02004067 return ALIGN(bytes, MLX5_IB_UMR_XLT_ALIGNMENT) /
4068 MLX5_IB_UMR_OCTOWORD;
Eli Cohene126ba92013-07-07 17:25:49 +03004069}
4070
4071static __be64 frwr_mkey_mask(void)
4072{
4073 u64 result;
4074
4075 result = MLX5_MKEY_MASK_LEN |
4076 MLX5_MKEY_MASK_PAGE_SIZE |
4077 MLX5_MKEY_MASK_START_ADDR |
4078 MLX5_MKEY_MASK_EN_RINVAL |
4079 MLX5_MKEY_MASK_KEY |
4080 MLX5_MKEY_MASK_LR |
4081 MLX5_MKEY_MASK_LW |
4082 MLX5_MKEY_MASK_RR |
4083 MLX5_MKEY_MASK_RW |
4084 MLX5_MKEY_MASK_A |
4085 MLX5_MKEY_MASK_SMALL_FENCE |
4086 MLX5_MKEY_MASK_FREE;
4087
4088 return cpu_to_be64(result);
4089}
4090
Sagi Grimberge6631812014-02-23 14:19:11 +02004091static __be64 sig_mkey_mask(void)
4092{
4093 u64 result;
4094
4095 result = MLX5_MKEY_MASK_LEN |
4096 MLX5_MKEY_MASK_PAGE_SIZE |
4097 MLX5_MKEY_MASK_START_ADDR |
Sagi Grimbergd5436ba2014-02-23 14:19:12 +02004098 MLX5_MKEY_MASK_EN_SIGERR |
Sagi Grimberge6631812014-02-23 14:19:11 +02004099 MLX5_MKEY_MASK_EN_RINVAL |
4100 MLX5_MKEY_MASK_KEY |
4101 MLX5_MKEY_MASK_LR |
4102 MLX5_MKEY_MASK_LW |
4103 MLX5_MKEY_MASK_RR |
4104 MLX5_MKEY_MASK_RW |
4105 MLX5_MKEY_MASK_SMALL_FENCE |
4106 MLX5_MKEY_MASK_FREE |
4107 MLX5_MKEY_MASK_BSF_EN;
4108
4109 return cpu_to_be64(result);
4110}
4111
Sagi Grimberg8a187ee2015-10-13 19:11:26 +03004112static void set_reg_umr_seg(struct mlx5_wqe_umr_ctrl_seg *umr,
Idan Burstein064e5262018-05-02 13:16:39 +03004113 struct mlx5_ib_mr *mr, bool umr_inline)
Sagi Grimberg8a187ee2015-10-13 19:11:26 +03004114{
Artemy Kovalyov31616252017-01-02 11:37:42 +02004115 int size = mr->ndescs * mr->desc_size;
Sagi Grimberg8a187ee2015-10-13 19:11:26 +03004116
4117 memset(umr, 0, sizeof(*umr));
Sagi Grimbergb005d312016-02-29 19:07:33 +02004118
Sagi Grimberg8a187ee2015-10-13 19:11:26 +03004119 umr->flags = MLX5_UMR_CHECK_NOT_FREE;
Idan Burstein064e5262018-05-02 13:16:39 +03004120 if (umr_inline)
4121 umr->flags |= MLX5_UMR_INLINE;
Artemy Kovalyov31616252017-01-02 11:37:42 +02004122 umr->xlt_octowords = cpu_to_be16(get_xlt_octo(size));
Sagi Grimberg8a187ee2015-10-13 19:11:26 +03004123 umr->mkey_mask = frwr_mkey_mask();
4124}
4125
Sagi Grimbergdd01e662015-10-13 19:11:42 +03004126static void set_linv_umr_seg(struct mlx5_wqe_umr_ctrl_seg *umr)
Eli Cohene126ba92013-07-07 17:25:49 +03004127{
4128 memset(umr, 0, sizeof(*umr));
Sagi Grimbergdd01e662015-10-13 19:11:42 +03004129 umr->mkey_mask = cpu_to_be64(MLX5_MKEY_MASK_FREE);
Max Gurtovoy2d221582016-10-27 16:36:36 +03004130 umr->flags = MLX5_UMR_INLINE;
Eli Cohene126ba92013-07-07 17:25:49 +03004131}
4132
Artemy Kovalyov31616252017-01-02 11:37:42 +02004133static __be64 get_umr_enable_mr_mask(void)
Haggai Eran968e78d2014-12-11 17:04:11 +02004134{
4135 u64 result;
4136
Artemy Kovalyov31616252017-01-02 11:37:42 +02004137 result = MLX5_MKEY_MASK_KEY |
Haggai Eran968e78d2014-12-11 17:04:11 +02004138 MLX5_MKEY_MASK_FREE;
4139
4140 return cpu_to_be64(result);
4141}
4142
Artemy Kovalyov31616252017-01-02 11:37:42 +02004143static __be64 get_umr_disable_mr_mask(void)
Haggai Eran968e78d2014-12-11 17:04:11 +02004144{
4145 u64 result;
4146
4147 result = MLX5_MKEY_MASK_FREE;
4148
4149 return cpu_to_be64(result);
4150}
4151
Noa Osherovich56e11d62016-02-29 16:46:51 +02004152static __be64 get_umr_update_translation_mask(void)
4153{
4154 u64 result;
4155
4156 result = MLX5_MKEY_MASK_LEN |
4157 MLX5_MKEY_MASK_PAGE_SIZE |
Artemy Kovalyov31616252017-01-02 11:37:42 +02004158 MLX5_MKEY_MASK_START_ADDR;
Noa Osherovich56e11d62016-02-29 16:46:51 +02004159
4160 return cpu_to_be64(result);
4161}
4162
Artemy Kovalyov31616252017-01-02 11:37:42 +02004163static __be64 get_umr_update_access_mask(int atomic)
Noa Osherovich56e11d62016-02-29 16:46:51 +02004164{
4165 u64 result;
4166
Artemy Kovalyov31616252017-01-02 11:37:42 +02004167 result = MLX5_MKEY_MASK_LR |
4168 MLX5_MKEY_MASK_LW |
Noa Osherovich56e11d62016-02-29 16:46:51 +02004169 MLX5_MKEY_MASK_RR |
Artemy Kovalyov31616252017-01-02 11:37:42 +02004170 MLX5_MKEY_MASK_RW;
4171
4172 if (atomic)
4173 result |= MLX5_MKEY_MASK_A;
Noa Osherovich56e11d62016-02-29 16:46:51 +02004174
4175 return cpu_to_be64(result);
4176}
4177
4178static __be64 get_umr_update_pd_mask(void)
4179{
4180 u64 result;
4181
Artemy Kovalyov31616252017-01-02 11:37:42 +02004182 result = MLX5_MKEY_MASK_PD;
Noa Osherovich56e11d62016-02-29 16:46:51 +02004183
4184 return cpu_to_be64(result);
4185}
4186
Majd Dibbinyc8d75a92018-03-22 15:34:04 +02004187static int umr_check_mkey_mask(struct mlx5_ib_dev *dev, u64 mask)
4188{
4189 if ((mask & MLX5_MKEY_MASK_PAGE_SIZE &&
4190 MLX5_CAP_GEN(dev->mdev, umr_modify_entity_size_disabled)) ||
4191 (mask & MLX5_MKEY_MASK_A &&
4192 MLX5_CAP_GEN(dev->mdev, umr_modify_atomic_disabled)))
4193 return -EPERM;
4194 return 0;
4195}
4196
4197static int set_reg_umr_segment(struct mlx5_ib_dev *dev,
4198 struct mlx5_wqe_umr_ctrl_seg *umr,
Bart Van Asschef696bf62018-07-18 09:25:14 -07004199 const struct ib_send_wr *wr, int atomic)
Eli Cohene126ba92013-07-07 17:25:49 +03004200{
Bart Van Asschef696bf62018-07-18 09:25:14 -07004201 const struct mlx5_umr_wr *umrwr = umr_wr(wr);
Eli Cohene126ba92013-07-07 17:25:49 +03004202
4203 memset(umr, 0, sizeof(*umr));
4204
Haggai Eran968e78d2014-12-11 17:04:11 +02004205 if (wr->send_flags & MLX5_IB_SEND_UMR_FAIL_IF_FREE)
4206 umr->flags = MLX5_UMR_CHECK_FREE; /* fail if free */
4207 else
4208 umr->flags = MLX5_UMR_CHECK_NOT_FREE; /* fail if not free */
4209
Artemy Kovalyov31616252017-01-02 11:37:42 +02004210 umr->xlt_octowords = cpu_to_be16(get_xlt_octo(umrwr->xlt_size));
4211 if (wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_XLT) {
4212 u64 offset = get_xlt_octo(umrwr->offset);
4213
4214 umr->xlt_offset = cpu_to_be16(offset & 0xffff);
4215 umr->xlt_offset_47_16 = cpu_to_be32(offset >> 16);
4216 umr->flags |= MLX5_UMR_TRANSLATION_OFFSET_EN;
Eli Cohene126ba92013-07-07 17:25:49 +03004217 }
Artemy Kovalyov31616252017-01-02 11:37:42 +02004218 if (wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_TRANSLATION)
4219 umr->mkey_mask |= get_umr_update_translation_mask();
4220 if (wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_PD_ACCESS) {
4221 umr->mkey_mask |= get_umr_update_access_mask(atomic);
4222 umr->mkey_mask |= get_umr_update_pd_mask();
4223 }
4224 if (wr->send_flags & MLX5_IB_SEND_UMR_ENABLE_MR)
4225 umr->mkey_mask |= get_umr_enable_mr_mask();
4226 if (wr->send_flags & MLX5_IB_SEND_UMR_DISABLE_MR)
4227 umr->mkey_mask |= get_umr_disable_mr_mask();
Eli Cohene126ba92013-07-07 17:25:49 +03004228
4229 if (!wr->num_sge)
Haggai Eran968e78d2014-12-11 17:04:11 +02004230 umr->flags |= MLX5_UMR_INLINE;
Majd Dibbinyc8d75a92018-03-22 15:34:04 +02004231
4232 return umr_check_mkey_mask(dev, be64_to_cpu(umr->mkey_mask));
Eli Cohene126ba92013-07-07 17:25:49 +03004233}
4234
4235static u8 get_umr_flags(int acc)
4236{
4237 return (acc & IB_ACCESS_REMOTE_ATOMIC ? MLX5_PERM_ATOMIC : 0) |
4238 (acc & IB_ACCESS_REMOTE_WRITE ? MLX5_PERM_REMOTE_WRITE : 0) |
4239 (acc & IB_ACCESS_REMOTE_READ ? MLX5_PERM_REMOTE_READ : 0) |
4240 (acc & IB_ACCESS_LOCAL_WRITE ? MLX5_PERM_LOCAL_WRITE : 0) |
Sagi Grimberg2ac45932014-02-23 14:19:09 +02004241 MLX5_PERM_LOCAL_READ | MLX5_PERM_UMR_EN;
Eli Cohene126ba92013-07-07 17:25:49 +03004242}
4243
Sagi Grimberg8a187ee2015-10-13 19:11:26 +03004244static void set_reg_mkey_seg(struct mlx5_mkey_seg *seg,
4245 struct mlx5_ib_mr *mr,
4246 u32 key, int access)
4247{
4248 int ndescs = ALIGN(mr->ndescs, 8) >> 1;
4249
4250 memset(seg, 0, sizeof(*seg));
Sagi Grimbergb005d312016-02-29 19:07:33 +02004251
Saeed Mahameedec22eb52016-07-16 06:28:36 +03004252 if (mr->access_mode == MLX5_MKC_ACCESS_MODE_MTT)
Sagi Grimbergb005d312016-02-29 19:07:33 +02004253 seg->log2_page_size = ilog2(mr->ibmr.page_size);
Saeed Mahameedec22eb52016-07-16 06:28:36 +03004254 else if (mr->access_mode == MLX5_MKC_ACCESS_MODE_KLMS)
Sagi Grimbergb005d312016-02-29 19:07:33 +02004255 /* KLMs take twice the size of MTTs */
4256 ndescs *= 2;
4257
4258 seg->flags = get_umr_flags(access) | mr->access_mode;
Sagi Grimberg8a187ee2015-10-13 19:11:26 +03004259 seg->qpn_mkey7_0 = cpu_to_be32((key & 0xff) | 0xffffff00);
4260 seg->flags_pd = cpu_to_be32(MLX5_MKEY_REMOTE_INVAL);
4261 seg->start_addr = cpu_to_be64(mr->ibmr.iova);
4262 seg->len = cpu_to_be64(mr->ibmr.length);
4263 seg->xlt_oct_size = cpu_to_be32(ndescs);
Sagi Grimberg8a187ee2015-10-13 19:11:26 +03004264}
4265
Sagi Grimbergdd01e662015-10-13 19:11:42 +03004266static void set_linv_mkey_seg(struct mlx5_mkey_seg *seg)
Eli Cohene126ba92013-07-07 17:25:49 +03004267{
4268 memset(seg, 0, sizeof(*seg));
Sagi Grimbergdd01e662015-10-13 19:11:42 +03004269 seg->status = MLX5_MKEY_STATUS_FREE;
Eli Cohene126ba92013-07-07 17:25:49 +03004270}
4271
Bart Van Asschef696bf62018-07-18 09:25:14 -07004272static void set_reg_mkey_segment(struct mlx5_mkey_seg *seg,
4273 const struct ib_send_wr *wr)
Eli Cohene126ba92013-07-07 17:25:49 +03004274{
Bart Van Asschef696bf62018-07-18 09:25:14 -07004275 const struct mlx5_umr_wr *umrwr = umr_wr(wr);
Haggai Eran968e78d2014-12-11 17:04:11 +02004276
Eli Cohene126ba92013-07-07 17:25:49 +03004277 memset(seg, 0, sizeof(*seg));
Artemy Kovalyov31616252017-01-02 11:37:42 +02004278 if (wr->send_flags & MLX5_IB_SEND_UMR_DISABLE_MR)
Haggai Eran968e78d2014-12-11 17:04:11 +02004279 seg->status = MLX5_MKEY_STATUS_FREE;
Eli Cohene126ba92013-07-07 17:25:49 +03004280
Haggai Eran968e78d2014-12-11 17:04:11 +02004281 seg->flags = convert_access(umrwr->access_flags);
Artemy Kovalyov31616252017-01-02 11:37:42 +02004282 if (umrwr->pd)
4283 seg->flags_pd = cpu_to_be32(to_mpd(umrwr->pd)->pdn);
4284 if (wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_TRANSLATION &&
4285 !umrwr->length)
4286 seg->flags_pd |= cpu_to_be32(MLX5_MKEY_LEN64);
4287
4288 seg->start_addr = cpu_to_be64(umrwr->virt_addr);
Haggai Eran968e78d2014-12-11 17:04:11 +02004289 seg->len = cpu_to_be64(umrwr->length);
4290 seg->log2_page_size = umrwr->page_shift;
Eli Cohen746b5582013-10-23 09:53:14 +03004291 seg->qpn_mkey7_0 = cpu_to_be32(0xffffff00 |
Haggai Eran968e78d2014-12-11 17:04:11 +02004292 mlx5_mkey_variant(umrwr->mkey));
Eli Cohene126ba92013-07-07 17:25:49 +03004293}
4294
Sagi Grimberg8a187ee2015-10-13 19:11:26 +03004295static void set_reg_data_seg(struct mlx5_wqe_data_seg *dseg,
4296 struct mlx5_ib_mr *mr,
4297 struct mlx5_ib_pd *pd)
4298{
4299 int bcount = mr->desc_size * mr->ndescs;
4300
4301 dseg->addr = cpu_to_be64(mr->desc_map);
4302 dseg->byte_count = cpu_to_be32(ALIGN(bcount, 64));
4303 dseg->lkey = cpu_to_be32(pd->ibpd.local_dma_lkey);
4304}
4305
Bart Van Asschef696bf62018-07-18 09:25:14 -07004306static __be32 send_ieth(const struct ib_send_wr *wr)
Eli Cohene126ba92013-07-07 17:25:49 +03004307{
4308 switch (wr->opcode) {
4309 case IB_WR_SEND_WITH_IMM:
4310 case IB_WR_RDMA_WRITE_WITH_IMM:
4311 return wr->ex.imm_data;
4312
4313 case IB_WR_SEND_WITH_INV:
4314 return cpu_to_be32(wr->ex.invalidate_rkey);
4315
4316 default:
4317 return 0;
4318 }
4319}
4320
4321static u8 calc_sig(void *wqe, int size)
4322{
4323 u8 *p = wqe;
4324 u8 res = 0;
4325 int i;
4326
4327 for (i = 0; i < size; i++)
4328 res ^= p[i];
4329
4330 return ~res;
4331}
4332
4333static u8 wq_sig(void *wqe)
4334{
4335 return calc_sig(wqe, (*((u8 *)wqe + 8) & 0x3f) << 4);
4336}
4337
Bart Van Asschef696bf62018-07-18 09:25:14 -07004338static int set_data_inl_seg(struct mlx5_ib_qp *qp, const struct ib_send_wr *wr,
Guy Levi34f4c952018-11-26 08:15:50 +02004339 void **wqe, int *wqe_sz, void **cur_edge)
Eli Cohene126ba92013-07-07 17:25:49 +03004340{
4341 struct mlx5_wqe_inline_seg *seg;
Guy Levi34f4c952018-11-26 08:15:50 +02004342 size_t offset;
Eli Cohene126ba92013-07-07 17:25:49 +03004343 int inl = 0;
Eli Cohene126ba92013-07-07 17:25:49 +03004344 int i;
4345
Guy Levi34f4c952018-11-26 08:15:50 +02004346 seg = *wqe;
4347 *wqe += sizeof(*seg);
4348 offset = sizeof(*seg);
4349
Eli Cohene126ba92013-07-07 17:25:49 +03004350 for (i = 0; i < wr->num_sge; i++) {
Guy Levi34f4c952018-11-26 08:15:50 +02004351 size_t len = wr->sg_list[i].length;
4352 void *addr = (void *)(unsigned long)(wr->sg_list[i].addr);
4353
Eli Cohene126ba92013-07-07 17:25:49 +03004354 inl += len;
4355
4356 if (unlikely(inl > qp->max_inline_data))
4357 return -ENOMEM;
4358
Guy Levi34f4c952018-11-26 08:15:50 +02004359 while (likely(len)) {
4360 size_t leftlen;
4361 size_t copysz;
4362
4363 handle_post_send_edge(&qp->sq, wqe,
4364 *wqe_sz + (offset >> 4),
4365 cur_edge);
4366
4367 leftlen = *cur_edge - *wqe;
4368 copysz = min_t(size_t, leftlen, len);
4369
4370 memcpy(*wqe, addr, copysz);
4371 len -= copysz;
4372 addr += copysz;
4373 *wqe += copysz;
4374 offset += copysz;
Eli Cohene126ba92013-07-07 17:25:49 +03004375 }
Eli Cohene126ba92013-07-07 17:25:49 +03004376 }
4377
4378 seg->byte_count = cpu_to_be32(inl | MLX5_INLINE_SEG);
4379
Guy Levi34f4c952018-11-26 08:15:50 +02004380 *wqe_sz += ALIGN(inl + sizeof(seg->byte_count), 16) / 16;
Eli Cohene126ba92013-07-07 17:25:49 +03004381
4382 return 0;
4383}
4384
Sagi Grimberge6631812014-02-23 14:19:11 +02004385static u16 prot_field_size(enum ib_signature_type type)
4386{
4387 switch (type) {
4388 case IB_SIG_TYPE_T10_DIF:
4389 return MLX5_DIF_SIZE;
4390 default:
4391 return 0;
4392 }
4393}
4394
4395static u8 bs_selector(int block_size)
4396{
4397 switch (block_size) {
4398 case 512: return 0x1;
4399 case 520: return 0x2;
4400 case 4096: return 0x3;
4401 case 4160: return 0x4;
4402 case 1073741824: return 0x5;
4403 default: return 0;
4404 }
4405}
4406
Sagi Grimberg78eda2b2014-08-13 19:54:35 +03004407static void mlx5_fill_inl_bsf(struct ib_sig_domain *domain,
4408 struct mlx5_bsf_inl *inl)
Sagi Grimberge6631812014-02-23 14:19:11 +02004409{
Sagi Grimberg142537f2014-08-13 19:54:32 +03004410 /* Valid inline section and allow BSF refresh */
4411 inl->vld_refresh = cpu_to_be16(MLX5_BSF_INL_VALID |
4412 MLX5_BSF_REFRESH_DIF);
4413 inl->dif_apptag = cpu_to_be16(domain->sig.dif.app_tag);
4414 inl->dif_reftag = cpu_to_be32(domain->sig.dif.ref_tag);
Sagi Grimberg78eda2b2014-08-13 19:54:35 +03004415 /* repeating block */
4416 inl->rp_inv_seed = MLX5_BSF_REPEAT_BLOCK;
4417 inl->sig_type = domain->sig.dif.bg_type == IB_T10DIF_CRC ?
4418 MLX5_DIF_CRC : MLX5_DIF_IPCS;
Sagi Grimberge6631812014-02-23 14:19:11 +02004419
Sagi Grimberg78eda2b2014-08-13 19:54:35 +03004420 if (domain->sig.dif.ref_remap)
4421 inl->dif_inc_ref_guard_check |= MLX5_BSF_INC_REFTAG;
Sagi Grimberge6631812014-02-23 14:19:11 +02004422
Sagi Grimberg78eda2b2014-08-13 19:54:35 +03004423 if (domain->sig.dif.app_escape) {
4424 if (domain->sig.dif.ref_escape)
4425 inl->dif_inc_ref_guard_check |= MLX5_BSF_APPREF_ESCAPE;
4426 else
4427 inl->dif_inc_ref_guard_check |= MLX5_BSF_APPTAG_ESCAPE;
Sagi Grimberge6631812014-02-23 14:19:11 +02004428 }
4429
Sagi Grimberg78eda2b2014-08-13 19:54:35 +03004430 inl->dif_app_bitmask_check =
4431 cpu_to_be16(domain->sig.dif.apptag_check_mask);
Sagi Grimberge6631812014-02-23 14:19:11 +02004432}
4433
4434static int mlx5_set_bsf(struct ib_mr *sig_mr,
4435 struct ib_sig_attrs *sig_attrs,
4436 struct mlx5_bsf *bsf, u32 data_size)
4437{
4438 struct mlx5_core_sig_ctx *msig = to_mmr(sig_mr)->sig;
4439 struct mlx5_bsf_basic *basic = &bsf->basic;
4440 struct ib_sig_domain *mem = &sig_attrs->mem;
4441 struct ib_sig_domain *wire = &sig_attrs->wire;
Sagi Grimberge6631812014-02-23 14:19:11 +02004442
Sagi Grimbergc7f44fb2014-05-18 18:32:40 +03004443 memset(bsf, 0, sizeof(*bsf));
Sagi Grimberge6631812014-02-23 14:19:11 +02004444
Sagi Grimberg78eda2b2014-08-13 19:54:35 +03004445 /* Basic + Extended + Inline */
4446 basic->bsf_size_sbs = 1 << 7;
4447 /* Input domain check byte mask */
4448 basic->check_byte_mask = sig_attrs->check_mask;
4449 basic->raw_data_size = cpu_to_be32(data_size);
4450
4451 /* Memory domain */
4452 switch (sig_attrs->mem.sig_type) {
4453 case IB_SIG_TYPE_NONE:
4454 break;
4455 case IB_SIG_TYPE_T10_DIF:
4456 basic->mem.bs_selector = bs_selector(mem->sig.dif.pi_interval);
4457 basic->m_bfs_psv = cpu_to_be32(msig->psv_memory.psv_idx);
4458 mlx5_fill_inl_bsf(mem, &bsf->m_inl);
4459 break;
4460 default:
4461 return -EINVAL;
4462 }
4463
4464 /* Wire domain */
4465 switch (sig_attrs->wire.sig_type) {
4466 case IB_SIG_TYPE_NONE:
4467 break;
4468 case IB_SIG_TYPE_T10_DIF:
Sagi Grimberge6631812014-02-23 14:19:11 +02004469 if (mem->sig.dif.pi_interval == wire->sig.dif.pi_interval &&
Sagi Grimberg78eda2b2014-08-13 19:54:35 +03004470 mem->sig_type == wire->sig_type) {
Sagi Grimberge6631812014-02-23 14:19:11 +02004471 /* Same block structure */
Sagi Grimberg142537f2014-08-13 19:54:32 +03004472 basic->bsf_size_sbs |= 1 << 4;
Sagi Grimberge6631812014-02-23 14:19:11 +02004473 if (mem->sig.dif.bg_type == wire->sig.dif.bg_type)
Sagi Grimbergfd22f782014-08-13 19:54:29 +03004474 basic->wire.copy_byte_mask |= MLX5_CPY_GRD_MASK;
Sagi Grimbergc7f44fb2014-05-18 18:32:40 +03004475 if (mem->sig.dif.app_tag == wire->sig.dif.app_tag)
Sagi Grimbergfd22f782014-08-13 19:54:29 +03004476 basic->wire.copy_byte_mask |= MLX5_CPY_APP_MASK;
Sagi Grimbergc7f44fb2014-05-18 18:32:40 +03004477 if (mem->sig.dif.ref_tag == wire->sig.dif.ref_tag)
Sagi Grimbergfd22f782014-08-13 19:54:29 +03004478 basic->wire.copy_byte_mask |= MLX5_CPY_REF_MASK;
Sagi Grimberge6631812014-02-23 14:19:11 +02004479 } else
4480 basic->wire.bs_selector = bs_selector(wire->sig.dif.pi_interval);
4481
Sagi Grimberg142537f2014-08-13 19:54:32 +03004482 basic->w_bfs_psv = cpu_to_be32(msig->psv_wire.psv_idx);
Sagi Grimberg78eda2b2014-08-13 19:54:35 +03004483 mlx5_fill_inl_bsf(wire, &bsf->w_inl);
Sagi Grimberge6631812014-02-23 14:19:11 +02004484 break;
Sagi Grimberge6631812014-02-23 14:19:11 +02004485 default:
4486 return -EINVAL;
4487 }
4488
4489 return 0;
4490}
4491
Bart Van Asschef696bf62018-07-18 09:25:14 -07004492static int set_sig_data_segment(const struct ib_sig_handover_wr *wr,
Guy Levi34f4c952018-11-26 08:15:50 +02004493 struct mlx5_ib_qp *qp, void **seg,
4494 int *size, void **cur_edge)
Sagi Grimberge6631812014-02-23 14:19:11 +02004495{
Christoph Hellwige622f2f2015-10-08 09:16:33 +01004496 struct ib_sig_attrs *sig_attrs = wr->sig_attrs;
4497 struct ib_mr *sig_mr = wr->sig_mr;
Sagi Grimberge6631812014-02-23 14:19:11 +02004498 struct mlx5_bsf *bsf;
Christoph Hellwige622f2f2015-10-08 09:16:33 +01004499 u32 data_len = wr->wr.sg_list->length;
4500 u32 data_key = wr->wr.sg_list->lkey;
4501 u64 data_va = wr->wr.sg_list->addr;
Sagi Grimberge6631812014-02-23 14:19:11 +02004502 int ret;
4503 int wqe_size;
4504
Christoph Hellwige622f2f2015-10-08 09:16:33 +01004505 if (!wr->prot ||
4506 (data_key == wr->prot->lkey &&
4507 data_va == wr->prot->addr &&
4508 data_len == wr->prot->length)) {
Sagi Grimberge6631812014-02-23 14:19:11 +02004509 /**
4510 * Source domain doesn't contain signature information
Sagi Grimberg5c273b12014-05-18 18:32:39 +03004511 * or data and protection are interleaved in memory.
Sagi Grimberge6631812014-02-23 14:19:11 +02004512 * So need construct:
4513 * ------------------
4514 * | data_klm |
4515 * ------------------
4516 * | BSF |
4517 * ------------------
4518 **/
4519 struct mlx5_klm *data_klm = *seg;
4520
4521 data_klm->bcount = cpu_to_be32(data_len);
4522 data_klm->key = cpu_to_be32(data_key);
4523 data_klm->va = cpu_to_be64(data_va);
4524 wqe_size = ALIGN(sizeof(*data_klm), 64);
4525 } else {
4526 /**
4527 * Source domain contains signature information
4528 * So need construct a strided block format:
4529 * ---------------------------
4530 * | stride_block_ctrl |
4531 * ---------------------------
4532 * | data_klm |
4533 * ---------------------------
4534 * | prot_klm |
4535 * ---------------------------
4536 * | BSF |
4537 * ---------------------------
4538 **/
4539 struct mlx5_stride_block_ctrl_seg *sblock_ctrl;
4540 struct mlx5_stride_block_entry *data_sentry;
4541 struct mlx5_stride_block_entry *prot_sentry;
Christoph Hellwige622f2f2015-10-08 09:16:33 +01004542 u32 prot_key = wr->prot->lkey;
4543 u64 prot_va = wr->prot->addr;
Sagi Grimberge6631812014-02-23 14:19:11 +02004544 u16 block_size = sig_attrs->mem.sig.dif.pi_interval;
4545 int prot_size;
4546
4547 sblock_ctrl = *seg;
4548 data_sentry = (void *)sblock_ctrl + sizeof(*sblock_ctrl);
4549 prot_sentry = (void *)data_sentry + sizeof(*data_sentry);
4550
4551 prot_size = prot_field_size(sig_attrs->mem.sig_type);
4552 if (!prot_size) {
4553 pr_err("Bad block size given: %u\n", block_size);
4554 return -EINVAL;
4555 }
4556 sblock_ctrl->bcount_per_cycle = cpu_to_be32(block_size +
4557 prot_size);
4558 sblock_ctrl->op = cpu_to_be32(MLX5_STRIDE_BLOCK_OP);
4559 sblock_ctrl->repeat_count = cpu_to_be32(data_len / block_size);
4560 sblock_ctrl->num_entries = cpu_to_be16(2);
4561
4562 data_sentry->bcount = cpu_to_be16(block_size);
4563 data_sentry->key = cpu_to_be32(data_key);
4564 data_sentry->va = cpu_to_be64(data_va);
Sagi Grimberg5c273b12014-05-18 18:32:39 +03004565 data_sentry->stride = cpu_to_be16(block_size);
4566
Sagi Grimberge6631812014-02-23 14:19:11 +02004567 prot_sentry->bcount = cpu_to_be16(prot_size);
4568 prot_sentry->key = cpu_to_be32(prot_key);
Sagi Grimberg5c273b12014-05-18 18:32:39 +03004569 prot_sentry->va = cpu_to_be64(prot_va);
4570 prot_sentry->stride = cpu_to_be16(prot_size);
Sagi Grimberge6631812014-02-23 14:19:11 +02004571
Sagi Grimberge6631812014-02-23 14:19:11 +02004572 wqe_size = ALIGN(sizeof(*sblock_ctrl) + sizeof(*data_sentry) +
4573 sizeof(*prot_sentry), 64);
4574 }
4575
4576 *seg += wqe_size;
4577 *size += wqe_size / 16;
Guy Levi34f4c952018-11-26 08:15:50 +02004578 handle_post_send_edge(&qp->sq, seg, *size, cur_edge);
Sagi Grimberge6631812014-02-23 14:19:11 +02004579
4580 bsf = *seg;
4581 ret = mlx5_set_bsf(sig_mr, sig_attrs, bsf, data_len);
4582 if (ret)
4583 return -EINVAL;
4584
4585 *seg += sizeof(*bsf);
4586 *size += sizeof(*bsf) / 16;
Guy Levi34f4c952018-11-26 08:15:50 +02004587 handle_post_send_edge(&qp->sq, seg, *size, cur_edge);
Sagi Grimberge6631812014-02-23 14:19:11 +02004588
4589 return 0;
4590}
4591
4592static void set_sig_mkey_segment(struct mlx5_mkey_seg *seg,
Bart Van Asschef696bf62018-07-18 09:25:14 -07004593 const struct ib_sig_handover_wr *wr, u32 size,
Sagi Grimberge6631812014-02-23 14:19:11 +02004594 u32 length, u32 pdn)
4595{
Christoph Hellwige622f2f2015-10-08 09:16:33 +01004596 struct ib_mr *sig_mr = wr->sig_mr;
Sagi Grimberge6631812014-02-23 14:19:11 +02004597 u32 sig_key = sig_mr->rkey;
Sagi Grimbergd5436ba2014-02-23 14:19:12 +02004598 u8 sigerr = to_mmr(sig_mr)->sig->sigerr_count & 1;
Sagi Grimberge6631812014-02-23 14:19:11 +02004599
4600 memset(seg, 0, sizeof(*seg));
4601
Christoph Hellwige622f2f2015-10-08 09:16:33 +01004602 seg->flags = get_umr_flags(wr->access_flags) |
Saeed Mahameedec22eb52016-07-16 06:28:36 +03004603 MLX5_MKC_ACCESS_MODE_KLMS;
Sagi Grimberge6631812014-02-23 14:19:11 +02004604 seg->qpn_mkey7_0 = cpu_to_be32((sig_key & 0xff) | 0xffffff00);
Sagi Grimbergd5436ba2014-02-23 14:19:12 +02004605 seg->flags_pd = cpu_to_be32(MLX5_MKEY_REMOTE_INVAL | sigerr << 26 |
Sagi Grimberge6631812014-02-23 14:19:11 +02004606 MLX5_MKEY_BSF_EN | pdn);
4607 seg->len = cpu_to_be64(length);
Artemy Kovalyov31616252017-01-02 11:37:42 +02004608 seg->xlt_oct_size = cpu_to_be32(get_xlt_octo(size));
Sagi Grimberge6631812014-02-23 14:19:11 +02004609 seg->bsfs_octo_size = cpu_to_be32(MLX5_MKEY_BSF_OCTO_SIZE);
4610}
4611
4612static void set_sig_umr_segment(struct mlx5_wqe_umr_ctrl_seg *umr,
Artemy Kovalyov31616252017-01-02 11:37:42 +02004613 u32 size)
Sagi Grimberge6631812014-02-23 14:19:11 +02004614{
4615 memset(umr, 0, sizeof(*umr));
4616
4617 umr->flags = MLX5_FLAGS_INLINE | MLX5_FLAGS_CHECK_FREE;
Artemy Kovalyov31616252017-01-02 11:37:42 +02004618 umr->xlt_octowords = cpu_to_be16(get_xlt_octo(size));
Sagi Grimberge6631812014-02-23 14:19:11 +02004619 umr->bsf_octowords = cpu_to_be16(MLX5_MKEY_BSF_OCTO_SIZE);
4620 umr->mkey_mask = sig_mkey_mask();
4621}
4622
4623
Bart Van Asschef696bf62018-07-18 09:25:14 -07004624static int set_sig_umr_wr(const struct ib_send_wr *send_wr,
Guy Levi34f4c952018-11-26 08:15:50 +02004625 struct mlx5_ib_qp *qp, void **seg, int *size,
4626 void **cur_edge)
Sagi Grimberge6631812014-02-23 14:19:11 +02004627{
Bart Van Asschef696bf62018-07-18 09:25:14 -07004628 const struct ib_sig_handover_wr *wr = sig_handover_wr(send_wr);
Christoph Hellwige622f2f2015-10-08 09:16:33 +01004629 struct mlx5_ib_mr *sig_mr = to_mmr(wr->sig_mr);
Sagi Grimberge6631812014-02-23 14:19:11 +02004630 u32 pdn = get_pd(qp)->pdn;
Artemy Kovalyov31616252017-01-02 11:37:42 +02004631 u32 xlt_size;
Sagi Grimberge6631812014-02-23 14:19:11 +02004632 int region_len, ret;
4633
Christoph Hellwige622f2f2015-10-08 09:16:33 +01004634 if (unlikely(wr->wr.num_sge != 1) ||
4635 unlikely(wr->access_flags & IB_ACCESS_REMOTE_ATOMIC) ||
Sagi Grimbergd5436ba2014-02-23 14:19:12 +02004636 unlikely(!sig_mr->sig) || unlikely(!qp->signature_en) ||
4637 unlikely(!sig_mr->sig->sig_status_checked))
Sagi Grimberge6631812014-02-23 14:19:11 +02004638 return -EINVAL;
4639
4640 /* length of the protected region, data + protection */
Christoph Hellwige622f2f2015-10-08 09:16:33 +01004641 region_len = wr->wr.sg_list->length;
4642 if (wr->prot &&
4643 (wr->prot->lkey != wr->wr.sg_list->lkey ||
4644 wr->prot->addr != wr->wr.sg_list->addr ||
4645 wr->prot->length != wr->wr.sg_list->length))
4646 region_len += wr->prot->length;
Sagi Grimberge6631812014-02-23 14:19:11 +02004647
4648 /**
4649 * KLM octoword size - if protection was provided
4650 * then we use strided block format (3 octowords),
4651 * else we use single KLM (1 octoword)
4652 **/
Artemy Kovalyov31616252017-01-02 11:37:42 +02004653 xlt_size = wr->prot ? 0x30 : sizeof(struct mlx5_klm);
Sagi Grimberge6631812014-02-23 14:19:11 +02004654
Artemy Kovalyov31616252017-01-02 11:37:42 +02004655 set_sig_umr_segment(*seg, xlt_size);
Sagi Grimberge6631812014-02-23 14:19:11 +02004656 *seg += sizeof(struct mlx5_wqe_umr_ctrl_seg);
4657 *size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16;
Guy Levi34f4c952018-11-26 08:15:50 +02004658 handle_post_send_edge(&qp->sq, seg, *size, cur_edge);
Sagi Grimberge6631812014-02-23 14:19:11 +02004659
Artemy Kovalyov31616252017-01-02 11:37:42 +02004660 set_sig_mkey_segment(*seg, wr, xlt_size, region_len, pdn);
Sagi Grimberge6631812014-02-23 14:19:11 +02004661 *seg += sizeof(struct mlx5_mkey_seg);
4662 *size += sizeof(struct mlx5_mkey_seg) / 16;
Guy Levi34f4c952018-11-26 08:15:50 +02004663 handle_post_send_edge(&qp->sq, seg, *size, cur_edge);
Sagi Grimberge6631812014-02-23 14:19:11 +02004664
Guy Levi34f4c952018-11-26 08:15:50 +02004665 ret = set_sig_data_segment(wr, qp, seg, size, cur_edge);
Sagi Grimberge6631812014-02-23 14:19:11 +02004666 if (ret)
4667 return ret;
4668
Sagi Grimbergd5436ba2014-02-23 14:19:12 +02004669 sig_mr->sig->sig_status_checked = false;
Sagi Grimberge6631812014-02-23 14:19:11 +02004670 return 0;
4671}
4672
4673static int set_psv_wr(struct ib_sig_domain *domain,
4674 u32 psv_idx, void **seg, int *size)
4675{
4676 struct mlx5_seg_set_psv *psv_seg = *seg;
4677
4678 memset(psv_seg, 0, sizeof(*psv_seg));
4679 psv_seg->psv_num = cpu_to_be32(psv_idx);
4680 switch (domain->sig_type) {
Sagi Grimberg78eda2b2014-08-13 19:54:35 +03004681 case IB_SIG_TYPE_NONE:
4682 break;
Sagi Grimberge6631812014-02-23 14:19:11 +02004683 case IB_SIG_TYPE_T10_DIF:
4684 psv_seg->transient_sig = cpu_to_be32(domain->sig.dif.bg << 16 |
4685 domain->sig.dif.app_tag);
4686 psv_seg->ref_tag = cpu_to_be32(domain->sig.dif.ref_tag);
Sagi Grimberge6631812014-02-23 14:19:11 +02004687 break;
Sagi Grimberge6631812014-02-23 14:19:11 +02004688 default:
Leon Romanovsky12bbf1e2017-01-18 14:10:31 +02004689 pr_err("Bad signature type (%d) is given.\n",
4690 domain->sig_type);
4691 return -EINVAL;
Sagi Grimberge6631812014-02-23 14:19:11 +02004692 }
4693
Sagi Grimberg78eda2b2014-08-13 19:54:35 +03004694 *seg += sizeof(*psv_seg);
4695 *size += sizeof(*psv_seg) / 16;
4696
Sagi Grimberge6631812014-02-23 14:19:11 +02004697 return 0;
4698}
4699
Sagi Grimberg8a187ee2015-10-13 19:11:26 +03004700static int set_reg_wr(struct mlx5_ib_qp *qp,
Bart Van Asschef696bf62018-07-18 09:25:14 -07004701 const struct ib_reg_wr *wr,
Guy Levi34f4c952018-11-26 08:15:50 +02004702 void **seg, int *size, void **cur_edge)
Sagi Grimberg8a187ee2015-10-13 19:11:26 +03004703{
4704 struct mlx5_ib_mr *mr = to_mmr(wr->mr);
4705 struct mlx5_ib_pd *pd = to_mpd(qp->ibqp.pd);
Guy Levi34f4c952018-11-26 08:15:50 +02004706 size_t mr_list_size = mr->ndescs * mr->desc_size;
Idan Burstein064e5262018-05-02 13:16:39 +03004707 bool umr_inline = mr_list_size <= MLX5_IB_SQ_UMR_INLINE_THRESHOLD;
Sagi Grimberg8a187ee2015-10-13 19:11:26 +03004708
4709 if (unlikely(wr->wr.send_flags & IB_SEND_INLINE)) {
4710 mlx5_ib_warn(to_mdev(qp->ibqp.device),
4711 "Invalid IB_SEND_INLINE send flag\n");
4712 return -EINVAL;
4713 }
4714
Idan Burstein064e5262018-05-02 13:16:39 +03004715 set_reg_umr_seg(*seg, mr, umr_inline);
Sagi Grimberg8a187ee2015-10-13 19:11:26 +03004716 *seg += sizeof(struct mlx5_wqe_umr_ctrl_seg);
4717 *size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16;
Guy Levi34f4c952018-11-26 08:15:50 +02004718 handle_post_send_edge(&qp->sq, seg, *size, cur_edge);
Sagi Grimberg8a187ee2015-10-13 19:11:26 +03004719
4720 set_reg_mkey_seg(*seg, mr, wr->key, wr->access);
4721 *seg += sizeof(struct mlx5_mkey_seg);
4722 *size += sizeof(struct mlx5_mkey_seg) / 16;
Guy Levi34f4c952018-11-26 08:15:50 +02004723 handle_post_send_edge(&qp->sq, seg, *size, cur_edge);
Sagi Grimberg8a187ee2015-10-13 19:11:26 +03004724
Idan Burstein064e5262018-05-02 13:16:39 +03004725 if (umr_inline) {
Guy Levi34f4c952018-11-26 08:15:50 +02004726 memcpy_send_wqe(&qp->sq, cur_edge, seg, size, mr->descs,
4727 mr_list_size);
4728 *size = ALIGN(*size, MLX5_SEND_WQE_BB >> 4);
Idan Burstein064e5262018-05-02 13:16:39 +03004729 } else {
4730 set_reg_data_seg(*seg, mr, pd);
4731 *seg += sizeof(struct mlx5_wqe_data_seg);
4732 *size += (sizeof(struct mlx5_wqe_data_seg) / 16);
4733 }
Sagi Grimberg8a187ee2015-10-13 19:11:26 +03004734 return 0;
4735}
4736
Guy Levi34f4c952018-11-26 08:15:50 +02004737static void set_linv_wr(struct mlx5_ib_qp *qp, void **seg, int *size,
4738 void **cur_edge)
Eli Cohene126ba92013-07-07 17:25:49 +03004739{
Sagi Grimbergdd01e662015-10-13 19:11:42 +03004740 set_linv_umr_seg(*seg);
Eli Cohene126ba92013-07-07 17:25:49 +03004741 *seg += sizeof(struct mlx5_wqe_umr_ctrl_seg);
4742 *size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16;
Guy Levi34f4c952018-11-26 08:15:50 +02004743 handle_post_send_edge(&qp->sq, seg, *size, cur_edge);
Sagi Grimbergdd01e662015-10-13 19:11:42 +03004744 set_linv_mkey_seg(*seg);
Eli Cohene126ba92013-07-07 17:25:49 +03004745 *seg += sizeof(struct mlx5_mkey_seg);
4746 *size += sizeof(struct mlx5_mkey_seg) / 16;
Guy Levi34f4c952018-11-26 08:15:50 +02004747 handle_post_send_edge(&qp->sq, seg, *size, cur_edge);
Eli Cohene126ba92013-07-07 17:25:49 +03004748}
4749
Guy Levi34f4c952018-11-26 08:15:50 +02004750static void dump_wqe(struct mlx5_ib_qp *qp, u32 idx, int size_16)
Eli Cohene126ba92013-07-07 17:25:49 +03004751{
4752 __be32 *p = NULL;
Eli Cohene126ba92013-07-07 17:25:49 +03004753 int i, j;
4754
Guy Levi34f4c952018-11-26 08:15:50 +02004755 pr_debug("dump WQE index %u:\n", idx);
Eli Cohene126ba92013-07-07 17:25:49 +03004756 for (i = 0, j = 0; i < size_16 * 4; i += 4, j += 4) {
4757 if ((i & 0xf) == 0) {
Artemy Kovalyov1e5887b2019-03-19 11:24:37 +02004758 p = mlx5_frag_buf_get_wqe(&qp->sq.fbc, idx);
Guy Levi34f4c952018-11-26 08:15:50 +02004759 pr_debug("WQBB at %p:\n", (void *)p);
Eli Cohene126ba92013-07-07 17:25:49 +03004760 j = 0;
Artemy Kovalyov1e5887b2019-03-19 11:24:37 +02004761 idx = (idx + 1) & (qp->sq.wqe_cnt - 1);
Eli Cohene126ba92013-07-07 17:25:49 +03004762 }
4763 pr_debug("%08x %08x %08x %08x\n", be32_to_cpu(p[j]),
4764 be32_to_cpu(p[j + 1]), be32_to_cpu(p[j + 2]),
4765 be32_to_cpu(p[j + 3]));
4766 }
4767}
4768
Bart Van Assche7bb1faf2018-07-18 09:25:15 -07004769static int __begin_wqe(struct mlx5_ib_qp *qp, void **seg,
Guy Levi34f4c952018-11-26 08:15:50 +02004770 struct mlx5_wqe_ctrl_seg **ctrl,
4771 const struct ib_send_wr *wr, unsigned int *idx,
4772 int *size, void **cur_edge, int nreq,
4773 bool send_signaled, bool solicited)
Sagi Grimberg6e5eadace2014-02-23 14:19:08 +02004774{
Leon Romanovskyb2a232d2016-08-28 10:58:35 +03004775 if (unlikely(mlx5_wq_overflow(&qp->sq, nreq, qp->ibqp.send_cq)))
4776 return -ENOMEM;
Sagi Grimberg6e5eadace2014-02-23 14:19:08 +02004777
4778 *idx = qp->sq.cur_post & (qp->sq.wqe_cnt - 1);
Guy Levi34f4c952018-11-26 08:15:50 +02004779 *seg = mlx5_frag_buf_get_wqe(&qp->sq.fbc, *idx);
Sagi Grimberg6e5eadace2014-02-23 14:19:08 +02004780 *ctrl = *seg;
4781 *(uint32_t *)(*seg + 8) = 0;
4782 (*ctrl)->imm = send_ieth(wr);
4783 (*ctrl)->fm_ce_se = qp->sq_signal_bits |
Bart Van Assche7bb1faf2018-07-18 09:25:15 -07004784 (send_signaled ? MLX5_WQE_CTRL_CQ_UPDATE : 0) |
4785 (solicited ? MLX5_WQE_CTRL_SOLICITED : 0);
Sagi Grimberg6e5eadace2014-02-23 14:19:08 +02004786
4787 *seg += sizeof(**ctrl);
4788 *size = sizeof(**ctrl) / 16;
Guy Levi34f4c952018-11-26 08:15:50 +02004789 *cur_edge = qp->sq.cur_edge;
Sagi Grimberg6e5eadace2014-02-23 14:19:08 +02004790
Leon Romanovskyb2a232d2016-08-28 10:58:35 +03004791 return 0;
Sagi Grimberg6e5eadace2014-02-23 14:19:08 +02004792}
4793
Bart Van Assche7bb1faf2018-07-18 09:25:15 -07004794static int begin_wqe(struct mlx5_ib_qp *qp, void **seg,
4795 struct mlx5_wqe_ctrl_seg **ctrl,
4796 const struct ib_send_wr *wr, unsigned *idx,
Guy Levi34f4c952018-11-26 08:15:50 +02004797 int *size, void **cur_edge, int nreq)
Bart Van Assche7bb1faf2018-07-18 09:25:15 -07004798{
Guy Levi34f4c952018-11-26 08:15:50 +02004799 return __begin_wqe(qp, seg, ctrl, wr, idx, size, cur_edge, nreq,
Bart Van Assche7bb1faf2018-07-18 09:25:15 -07004800 wr->send_flags & IB_SEND_SIGNALED,
4801 wr->send_flags & IB_SEND_SOLICITED);
4802}
4803
Sagi Grimberg6e5eadace2014-02-23 14:19:08 +02004804static void finish_wqe(struct mlx5_ib_qp *qp,
4805 struct mlx5_wqe_ctrl_seg *ctrl,
Guy Levi34f4c952018-11-26 08:15:50 +02004806 void *seg, u8 size, void *cur_edge,
4807 unsigned int idx, u64 wr_id, int nreq, u8 fence,
4808 u32 mlx5_opcode)
Sagi Grimberg6e5eadace2014-02-23 14:19:08 +02004809{
4810 u8 opmod = 0;
4811
4812 ctrl->opmod_idx_opcode = cpu_to_be32(((u32)(qp->sq.cur_post) << 8) |
4813 mlx5_opcode | ((u32)opmod << 24));
majd@mellanox.com19098df2016-01-14 19:13:03 +02004814 ctrl->qpn_ds = cpu_to_be32(size | (qp->trans_qp.base.mqp.qpn << 8));
Sagi Grimberg6e5eadace2014-02-23 14:19:08 +02004815 ctrl->fm_ce_se |= fence;
Sagi Grimberg6e5eadace2014-02-23 14:19:08 +02004816 if (unlikely(qp->wq_sig))
4817 ctrl->signature = wq_sig(ctrl);
4818
4819 qp->sq.wrid[idx] = wr_id;
4820 qp->sq.w_list[idx].opcode = mlx5_opcode;
4821 qp->sq.wqe_head[idx] = qp->sq.head + nreq;
4822 qp->sq.cur_post += DIV_ROUND_UP(size * 16, MLX5_SEND_WQE_BB);
4823 qp->sq.w_list[idx].next = qp->sq.cur_post;
Guy Levi34f4c952018-11-26 08:15:50 +02004824
4825 /* We save the edge which was possibly updated during the WQE
4826 * construction, into SQ's cache.
4827 */
4828 seg = PTR_ALIGN(seg, MLX5_SEND_WQE_BB);
4829 qp->sq.cur_edge = (unlikely(seg == cur_edge)) ?
4830 get_sq_edge(&qp->sq, qp->sq.cur_post &
4831 (qp->sq.wqe_cnt - 1)) :
4832 cur_edge;
Sagi Grimberg6e5eadace2014-02-23 14:19:08 +02004833}
4834
Bart Van Assched34ac5c2018-07-18 09:25:32 -07004835static int _mlx5_ib_post_send(struct ib_qp *ibqp, const struct ib_send_wr *wr,
4836 const struct ib_send_wr **bad_wr, bool drain)
Eli Cohene126ba92013-07-07 17:25:49 +03004837{
4838 struct mlx5_wqe_ctrl_seg *ctrl = NULL; /* compiler warning */
4839 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
Maor Gottlieb89ea94a72016-06-17 15:01:38 +03004840 struct mlx5_core_dev *mdev = dev->mdev;
Haggai Erand16e91d2016-02-29 15:45:05 +02004841 struct mlx5_ib_qp *qp;
Sagi Grimberge6631812014-02-23 14:19:11 +02004842 struct mlx5_ib_mr *mr;
Eli Cohene126ba92013-07-07 17:25:49 +03004843 struct mlx5_wqe_xrc_seg *xrc;
Haggai Erand16e91d2016-02-29 15:45:05 +02004844 struct mlx5_bf *bf;
Guy Levi34f4c952018-11-26 08:15:50 +02004845 void *cur_edge;
Eli Cohene126ba92013-07-07 17:25:49 +03004846 int uninitialized_var(size);
Eli Cohene126ba92013-07-07 17:25:49 +03004847 unsigned long flags;
Eli Cohene126ba92013-07-07 17:25:49 +03004848 unsigned idx;
4849 int err = 0;
Eli Cohene126ba92013-07-07 17:25:49 +03004850 int num_sge;
4851 void *seg;
4852 int nreq;
4853 int i;
4854 u8 next_fence = 0;
Eli Cohene126ba92013-07-07 17:25:49 +03004855 u8 fence;
4856
Parav Pandit6c755202018-08-28 14:45:29 +03004857 if (unlikely(mdev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR &&
4858 !drain)) {
4859 *bad_wr = wr;
4860 return -EIO;
4861 }
4862
Haggai Erand16e91d2016-02-29 15:45:05 +02004863 if (unlikely(ibqp->qp_type == IB_QPT_GSI))
4864 return mlx5_ib_gsi_post_send(ibqp, wr, bad_wr);
4865
4866 qp = to_mqp(ibqp);
Eli Cohen5fe9dec2017-01-03 23:55:25 +02004867 bf = &qp->bf;
Haggai Erand16e91d2016-02-29 15:45:05 +02004868
Eli Cohene126ba92013-07-07 17:25:49 +03004869 spin_lock_irqsave(&qp->sq.lock, flags);
4870
4871 for (nreq = 0; wr; nreq++, wr = wr->next) {
Fabian Fredericka8f731e2014-08-12 19:20:08 -04004872 if (unlikely(wr->opcode >= ARRAY_SIZE(mlx5_ib_opcode))) {
Eli Cohene126ba92013-07-07 17:25:49 +03004873 mlx5_ib_warn(dev, "\n");
4874 err = -EINVAL;
4875 *bad_wr = wr;
4876 goto out;
4877 }
4878
Eli Cohene126ba92013-07-07 17:25:49 +03004879 num_sge = wr->num_sge;
4880 if (unlikely(num_sge > qp->sq.max_gs)) {
4881 mlx5_ib_warn(dev, "\n");
Chuck Lever24be4092016-08-28 10:58:34 +03004882 err = -EINVAL;
Eli Cohene126ba92013-07-07 17:25:49 +03004883 *bad_wr = wr;
4884 goto out;
4885 }
4886
Guy Levi34f4c952018-11-26 08:15:50 +02004887 err = begin_wqe(qp, &seg, &ctrl, wr, &idx, &size, &cur_edge,
4888 nreq);
Sagi Grimberg6e5eadace2014-02-23 14:19:08 +02004889 if (err) {
4890 mlx5_ib_warn(dev, "\n");
4891 err = -ENOMEM;
4892 *bad_wr = wr;
4893 goto out;
4894 }
Eli Cohene126ba92013-07-07 17:25:49 +03004895
Majd Dibbiny074fca32018-11-05 08:07:37 +02004896 if (wr->opcode == IB_WR_REG_MR) {
Max Gurtovoy6e8484c2017-05-28 10:53:11 +03004897 fence = dev->umr_fence;
4898 next_fence = MLX5_FENCE_MODE_INITIATOR_SMALL;
Majd Dibbiny074fca32018-11-05 08:07:37 +02004899 } else {
4900 if (wr->send_flags & IB_SEND_FENCE) {
4901 if (qp->next_fence)
4902 fence = MLX5_FENCE_MODE_SMALL_AND_FENCE;
4903 else
4904 fence = MLX5_FENCE_MODE_FENCE;
4905 } else {
4906 fence = qp->next_fence;
4907 }
Max Gurtovoy6e8484c2017-05-28 10:53:11 +03004908 }
4909
Eli Cohene126ba92013-07-07 17:25:49 +03004910 switch (ibqp->qp_type) {
4911 case IB_QPT_XRC_INI:
4912 xrc = seg;
Eli Cohene126ba92013-07-07 17:25:49 +03004913 seg += sizeof(*xrc);
4914 size += sizeof(*xrc) / 16;
4915 /* fall through */
4916 case IB_QPT_RC:
4917 switch (wr->opcode) {
4918 case IB_WR_RDMA_READ:
4919 case IB_WR_RDMA_WRITE:
4920 case IB_WR_RDMA_WRITE_WITH_IMM:
Christoph Hellwige622f2f2015-10-08 09:16:33 +01004921 set_raddr_seg(seg, rdma_wr(wr)->remote_addr,
4922 rdma_wr(wr)->rkey);
Jack Morgensteinf241e742014-07-28 23:30:23 +03004923 seg += sizeof(struct mlx5_wqe_raddr_seg);
Eli Cohene126ba92013-07-07 17:25:49 +03004924 size += sizeof(struct mlx5_wqe_raddr_seg) / 16;
4925 break;
4926
4927 case IB_WR_ATOMIC_CMP_AND_SWP:
4928 case IB_WR_ATOMIC_FETCH_AND_ADD:
Eli Cohene126ba92013-07-07 17:25:49 +03004929 case IB_WR_MASKED_ATOMIC_CMP_AND_SWP:
Eli Cohen81bea282013-09-11 16:35:30 +03004930 mlx5_ib_warn(dev, "Atomic operations are not supported yet\n");
4931 err = -ENOSYS;
4932 *bad_wr = wr;
4933 goto out;
Eli Cohene126ba92013-07-07 17:25:49 +03004934
4935 case IB_WR_LOCAL_INV:
Eli Cohene126ba92013-07-07 17:25:49 +03004936 qp->sq.wr_data[idx] = IB_WR_LOCAL_INV;
4937 ctrl->imm = cpu_to_be32(wr->ex.invalidate_rkey);
Guy Levi34f4c952018-11-26 08:15:50 +02004938 set_linv_wr(qp, &seg, &size, &cur_edge);
Eli Cohene126ba92013-07-07 17:25:49 +03004939 num_sge = 0;
4940 break;
4941
Sagi Grimberg8a187ee2015-10-13 19:11:26 +03004942 case IB_WR_REG_MR:
Sagi Grimberg8a187ee2015-10-13 19:11:26 +03004943 qp->sq.wr_data[idx] = IB_WR_REG_MR;
4944 ctrl->imm = cpu_to_be32(reg_wr(wr)->key);
Guy Levi34f4c952018-11-26 08:15:50 +02004945 err = set_reg_wr(qp, reg_wr(wr), &seg, &size,
4946 &cur_edge);
Sagi Grimberg8a187ee2015-10-13 19:11:26 +03004947 if (err) {
4948 *bad_wr = wr;
4949 goto out;
4950 }
4951 num_sge = 0;
4952 break;
4953
Sagi Grimberge6631812014-02-23 14:19:11 +02004954 case IB_WR_REG_SIG_MR:
4955 qp->sq.wr_data[idx] = IB_WR_REG_SIG_MR;
Christoph Hellwige622f2f2015-10-08 09:16:33 +01004956 mr = to_mmr(sig_handover_wr(wr)->sig_mr);
Sagi Grimberge6631812014-02-23 14:19:11 +02004957
4958 ctrl->imm = cpu_to_be32(mr->ibmr.rkey);
Guy Levi34f4c952018-11-26 08:15:50 +02004959 err = set_sig_umr_wr(wr, qp, &seg, &size,
4960 &cur_edge);
Sagi Grimberge6631812014-02-23 14:19:11 +02004961 if (err) {
4962 mlx5_ib_warn(dev, "\n");
4963 *bad_wr = wr;
4964 goto out;
4965 }
4966
Guy Levi34f4c952018-11-26 08:15:50 +02004967 finish_wqe(qp, ctrl, seg, size, cur_edge, idx,
4968 wr->wr_id, nreq, fence,
4969 MLX5_OPCODE_UMR);
Sagi Grimberge6631812014-02-23 14:19:11 +02004970 /*
4971 * SET_PSV WQEs are not signaled and solicited
4972 * on error
4973 */
Bart Van Assche7bb1faf2018-07-18 09:25:15 -07004974 err = __begin_wqe(qp, &seg, &ctrl, wr, &idx,
Guy Levi34f4c952018-11-26 08:15:50 +02004975 &size, &cur_edge, nreq, false,
4976 true);
Sagi Grimberge6631812014-02-23 14:19:11 +02004977 if (err) {
4978 mlx5_ib_warn(dev, "\n");
4979 err = -ENOMEM;
4980 *bad_wr = wr;
4981 goto out;
4982 }
4983
Christoph Hellwige622f2f2015-10-08 09:16:33 +01004984 err = set_psv_wr(&sig_handover_wr(wr)->sig_attrs->mem,
Sagi Grimberge6631812014-02-23 14:19:11 +02004985 mr->sig->psv_memory.psv_idx, &seg,
4986 &size);
4987 if (err) {
4988 mlx5_ib_warn(dev, "\n");
4989 *bad_wr = wr;
4990 goto out;
4991 }
4992
Guy Levi34f4c952018-11-26 08:15:50 +02004993 finish_wqe(qp, ctrl, seg, size, cur_edge, idx,
4994 wr->wr_id, nreq, fence,
4995 MLX5_OPCODE_SET_PSV);
Bart Van Assche7bb1faf2018-07-18 09:25:15 -07004996 err = __begin_wqe(qp, &seg, &ctrl, wr, &idx,
Guy Levi34f4c952018-11-26 08:15:50 +02004997 &size, &cur_edge, nreq, false,
4998 true);
Sagi Grimberge6631812014-02-23 14:19:11 +02004999 if (err) {
5000 mlx5_ib_warn(dev, "\n");
5001 err = -ENOMEM;
5002 *bad_wr = wr;
5003 goto out;
5004 }
5005
Christoph Hellwige622f2f2015-10-08 09:16:33 +01005006 err = set_psv_wr(&sig_handover_wr(wr)->sig_attrs->wire,
Sagi Grimberge6631812014-02-23 14:19:11 +02005007 mr->sig->psv_wire.psv_idx, &seg,
5008 &size);
5009 if (err) {
5010 mlx5_ib_warn(dev, "\n");
5011 *bad_wr = wr;
5012 goto out;
5013 }
5014
Guy Levi34f4c952018-11-26 08:15:50 +02005015 finish_wqe(qp, ctrl, seg, size, cur_edge, idx,
5016 wr->wr_id, nreq, fence,
5017 MLX5_OPCODE_SET_PSV);
Max Gurtovoy6e8484c2017-05-28 10:53:11 +03005018 qp->next_fence = MLX5_FENCE_MODE_INITIATOR_SMALL;
Sagi Grimberge6631812014-02-23 14:19:11 +02005019 num_sge = 0;
5020 goto skip_psv;
5021
Eli Cohene126ba92013-07-07 17:25:49 +03005022 default:
5023 break;
5024 }
5025 break;
5026
5027 case IB_QPT_UC:
5028 switch (wr->opcode) {
5029 case IB_WR_RDMA_WRITE:
5030 case IB_WR_RDMA_WRITE_WITH_IMM:
Christoph Hellwige622f2f2015-10-08 09:16:33 +01005031 set_raddr_seg(seg, rdma_wr(wr)->remote_addr,
5032 rdma_wr(wr)->rkey);
Eli Cohene126ba92013-07-07 17:25:49 +03005033 seg += sizeof(struct mlx5_wqe_raddr_seg);
5034 size += sizeof(struct mlx5_wqe_raddr_seg) / 16;
5035 break;
5036
5037 default:
5038 break;
5039 }
5040 break;
5041
Eli Cohene126ba92013-07-07 17:25:49 +03005042 case IB_QPT_SMI:
Maor Gottlieb1e0e50b2017-01-18 14:10:34 +02005043 if (unlikely(!mdev->port_caps[qp->port - 1].has_smi)) {
5044 mlx5_ib_warn(dev, "Send SMP MADs is not allowed\n");
5045 err = -EPERM;
5046 *bad_wr = wr;
5047 goto out;
5048 }
Bart Van Asschef6b1ee32017-10-11 10:49:07 -07005049 /* fall through */
Haggai Erand16e91d2016-02-29 15:45:05 +02005050 case MLX5_IB_QPT_HW_GSI:
Eli Cohene126ba92013-07-07 17:25:49 +03005051 set_datagram_seg(seg, wr);
Jack Morgensteinf241e742014-07-28 23:30:23 +03005052 seg += sizeof(struct mlx5_wqe_datagram_seg);
Eli Cohene126ba92013-07-07 17:25:49 +03005053 size += sizeof(struct mlx5_wqe_datagram_seg) / 16;
Guy Levi34f4c952018-11-26 08:15:50 +02005054 handle_post_send_edge(&qp->sq, &seg, size, &cur_edge);
5055
Eli Cohene126ba92013-07-07 17:25:49 +03005056 break;
Erez Shitritf0313962016-02-21 16:27:17 +02005057 case IB_QPT_UD:
5058 set_datagram_seg(seg, wr);
5059 seg += sizeof(struct mlx5_wqe_datagram_seg);
5060 size += sizeof(struct mlx5_wqe_datagram_seg) / 16;
Guy Levi34f4c952018-11-26 08:15:50 +02005061 handle_post_send_edge(&qp->sq, &seg, size, &cur_edge);
Erez Shitritf0313962016-02-21 16:27:17 +02005062
5063 /* handle qp that supports ud offload */
5064 if (qp->flags & IB_QP_CREATE_IPOIB_UD_LSO) {
5065 struct mlx5_wqe_eth_pad *pad;
5066
5067 pad = seg;
5068 memset(pad, 0, sizeof(struct mlx5_wqe_eth_pad));
5069 seg += sizeof(struct mlx5_wqe_eth_pad);
5070 size += sizeof(struct mlx5_wqe_eth_pad) / 16;
Guy Levi34f4c952018-11-26 08:15:50 +02005071 set_eth_seg(wr, qp, &seg, &size, &cur_edge);
5072 handle_post_send_edge(&qp->sq, &seg, size,
5073 &cur_edge);
Erez Shitritf0313962016-02-21 16:27:17 +02005074 }
5075 break;
Eli Cohene126ba92013-07-07 17:25:49 +03005076 case MLX5_IB_QPT_REG_UMR:
5077 if (wr->opcode != MLX5_IB_WR_UMR) {
5078 err = -EINVAL;
5079 mlx5_ib_warn(dev, "bad opcode\n");
5080 goto out;
5081 }
5082 qp->sq.wr_data[idx] = MLX5_IB_WR_UMR;
Christoph Hellwige622f2f2015-10-08 09:16:33 +01005083 ctrl->imm = cpu_to_be32(umr_wr(wr)->mkey);
Majd Dibbinyc8d75a92018-03-22 15:34:04 +02005084 err = set_reg_umr_segment(dev, seg, wr, !!(MLX5_CAP_GEN(mdev, atomic)));
5085 if (unlikely(err))
5086 goto out;
Eli Cohene126ba92013-07-07 17:25:49 +03005087 seg += sizeof(struct mlx5_wqe_umr_ctrl_seg);
5088 size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16;
Guy Levi34f4c952018-11-26 08:15:50 +02005089 handle_post_send_edge(&qp->sq, &seg, size, &cur_edge);
Eli Cohene126ba92013-07-07 17:25:49 +03005090 set_reg_mkey_segment(seg, wr);
5091 seg += sizeof(struct mlx5_mkey_seg);
5092 size += sizeof(struct mlx5_mkey_seg) / 16;
Guy Levi34f4c952018-11-26 08:15:50 +02005093 handle_post_send_edge(&qp->sq, &seg, size, &cur_edge);
Eli Cohene126ba92013-07-07 17:25:49 +03005094 break;
5095
5096 default:
5097 break;
5098 }
5099
5100 if (wr->send_flags & IB_SEND_INLINE && num_sge) {
Guy Levi34f4c952018-11-26 08:15:50 +02005101 err = set_data_inl_seg(qp, wr, &seg, &size, &cur_edge);
Eli Cohene126ba92013-07-07 17:25:49 +03005102 if (unlikely(err)) {
5103 mlx5_ib_warn(dev, "\n");
5104 *bad_wr = wr;
5105 goto out;
5106 }
Eli Cohene126ba92013-07-07 17:25:49 +03005107 } else {
Eli Cohene126ba92013-07-07 17:25:49 +03005108 for (i = 0; i < num_sge; i++) {
Guy Levi34f4c952018-11-26 08:15:50 +02005109 handle_post_send_edge(&qp->sq, &seg, size,
5110 &cur_edge);
Eli Cohene126ba92013-07-07 17:25:49 +03005111 if (likely(wr->sg_list[i].length)) {
Guy Levi34f4c952018-11-26 08:15:50 +02005112 set_data_ptr_seg
5113 ((struct mlx5_wqe_data_seg *)seg,
5114 wr->sg_list + i);
Eli Cohene126ba92013-07-07 17:25:49 +03005115 size += sizeof(struct mlx5_wqe_data_seg) / 16;
Guy Levi34f4c952018-11-26 08:15:50 +02005116 seg += sizeof(struct mlx5_wqe_data_seg);
Eli Cohene126ba92013-07-07 17:25:49 +03005117 }
5118 }
5119 }
5120
Max Gurtovoy6e8484c2017-05-28 10:53:11 +03005121 qp->next_fence = next_fence;
Guy Levi34f4c952018-11-26 08:15:50 +02005122 finish_wqe(qp, ctrl, seg, size, cur_edge, idx, wr->wr_id, nreq,
5123 fence, mlx5_ib_opcode[wr->opcode]);
Sagi Grimberge6631812014-02-23 14:19:11 +02005124skip_psv:
Eli Cohene126ba92013-07-07 17:25:49 +03005125 if (0)
5126 dump_wqe(qp, idx, size);
5127 }
5128
5129out:
5130 if (likely(nreq)) {
5131 qp->sq.head += nreq;
5132
5133 /* Make sure that descriptors are written before
5134 * updating doorbell record and ringing the doorbell
5135 */
5136 wmb();
5137
5138 qp->db.db[MLX5_SND_DBR] = cpu_to_be32(qp->sq.cur_post);
5139
Eli Cohenada388f2014-01-14 17:45:16 +02005140 /* Make sure doorbell record is visible to the HCA before
5141 * we hit doorbell */
5142 wmb();
5143
Eli Cohen5fe9dec2017-01-03 23:55:25 +02005144 /* currently we support only regular doorbells */
Maxim Mikityanskiybbf29f62019-03-29 15:37:52 -07005145 mlx5_write64((__be32 *)ctrl, bf->bfreg->map + bf->offset);
Eli Cohen5fe9dec2017-01-03 23:55:25 +02005146 /* Make sure doorbells don't leak out of SQ spinlock
5147 * and reach the HCA out of order.
5148 */
5149 mmiowb();
Eli Cohene126ba92013-07-07 17:25:49 +03005150 bf->offset ^= bf->buf_size;
Eli Cohene126ba92013-07-07 17:25:49 +03005151 }
5152
5153 spin_unlock_irqrestore(&qp->sq.lock, flags);
5154
5155 return err;
5156}
5157
Bart Van Assched34ac5c2018-07-18 09:25:32 -07005158int mlx5_ib_post_send(struct ib_qp *ibqp, const struct ib_send_wr *wr,
5159 const struct ib_send_wr **bad_wr)
Yishai Hadasd0e84c02018-06-19 10:43:55 +03005160{
5161 return _mlx5_ib_post_send(ibqp, wr, bad_wr, false);
5162}
5163
Eli Cohene126ba92013-07-07 17:25:49 +03005164static void set_sig_seg(struct mlx5_rwqe_sig *sig, int size)
5165{
5166 sig->signature = calc_sig(sig, size);
5167}
5168
Bart Van Assched34ac5c2018-07-18 09:25:32 -07005169static int _mlx5_ib_post_recv(struct ib_qp *ibqp, const struct ib_recv_wr *wr,
5170 const struct ib_recv_wr **bad_wr, bool drain)
Eli Cohene126ba92013-07-07 17:25:49 +03005171{
5172 struct mlx5_ib_qp *qp = to_mqp(ibqp);
5173 struct mlx5_wqe_data_seg *scat;
5174 struct mlx5_rwqe_sig *sig;
Maor Gottlieb89ea94a72016-06-17 15:01:38 +03005175 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
5176 struct mlx5_core_dev *mdev = dev->mdev;
Eli Cohene126ba92013-07-07 17:25:49 +03005177 unsigned long flags;
5178 int err = 0;
5179 int nreq;
5180 int ind;
5181 int i;
5182
Parav Pandit6c755202018-08-28 14:45:29 +03005183 if (unlikely(mdev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR &&
5184 !drain)) {
5185 *bad_wr = wr;
5186 return -EIO;
5187 }
5188
Haggai Erand16e91d2016-02-29 15:45:05 +02005189 if (unlikely(ibqp->qp_type == IB_QPT_GSI))
5190 return mlx5_ib_gsi_post_recv(ibqp, wr, bad_wr);
5191
Eli Cohene126ba92013-07-07 17:25:49 +03005192 spin_lock_irqsave(&qp->rq.lock, flags);
5193
5194 ind = qp->rq.head & (qp->rq.wqe_cnt - 1);
5195
5196 for (nreq = 0; wr; nreq++, wr = wr->next) {
5197 if (mlx5_wq_overflow(&qp->rq, nreq, qp->ibqp.recv_cq)) {
5198 err = -ENOMEM;
5199 *bad_wr = wr;
5200 goto out;
5201 }
5202
5203 if (unlikely(wr->num_sge > qp->rq.max_gs)) {
5204 err = -EINVAL;
5205 *bad_wr = wr;
5206 goto out;
5207 }
5208
Guy Levi34f4c952018-11-26 08:15:50 +02005209 scat = mlx5_frag_buf_get_wqe(&qp->rq.fbc, ind);
Eli Cohene126ba92013-07-07 17:25:49 +03005210 if (qp->wq_sig)
5211 scat++;
5212
5213 for (i = 0; i < wr->num_sge; i++)
5214 set_data_ptr_seg(scat + i, wr->sg_list + i);
5215
5216 if (i < qp->rq.max_gs) {
5217 scat[i].byte_count = 0;
5218 scat[i].lkey = cpu_to_be32(MLX5_INVALID_LKEY);
5219 scat[i].addr = 0;
5220 }
5221
5222 if (qp->wq_sig) {
5223 sig = (struct mlx5_rwqe_sig *)scat;
5224 set_sig_seg(sig, (qp->rq.max_gs + 1) << 2);
5225 }
5226
5227 qp->rq.wrid[ind] = wr->wr_id;
5228
5229 ind = (ind + 1) & (qp->rq.wqe_cnt - 1);
5230 }
5231
5232out:
5233 if (likely(nreq)) {
5234 qp->rq.head += nreq;
5235
5236 /* Make sure that descriptors are written before
5237 * doorbell record.
5238 */
5239 wmb();
5240
5241 *qp->db.db = cpu_to_be32(qp->rq.head & 0xffff);
5242 }
5243
5244 spin_unlock_irqrestore(&qp->rq.lock, flags);
5245
5246 return err;
5247}
5248
Bart Van Assched34ac5c2018-07-18 09:25:32 -07005249int mlx5_ib_post_recv(struct ib_qp *ibqp, const struct ib_recv_wr *wr,
5250 const struct ib_recv_wr **bad_wr)
Yishai Hadasd0e84c02018-06-19 10:43:55 +03005251{
5252 return _mlx5_ib_post_recv(ibqp, wr, bad_wr, false);
5253}
5254
Eli Cohene126ba92013-07-07 17:25:49 +03005255static inline enum ib_qp_state to_ib_qp_state(enum mlx5_qp_state mlx5_state)
5256{
5257 switch (mlx5_state) {
5258 case MLX5_QP_STATE_RST: return IB_QPS_RESET;
5259 case MLX5_QP_STATE_INIT: return IB_QPS_INIT;
5260 case MLX5_QP_STATE_RTR: return IB_QPS_RTR;
5261 case MLX5_QP_STATE_RTS: return IB_QPS_RTS;
5262 case MLX5_QP_STATE_SQ_DRAINING:
5263 case MLX5_QP_STATE_SQD: return IB_QPS_SQD;
5264 case MLX5_QP_STATE_SQER: return IB_QPS_SQE;
5265 case MLX5_QP_STATE_ERR: return IB_QPS_ERR;
5266 default: return -1;
5267 }
5268}
5269
5270static inline enum ib_mig_state to_ib_mig_state(int mlx5_mig_state)
5271{
5272 switch (mlx5_mig_state) {
5273 case MLX5_QP_PM_ARMED: return IB_MIG_ARMED;
5274 case MLX5_QP_PM_REARM: return IB_MIG_REARM;
5275 case MLX5_QP_PM_MIGRATED: return IB_MIG_MIGRATED;
5276 default: return -1;
5277 }
5278}
5279
5280static int to_ib_qp_access_flags(int mlx5_flags)
5281{
5282 int ib_flags = 0;
5283
5284 if (mlx5_flags & MLX5_QP_BIT_RRE)
5285 ib_flags |= IB_ACCESS_REMOTE_READ;
5286 if (mlx5_flags & MLX5_QP_BIT_RWE)
5287 ib_flags |= IB_ACCESS_REMOTE_WRITE;
5288 if (mlx5_flags & MLX5_QP_BIT_RAE)
5289 ib_flags |= IB_ACCESS_REMOTE_ATOMIC;
5290
5291 return ib_flags;
5292}
5293
Dasaratharaman Chandramouli38349382017-04-29 14:41:24 -04005294static void to_rdma_ah_attr(struct mlx5_ib_dev *ibdev,
Dasaratharaman Chandramoulid8966fc2017-04-29 14:41:28 -04005295 struct rdma_ah_attr *ah_attr,
Dasaratharaman Chandramouli38349382017-04-29 14:41:24 -04005296 struct mlx5_qp_path *path)
Eli Cohene126ba92013-07-07 17:25:49 +03005297{
Eli Cohene126ba92013-07-07 17:25:49 +03005298
Dasaratharaman Chandramoulid8966fc2017-04-29 14:41:28 -04005299 memset(ah_attr, 0, sizeof(*ah_attr));
Eli Cohene126ba92013-07-07 17:25:49 +03005300
Jason Gunthorpee7996a92018-01-29 13:26:40 -07005301 if (!path->port || path->port > ibdev->num_ports)
Eli Cohene126ba92013-07-07 17:25:49 +03005302 return;
5303
Leon Romanovskyae59c3f2018-01-12 07:58:39 +02005304 ah_attr->type = rdma_ah_find_type(&ibdev->ib_dev, path->port);
5305
Dasaratharaman Chandramoulid8966fc2017-04-29 14:41:28 -04005306 rdma_ah_set_port_num(ah_attr, path->port);
5307 rdma_ah_set_sl(ah_attr, path->dci_cfi_prio_sl & 0xf);
Eli Cohene126ba92013-07-07 17:25:49 +03005308
Dasaratharaman Chandramoulid8966fc2017-04-29 14:41:28 -04005309 rdma_ah_set_dlid(ah_attr, be16_to_cpu(path->rlid));
5310 rdma_ah_set_path_bits(ah_attr, path->grh_mlid & 0x7f);
5311 rdma_ah_set_static_rate(ah_attr,
5312 path->static_rate ? path->static_rate - 5 : 0);
5313 if (path->grh_mlid & (1 << 7)) {
5314 u32 tc_fl = be32_to_cpu(path->tclass_flowlabel);
5315
5316 rdma_ah_set_grh(ah_attr, NULL,
5317 tc_fl & 0xfffff,
5318 path->mgid_index,
5319 path->hop_limit,
5320 (tc_fl >> 20) & 0xff);
5321 rdma_ah_set_dgid_raw(ah_attr, path->rgid);
Eli Cohene126ba92013-07-07 17:25:49 +03005322 }
5323}
5324
majd@mellanox.com6d2f89df2016-01-14 19:13:05 +02005325static int query_raw_packet_qp_sq_state(struct mlx5_ib_dev *dev,
5326 struct mlx5_ib_sq *sq,
5327 u8 *sq_state)
Eli Cohene126ba92013-07-07 17:25:49 +03005328{
majd@mellanox.com6d2f89df2016-01-14 19:13:05 +02005329 int err;
5330
Eran Ben Elisha28160772017-12-26 15:17:05 +02005331 err = mlx5_core_query_sq_state(dev->mdev, sq->base.mqp.qpn, sq_state);
majd@mellanox.com6d2f89df2016-01-14 19:13:05 +02005332 if (err)
5333 goto out;
majd@mellanox.com6d2f89df2016-01-14 19:13:05 +02005334 sq->state = *sq_state;
5335
5336out:
majd@mellanox.com6d2f89df2016-01-14 19:13:05 +02005337 return err;
5338}
5339
5340static int query_raw_packet_qp_rq_state(struct mlx5_ib_dev *dev,
5341 struct mlx5_ib_rq *rq,
5342 u8 *rq_state)
5343{
5344 void *out;
5345 void *rqc;
5346 int inlen;
5347 int err;
5348
5349 inlen = MLX5_ST_SZ_BYTES(query_rq_out);
Leon Romanovsky1b9a07e2017-05-10 21:32:18 +03005350 out = kvzalloc(inlen, GFP_KERNEL);
majd@mellanox.com6d2f89df2016-01-14 19:13:05 +02005351 if (!out)
5352 return -ENOMEM;
5353
5354 err = mlx5_core_query_rq(dev->mdev, rq->base.mqp.qpn, out);
5355 if (err)
5356 goto out;
5357
5358 rqc = MLX5_ADDR_OF(query_rq_out, out, rq_context);
5359 *rq_state = MLX5_GET(rqc, rqc, state);
5360 rq->state = *rq_state;
5361
5362out:
5363 kvfree(out);
5364 return err;
5365}
5366
5367static int sqrq_state_to_qp_state(u8 sq_state, u8 rq_state,
5368 struct mlx5_ib_qp *qp, u8 *qp_state)
5369{
5370 static const u8 sqrq_trans[MLX5_RQ_NUM_STATE][MLX5_SQ_NUM_STATE] = {
5371 [MLX5_RQC_STATE_RST] = {
5372 [MLX5_SQC_STATE_RST] = IB_QPS_RESET,
5373 [MLX5_SQC_STATE_RDY] = MLX5_QP_STATE_BAD,
5374 [MLX5_SQC_STATE_ERR] = MLX5_QP_STATE_BAD,
5375 [MLX5_SQ_STATE_NA] = IB_QPS_RESET,
5376 },
5377 [MLX5_RQC_STATE_RDY] = {
5378 [MLX5_SQC_STATE_RST] = MLX5_QP_STATE_BAD,
5379 [MLX5_SQC_STATE_RDY] = MLX5_QP_STATE,
5380 [MLX5_SQC_STATE_ERR] = IB_QPS_SQE,
5381 [MLX5_SQ_STATE_NA] = MLX5_QP_STATE,
5382 },
5383 [MLX5_RQC_STATE_ERR] = {
5384 [MLX5_SQC_STATE_RST] = MLX5_QP_STATE_BAD,
5385 [MLX5_SQC_STATE_RDY] = MLX5_QP_STATE_BAD,
5386 [MLX5_SQC_STATE_ERR] = IB_QPS_ERR,
5387 [MLX5_SQ_STATE_NA] = IB_QPS_ERR,
5388 },
5389 [MLX5_RQ_STATE_NA] = {
5390 [MLX5_SQC_STATE_RST] = IB_QPS_RESET,
5391 [MLX5_SQC_STATE_RDY] = MLX5_QP_STATE,
5392 [MLX5_SQC_STATE_ERR] = MLX5_QP_STATE,
5393 [MLX5_SQ_STATE_NA] = MLX5_QP_STATE_BAD,
5394 },
5395 };
5396
5397 *qp_state = sqrq_trans[rq_state][sq_state];
5398
5399 if (*qp_state == MLX5_QP_STATE_BAD) {
5400 WARN(1, "Buggy Raw Packet QP state, SQ 0x%x state: 0x%x, RQ 0x%x state: 0x%x",
5401 qp->raw_packet_qp.sq.base.mqp.qpn, sq_state,
5402 qp->raw_packet_qp.rq.base.mqp.qpn, rq_state);
5403 return -EINVAL;
5404 }
5405
5406 if (*qp_state == MLX5_QP_STATE)
5407 *qp_state = qp->state;
5408
5409 return 0;
5410}
5411
5412static int query_raw_packet_qp_state(struct mlx5_ib_dev *dev,
5413 struct mlx5_ib_qp *qp,
5414 u8 *raw_packet_qp_state)
5415{
5416 struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp;
5417 struct mlx5_ib_sq *sq = &raw_packet_qp->sq;
5418 struct mlx5_ib_rq *rq = &raw_packet_qp->rq;
5419 int err;
5420 u8 sq_state = MLX5_SQ_STATE_NA;
5421 u8 rq_state = MLX5_RQ_STATE_NA;
5422
5423 if (qp->sq.wqe_cnt) {
5424 err = query_raw_packet_qp_sq_state(dev, sq, &sq_state);
5425 if (err)
5426 return err;
5427 }
5428
5429 if (qp->rq.wqe_cnt) {
5430 err = query_raw_packet_qp_rq_state(dev, rq, &rq_state);
5431 if (err)
5432 return err;
5433 }
5434
5435 return sqrq_state_to_qp_state(sq_state, rq_state, qp,
5436 raw_packet_qp_state);
5437}
5438
5439static int query_qp_attr(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
5440 struct ib_qp_attr *qp_attr)
5441{
Saeed Mahameed09a7d9e2016-07-19 01:17:59 +03005442 int outlen = MLX5_ST_SZ_BYTES(query_qp_out);
Eli Cohene126ba92013-07-07 17:25:49 +03005443 struct mlx5_qp_context *context;
5444 int mlx5_state;
Saeed Mahameed09a7d9e2016-07-19 01:17:59 +03005445 u32 *outb;
Eli Cohene126ba92013-07-07 17:25:49 +03005446 int err = 0;
5447
Saeed Mahameed09a7d9e2016-07-19 01:17:59 +03005448 outb = kzalloc(outlen, GFP_KERNEL);
majd@mellanox.com6d2f89df2016-01-14 19:13:05 +02005449 if (!outb)
5450 return -ENOMEM;
5451
majd@mellanox.com19098df2016-01-14 19:13:03 +02005452 err = mlx5_core_qp_query(dev->mdev, &qp->trans_qp.base.mqp, outb,
Saeed Mahameed09a7d9e2016-07-19 01:17:59 +03005453 outlen);
Eli Cohene126ba92013-07-07 17:25:49 +03005454 if (err)
majd@mellanox.com6d2f89df2016-01-14 19:13:05 +02005455 goto out;
Eli Cohene126ba92013-07-07 17:25:49 +03005456
Saeed Mahameed09a7d9e2016-07-19 01:17:59 +03005457 /* FIXME: use MLX5_GET rather than mlx5_qp_context manual struct */
5458 context = (struct mlx5_qp_context *)MLX5_ADDR_OF(query_qp_out, outb, qpc);
5459
Eli Cohene126ba92013-07-07 17:25:49 +03005460 mlx5_state = be32_to_cpu(context->flags) >> 28;
5461
5462 qp->state = to_ib_qp_state(mlx5_state);
Eli Cohene126ba92013-07-07 17:25:49 +03005463 qp_attr->path_mtu = context->mtu_msgmax >> 5;
5464 qp_attr->path_mig_state =
5465 to_ib_mig_state((be32_to_cpu(context->flags) >> 11) & 0x3);
5466 qp_attr->qkey = be32_to_cpu(context->qkey);
5467 qp_attr->rq_psn = be32_to_cpu(context->rnr_nextrecvpsn) & 0xffffff;
5468 qp_attr->sq_psn = be32_to_cpu(context->next_send_psn) & 0xffffff;
5469 qp_attr->dest_qp_num = be32_to_cpu(context->log_pg_sz_remote_qpn) & 0xffffff;
5470 qp_attr->qp_access_flags =
5471 to_ib_qp_access_flags(be32_to_cpu(context->params2));
5472
5473 if (qp->ibqp.qp_type == IB_QPT_RC || qp->ibqp.qp_type == IB_QPT_UC) {
Dasaratharaman Chandramouli38349382017-04-29 14:41:24 -04005474 to_rdma_ah_attr(dev, &qp_attr->ah_attr, &context->pri_path);
5475 to_rdma_ah_attr(dev, &qp_attr->alt_ah_attr, &context->alt_path);
Noa Osherovichd3ae2bd2016-06-04 15:15:36 +03005476 qp_attr->alt_pkey_index =
5477 be16_to_cpu(context->alt_path.pkey_index);
Dasaratharaman Chandramoulid8966fc2017-04-29 14:41:28 -04005478 qp_attr->alt_port_num =
5479 rdma_ah_get_port_num(&qp_attr->alt_ah_attr);
Eli Cohene126ba92013-07-07 17:25:49 +03005480 }
5481
Noa Osherovichd3ae2bd2016-06-04 15:15:36 +03005482 qp_attr->pkey_index = be16_to_cpu(context->pri_path.pkey_index);
Eli Cohene126ba92013-07-07 17:25:49 +03005483 qp_attr->port_num = context->pri_path.port;
5484
5485 /* qp_attr->en_sqd_async_notify is only applicable in modify qp */
5486 qp_attr->sq_draining = mlx5_state == MLX5_QP_STATE_SQ_DRAINING;
5487
5488 qp_attr->max_rd_atomic = 1 << ((be32_to_cpu(context->params1) >> 21) & 0x7);
5489
5490 qp_attr->max_dest_rd_atomic =
5491 1 << ((be32_to_cpu(context->params2) >> 21) & 0x7);
5492 qp_attr->min_rnr_timer =
5493 (be32_to_cpu(context->rnr_nextrecvpsn) >> 24) & 0x1f;
5494 qp_attr->timeout = context->pri_path.ackto_lt >> 3;
5495 qp_attr->retry_cnt = (be32_to_cpu(context->params1) >> 16) & 0x7;
5496 qp_attr->rnr_retry = (be32_to_cpu(context->params1) >> 13) & 0x7;
5497 qp_attr->alt_timeout = context->alt_path.ackto_lt >> 3;
majd@mellanox.com6d2f89df2016-01-14 19:13:05 +02005498
5499out:
5500 kfree(outb);
5501 return err;
5502}
5503
Moni Shoua776a3902018-01-02 16:19:33 +02005504static int mlx5_ib_dct_query_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *mqp,
5505 struct ib_qp_attr *qp_attr, int qp_attr_mask,
5506 struct ib_qp_init_attr *qp_init_attr)
5507{
5508 struct mlx5_core_dct *dct = &mqp->dct.mdct;
5509 u32 *out;
5510 u32 access_flags = 0;
5511 int outlen = MLX5_ST_SZ_BYTES(query_dct_out);
5512 void *dctc;
5513 int err;
5514 int supported_mask = IB_QP_STATE |
5515 IB_QP_ACCESS_FLAGS |
5516 IB_QP_PORT |
5517 IB_QP_MIN_RNR_TIMER |
5518 IB_QP_AV |
5519 IB_QP_PATH_MTU |
5520 IB_QP_PKEY_INDEX;
5521
5522 if (qp_attr_mask & ~supported_mask)
5523 return -EINVAL;
5524 if (mqp->state != IB_QPS_RTR)
5525 return -EINVAL;
5526
5527 out = kzalloc(outlen, GFP_KERNEL);
5528 if (!out)
5529 return -ENOMEM;
5530
5531 err = mlx5_core_dct_query(dev->mdev, dct, out, outlen);
5532 if (err)
5533 goto out;
5534
5535 dctc = MLX5_ADDR_OF(query_dct_out, out, dct_context_entry);
5536
5537 if (qp_attr_mask & IB_QP_STATE)
5538 qp_attr->qp_state = IB_QPS_RTR;
5539
5540 if (qp_attr_mask & IB_QP_ACCESS_FLAGS) {
5541 if (MLX5_GET(dctc, dctc, rre))
5542 access_flags |= IB_ACCESS_REMOTE_READ;
5543 if (MLX5_GET(dctc, dctc, rwe))
5544 access_flags |= IB_ACCESS_REMOTE_WRITE;
5545 if (MLX5_GET(dctc, dctc, rae))
5546 access_flags |= IB_ACCESS_REMOTE_ATOMIC;
5547 qp_attr->qp_access_flags = access_flags;
5548 }
5549
5550 if (qp_attr_mask & IB_QP_PORT)
5551 qp_attr->port_num = MLX5_GET(dctc, dctc, port);
5552 if (qp_attr_mask & IB_QP_MIN_RNR_TIMER)
5553 qp_attr->min_rnr_timer = MLX5_GET(dctc, dctc, min_rnr_nak);
5554 if (qp_attr_mask & IB_QP_AV) {
5555 qp_attr->ah_attr.grh.traffic_class = MLX5_GET(dctc, dctc, tclass);
5556 qp_attr->ah_attr.grh.flow_label = MLX5_GET(dctc, dctc, flow_label);
5557 qp_attr->ah_attr.grh.sgid_index = MLX5_GET(dctc, dctc, my_addr_index);
5558 qp_attr->ah_attr.grh.hop_limit = MLX5_GET(dctc, dctc, hop_limit);
5559 }
5560 if (qp_attr_mask & IB_QP_PATH_MTU)
5561 qp_attr->path_mtu = MLX5_GET(dctc, dctc, mtu);
5562 if (qp_attr_mask & IB_QP_PKEY_INDEX)
5563 qp_attr->pkey_index = MLX5_GET(dctc, dctc, pkey_index);
5564out:
5565 kfree(out);
5566 return err;
5567}
5568
majd@mellanox.com6d2f89df2016-01-14 19:13:05 +02005569int mlx5_ib_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr,
5570 int qp_attr_mask, struct ib_qp_init_attr *qp_init_attr)
5571{
5572 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
5573 struct mlx5_ib_qp *qp = to_mqp(ibqp);
5574 int err = 0;
5575 u8 raw_packet_qp_state;
5576
Yishai Hadas28d61372016-05-23 15:20:56 +03005577 if (ibqp->rwq_ind_tbl)
5578 return -ENOSYS;
5579
Haggai Erand16e91d2016-02-29 15:45:05 +02005580 if (unlikely(ibqp->qp_type == IB_QPT_GSI))
5581 return mlx5_ib_gsi_query_qp(ibqp, qp_attr, qp_attr_mask,
5582 qp_init_attr);
5583
Yishai Hadasc2e53b22017-06-08 16:15:08 +03005584 /* Not all of output fields are applicable, make sure to zero them */
5585 memset(qp_init_attr, 0, sizeof(*qp_init_attr));
5586 memset(qp_attr, 0, sizeof(*qp_attr));
5587
Moni Shoua776a3902018-01-02 16:19:33 +02005588 if (unlikely(qp->qp_sub_type == MLX5_IB_QPT_DCT))
5589 return mlx5_ib_dct_query_qp(dev, qp, qp_attr,
5590 qp_attr_mask, qp_init_attr);
5591
majd@mellanox.com6d2f89df2016-01-14 19:13:05 +02005592 mutex_lock(&qp->mutex);
5593
Yishai Hadasc2e53b22017-06-08 16:15:08 +03005594 if (qp->ibqp.qp_type == IB_QPT_RAW_PACKET ||
5595 qp->flags & MLX5_IB_QP_UNDERLAY) {
majd@mellanox.com6d2f89df2016-01-14 19:13:05 +02005596 err = query_raw_packet_qp_state(dev, qp, &raw_packet_qp_state);
5597 if (err)
5598 goto out;
5599 qp->state = raw_packet_qp_state;
5600 qp_attr->port_num = 1;
5601 } else {
5602 err = query_qp_attr(dev, qp, qp_attr);
5603 if (err)
5604 goto out;
5605 }
5606
5607 qp_attr->qp_state = qp->state;
Eli Cohene126ba92013-07-07 17:25:49 +03005608 qp_attr->cur_qp_state = qp_attr->qp_state;
5609 qp_attr->cap.max_recv_wr = qp->rq.wqe_cnt;
5610 qp_attr->cap.max_recv_sge = qp->rq.max_gs;
5611
5612 if (!ibqp->uobject) {
Noa Osherovich0540d812016-06-04 15:15:32 +03005613 qp_attr->cap.max_send_wr = qp->sq.max_post;
Eli Cohene126ba92013-07-07 17:25:49 +03005614 qp_attr->cap.max_send_sge = qp->sq.max_gs;
Noa Osherovich0540d812016-06-04 15:15:32 +03005615 qp_init_attr->qp_context = ibqp->qp_context;
Eli Cohene126ba92013-07-07 17:25:49 +03005616 } else {
5617 qp_attr->cap.max_send_wr = 0;
5618 qp_attr->cap.max_send_sge = 0;
5619 }
5620
Noa Osherovich0540d812016-06-04 15:15:32 +03005621 qp_init_attr->qp_type = ibqp->qp_type;
5622 qp_init_attr->recv_cq = ibqp->recv_cq;
5623 qp_init_attr->send_cq = ibqp->send_cq;
5624 qp_init_attr->srq = ibqp->srq;
5625 qp_attr->cap.max_inline_data = qp->max_inline_data;
Eli Cohene126ba92013-07-07 17:25:49 +03005626
5627 qp_init_attr->cap = qp_attr->cap;
5628
5629 qp_init_attr->create_flags = 0;
5630 if (qp->flags & MLX5_IB_QP_BLOCK_MULTICAST_LOOPBACK)
5631 qp_init_attr->create_flags |= IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK;
5632
Leon Romanovsky051f2632015-12-20 12:16:11 +02005633 if (qp->flags & MLX5_IB_QP_CROSS_CHANNEL)
5634 qp_init_attr->create_flags |= IB_QP_CREATE_CROSS_CHANNEL;
5635 if (qp->flags & MLX5_IB_QP_MANAGED_SEND)
5636 qp_init_attr->create_flags |= IB_QP_CREATE_MANAGED_SEND;
5637 if (qp->flags & MLX5_IB_QP_MANAGED_RECV)
5638 qp_init_attr->create_flags |= IB_QP_CREATE_MANAGED_RECV;
Haggai Eranb11a4f92016-02-29 15:45:03 +02005639 if (qp->flags & MLX5_IB_QP_SQPN_QP1)
5640 qp_init_attr->create_flags |= mlx5_ib_create_qp_sqpn_qp1();
Leon Romanovsky051f2632015-12-20 12:16:11 +02005641
Eli Cohene126ba92013-07-07 17:25:49 +03005642 qp_init_attr->sq_sig_type = qp->sq_signal_bits & MLX5_WQE_CTRL_CQ_UPDATE ?
5643 IB_SIGNAL_ALL_WR : IB_SIGNAL_REQ_WR;
5644
Eli Cohene126ba92013-07-07 17:25:49 +03005645out:
5646 mutex_unlock(&qp->mutex);
5647 return err;
5648}
5649
5650struct ib_xrcd *mlx5_ib_alloc_xrcd(struct ib_device *ibdev,
Shamir Rabinovitchff23dfa2019-03-31 19:10:07 +03005651 struct ib_udata *udata)
Eli Cohene126ba92013-07-07 17:25:49 +03005652{
5653 struct mlx5_ib_dev *dev = to_mdev(ibdev);
5654 struct mlx5_ib_xrcd *xrcd;
5655 int err;
5656
Saeed Mahameed938fe832015-05-28 22:28:41 +03005657 if (!MLX5_CAP_GEN(dev->mdev, xrc))
Eli Cohene126ba92013-07-07 17:25:49 +03005658 return ERR_PTR(-ENOSYS);
5659
5660 xrcd = kmalloc(sizeof(*xrcd), GFP_KERNEL);
5661 if (!xrcd)
5662 return ERR_PTR(-ENOMEM);
5663
Yishai Hadas5aa37712018-11-26 08:28:38 +02005664 err = mlx5_cmd_xrcd_alloc(dev->mdev, &xrcd->xrcdn, 0);
Eli Cohene126ba92013-07-07 17:25:49 +03005665 if (err) {
5666 kfree(xrcd);
5667 return ERR_PTR(-ENOMEM);
5668 }
5669
5670 return &xrcd->ibxrcd;
5671}
5672
Shamir Rabinovitchc4367a22019-03-31 19:10:05 +03005673int mlx5_ib_dealloc_xrcd(struct ib_xrcd *xrcd, struct ib_udata *udata)
Eli Cohene126ba92013-07-07 17:25:49 +03005674{
5675 struct mlx5_ib_dev *dev = to_mdev(xrcd->device);
5676 u32 xrcdn = to_mxrcd(xrcd)->xrcdn;
5677 int err;
5678
Yishai Hadas5aa37712018-11-26 08:28:38 +02005679 err = mlx5_cmd_xrcd_dealloc(dev->mdev, xrcdn, 0);
Leon Romanovskyb0818082018-01-28 11:25:30 +02005680 if (err)
Eli Cohene126ba92013-07-07 17:25:49 +03005681 mlx5_ib_warn(dev, "failed to dealloc xrcdn 0x%x\n", xrcdn);
Eli Cohene126ba92013-07-07 17:25:49 +03005682
5683 kfree(xrcd);
Eli Cohene126ba92013-07-07 17:25:49 +03005684 return 0;
5685}
Yishai Hadas79b20a62016-05-23 15:20:50 +03005686
Yishai Hadas350d0e42016-08-28 14:58:18 +03005687static void mlx5_ib_wq_event(struct mlx5_core_qp *core_qp, int type)
5688{
5689 struct mlx5_ib_rwq *rwq = to_mibrwq(core_qp);
5690 struct mlx5_ib_dev *dev = to_mdev(rwq->ibwq.device);
5691 struct ib_event event;
5692
5693 if (rwq->ibwq.event_handler) {
5694 event.device = rwq->ibwq.device;
5695 event.element.wq = &rwq->ibwq;
5696 switch (type) {
5697 case MLX5_EVENT_TYPE_WQ_CATAS_ERROR:
5698 event.event = IB_EVENT_WQ_FATAL;
5699 break;
5700 default:
5701 mlx5_ib_warn(dev, "Unexpected event type %d on WQ %06x\n", type, core_qp->qpn);
5702 return;
5703 }
5704
5705 rwq->ibwq.event_handler(&event, rwq->ibwq.wq_context);
5706 }
5707}
5708
Maor Gottlieb03404e82017-05-30 10:29:13 +03005709static int set_delay_drop(struct mlx5_ib_dev *dev)
5710{
5711 int err = 0;
5712
5713 mutex_lock(&dev->delay_drop.lock);
5714 if (dev->delay_drop.activate)
5715 goto out;
5716
5717 err = mlx5_core_set_delay_drop(dev->mdev, dev->delay_drop.timeout);
5718 if (err)
5719 goto out;
5720
5721 dev->delay_drop.activate = true;
5722out:
5723 mutex_unlock(&dev->delay_drop.lock);
Maor Gottliebfe248c32017-05-30 10:29:14 +03005724
5725 if (!err)
5726 atomic_inc(&dev->delay_drop.rqs_cnt);
Maor Gottlieb03404e82017-05-30 10:29:13 +03005727 return err;
5728}
5729
Yishai Hadas79b20a62016-05-23 15:20:50 +03005730static int create_rq(struct mlx5_ib_rwq *rwq, struct ib_pd *pd,
5731 struct ib_wq_init_attr *init_attr)
5732{
5733 struct mlx5_ib_dev *dev;
Noa Osherovich4be6da12017-01-18 15:40:04 +02005734 int has_net_offloads;
Yishai Hadas79b20a62016-05-23 15:20:50 +03005735 __be64 *rq_pas0;
5736 void *in;
5737 void *rqc;
5738 void *wq;
5739 int inlen;
5740 int err;
5741
5742 dev = to_mdev(pd->device);
5743
5744 inlen = MLX5_ST_SZ_BYTES(create_rq_in) + sizeof(u64) * rwq->rq_num_pas;
Leon Romanovsky1b9a07e2017-05-10 21:32:18 +03005745 in = kvzalloc(inlen, GFP_KERNEL);
Yishai Hadas79b20a62016-05-23 15:20:50 +03005746 if (!in)
5747 return -ENOMEM;
5748
Yishai Hadas34d57582018-09-20 21:39:21 +03005749 MLX5_SET(create_rq_in, in, uid, to_mpd(pd)->uid);
Yishai Hadas79b20a62016-05-23 15:20:50 +03005750 rqc = MLX5_ADDR_OF(create_rq_in, in, ctx);
5751 MLX5_SET(rqc, rqc, mem_rq_type,
5752 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE);
5753 MLX5_SET(rqc, rqc, user_index, rwq->user_index);
5754 MLX5_SET(rqc, rqc, cqn, to_mcq(init_attr->cq)->mcq.cqn);
5755 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RST);
5756 MLX5_SET(rqc, rqc, flush_in_error_en, 1);
5757 wq = MLX5_ADDR_OF(rqc, rqc, wq);
Noa Osherovichccc87082017-10-17 18:01:13 +03005758 MLX5_SET(wq, wq, wq_type,
5759 rwq->create_flags & MLX5_IB_WQ_FLAGS_STRIDING_RQ ?
5760 MLX5_WQ_TYPE_CYCLIC_STRIDING_RQ : MLX5_WQ_TYPE_CYCLIC);
Noa Osherovichb1383aa2017-10-29 13:59:45 +02005761 if (init_attr->create_flags & IB_WQ_FLAGS_PCI_WRITE_END_PADDING) {
5762 if (!MLX5_CAP_GEN(dev->mdev, end_pad)) {
5763 mlx5_ib_dbg(dev, "Scatter end padding is not supported\n");
5764 err = -EOPNOTSUPP;
5765 goto out;
5766 } else {
5767 MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN);
5768 }
5769 }
Yishai Hadas79b20a62016-05-23 15:20:50 +03005770 MLX5_SET(wq, wq, log_wq_stride, rwq->log_rq_stride);
Noa Osherovichccc87082017-10-17 18:01:13 +03005771 if (rwq->create_flags & MLX5_IB_WQ_FLAGS_STRIDING_RQ) {
5772 MLX5_SET(wq, wq, two_byte_shift_en, rwq->two_byte_shift_en);
5773 MLX5_SET(wq, wq, log_wqe_stride_size,
5774 rwq->single_stride_log_num_of_bytes -
5775 MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES);
5776 MLX5_SET(wq, wq, log_wqe_num_of_strides, rwq->log_num_strides -
5777 MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES);
5778 }
Yishai Hadas79b20a62016-05-23 15:20:50 +03005779 MLX5_SET(wq, wq, log_wq_sz, rwq->log_rq_size);
5780 MLX5_SET(wq, wq, pd, to_mpd(pd)->pdn);
5781 MLX5_SET(wq, wq, page_offset, rwq->rq_page_offset);
5782 MLX5_SET(wq, wq, log_wq_pg_sz, rwq->log_page_size);
5783 MLX5_SET(wq, wq, wq_signature, rwq->wq_sig);
5784 MLX5_SET64(wq, wq, dbr_addr, rwq->db.dma);
Noa Osherovich4be6da12017-01-18 15:40:04 +02005785 has_net_offloads = MLX5_CAP_GEN(dev->mdev, eth_net_offloads);
Noa Osherovichb1f74a82017-01-18 15:40:02 +02005786 if (init_attr->create_flags & IB_WQ_FLAGS_CVLAN_STRIPPING) {
Noa Osherovich4be6da12017-01-18 15:40:04 +02005787 if (!(has_net_offloads && MLX5_CAP_ETH(dev->mdev, vlan_cap))) {
Noa Osherovichb1f74a82017-01-18 15:40:02 +02005788 mlx5_ib_dbg(dev, "VLAN offloads are not supported\n");
5789 err = -EOPNOTSUPP;
5790 goto out;
5791 }
5792 } else {
5793 MLX5_SET(rqc, rqc, vsd, 1);
5794 }
Noa Osherovich4be6da12017-01-18 15:40:04 +02005795 if (init_attr->create_flags & IB_WQ_FLAGS_SCATTER_FCS) {
5796 if (!(has_net_offloads && MLX5_CAP_ETH(dev->mdev, scatter_fcs))) {
5797 mlx5_ib_dbg(dev, "Scatter FCS is not supported\n");
5798 err = -EOPNOTSUPP;
5799 goto out;
5800 }
5801 MLX5_SET(rqc, rqc, scatter_fcs, 1);
5802 }
Maor Gottlieb03404e82017-05-30 10:29:13 +03005803 if (init_attr->create_flags & IB_WQ_FLAGS_DELAY_DROP) {
5804 if (!(dev->ib_dev.attrs.raw_packet_caps &
5805 IB_RAW_PACKET_CAP_DELAY_DROP)) {
5806 mlx5_ib_dbg(dev, "Delay drop is not supported\n");
5807 err = -EOPNOTSUPP;
5808 goto out;
5809 }
5810 MLX5_SET(rqc, rqc, delay_drop_en, 1);
5811 }
Yishai Hadas79b20a62016-05-23 15:20:50 +03005812 rq_pas0 = (__be64 *)MLX5_ADDR_OF(wq, wq, pas);
5813 mlx5_ib_populate_pas(dev, rwq->umem, rwq->page_shift, rq_pas0, 0);
Yishai Hadas350d0e42016-08-28 14:58:18 +03005814 err = mlx5_core_create_rq_tracked(dev->mdev, in, inlen, &rwq->core_qp);
Maor Gottlieb03404e82017-05-30 10:29:13 +03005815 if (!err && init_attr->create_flags & IB_WQ_FLAGS_DELAY_DROP) {
5816 err = set_delay_drop(dev);
5817 if (err) {
5818 mlx5_ib_warn(dev, "Failed to enable delay drop err=%d\n",
5819 err);
5820 mlx5_core_destroy_rq_tracked(dev->mdev, &rwq->core_qp);
5821 } else {
5822 rwq->create_flags |= MLX5_IB_WQ_FLAGS_DELAY_DROP;
5823 }
5824 }
Noa Osherovichb1f74a82017-01-18 15:40:02 +02005825out:
Yishai Hadas79b20a62016-05-23 15:20:50 +03005826 kvfree(in);
5827 return err;
5828}
5829
5830static int set_user_rq_size(struct mlx5_ib_dev *dev,
5831 struct ib_wq_init_attr *wq_init_attr,
5832 struct mlx5_ib_create_wq *ucmd,
5833 struct mlx5_ib_rwq *rwq)
5834{
5835 /* Sanity check RQ size before proceeding */
5836 if (wq_init_attr->max_wr > (1 << MLX5_CAP_GEN(dev->mdev, log_max_wq_sz)))
5837 return -EINVAL;
5838
5839 if (!ucmd->rq_wqe_count)
5840 return -EINVAL;
5841
5842 rwq->wqe_count = ucmd->rq_wqe_count;
5843 rwq->wqe_shift = ucmd->rq_wqe_shift;
Leon Romanovsky0dfe4522018-08-01 14:25:41 -07005844 if (check_shl_overflow(rwq->wqe_count, rwq->wqe_shift, &rwq->buf_size))
5845 return -EINVAL;
5846
Yishai Hadas79b20a62016-05-23 15:20:50 +03005847 rwq->log_rq_stride = rwq->wqe_shift;
5848 rwq->log_rq_size = ilog2(rwq->wqe_count);
5849 return 0;
5850}
5851
5852static int prepare_user_rq(struct ib_pd *pd,
5853 struct ib_wq_init_attr *init_attr,
5854 struct ib_udata *udata,
5855 struct mlx5_ib_rwq *rwq)
5856{
5857 struct mlx5_ib_dev *dev = to_mdev(pd->device);
5858 struct mlx5_ib_create_wq ucmd = {};
5859 int err;
5860 size_t required_cmd_sz;
5861
Noa Osherovichccc87082017-10-17 18:01:13 +03005862 required_cmd_sz = offsetof(typeof(ucmd), single_stride_log_num_of_bytes)
5863 + sizeof(ucmd.single_stride_log_num_of_bytes);
Yishai Hadas79b20a62016-05-23 15:20:50 +03005864 if (udata->inlen < required_cmd_sz) {
5865 mlx5_ib_dbg(dev, "invalid inlen\n");
5866 return -EINVAL;
5867 }
5868
5869 if (udata->inlen > sizeof(ucmd) &&
5870 !ib_is_udata_cleared(udata, sizeof(ucmd),
5871 udata->inlen - sizeof(ucmd))) {
5872 mlx5_ib_dbg(dev, "inlen is not supported\n");
5873 return -EOPNOTSUPP;
5874 }
5875
5876 if (ib_copy_from_udata(&ucmd, udata, min(sizeof(ucmd), udata->inlen))) {
5877 mlx5_ib_dbg(dev, "copy failed\n");
5878 return -EFAULT;
5879 }
5880
Noa Osherovichccc87082017-10-17 18:01:13 +03005881 if (ucmd.comp_mask & (~MLX5_IB_CREATE_WQ_STRIDING_RQ)) {
Yishai Hadas79b20a62016-05-23 15:20:50 +03005882 mlx5_ib_dbg(dev, "invalid comp mask\n");
5883 return -EOPNOTSUPP;
Noa Osherovichccc87082017-10-17 18:01:13 +03005884 } else if (ucmd.comp_mask & MLX5_IB_CREATE_WQ_STRIDING_RQ) {
5885 if (!MLX5_CAP_GEN(dev->mdev, striding_rq)) {
5886 mlx5_ib_dbg(dev, "Striding RQ is not supported\n");
5887 return -EOPNOTSUPP;
5888 }
5889 if ((ucmd.single_stride_log_num_of_bytes <
5890 MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES) ||
5891 (ucmd.single_stride_log_num_of_bytes >
5892 MLX5_MAX_SINGLE_STRIDE_LOG_NUM_BYTES)) {
5893 mlx5_ib_dbg(dev, "Invalid log stride size (%u. Range is %u - %u)\n",
5894 ucmd.single_stride_log_num_of_bytes,
5895 MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES,
5896 MLX5_MAX_SINGLE_STRIDE_LOG_NUM_BYTES);
5897 return -EINVAL;
5898 }
5899 if ((ucmd.single_wqe_log_num_of_strides >
5900 MLX5_MAX_SINGLE_WQE_LOG_NUM_STRIDES) ||
5901 (ucmd.single_wqe_log_num_of_strides <
5902 MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES)) {
5903 mlx5_ib_dbg(dev, "Invalid log num strides (%u. Range is %u - %u)\n",
5904 ucmd.single_wqe_log_num_of_strides,
5905 MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES,
5906 MLX5_MAX_SINGLE_WQE_LOG_NUM_STRIDES);
5907 return -EINVAL;
5908 }
5909 rwq->single_stride_log_num_of_bytes =
5910 ucmd.single_stride_log_num_of_bytes;
5911 rwq->log_num_strides = ucmd.single_wqe_log_num_of_strides;
5912 rwq->two_byte_shift_en = !!ucmd.two_byte_shift_en;
5913 rwq->create_flags |= MLX5_IB_WQ_FLAGS_STRIDING_RQ;
Yishai Hadas79b20a62016-05-23 15:20:50 +03005914 }
5915
5916 err = set_user_rq_size(dev, init_attr, &ucmd, rwq);
5917 if (err) {
5918 mlx5_ib_dbg(dev, "err %d\n", err);
5919 return err;
5920 }
5921
Jason Gunthorpeb0ea0fa2019-01-09 11:15:16 +02005922 err = create_user_rq(dev, pd, udata, rwq, &ucmd);
Yishai Hadas79b20a62016-05-23 15:20:50 +03005923 if (err) {
5924 mlx5_ib_dbg(dev, "err %d\n", err);
Gal Pressman645ba592018-10-08 19:44:03 +03005925 return err;
Yishai Hadas79b20a62016-05-23 15:20:50 +03005926 }
5927
5928 rwq->user_index = ucmd.user_index;
5929 return 0;
5930}
5931
5932struct ib_wq *mlx5_ib_create_wq(struct ib_pd *pd,
5933 struct ib_wq_init_attr *init_attr,
5934 struct ib_udata *udata)
5935{
5936 struct mlx5_ib_dev *dev;
5937 struct mlx5_ib_rwq *rwq;
5938 struct mlx5_ib_create_wq_resp resp = {};
5939 size_t min_resp_len;
5940 int err;
5941
5942 if (!udata)
5943 return ERR_PTR(-ENOSYS);
5944
5945 min_resp_len = offsetof(typeof(resp), reserved) + sizeof(resp.reserved);
5946 if (udata->outlen && udata->outlen < min_resp_len)
5947 return ERR_PTR(-EINVAL);
5948
5949 dev = to_mdev(pd->device);
5950 switch (init_attr->wq_type) {
5951 case IB_WQT_RQ:
5952 rwq = kzalloc(sizeof(*rwq), GFP_KERNEL);
5953 if (!rwq)
5954 return ERR_PTR(-ENOMEM);
5955 err = prepare_user_rq(pd, init_attr, udata, rwq);
5956 if (err)
5957 goto err;
5958 err = create_rq(rwq, pd, init_attr);
5959 if (err)
5960 goto err_user_rq;
5961 break;
5962 default:
5963 mlx5_ib_dbg(dev, "unsupported wq type %d\n",
5964 init_attr->wq_type);
5965 return ERR_PTR(-EINVAL);
5966 }
5967
Yishai Hadas350d0e42016-08-28 14:58:18 +03005968 rwq->ibwq.wq_num = rwq->core_qp.qpn;
Yishai Hadas79b20a62016-05-23 15:20:50 +03005969 rwq->ibwq.state = IB_WQS_RESET;
5970 if (udata->outlen) {
5971 resp.response_length = offsetof(typeof(resp), response_length) +
5972 sizeof(resp.response_length);
5973 err = ib_copy_to_udata(udata, &resp, resp.response_length);
5974 if (err)
5975 goto err_copy;
5976 }
5977
Yishai Hadas350d0e42016-08-28 14:58:18 +03005978 rwq->core_qp.event = mlx5_ib_wq_event;
5979 rwq->ibwq.event_handler = init_attr->event_handler;
Yishai Hadas79b20a62016-05-23 15:20:50 +03005980 return &rwq->ibwq;
5981
5982err_copy:
Yishai Hadas350d0e42016-08-28 14:58:18 +03005983 mlx5_core_destroy_rq_tracked(dev->mdev, &rwq->core_qp);
Yishai Hadas79b20a62016-05-23 15:20:50 +03005984err_user_rq:
Shamir Rabinovitchbdeacab2019-03-31 19:10:06 +03005985 destroy_user_rq(dev, pd, rwq, udata);
Yishai Hadas79b20a62016-05-23 15:20:50 +03005986err:
5987 kfree(rwq);
5988 return ERR_PTR(err);
5989}
5990
Shamir Rabinovitchc4367a22019-03-31 19:10:05 +03005991int mlx5_ib_destroy_wq(struct ib_wq *wq, struct ib_udata *udata)
Yishai Hadas79b20a62016-05-23 15:20:50 +03005992{
5993 struct mlx5_ib_dev *dev = to_mdev(wq->device);
5994 struct mlx5_ib_rwq *rwq = to_mrwq(wq);
5995
Yishai Hadas350d0e42016-08-28 14:58:18 +03005996 mlx5_core_destroy_rq_tracked(dev->mdev, &rwq->core_qp);
Shamir Rabinovitchbdeacab2019-03-31 19:10:06 +03005997 destroy_user_rq(dev, wq->pd, rwq, udata);
Yishai Hadas79b20a62016-05-23 15:20:50 +03005998 kfree(rwq);
5999
6000 return 0;
6001}
6002
Yishai Hadasc5f90922016-05-23 15:20:53 +03006003struct ib_rwq_ind_table *mlx5_ib_create_rwq_ind_table(struct ib_device *device,
6004 struct ib_rwq_ind_table_init_attr *init_attr,
6005 struct ib_udata *udata)
6006{
6007 struct mlx5_ib_dev *dev = to_mdev(device);
6008 struct mlx5_ib_rwq_ind_table *rwq_ind_tbl;
6009 int sz = 1 << init_attr->log_ind_tbl_size;
6010 struct mlx5_ib_create_rwq_ind_tbl_resp resp = {};
6011 size_t min_resp_len;
6012 int inlen;
6013 int err;
6014 int i;
6015 u32 *in;
6016 void *rqtc;
6017
6018 if (udata->inlen > 0 &&
6019 !ib_is_udata_cleared(udata, 0,
6020 udata->inlen))
6021 return ERR_PTR(-EOPNOTSUPP);
6022
Maor Gottliebefd7f402016-10-27 16:36:40 +03006023 if (init_attr->log_ind_tbl_size >
6024 MLX5_CAP_GEN(dev->mdev, log_max_rqt_size)) {
6025 mlx5_ib_dbg(dev, "log_ind_tbl_size = %d is bigger than supported = %d\n",
6026 init_attr->log_ind_tbl_size,
6027 MLX5_CAP_GEN(dev->mdev, log_max_rqt_size));
6028 return ERR_PTR(-EINVAL);
6029 }
6030
Yishai Hadasc5f90922016-05-23 15:20:53 +03006031 min_resp_len = offsetof(typeof(resp), reserved) + sizeof(resp.reserved);
6032 if (udata->outlen && udata->outlen < min_resp_len)
6033 return ERR_PTR(-EINVAL);
6034
6035 rwq_ind_tbl = kzalloc(sizeof(*rwq_ind_tbl), GFP_KERNEL);
6036 if (!rwq_ind_tbl)
6037 return ERR_PTR(-ENOMEM);
6038
6039 inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz;
Leon Romanovsky1b9a07e2017-05-10 21:32:18 +03006040 in = kvzalloc(inlen, GFP_KERNEL);
Yishai Hadasc5f90922016-05-23 15:20:53 +03006041 if (!in) {
6042 err = -ENOMEM;
6043 goto err;
6044 }
6045
6046 rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context);
6047
6048 MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
6049 MLX5_SET(rqtc, rqtc, rqt_max_size, sz);
6050
6051 for (i = 0; i < sz; i++)
6052 MLX5_SET(rqtc, rqtc, rq_num[i], init_attr->ind_tbl[i]->wq_num);
6053
Yishai Hadas5deba862018-09-20 21:39:28 +03006054 rwq_ind_tbl->uid = to_mpd(init_attr->ind_tbl[0]->pd)->uid;
6055 MLX5_SET(create_rqt_in, in, uid, rwq_ind_tbl->uid);
6056
Yishai Hadasc5f90922016-05-23 15:20:53 +03006057 err = mlx5_core_create_rqt(dev->mdev, in, inlen, &rwq_ind_tbl->rqtn);
6058 kvfree(in);
6059
6060 if (err)
6061 goto err;
6062
6063 rwq_ind_tbl->ib_rwq_ind_tbl.ind_tbl_num = rwq_ind_tbl->rqtn;
6064 if (udata->outlen) {
6065 resp.response_length = offsetof(typeof(resp), response_length) +
6066 sizeof(resp.response_length);
6067 err = ib_copy_to_udata(udata, &resp, resp.response_length);
6068 if (err)
6069 goto err_copy;
6070 }
6071
6072 return &rwq_ind_tbl->ib_rwq_ind_tbl;
6073
6074err_copy:
Yishai Hadas5deba862018-09-20 21:39:28 +03006075 mlx5_cmd_destroy_rqt(dev->mdev, rwq_ind_tbl->rqtn, rwq_ind_tbl->uid);
Yishai Hadasc5f90922016-05-23 15:20:53 +03006076err:
6077 kfree(rwq_ind_tbl);
6078 return ERR_PTR(err);
6079}
6080
6081int mlx5_ib_destroy_rwq_ind_table(struct ib_rwq_ind_table *ib_rwq_ind_tbl)
6082{
6083 struct mlx5_ib_rwq_ind_table *rwq_ind_tbl = to_mrwq_ind_table(ib_rwq_ind_tbl);
6084 struct mlx5_ib_dev *dev = to_mdev(ib_rwq_ind_tbl->device);
6085
Yishai Hadas5deba862018-09-20 21:39:28 +03006086 mlx5_cmd_destroy_rqt(dev->mdev, rwq_ind_tbl->rqtn, rwq_ind_tbl->uid);
Yishai Hadasc5f90922016-05-23 15:20:53 +03006087
6088 kfree(rwq_ind_tbl);
6089 return 0;
6090}
6091
Yishai Hadas79b20a62016-05-23 15:20:50 +03006092int mlx5_ib_modify_wq(struct ib_wq *wq, struct ib_wq_attr *wq_attr,
6093 u32 wq_attr_mask, struct ib_udata *udata)
6094{
6095 struct mlx5_ib_dev *dev = to_mdev(wq->device);
6096 struct mlx5_ib_rwq *rwq = to_mrwq(wq);
6097 struct mlx5_ib_modify_wq ucmd = {};
6098 size_t required_cmd_sz;
6099 int curr_wq_state;
6100 int wq_state;
6101 int inlen;
6102 int err;
6103 void *rqc;
6104 void *in;
6105
6106 required_cmd_sz = offsetof(typeof(ucmd), reserved) + sizeof(ucmd.reserved);
6107 if (udata->inlen < required_cmd_sz)
6108 return -EINVAL;
6109
6110 if (udata->inlen > sizeof(ucmd) &&
6111 !ib_is_udata_cleared(udata, sizeof(ucmd),
6112 udata->inlen - sizeof(ucmd)))
6113 return -EOPNOTSUPP;
6114
6115 if (ib_copy_from_udata(&ucmd, udata, min(sizeof(ucmd), udata->inlen)))
6116 return -EFAULT;
6117
6118 if (ucmd.comp_mask || ucmd.reserved)
6119 return -EOPNOTSUPP;
6120
6121 inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
Leon Romanovsky1b9a07e2017-05-10 21:32:18 +03006122 in = kvzalloc(inlen, GFP_KERNEL);
Yishai Hadas79b20a62016-05-23 15:20:50 +03006123 if (!in)
6124 return -ENOMEM;
6125
6126 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
6127
6128 curr_wq_state = (wq_attr_mask & IB_WQ_CUR_STATE) ?
6129 wq_attr->curr_wq_state : wq->state;
6130 wq_state = (wq_attr_mask & IB_WQ_STATE) ?
6131 wq_attr->wq_state : curr_wq_state;
6132 if (curr_wq_state == IB_WQS_ERR)
6133 curr_wq_state = MLX5_RQC_STATE_ERR;
6134 if (wq_state == IB_WQS_ERR)
6135 wq_state = MLX5_RQC_STATE_ERR;
6136 MLX5_SET(modify_rq_in, in, rq_state, curr_wq_state);
Yishai Hadas34d57582018-09-20 21:39:21 +03006137 MLX5_SET(modify_rq_in, in, uid, to_mpd(wq->pd)->uid);
Yishai Hadas79b20a62016-05-23 15:20:50 +03006138 MLX5_SET(rqc, rqc, state, wq_state);
6139
Noa Osherovichb1f74a82017-01-18 15:40:02 +02006140 if (wq_attr_mask & IB_WQ_FLAGS) {
6141 if (wq_attr->flags_mask & IB_WQ_FLAGS_CVLAN_STRIPPING) {
6142 if (!(MLX5_CAP_GEN(dev->mdev, eth_net_offloads) &&
6143 MLX5_CAP_ETH(dev->mdev, vlan_cap))) {
6144 mlx5_ib_dbg(dev, "VLAN offloads are not "
6145 "supported\n");
6146 err = -EOPNOTSUPP;
6147 goto out;
6148 }
6149 MLX5_SET64(modify_rq_in, in, modify_bitmask,
6150 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD);
6151 MLX5_SET(rqc, rqc, vsd,
6152 (wq_attr->flags & IB_WQ_FLAGS_CVLAN_STRIPPING) ? 0 : 1);
6153 }
Noa Osherovichb1383aa2017-10-29 13:59:45 +02006154
6155 if (wq_attr->flags_mask & IB_WQ_FLAGS_PCI_WRITE_END_PADDING) {
6156 mlx5_ib_dbg(dev, "Modifying scatter end padding is not supported\n");
6157 err = -EOPNOTSUPP;
6158 goto out;
6159 }
Noa Osherovichb1f74a82017-01-18 15:40:02 +02006160 }
6161
Majd Dibbiny23a69642017-01-18 15:25:10 +02006162 if (curr_wq_state == IB_WQS_RESET && wq_state == IB_WQS_RDY) {
6163 if (MLX5_CAP_GEN(dev->mdev, modify_rq_counter_set_id)) {
6164 MLX5_SET64(modify_rq_in, in, modify_bitmask,
6165 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID);
Parav Pandite1f24a72017-04-16 07:29:29 +03006166 MLX5_SET(rqc, rqc, counter_set_id,
6167 dev->port->cnts.set_id);
Majd Dibbiny23a69642017-01-18 15:25:10 +02006168 } else
Jason Gunthorpe5a738b52018-09-20 16:42:24 -06006169 dev_info_once(
6170 &dev->ib_dev.dev,
6171 "Receive WQ counters are not supported on current FW\n");
Majd Dibbiny23a69642017-01-18 15:25:10 +02006172 }
6173
Yishai Hadas350d0e42016-08-28 14:58:18 +03006174 err = mlx5_core_modify_rq(dev->mdev, rwq->core_qp.qpn, in, inlen);
Yishai Hadas79b20a62016-05-23 15:20:50 +03006175 if (!err)
6176 rwq->ibwq.state = (wq_state == MLX5_RQC_STATE_ERR) ? IB_WQS_ERR : wq_state;
6177
Noa Osherovichb1f74a82017-01-18 15:40:02 +02006178out:
6179 kvfree(in);
Yishai Hadas79b20a62016-05-23 15:20:50 +03006180 return err;
6181}
Yishai Hadasd0e84c02018-06-19 10:43:55 +03006182
6183struct mlx5_ib_drain_cqe {
6184 struct ib_cqe cqe;
6185 struct completion done;
6186};
6187
6188static void mlx5_ib_drain_qp_done(struct ib_cq *cq, struct ib_wc *wc)
6189{
6190 struct mlx5_ib_drain_cqe *cqe = container_of(wc->wr_cqe,
6191 struct mlx5_ib_drain_cqe,
6192 cqe);
6193
6194 complete(&cqe->done);
6195}
6196
6197/* This function returns only once the drained WR was completed */
6198static void handle_drain_completion(struct ib_cq *cq,
6199 struct mlx5_ib_drain_cqe *sdrain,
6200 struct mlx5_ib_dev *dev)
6201{
6202 struct mlx5_core_dev *mdev = dev->mdev;
6203
6204 if (cq->poll_ctx == IB_POLL_DIRECT) {
6205 while (wait_for_completion_timeout(&sdrain->done, HZ / 10) <= 0)
6206 ib_process_cq_direct(cq, -1);
6207 return;
6208 }
6209
6210 if (mdev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR) {
6211 struct mlx5_ib_cq *mcq = to_mcq(cq);
6212 bool triggered = false;
6213 unsigned long flags;
6214
6215 spin_lock_irqsave(&dev->reset_flow_resource_lock, flags);
6216 /* Make sure that the CQ handler won't run if wasn't run yet */
6217 if (!mcq->mcq.reset_notify_added)
6218 mcq->mcq.reset_notify_added = 1;
6219 else
6220 triggered = true;
6221 spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags);
6222
6223 if (triggered) {
6224 /* Wait for any scheduled/running task to be ended */
6225 switch (cq->poll_ctx) {
6226 case IB_POLL_SOFTIRQ:
6227 irq_poll_disable(&cq->iop);
6228 irq_poll_enable(&cq->iop);
6229 break;
6230 case IB_POLL_WORKQUEUE:
6231 cancel_work_sync(&cq->work);
6232 break;
6233 default:
6234 WARN_ON_ONCE(1);
6235 }
6236 }
6237
6238 /* Run the CQ handler - this makes sure that the drain WR will
6239 * be processed if wasn't processed yet.
6240 */
6241 mcq->mcq.comp(&mcq->mcq);
6242 }
6243
6244 wait_for_completion(&sdrain->done);
6245}
6246
6247void mlx5_ib_drain_sq(struct ib_qp *qp)
6248{
6249 struct ib_cq *cq = qp->send_cq;
6250 struct ib_qp_attr attr = { .qp_state = IB_QPS_ERR };
6251 struct mlx5_ib_drain_cqe sdrain;
Bart Van Assched34ac5c2018-07-18 09:25:32 -07006252 const struct ib_send_wr *bad_swr;
Yishai Hadasd0e84c02018-06-19 10:43:55 +03006253 struct ib_rdma_wr swr = {
6254 .wr = {
6255 .next = NULL,
6256 { .wr_cqe = &sdrain.cqe, },
6257 .opcode = IB_WR_RDMA_WRITE,
6258 },
6259 };
6260 int ret;
6261 struct mlx5_ib_dev *dev = to_mdev(qp->device);
6262 struct mlx5_core_dev *mdev = dev->mdev;
6263
6264 ret = ib_modify_qp(qp, &attr, IB_QP_STATE);
6265 if (ret && mdev->state != MLX5_DEVICE_STATE_INTERNAL_ERROR) {
6266 WARN_ONCE(ret, "failed to drain send queue: %d\n", ret);
6267 return;
6268 }
6269
6270 sdrain.cqe.done = mlx5_ib_drain_qp_done;
6271 init_completion(&sdrain.done);
6272
6273 ret = _mlx5_ib_post_send(qp, &swr.wr, &bad_swr, true);
6274 if (ret) {
6275 WARN_ONCE(ret, "failed to drain send queue: %d\n", ret);
6276 return;
6277 }
6278
6279 handle_drain_completion(cq, &sdrain, dev);
6280}
6281
6282void mlx5_ib_drain_rq(struct ib_qp *qp)
6283{
6284 struct ib_cq *cq = qp->recv_cq;
6285 struct ib_qp_attr attr = { .qp_state = IB_QPS_ERR };
6286 struct mlx5_ib_drain_cqe rdrain;
Bart Van Assched34ac5c2018-07-18 09:25:32 -07006287 struct ib_recv_wr rwr = {};
6288 const struct ib_recv_wr *bad_rwr;
Yishai Hadasd0e84c02018-06-19 10:43:55 +03006289 int ret;
6290 struct mlx5_ib_dev *dev = to_mdev(qp->device);
6291 struct mlx5_core_dev *mdev = dev->mdev;
6292
6293 ret = ib_modify_qp(qp, &attr, IB_QP_STATE);
6294 if (ret && mdev->state != MLX5_DEVICE_STATE_INTERNAL_ERROR) {
6295 WARN_ONCE(ret, "failed to drain recv queue: %d\n", ret);
6296 return;
6297 }
6298
6299 rwr.wr_cqe = &rdrain.cqe;
6300 rdrain.cqe.done = mlx5_ib_drain_qp_done;
6301 init_completion(&rdrain.done);
6302
6303 ret = _mlx5_ib_post_recv(qp, &rwr, &bad_rwr, true);
6304 if (ret) {
6305 WARN_ONCE(ret, "failed to drain recv queue: %d\n", ret);
6306 return;
6307 }
6308
6309 handle_drain_completion(cq, &rdrain, dev);
6310}