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Thomas Gleixnerc51669e2019-05-31 01:09:37 -07001// SPDX-License-Identifier: GPL-2.0-only
Paul Mundt739d3402008-02-06 01:38:44 -08002/*
3 * Dallas DS1302 RTC Support
4 *
Alessandro Zummo2bfc3302009-08-20 12:31:49 +09005 * Copyright (C) 2002 David McCullough
6 * Copyright (C) 2003 - 2007 Paul Mundt
Paul Mundt739d3402008-02-06 01:38:44 -08007 */
Alessandro Zummo2bfc3302009-08-20 12:31:49 +09008
Paul Mundt739d3402008-02-06 01:38:44 -08009#include <linux/bcd.h>
Sergey Yanovichd25a5ed2016-02-23 13:54:57 +030010#include <linux/init.h>
11#include <linux/io.h>
12#include <linux/kernel.h>
13#include <linux/module.h>
14#include <linux/of.h>
15#include <linux/rtc.h>
16#include <linux/spi/spi.h>
Paul Mundt739d3402008-02-06 01:38:44 -080017
Paul Mundt739d3402008-02-06 01:38:44 -080018#define RTC_CMD_READ 0x81 /* Read command */
19#define RTC_CMD_WRITE 0x80 /* Write command */
20
Sergey Yanovichdfc657b2013-07-03 15:07:46 -070021#define RTC_CMD_WRITE_ENABLE 0x00 /* Write enable */
22#define RTC_CMD_WRITE_DISABLE 0x80 /* Write disable */
23
Paul Mundt739d3402008-02-06 01:38:44 -080024#define RTC_ADDR_RAM0 0x20 /* Address of RAM0 */
25#define RTC_ADDR_TCR 0x08 /* Address of trickle charge register */
Sergey Yanovichd25a5ed2016-02-23 13:54:57 +030026#define RTC_CLCK_BURST 0x1F /* Address of clock burst */
27#define RTC_CLCK_LEN 0x08 /* Size of clock burst */
Sergey Yanovichdfc657b2013-07-03 15:07:46 -070028#define RTC_ADDR_CTRL 0x07 /* Address of control register */
Paul Mundt739d3402008-02-06 01:38:44 -080029#define RTC_ADDR_YEAR 0x06 /* Address of year register */
30#define RTC_ADDR_DAY 0x05 /* Address of day of week register */
31#define RTC_ADDR_MON 0x04 /* Address of month register */
32#define RTC_ADDR_DATE 0x03 /* Address of day of month register */
33#define RTC_ADDR_HOUR 0x02 /* Address of hour register */
34#define RTC_ADDR_MIN 0x01 /* Address of minute register */
35#define RTC_ADDR_SEC 0x00 /* Address of second register */
36
Sergey Yanovichd25a5ed2016-02-23 13:54:57 +030037static int ds1302_rtc_set_time(struct device *dev, struct rtc_time *time)
Marc Zyngier72cc8e52010-05-24 14:33:47 -070038{
Sergey Yanovichd25a5ed2016-02-23 13:54:57 +030039 struct spi_device *spi = dev_get_drvdata(dev);
40 u8 buf[1 + RTC_CLCK_LEN];
Colin Ian King5134d2f2018-01-23 10:17:27 +000041 u8 *bp;
Sergey Yanovichd25a5ed2016-02-23 13:54:57 +030042 int status;
43
44 /* Enable writing */
45 bp = buf;
46 *bp++ = RTC_ADDR_CTRL << 1 | RTC_CMD_WRITE;
47 *bp++ = RTC_CMD_WRITE_ENABLE;
48
49 status = spi_write_then_read(spi, buf, 2,
50 NULL, 0);
Akinobu Mitabc83a142016-04-10 23:59:23 +090051 if (status)
Sergey Yanovichd25a5ed2016-02-23 13:54:57 +030052 return status;
53
54 /* Write registers starting at the first time/date address. */
55 bp = buf;
56 *bp++ = RTC_CLCK_BURST << 1 | RTC_CMD_WRITE;
57
58 *bp++ = bin2bcd(time->tm_sec);
59 *bp++ = bin2bcd(time->tm_min);
60 *bp++ = bin2bcd(time->tm_hour);
61 *bp++ = bin2bcd(time->tm_mday);
62 *bp++ = bin2bcd(time->tm_mon + 1);
Akinobu Mitaef50f862016-04-10 23:59:24 +090063 *bp++ = time->tm_wday + 1;
Sergey Yanovichd25a5ed2016-02-23 13:54:57 +030064 *bp++ = bin2bcd(time->tm_year % 100);
65 *bp++ = RTC_CMD_WRITE_DISABLE;
66
67 /* use write-then-read since dma from stack is nonportable */
68 return spi_write_then_read(spi, buf, sizeof(buf),
69 NULL, 0);
Marc Zyngier72cc8e52010-05-24 14:33:47 -070070}
71
Sergey Yanovichd25a5ed2016-02-23 13:54:57 +030072static int ds1302_rtc_get_time(struct device *dev, struct rtc_time *time)
Marc Zyngier72cc8e52010-05-24 14:33:47 -070073{
Sergey Yanovichd25a5ed2016-02-23 13:54:57 +030074 struct spi_device *spi = dev_get_drvdata(dev);
75 u8 addr = RTC_CLCK_BURST << 1 | RTC_CMD_READ;
76 u8 buf[RTC_CLCK_LEN - 1];
77 int status;
Marc Zyngier72cc8e52010-05-24 14:33:47 -070078
Sergey Yanovichd25a5ed2016-02-23 13:54:57 +030079 /* Use write-then-read to get all the date/time registers
80 * since dma from stack is nonportable
81 */
82 status = spi_write_then_read(spi, &addr, sizeof(addr),
83 buf, sizeof(buf));
84 if (status < 0)
85 return status;
Marc Zyngier72cc8e52010-05-24 14:33:47 -070086
Sergey Yanovichd25a5ed2016-02-23 13:54:57 +030087 /* Decode the registers */
88 time->tm_sec = bcd2bin(buf[RTC_ADDR_SEC]);
89 time->tm_min = bcd2bin(buf[RTC_ADDR_MIN]);
90 time->tm_hour = bcd2bin(buf[RTC_ADDR_HOUR]);
91 time->tm_wday = buf[RTC_ADDR_DAY] - 1;
92 time->tm_mday = bcd2bin(buf[RTC_ADDR_DATE]);
93 time->tm_mon = bcd2bin(buf[RTC_ADDR_MON]) - 1;
94 time->tm_year = bcd2bin(buf[RTC_ADDR_YEAR]) + 100;
Marc Zyngier72cc8e52010-05-24 14:33:47 -070095
Alexandre Belloni22652ba2018-02-19 16:23:56 +010096 return 0;
Paul Mundt739d3402008-02-06 01:38:44 -080097}
98
Julia Lawall34c7b3a2016-08-31 10:05:25 +020099static const struct rtc_class_ops ds1302_rtc_ops = {
Sergey Yanovichd25a5ed2016-02-23 13:54:57 +0300100 .read_time = ds1302_rtc_get_time,
Paul Mundt739d3402008-02-06 01:38:44 -0800101 .set_time = ds1302_rtc_set_time,
Paul Mundt739d3402008-02-06 01:38:44 -0800102};
103
Sergey Yanovichd25a5ed2016-02-23 13:54:57 +0300104static int ds1302_probe(struct spi_device *spi)
Paul Mundt739d3402008-02-06 01:38:44 -0800105{
Sergey Yanovichd25a5ed2016-02-23 13:54:57 +0300106 struct rtc_device *rtc;
107 u8 addr;
108 u8 buf[4];
Colin Ian King5134d2f2018-01-23 10:17:27 +0000109 u8 *bp;
Sergey Yanovichd25a5ed2016-02-23 13:54:57 +0300110 int status;
Paul Mundt739d3402008-02-06 01:38:44 -0800111
Sergey Yanovichd25a5ed2016-02-23 13:54:57 +0300112 /* Sanity check board setup data. This may be hooked up
113 * in 3wire mode, but we don't care. Note that unless
114 * there's an inverter in place, this needs SPI_CS_HIGH!
115 */
116 if (spi->bits_per_word && (spi->bits_per_word != 8)) {
117 dev_err(&spi->dev, "bad word length\n");
118 return -EINVAL;
119 } else if (spi->max_speed_hz > 2000000) {
120 dev_err(&spi->dev, "speed is too high\n");
121 return -EINVAL;
122 } else if (spi->mode & SPI_CPHA) {
123 dev_err(&spi->dev, "bad mode\n");
Marc Zyngier72cc8e52010-05-24 14:33:47 -0700124 return -EINVAL;
125 }
126
Sergey Yanovichd25a5ed2016-02-23 13:54:57 +0300127 addr = RTC_ADDR_CTRL << 1 | RTC_CMD_READ;
128 status = spi_write_then_read(spi, &addr, sizeof(addr), buf, 1);
129 if (status < 0) {
130 dev_err(&spi->dev, "control register read error %d\n",
131 status);
132 return status;
Marc Zyngier72cc8e52010-05-24 14:33:47 -0700133 }
Paul Mundt739d3402008-02-06 01:38:44 -0800134
Sergey Yanovichd25a5ed2016-02-23 13:54:57 +0300135 if ((buf[0] & ~RTC_CMD_WRITE_DISABLE) != 0) {
136 status = spi_write_then_read(spi, &addr, sizeof(addr), buf, 1);
137 if (status < 0) {
138 dev_err(&spi->dev, "control register read error %d\n",
139 status);
140 return status;
141 }
Paul Mundt739d3402008-02-06 01:38:44 -0800142
Sergey Yanovichd25a5ed2016-02-23 13:54:57 +0300143 if ((buf[0] & ~RTC_CMD_WRITE_DISABLE) != 0) {
144 dev_err(&spi->dev, "junk in control register\n");
145 return -ENODEV;
146 }
147 }
148 if (buf[0] == 0) {
149 bp = buf;
150 *bp++ = RTC_ADDR_CTRL << 1 | RTC_CMD_WRITE;
151 *bp++ = RTC_CMD_WRITE_DISABLE;
152
153 status = spi_write_then_read(spi, buf, 2, NULL, 0);
154 if (status < 0) {
155 dev_err(&spi->dev, "control register write error %d\n",
156 status);
157 return status;
158 }
159
160 addr = RTC_ADDR_CTRL << 1 | RTC_CMD_READ;
161 status = spi_write_then_read(spi, &addr, sizeof(addr), buf, 1);
162 if (status < 0) {
163 dev_err(&spi->dev,
164 "error %d reading control register\n",
165 status);
166 return status;
167 }
168
169 if (buf[0] != RTC_CMD_WRITE_DISABLE) {
170 dev_err(&spi->dev, "failed to detect chip\n");
171 return -ENODEV;
172 }
173 }
174
175 spi_set_drvdata(spi, spi);
176
177 rtc = devm_rtc_device_register(&spi->dev, "ds1302",
178 &ds1302_rtc_ops, THIS_MODULE);
179 if (IS_ERR(rtc)) {
180 status = PTR_ERR(rtc);
181 dev_err(&spi->dev, "error %d registering rtc\n", status);
182 return status;
183 }
Paul Mundt739d3402008-02-06 01:38:44 -0800184
185 return 0;
Paul Mundt739d3402008-02-06 01:38:44 -0800186}
187
Sergey Yanovichd25a5ed2016-02-23 13:54:57 +0300188static int ds1302_remove(struct spi_device *spi)
189{
190 spi_set_drvdata(spi, NULL);
191 return 0;
192}
193
194#ifdef CONFIG_OF
195static const struct of_device_id ds1302_dt_ids[] = {
196 { .compatible = "maxim,ds1302", },
197 { /* sentinel */ }
198};
199MODULE_DEVICE_TABLE(of, ds1302_dt_ids);
200#endif
201
Mark Brown8719a172021-09-23 20:49:20 +0100202static const struct spi_device_id ds1302_spi_ids[] = {
203 { .name = "ds1302", },
204 { /* sentinel */ }
205};
206MODULE_DEVICE_TABLE(spi, ds1302_spi_ids);
207
Sergey Yanovichd25a5ed2016-02-23 13:54:57 +0300208static struct spi_driver ds1302_driver = {
209 .driver.name = "rtc-ds1302",
210 .driver.of_match_table = of_match_ptr(ds1302_dt_ids),
211 .probe = ds1302_probe,
212 .remove = ds1302_remove,
Mark Brown8719a172021-09-23 20:49:20 +0100213 .id_table = ds1302_spi_ids,
Paul Mundt739d3402008-02-06 01:38:44 -0800214};
215
Sergey Yanovichd25a5ed2016-02-23 13:54:57 +0300216module_spi_driver(ds1302_driver);
Paul Mundt739d3402008-02-06 01:38:44 -0800217
218MODULE_DESCRIPTION("Dallas DS1302 RTC driver");
Paul Mundt739d3402008-02-06 01:38:44 -0800219MODULE_AUTHOR("Paul Mundt, David McCullough");
220MODULE_LICENSE("GPL v2");