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Thomas Gleixnerec8f24b2019-05-19 13:07:45 +01001# SPDX-License-Identifier: GPL-2.0-only
Aneesh V7ec94452012-04-27 17:54:05 +05302#
3# Memory devices
4#
5
6menuconfig MEMORY
7 bool "Memory Controller drivers"
Krzysztof Kozlowski2664a072020-07-24 09:40:37 +02008 help
9 This option allows to enable specific memory controller drivers,
10 useful mostly on embedded systems. These could be controllers
11 for DRAM (SDR, DDR), ROM, SRAM and others. The drivers features
12 vary from memory tuning and frequency scaling to enabling
13 access to attached peripherals through memory bus.
Aneesh V7ec94452012-04-27 17:54:05 +053014
15if MEMORY
16
Masahiro Yamada7b43b8f2019-06-03 17:12:32 +090017config DDR
18 bool
19 help
20 Data from JEDEC specs for DDR SDRAM memories,
21 particularly the AC timing parameters and addressing
22 information. This data is useful for drivers handling
23 DDR SDRAM controllers.
24
Joachim Eastwood17c50b72015-07-13 23:20:11 +020025config ARM_PL172_MPMC
26 tristate "ARM PL172 MPMC driver"
27 depends on ARM_AMBA && OF
28 help
29 This selects the ARM PrimeCell PL172 MultiPort Memory Controller.
30 If you have an embedded system with an AMBA bus and a PL172
31 controller, say Y or M here.
32
Alexandre Bellonie81b6ab2014-07-08 18:21:12 +020033config ATMEL_SDRAMC
34 bool "Atmel (Multi-port DDR-)SDRAM Controller"
Krzysztof Kozlowskiea0c0ad2020-07-24 09:40:15 +020035 default y if ARCH_AT91
36 depends on ARCH_AT91 || COMPILE_TEST
37 depends on OF
Alexandre Bellonie81b6ab2014-07-08 18:21:12 +020038 help
39 This driver is for Atmel SDRAM Controller or Atmel Multi-port
40 DDR-SDRAM Controller available on Atmel AT91SAM9 and SAMA5 SoCs.
41 Starting with the at91sam9g45, this controller supports SDR, DDR and
42 LP-DDR memories.
43
Boris Brezillon6a4ec4c2016-05-23 09:44:54 +020044config ATMEL_EBI
45 bool "Atmel EBI driver"
Krzysztof Kozlowskiea0c0ad2020-07-24 09:40:15 +020046 default y if ARCH_AT91
47 depends on ARCH_AT91 || COMPILE_TEST
48 depends on OF
Boris Brezillon6a4ec4c2016-05-23 09:44:54 +020049 select MFD_SYSCON
Boris Brezillon8eb8c7d2017-03-16 09:30:29 +010050 select MFD_ATMEL_SMC
Boris Brezillon6a4ec4c2016-05-23 09:44:54 +020051 help
52 Driver for Atmel EBI controller.
53 Used to configure the EBI (external bus interface) when the device-
54 tree is used. This bus supports NANDs, external ethernet controller,
55 SRAMs, ATA devices, etc.
56
Krzysztof Kozlowski904ffa82020-07-24 19:40:16 +020057config BRCMSTB_DPFE
Florian Fainelli13f995c2021-09-23 20:14:59 -070058 tristate "Broadcom STB DPFE driver"
59 default ARCH_BRCMSTB
Krzysztof Kozlowski904ffa82020-07-24 19:40:16 +020060 depends on ARCH_BRCMSTB || COMPILE_TEST
61 help
62 This driver provides access to the DPFE interface of Broadcom
63 STB SoCs. The firmware running on the DCPU inside the DDR PHY can
64 provide current information about the system's RAM, for instance
65 the DRAM refresh rate. This can be used as an indirect indicator
66 for the DRAM's temperature. Slower refresh rate means cooler RAM,
67 higher refresh rate means hotter RAM.
68
Serge Semin83ca8b32020-05-26 15:59:28 +030069config BT1_L2_CTL
70 bool "Baikal-T1 CM2 L2-RAM Cache Control Block"
71 depends on MIPS_BAIKAL_T1 || COMPILE_TEST
72 select MFD_SYSCON
73 help
74 Baikal-T1 CPU is based on the MIPS P5600 Warrior IP-core. The CPU
75 resides Coherency Manager v2 with embedded 1MB L2-cache. It's
76 possible to tune the L2 cache performance up by setting the data,
77 tags and way-select latencies of RAM access. This driver provides a
78 dt properties-based and sysfs interface for it.
79
Ivan Khoronzhuk5a7c8152014-02-24 19:26:11 +020080config TI_AEMIF
81 tristate "Texas Instruments AEMIF driver"
Krzysztof Kozlowskiea0c0ad2020-07-24 09:40:15 +020082 depends on ARCH_DAVINCI || ARCH_KEYSTONE || COMPILE_TEST
83 depends on OF
Ivan Khoronzhuk5a7c8152014-02-24 19:26:11 +020084 help
85 This driver is for the AEMIF module available in Texas Instruments
86 SoCs. AEMIF stands for Asynchronous External Memory Interface and
87 is intended to provide a glue-less interface to a variety of
88 asynchronuous memory devices like ASRAM, NOR and NAND memory. A total
89 of 256M bytes of any of these memories can be accessed at a given
90 time via four chip selects with 64M byte access per chip select.
91
Aneesh V7ec94452012-04-27 17:54:05 +053092config TI_EMIF
93 tristate "Texas Instruments EMIF driver"
Krzysztof Kozlowskiea0c0ad2020-07-24 09:40:15 +020094 depends on ARCH_OMAP2PLUS || COMPILE_TEST
Aneesh V7ec94452012-04-27 17:54:05 +053095 select DDR
96 help
97 This driver is for the EMIF module available in Texas Instruments
98 SoCs. EMIF is an SDRAM controller that, based on its revision,
99 supports one or more of DDR2, DDR3, and LPDDR2 SDRAM protocols.
100 This driver takes care of only LPDDR2 memories presently. The
101 functions of the driver includes re-configuring AC timing
102 parameters and other settings during frequency, voltage and
103 temperature changes
104
Tony Lindgren18640192014-11-20 09:13:42 -0800105config OMAP_GPMC
Krzysztof Kozlowskiea0c0ad2020-07-24 09:40:15 +0200106 bool "Texas Instruments OMAP SoC GPMC driver" if COMPILE_TEST
Krzysztof Kozlowski26cb1d22020-09-11 16:32:51 +0200107 depends on OF_ADDRESS
Roger Quadrosd2d00862016-03-07 12:18:43 +0200108 select GPIOLIB
Tony Lindgren18640192014-11-20 09:13:42 -0800109 help
110 This driver is for the General Purpose Memory Controller (GPMC)
111 present on Texas Instruments SoCs (e.g. OMAP2+). GPMC allows
112 interfacing to a variety of asynchronous as well as synchronous
113 memory drives like NOR, NAND, OneNAND, SRAM.
114
Tony Lindgren63aa9452015-06-01 19:22:10 -0600115config OMAP_GPMC_DEBUG
Tony Lindgrenbe59b612015-10-12 16:19:54 -0700116 bool "Enable GPMC debug output and skip reset of GPMC during init"
Tony Lindgren63aa9452015-06-01 19:22:10 -0600117 depends on OMAP_GPMC
118 help
119 Enables verbose debugging mostly to decode the bootloader provided
Tony Lindgrenbe59b612015-10-12 16:19:54 -0700120 timings. To preserve the bootloader provided timings, the reset
121 of GPMC is skipped during init. Enable this during development to
122 configure devices connected to the GPMC bus.
123
124 NOTE: In addition to matching the register setup with the bootloader
125 you also need to match the GPMC FCLK frequency used by the
126 bootloader or else the GPMC timings won't be identical with the
127 bootloader timings.
Tony Lindgren63aa9452015-06-01 19:22:10 -0600128
Dave Gerlach8428e5a2015-06-17 14:52:10 -0500129config TI_EMIF_SRAM
130 tristate "Texas Instruments EMIF SRAM driver"
Arnd Bergmannd77d22d2020-12-04 00:08:14 +0100131 depends on SOC_AM33XX || SOC_AM43XX || (ARM && CPU_V7 && COMPILE_TEST)
Krzysztof Kozlowskiea0c0ad2020-07-24 09:40:15 +0200132 depends on SRAM
Dave Gerlach8428e5a2015-06-17 14:52:10 -0500133 help
134 This driver is for the EMIF module available on Texas Instruments
135 AM33XX and AM43XX SoCs and is required for PM. Certain parts of
136 the EMIF PM code must run from on-chip SRAM late in the suspend
137 sequence so this driver provides several relocatable PM functions
138 for the SoC PM code to use.
139
Xu Yilun477dfdc2021-01-06 20:37:14 -0800140config FPGA_DFL_EMIF
141 tristate "FPGA DFL EMIF Driver"
142 depends on FPGA_DFL && HAS_IOMEM
143 help
144 This driver is for the EMIF private feature implemented under
145 FPGA Device Feature List (DFL) framework. It is used to expose
146 memory interface status information as well as memory clearing
147 control.
148
Ezequiel Garcia3edad322013-04-23 16:21:26 -0300149config MVEBU_DEVBUS
150 bool "Marvell EBU Device Bus Controller"
Krzysztof Kozlowskiea0c0ad2020-07-24 09:40:15 +0200151 default y if PLAT_ORION
152 depends on PLAT_ORION || COMPILE_TEST
153 depends on OF
Ezequiel Garcia3edad322013-04-23 16:21:26 -0300154 help
155 This driver is for the Device Bus controller available in some
156 Marvell EBU SoCs such as Discovery (mv78xx0), Orion (88f5xxx) and
157 Armada 370 and Armada XP. This controller allows to handle flash
158 devices such as NOR, NAND, SRAM, and FPGA.
159
Scott Wood54afbec2014-07-02 18:52:11 -0500160config FSL_CORENET_CF
161 tristate "Freescale CoreNet Error Reporting"
Krzysztof Kozlowskiea0c0ad2020-07-24 09:40:15 +0200162 depends on FSL_SOC_BOOKE || COMPILE_TEST
Scott Wood54afbec2014-07-02 18:52:11 -0500163 help
164 Say Y for reporting of errors from the Freescale CoreNet
165 Coherency Fabric. Errors reported include accesses to
166 physical addresses that mapped by no local access window
167 (LAW) or an invalid LAW, as well as bad cache state that
168 represents a coherency violation.
169
Paul Gortmaker42d87b12014-02-19 17:46:40 -0500170config FSL_IFC
Krzysztof Kozlowskiea0c0ad2020-07-24 09:40:15 +0200171 bool "Freescale IFC driver" if COMPILE_TEST
Boris Brezillonb30a2bd2018-07-09 22:09:37 +0200172 depends on FSL_SOC || ARCH_LAYERSCAPE || SOC_LS1021A || COMPILE_TEST
173 depends on HAS_IOMEM
Paul Gortmaker42d87b12014-02-19 17:46:40 -0500174
Alex Smith911a8882015-03-09 14:29:04 +0000175config JZ4780_NEMC
176 bool "Ingenic JZ4780 SoC NEMC driver"
Paul Cercueil94b3a022019-06-04 16:30:16 +0200177 depends on MIPS || COMPILE_TEST
Anders Roxell16909c82018-07-25 11:19:28 +0200178 depends on HAS_IOMEM && OF
Alex Smith911a8882015-03-09 14:29:04 +0000179 help
180 This driver is for the NAND/External Memory Controller (NEMC) in
181 the Ingenic JZ4780. This controller is used to handle external
182 memory devices such as NAND and SRAM.
183
Yong Wucc8bbe12016-02-23 01:20:49 +0800184config MTK_SMI
Yong Wu50fc8d92021-01-26 14:00:55 +0800185 tristate "MediaTek SoC Memory Controller driver" if COMPILE_TEST
Yong Wucc8bbe12016-02-23 01:20:49 +0800186 depends on ARCH_MEDIATEK || COMPILE_TEST
187 help
188 This driver is for the Memory Controller module in MediaTek SoCs,
189 mainly help enable/disable iommu and control the power domain and
190 clocks for each local arbiter.
191
Bartosz Golaszewski62a8a732016-10-31 15:45:34 +0100192config DA8XX_DDRCTL
193 bool "Texas Instruments da8xx DDR2/mDDR driver"
Krzysztof Kozlowskiea0c0ad2020-07-24 09:40:15 +0200194 depends on ARCH_DAVINCI_DA8XX || COMPILE_TEST
Bartosz Golaszewski62a8a732016-10-31 15:45:34 +0100195 help
196 This driver is for the DDR2/mDDR Memory Controller present on
197 Texas Instruments da8xx SoCs. It's used to tweak various memory
198 controller configuration options.
199
Naga Sureshkumar Rellifee10bd2018-12-06 18:17:34 +0530200config PL353_SMC
201 tristate "ARM PL35X Static Memory Controller(SMC) driver"
Krzysztof Kozlowskiea0c0ad2020-07-24 09:40:15 +0200202 default y if ARM
Krzysztof Kozlowski5445a0c2020-10-29 20:33:57 +0100203 depends on ARM || COMPILE_TEST
204 depends on ARM_AMBA
Naga Sureshkumar Rellifee10bd2018-12-06 18:17:34 +0530205 help
206 This driver is for the ARM PL351/PL353 Static Memory
207 Controller(SMC) module.
208
Sergei Shtylyovca7d8b92020-06-16 23:03:48 +0300209config RENESAS_RPCIF
210 tristate "Renesas RPC-IF driver"
Krzysztof Kozlowskiea0c0ad2020-07-24 09:40:15 +0200211 depends on ARCH_RENESAS || COMPILE_TEST
Sergei Shtylyovca7d8b92020-06-16 23:03:48 +0300212 select REGMAP_MMIO
Geert Uytterhoeven4a26df82021-10-05 17:29:22 +0200213 select RESET_CONTROLLER
Sergei Shtylyovca7d8b92020-06-16 23:03:48 +0300214 help
Adam Ford409f9fe2021-01-02 05:54:10 -0600215 This supports Renesas R-Car Gen3 or RZ/G2 RPC-IF which provides
216 either SPI host or HyperFlash. You'll have to select individual
217 components under the corresponding menu.
Sergei Shtylyovca7d8b92020-06-16 23:03:48 +0300218
Christophe Kerello66b81732020-06-12 17:22:40 +0200219config STM32_FMC2_EBI
220 tristate "Support for FMC2 External Bus Interface on STM32MP SoCs"
221 depends on MACH_STM32MP157 || COMPILE_TEST
222 select MFD_SYSCON
223 help
224 Select this option to enable the STM32 FMC2 External Bus Interface
225 controller. This driver configures the transactions with external
226 devices (like SRAM, ethernet adapters, FPGAs, LCD displays, ...) on
227 SOCs containing the FMC2 External Bus Interface.
228
Pankaj Dubeya8aabb92016-04-11 13:12:24 +0530229source "drivers/memory/samsung/Kconfig"
Thierry Reding89184652014-04-16 09:24:44 +0200230source "drivers/memory/tegra/Kconfig"
231
Aneesh V7ec94452012-04-27 17:54:05 +0530232endif