Stephen Boyd | e1bd55e | 2018-12-11 09:57:48 -0800 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0 |
Prashant Gaikwad | ece7009 | 2013-03-20 17:30:34 +0530 | [diff] [blame] | 2 | /* |
| 3 | * Copyright (c) 2013 NVIDIA CORPORATION. All rights reserved. |
Prashant Gaikwad | ece7009 | 2013-03-20 17:30:34 +0530 | [diff] [blame] | 4 | */ |
| 5 | |
Prashant Gaikwad | ece7009 | 2013-03-20 17:30:34 +0530 | [diff] [blame] | 6 | #include <linux/clk-provider.h> |
Michael Walle | 0eba770 | 2020-11-05 20:27:45 +0100 | [diff] [blame] | 7 | #include <linux/device.h> |
Prashant Gaikwad | ece7009 | 2013-03-20 17:30:34 +0530 | [diff] [blame] | 8 | #include <linux/err.h> |
| 9 | #include <linux/slab.h> |
| 10 | |
Prashant Gaikwad | ece7009 | 2013-03-20 17:30:34 +0530 | [diff] [blame] | 11 | static u8 clk_composite_get_parent(struct clk_hw *hw) |
| 12 | { |
| 13 | struct clk_composite *composite = to_clk_composite(hw); |
| 14 | const struct clk_ops *mux_ops = composite->mux_ops; |
| 15 | struct clk_hw *mux_hw = composite->mux_hw; |
| 16 | |
Javier Martinez Canillas | 4e907ef | 2015-02-12 14:58:30 +0100 | [diff] [blame] | 17 | __clk_hw_set_clk(mux_hw, hw); |
Prashant Gaikwad | ece7009 | 2013-03-20 17:30:34 +0530 | [diff] [blame] | 18 | |
| 19 | return mux_ops->get_parent(mux_hw); |
| 20 | } |
| 21 | |
| 22 | static int clk_composite_set_parent(struct clk_hw *hw, u8 index) |
| 23 | { |
| 24 | struct clk_composite *composite = to_clk_composite(hw); |
| 25 | const struct clk_ops *mux_ops = composite->mux_ops; |
| 26 | struct clk_hw *mux_hw = composite->mux_hw; |
| 27 | |
Javier Martinez Canillas | 4e907ef | 2015-02-12 14:58:30 +0100 | [diff] [blame] | 28 | __clk_hw_set_clk(mux_hw, hw); |
Prashant Gaikwad | ece7009 | 2013-03-20 17:30:34 +0530 | [diff] [blame] | 29 | |
| 30 | return mux_ops->set_parent(mux_hw, index); |
| 31 | } |
| 32 | |
| 33 | static unsigned long clk_composite_recalc_rate(struct clk_hw *hw, |
| 34 | unsigned long parent_rate) |
| 35 | { |
| 36 | struct clk_composite *composite = to_clk_composite(hw); |
Mike Turquette | d3a1c7b | 2013-04-11 11:31:36 -0700 | [diff] [blame] | 37 | const struct clk_ops *rate_ops = composite->rate_ops; |
| 38 | struct clk_hw *rate_hw = composite->rate_hw; |
Prashant Gaikwad | ece7009 | 2013-03-20 17:30:34 +0530 | [diff] [blame] | 39 | |
Javier Martinez Canillas | 4e907ef | 2015-02-12 14:58:30 +0100 | [diff] [blame] | 40 | __clk_hw_set_clk(rate_hw, hw); |
Prashant Gaikwad | ece7009 | 2013-03-20 17:30:34 +0530 | [diff] [blame] | 41 | |
Mike Turquette | d3a1c7b | 2013-04-11 11:31:36 -0700 | [diff] [blame] | 42 | return rate_ops->recalc_rate(rate_hw, parent_rate); |
Prashant Gaikwad | ece7009 | 2013-03-20 17:30:34 +0530 | [diff] [blame] | 43 | } |
| 44 | |
Boris Brezillon | 0817b62 | 2015-07-07 20:48:08 +0200 | [diff] [blame] | 45 | static int clk_composite_determine_rate(struct clk_hw *hw, |
| 46 | struct clk_rate_request *req) |
Emilio López | 107f319 | 2013-09-14 21:37:59 -0300 | [diff] [blame] | 47 | { |
| 48 | struct clk_composite *composite = to_clk_composite(hw); |
| 49 | const struct clk_ops *rate_ops = composite->rate_ops; |
| 50 | const struct clk_ops *mux_ops = composite->mux_ops; |
| 51 | struct clk_hw *rate_hw = composite->rate_hw; |
| 52 | struct clk_hw *mux_hw = composite->mux_hw; |
Stephen Boyd | 2f508a9 | 2015-07-30 17:20:57 -0700 | [diff] [blame] | 53 | struct clk_hw *parent; |
Boris BREZILLON | 3eb635f | 2014-07-03 01:56:45 +0200 | [diff] [blame] | 54 | unsigned long parent_rate; |
| 55 | long tmp_rate, best_rate = 0; |
| 56 | unsigned long rate_diff; |
| 57 | unsigned long best_rate_diff = ULONG_MAX; |
Boris Brezillon | 0817b62 | 2015-07-07 20:48:08 +0200 | [diff] [blame] | 58 | long rate; |
Boris BREZILLON | 3eb635f | 2014-07-03 01:56:45 +0200 | [diff] [blame] | 59 | int i; |
Emilio López | 107f319 | 2013-09-14 21:37:59 -0300 | [diff] [blame] | 60 | |
| 61 | if (rate_hw && rate_ops && rate_ops->determine_rate) { |
Javier Martinez Canillas | 4e907ef | 2015-02-12 14:58:30 +0100 | [diff] [blame] | 62 | __clk_hw_set_clk(rate_hw, hw); |
Boris Brezillon | 0817b62 | 2015-07-07 20:48:08 +0200 | [diff] [blame] | 63 | return rate_ops->determine_rate(rate_hw, req); |
Boris BREZILLON | 3eb635f | 2014-07-03 01:56:45 +0200 | [diff] [blame] | 64 | } else if (rate_hw && rate_ops && rate_ops->round_rate && |
| 65 | mux_hw && mux_ops && mux_ops->set_parent) { |
Boris Brezillon | 0817b62 | 2015-07-07 20:48:08 +0200 | [diff] [blame] | 66 | req->best_parent_hw = NULL; |
Boris BREZILLON | 3eb635f | 2014-07-03 01:56:45 +0200 | [diff] [blame] | 67 | |
Stephen Boyd | 98d8a60 | 2015-06-29 16:56:30 -0700 | [diff] [blame] | 68 | if (clk_hw_get_flags(hw) & CLK_SET_RATE_NO_REPARENT) { |
Stephen Boyd | 2f508a9 | 2015-07-30 17:20:57 -0700 | [diff] [blame] | 69 | parent = clk_hw_get_parent(mux_hw); |
| 70 | req->best_parent_hw = parent; |
| 71 | req->best_parent_rate = clk_hw_get_rate(parent); |
Boris BREZILLON | 3eb635f | 2014-07-03 01:56:45 +0200 | [diff] [blame] | 72 | |
Boris Brezillon | 0817b62 | 2015-07-07 20:48:08 +0200 | [diff] [blame] | 73 | rate = rate_ops->round_rate(rate_hw, req->rate, |
| 74 | &req->best_parent_rate); |
| 75 | if (rate < 0) |
| 76 | return rate; |
| 77 | |
| 78 | req->rate = rate; |
| 79 | return 0; |
Boris BREZILLON | 3eb635f | 2014-07-03 01:56:45 +0200 | [diff] [blame] | 80 | } |
| 81 | |
Stephen Boyd | 497295a | 2015-06-25 16:53:23 -0700 | [diff] [blame] | 82 | for (i = 0; i < clk_hw_get_num_parents(mux_hw); i++) { |
Stephen Boyd | 2f508a9 | 2015-07-30 17:20:57 -0700 | [diff] [blame] | 83 | parent = clk_hw_get_parent_by_index(mux_hw, i); |
Boris BREZILLON | 3eb635f | 2014-07-03 01:56:45 +0200 | [diff] [blame] | 84 | if (!parent) |
| 85 | continue; |
| 86 | |
Stephen Boyd | 2f508a9 | 2015-07-30 17:20:57 -0700 | [diff] [blame] | 87 | parent_rate = clk_hw_get_rate(parent); |
Boris BREZILLON | 3eb635f | 2014-07-03 01:56:45 +0200 | [diff] [blame] | 88 | |
Boris Brezillon | 0817b62 | 2015-07-07 20:48:08 +0200 | [diff] [blame] | 89 | tmp_rate = rate_ops->round_rate(rate_hw, req->rate, |
Boris BREZILLON | 3eb635f | 2014-07-03 01:56:45 +0200 | [diff] [blame] | 90 | &parent_rate); |
| 91 | if (tmp_rate < 0) |
| 92 | continue; |
| 93 | |
Boris Brezillon | 0817b62 | 2015-07-07 20:48:08 +0200 | [diff] [blame] | 94 | rate_diff = abs(req->rate - tmp_rate); |
Boris BREZILLON | 3eb635f | 2014-07-03 01:56:45 +0200 | [diff] [blame] | 95 | |
Boris Brezillon | 0817b62 | 2015-07-07 20:48:08 +0200 | [diff] [blame] | 96 | if (!rate_diff || !req->best_parent_hw |
Boris BREZILLON | 3eb635f | 2014-07-03 01:56:45 +0200 | [diff] [blame] | 97 | || best_rate_diff > rate_diff) { |
Stephen Boyd | 2f508a9 | 2015-07-30 17:20:57 -0700 | [diff] [blame] | 98 | req->best_parent_hw = parent; |
Boris Brezillon | 0817b62 | 2015-07-07 20:48:08 +0200 | [diff] [blame] | 99 | req->best_parent_rate = parent_rate; |
Boris BREZILLON | 3eb635f | 2014-07-03 01:56:45 +0200 | [diff] [blame] | 100 | best_rate_diff = rate_diff; |
| 101 | best_rate = tmp_rate; |
| 102 | } |
| 103 | |
| 104 | if (!rate_diff) |
Boris Brezillon | 0817b62 | 2015-07-07 20:48:08 +0200 | [diff] [blame] | 105 | return 0; |
Boris BREZILLON | 3eb635f | 2014-07-03 01:56:45 +0200 | [diff] [blame] | 106 | } |
| 107 | |
Boris Brezillon | 0817b62 | 2015-07-07 20:48:08 +0200 | [diff] [blame] | 108 | req->rate = best_rate; |
| 109 | return 0; |
Emilio López | 107f319 | 2013-09-14 21:37:59 -0300 | [diff] [blame] | 110 | } else if (mux_hw && mux_ops && mux_ops->determine_rate) { |
Javier Martinez Canillas | 4e907ef | 2015-02-12 14:58:30 +0100 | [diff] [blame] | 111 | __clk_hw_set_clk(mux_hw, hw); |
Boris Brezillon | 0817b62 | 2015-07-07 20:48:08 +0200 | [diff] [blame] | 112 | return mux_ops->determine_rate(mux_hw, req); |
Emilio López | 107f319 | 2013-09-14 21:37:59 -0300 | [diff] [blame] | 113 | } else { |
| 114 | pr_err("clk: clk_composite_determine_rate function called, but no mux or rate callback set!\n"); |
Boris Brezillon | 57d866e | 2015-07-09 22:39:38 +0200 | [diff] [blame] | 115 | return -EINVAL; |
Emilio López | 107f319 | 2013-09-14 21:37:59 -0300 | [diff] [blame] | 116 | } |
| 117 | } |
| 118 | |
Prashant Gaikwad | ece7009 | 2013-03-20 17:30:34 +0530 | [diff] [blame] | 119 | static long clk_composite_round_rate(struct clk_hw *hw, unsigned long rate, |
| 120 | unsigned long *prate) |
| 121 | { |
| 122 | struct clk_composite *composite = to_clk_composite(hw); |
Mike Turquette | d3a1c7b | 2013-04-11 11:31:36 -0700 | [diff] [blame] | 123 | const struct clk_ops *rate_ops = composite->rate_ops; |
| 124 | struct clk_hw *rate_hw = composite->rate_hw; |
Prashant Gaikwad | ece7009 | 2013-03-20 17:30:34 +0530 | [diff] [blame] | 125 | |
Javier Martinez Canillas | 4e907ef | 2015-02-12 14:58:30 +0100 | [diff] [blame] | 126 | __clk_hw_set_clk(rate_hw, hw); |
Prashant Gaikwad | ece7009 | 2013-03-20 17:30:34 +0530 | [diff] [blame] | 127 | |
Mike Turquette | d3a1c7b | 2013-04-11 11:31:36 -0700 | [diff] [blame] | 128 | return rate_ops->round_rate(rate_hw, rate, prate); |
Prashant Gaikwad | ece7009 | 2013-03-20 17:30:34 +0530 | [diff] [blame] | 129 | } |
| 130 | |
| 131 | static int clk_composite_set_rate(struct clk_hw *hw, unsigned long rate, |
| 132 | unsigned long parent_rate) |
| 133 | { |
| 134 | struct clk_composite *composite = to_clk_composite(hw); |
Mike Turquette | d3a1c7b | 2013-04-11 11:31:36 -0700 | [diff] [blame] | 135 | const struct clk_ops *rate_ops = composite->rate_ops; |
| 136 | struct clk_hw *rate_hw = composite->rate_hw; |
Prashant Gaikwad | ece7009 | 2013-03-20 17:30:34 +0530 | [diff] [blame] | 137 | |
Javier Martinez Canillas | 4e907ef | 2015-02-12 14:58:30 +0100 | [diff] [blame] | 138 | __clk_hw_set_clk(rate_hw, hw); |
Prashant Gaikwad | ece7009 | 2013-03-20 17:30:34 +0530 | [diff] [blame] | 139 | |
Mike Turquette | d3a1c7b | 2013-04-11 11:31:36 -0700 | [diff] [blame] | 140 | return rate_ops->set_rate(rate_hw, rate, parent_rate); |
Prashant Gaikwad | ece7009 | 2013-03-20 17:30:34 +0530 | [diff] [blame] | 141 | } |
| 142 | |
Finley Xiao | 9e52cec | 2016-04-12 16:43:39 +0800 | [diff] [blame] | 143 | static int clk_composite_set_rate_and_parent(struct clk_hw *hw, |
| 144 | unsigned long rate, |
| 145 | unsigned long parent_rate, |
| 146 | u8 index) |
| 147 | { |
| 148 | struct clk_composite *composite = to_clk_composite(hw); |
| 149 | const struct clk_ops *rate_ops = composite->rate_ops; |
| 150 | const struct clk_ops *mux_ops = composite->mux_ops; |
| 151 | struct clk_hw *rate_hw = composite->rate_hw; |
| 152 | struct clk_hw *mux_hw = composite->mux_hw; |
| 153 | unsigned long temp_rate; |
| 154 | |
| 155 | __clk_hw_set_clk(rate_hw, hw); |
| 156 | __clk_hw_set_clk(mux_hw, hw); |
| 157 | |
| 158 | temp_rate = rate_ops->recalc_rate(rate_hw, parent_rate); |
| 159 | if (temp_rate > rate) { |
| 160 | rate_ops->set_rate(rate_hw, rate, parent_rate); |
| 161 | mux_ops->set_parent(mux_hw, index); |
| 162 | } else { |
| 163 | mux_ops->set_parent(mux_hw, index); |
| 164 | rate_ops->set_rate(rate_hw, rate, parent_rate); |
| 165 | } |
| 166 | |
| 167 | return 0; |
| 168 | } |
| 169 | |
Prashant Gaikwad | ece7009 | 2013-03-20 17:30:34 +0530 | [diff] [blame] | 170 | static int clk_composite_is_enabled(struct clk_hw *hw) |
| 171 | { |
| 172 | struct clk_composite *composite = to_clk_composite(hw); |
| 173 | const struct clk_ops *gate_ops = composite->gate_ops; |
| 174 | struct clk_hw *gate_hw = composite->gate_hw; |
| 175 | |
Javier Martinez Canillas | 4e907ef | 2015-02-12 14:58:30 +0100 | [diff] [blame] | 176 | __clk_hw_set_clk(gate_hw, hw); |
Prashant Gaikwad | ece7009 | 2013-03-20 17:30:34 +0530 | [diff] [blame] | 177 | |
| 178 | return gate_ops->is_enabled(gate_hw); |
| 179 | } |
| 180 | |
| 181 | static int clk_composite_enable(struct clk_hw *hw) |
| 182 | { |
| 183 | struct clk_composite *composite = to_clk_composite(hw); |
| 184 | const struct clk_ops *gate_ops = composite->gate_ops; |
| 185 | struct clk_hw *gate_hw = composite->gate_hw; |
| 186 | |
Javier Martinez Canillas | 4e907ef | 2015-02-12 14:58:30 +0100 | [diff] [blame] | 187 | __clk_hw_set_clk(gate_hw, hw); |
Prashant Gaikwad | ece7009 | 2013-03-20 17:30:34 +0530 | [diff] [blame] | 188 | |
| 189 | return gate_ops->enable(gate_hw); |
| 190 | } |
| 191 | |
| 192 | static void clk_composite_disable(struct clk_hw *hw) |
| 193 | { |
| 194 | struct clk_composite *composite = to_clk_composite(hw); |
| 195 | const struct clk_ops *gate_ops = composite->gate_ops; |
| 196 | struct clk_hw *gate_hw = composite->gate_hw; |
| 197 | |
Javier Martinez Canillas | 4e907ef | 2015-02-12 14:58:30 +0100 | [diff] [blame] | 198 | __clk_hw_set_clk(gate_hw, hw); |
Prashant Gaikwad | ece7009 | 2013-03-20 17:30:34 +0530 | [diff] [blame] | 199 | |
| 200 | gate_ops->disable(gate_hw); |
| 201 | } |
| 202 | |
Michael Walle | 73ef657 | 2020-01-03 00:10:59 +0100 | [diff] [blame] | 203 | static struct clk_hw *__clk_hw_register_composite(struct device *dev, |
| 204 | const char *name, const char * const *parent_names, |
| 205 | const struct clk_parent_data *pdata, int num_parents, |
Prashant Gaikwad | ece7009 | 2013-03-20 17:30:34 +0530 | [diff] [blame] | 206 | struct clk_hw *mux_hw, const struct clk_ops *mux_ops, |
Mike Turquette | d3a1c7b | 2013-04-11 11:31:36 -0700 | [diff] [blame] | 207 | struct clk_hw *rate_hw, const struct clk_ops *rate_ops, |
Prashant Gaikwad | ece7009 | 2013-03-20 17:30:34 +0530 | [diff] [blame] | 208 | struct clk_hw *gate_hw, const struct clk_ops *gate_ops, |
| 209 | unsigned long flags) |
| 210 | { |
Stephen Boyd | 49cb392 | 2016-02-07 00:20:31 -0800 | [diff] [blame] | 211 | struct clk_hw *hw; |
Manivannan Sadhasivam | cc819cf | 2019-11-15 21:58:55 +0530 | [diff] [blame] | 212 | struct clk_init_data init = {}; |
Prashant Gaikwad | ece7009 | 2013-03-20 17:30:34 +0530 | [diff] [blame] | 213 | struct clk_composite *composite; |
| 214 | struct clk_ops *clk_composite_ops; |
Stephen Boyd | 49cb392 | 2016-02-07 00:20:31 -0800 | [diff] [blame] | 215 | int ret; |
Prashant Gaikwad | ece7009 | 2013-03-20 17:30:34 +0530 | [diff] [blame] | 216 | |
| 217 | composite = kzalloc(sizeof(*composite), GFP_KERNEL); |
Stephen Boyd | d122db7 | 2015-05-14 16:47:10 -0700 | [diff] [blame] | 218 | if (!composite) |
Prashant Gaikwad | ece7009 | 2013-03-20 17:30:34 +0530 | [diff] [blame] | 219 | return ERR_PTR(-ENOMEM); |
Prashant Gaikwad | ece7009 | 2013-03-20 17:30:34 +0530 | [diff] [blame] | 220 | |
| 221 | init.name = name; |
Stephen Boyd | 90b6c5c | 2019-04-25 10:57:37 -0700 | [diff] [blame] | 222 | init.flags = flags; |
Michael Walle | 73ef657 | 2020-01-03 00:10:59 +0100 | [diff] [blame] | 223 | if (parent_names) |
| 224 | init.parent_names = parent_names; |
| 225 | else |
| 226 | init.parent_data = pdata; |
Prashant Gaikwad | ece7009 | 2013-03-20 17:30:34 +0530 | [diff] [blame] | 227 | init.num_parents = num_parents; |
Stephen Boyd | 49cb392 | 2016-02-07 00:20:31 -0800 | [diff] [blame] | 228 | hw = &composite->hw; |
Prashant Gaikwad | ece7009 | 2013-03-20 17:30:34 +0530 | [diff] [blame] | 229 | |
| 230 | clk_composite_ops = &composite->ops; |
| 231 | |
| 232 | if (mux_hw && mux_ops) { |
Heiko Stübner | 0c02cf2 | 2014-07-03 01:57:30 +0200 | [diff] [blame] | 233 | if (!mux_ops->get_parent) { |
Stephen Boyd | 49cb392 | 2016-02-07 00:20:31 -0800 | [diff] [blame] | 234 | hw = ERR_PTR(-EINVAL); |
Prashant Gaikwad | ece7009 | 2013-03-20 17:30:34 +0530 | [diff] [blame] | 235 | goto err; |
| 236 | } |
| 237 | |
| 238 | composite->mux_hw = mux_hw; |
| 239 | composite->mux_ops = mux_ops; |
| 240 | clk_composite_ops->get_parent = clk_composite_get_parent; |
Heiko Stübner | 0c02cf2 | 2014-07-03 01:57:30 +0200 | [diff] [blame] | 241 | if (mux_ops->set_parent) |
| 242 | clk_composite_ops->set_parent = clk_composite_set_parent; |
Emilio López | 107f319 | 2013-09-14 21:37:59 -0300 | [diff] [blame] | 243 | if (mux_ops->determine_rate) |
| 244 | clk_composite_ops->determine_rate = clk_composite_determine_rate; |
Prashant Gaikwad | ece7009 | 2013-03-20 17:30:34 +0530 | [diff] [blame] | 245 | } |
| 246 | |
Mike Turquette | d3a1c7b | 2013-04-11 11:31:36 -0700 | [diff] [blame] | 247 | if (rate_hw && rate_ops) { |
Mike Turquette | f363e21 | 2013-04-11 11:31:37 -0700 | [diff] [blame] | 248 | if (!rate_ops->recalc_rate) { |
Stephen Boyd | 49cb392 | 2016-02-07 00:20:31 -0800 | [diff] [blame] | 249 | hw = ERR_PTR(-EINVAL); |
Prashant Gaikwad | ece7009 | 2013-03-20 17:30:34 +0530 | [diff] [blame] | 250 | goto err; |
| 251 | } |
Mike Turquette | 5a994e1 | 2014-07-03 01:58:14 +0200 | [diff] [blame] | 252 | clk_composite_ops->recalc_rate = clk_composite_recalc_rate; |
Prashant Gaikwad | ece7009 | 2013-03-20 17:30:34 +0530 | [diff] [blame] | 253 | |
Mike Turquette | 5a994e1 | 2014-07-03 01:58:14 +0200 | [diff] [blame] | 254 | if (rate_ops->determine_rate) |
| 255 | clk_composite_ops->determine_rate = |
| 256 | clk_composite_determine_rate; |
| 257 | else if (rate_ops->round_rate) |
| 258 | clk_composite_ops->round_rate = |
| 259 | clk_composite_round_rate; |
| 260 | |
| 261 | /* .set_rate requires either .round_rate or .determine_rate */ |
| 262 | if (rate_ops->set_rate) { |
| 263 | if (rate_ops->determine_rate || rate_ops->round_rate) |
| 264 | clk_composite_ops->set_rate = |
| 265 | clk_composite_set_rate; |
| 266 | else |
| 267 | WARN(1, "%s: missing round_rate op is required\n", |
| 268 | __func__); |
Mike Turquette | f363e21 | 2013-04-11 11:31:37 -0700 | [diff] [blame] | 269 | } |
| 270 | |
Mike Turquette | d3a1c7b | 2013-04-11 11:31:36 -0700 | [diff] [blame] | 271 | composite->rate_hw = rate_hw; |
| 272 | composite->rate_ops = rate_ops; |
Prashant Gaikwad | ece7009 | 2013-03-20 17:30:34 +0530 | [diff] [blame] | 273 | } |
| 274 | |
Finley Xiao | 9e52cec | 2016-04-12 16:43:39 +0800 | [diff] [blame] | 275 | if (mux_hw && mux_ops && rate_hw && rate_ops) { |
| 276 | if (mux_ops->set_parent && rate_ops->set_rate) |
| 277 | clk_composite_ops->set_rate_and_parent = |
| 278 | clk_composite_set_rate_and_parent; |
| 279 | } |
| 280 | |
Prashant Gaikwad | ece7009 | 2013-03-20 17:30:34 +0530 | [diff] [blame] | 281 | if (gate_hw && gate_ops) { |
| 282 | if (!gate_ops->is_enabled || !gate_ops->enable || |
| 283 | !gate_ops->disable) { |
Stephen Boyd | 49cb392 | 2016-02-07 00:20:31 -0800 | [diff] [blame] | 284 | hw = ERR_PTR(-EINVAL); |
Prashant Gaikwad | ece7009 | 2013-03-20 17:30:34 +0530 | [diff] [blame] | 285 | goto err; |
| 286 | } |
| 287 | |
| 288 | composite->gate_hw = gate_hw; |
| 289 | composite->gate_ops = gate_ops; |
| 290 | clk_composite_ops->is_enabled = clk_composite_is_enabled; |
| 291 | clk_composite_ops->enable = clk_composite_enable; |
| 292 | clk_composite_ops->disable = clk_composite_disable; |
| 293 | } |
| 294 | |
| 295 | init.ops = clk_composite_ops; |
| 296 | composite->hw.init = &init; |
| 297 | |
Stephen Boyd | 49cb392 | 2016-02-07 00:20:31 -0800 | [diff] [blame] | 298 | ret = clk_hw_register(dev, hw); |
| 299 | if (ret) { |
| 300 | hw = ERR_PTR(ret); |
Prashant Gaikwad | ece7009 | 2013-03-20 17:30:34 +0530 | [diff] [blame] | 301 | goto err; |
Stephen Boyd | 49cb392 | 2016-02-07 00:20:31 -0800 | [diff] [blame] | 302 | } |
Prashant Gaikwad | ece7009 | 2013-03-20 17:30:34 +0530 | [diff] [blame] | 303 | |
| 304 | if (composite->mux_hw) |
Stephen Boyd | 49cb392 | 2016-02-07 00:20:31 -0800 | [diff] [blame] | 305 | composite->mux_hw->clk = hw->clk; |
Prashant Gaikwad | ece7009 | 2013-03-20 17:30:34 +0530 | [diff] [blame] | 306 | |
Mike Turquette | d3a1c7b | 2013-04-11 11:31:36 -0700 | [diff] [blame] | 307 | if (composite->rate_hw) |
Stephen Boyd | 49cb392 | 2016-02-07 00:20:31 -0800 | [diff] [blame] | 308 | composite->rate_hw->clk = hw->clk; |
Prashant Gaikwad | ece7009 | 2013-03-20 17:30:34 +0530 | [diff] [blame] | 309 | |
| 310 | if (composite->gate_hw) |
Stephen Boyd | 49cb392 | 2016-02-07 00:20:31 -0800 | [diff] [blame] | 311 | composite->gate_hw->clk = hw->clk; |
Prashant Gaikwad | ece7009 | 2013-03-20 17:30:34 +0530 | [diff] [blame] | 312 | |
Stephen Boyd | 49cb392 | 2016-02-07 00:20:31 -0800 | [diff] [blame] | 313 | return hw; |
Prashant Gaikwad | ece7009 | 2013-03-20 17:30:34 +0530 | [diff] [blame] | 314 | |
| 315 | err: |
| 316 | kfree(composite); |
Stephen Boyd | 49cb392 | 2016-02-07 00:20:31 -0800 | [diff] [blame] | 317 | return hw; |
| 318 | } |
| 319 | |
Michael Walle | 73ef657 | 2020-01-03 00:10:59 +0100 | [diff] [blame] | 320 | struct clk_hw *clk_hw_register_composite(struct device *dev, const char *name, |
| 321 | const char * const *parent_names, int num_parents, |
| 322 | struct clk_hw *mux_hw, const struct clk_ops *mux_ops, |
| 323 | struct clk_hw *rate_hw, const struct clk_ops *rate_ops, |
| 324 | struct clk_hw *gate_hw, const struct clk_ops *gate_ops, |
| 325 | unsigned long flags) |
| 326 | { |
| 327 | return __clk_hw_register_composite(dev, name, parent_names, NULL, |
| 328 | num_parents, mux_hw, mux_ops, |
| 329 | rate_hw, rate_ops, gate_hw, |
| 330 | gate_ops, flags); |
| 331 | } |
Anson Huang | d7d7518 | 2020-07-30 09:22:50 +0800 | [diff] [blame] | 332 | EXPORT_SYMBOL_GPL(clk_hw_register_composite); |
Michael Walle | 73ef657 | 2020-01-03 00:10:59 +0100 | [diff] [blame] | 333 | |
| 334 | struct clk_hw *clk_hw_register_composite_pdata(struct device *dev, |
| 335 | const char *name, |
| 336 | const struct clk_parent_data *parent_data, |
| 337 | int num_parents, |
| 338 | struct clk_hw *mux_hw, const struct clk_ops *mux_ops, |
| 339 | struct clk_hw *rate_hw, const struct clk_ops *rate_ops, |
| 340 | struct clk_hw *gate_hw, const struct clk_ops *gate_ops, |
| 341 | unsigned long flags) |
| 342 | { |
| 343 | return __clk_hw_register_composite(dev, name, NULL, parent_data, |
| 344 | num_parents, mux_hw, mux_ops, |
| 345 | rate_hw, rate_ops, gate_hw, |
| 346 | gate_ops, flags); |
| 347 | } |
| 348 | |
Stephen Boyd | 49cb392 | 2016-02-07 00:20:31 -0800 | [diff] [blame] | 349 | struct clk *clk_register_composite(struct device *dev, const char *name, |
| 350 | const char * const *parent_names, int num_parents, |
| 351 | struct clk_hw *mux_hw, const struct clk_ops *mux_ops, |
| 352 | struct clk_hw *rate_hw, const struct clk_ops *rate_ops, |
| 353 | struct clk_hw *gate_hw, const struct clk_ops *gate_ops, |
| 354 | unsigned long flags) |
| 355 | { |
| 356 | struct clk_hw *hw; |
| 357 | |
| 358 | hw = clk_hw_register_composite(dev, name, parent_names, num_parents, |
| 359 | mux_hw, mux_ops, rate_hw, rate_ops, gate_hw, gate_ops, |
| 360 | flags); |
| 361 | if (IS_ERR(hw)) |
| 362 | return ERR_CAST(hw); |
| 363 | return hw->clk; |
Prashant Gaikwad | ece7009 | 2013-03-20 17:30:34 +0530 | [diff] [blame] | 364 | } |
Maxime Ripard | 92a39d9 | 2016-03-23 17:38:24 +0100 | [diff] [blame] | 365 | |
Michael Walle | 73ef657 | 2020-01-03 00:10:59 +0100 | [diff] [blame] | 366 | struct clk *clk_register_composite_pdata(struct device *dev, const char *name, |
| 367 | const struct clk_parent_data *parent_data, |
| 368 | int num_parents, |
| 369 | struct clk_hw *mux_hw, const struct clk_ops *mux_ops, |
| 370 | struct clk_hw *rate_hw, const struct clk_ops *rate_ops, |
| 371 | struct clk_hw *gate_hw, const struct clk_ops *gate_ops, |
| 372 | unsigned long flags) |
| 373 | { |
| 374 | struct clk_hw *hw; |
| 375 | |
| 376 | hw = clk_hw_register_composite_pdata(dev, name, parent_data, |
| 377 | num_parents, mux_hw, mux_ops, rate_hw, rate_ops, |
| 378 | gate_hw, gate_ops, flags); |
| 379 | if (IS_ERR(hw)) |
| 380 | return ERR_CAST(hw); |
| 381 | return hw->clk; |
| 382 | } |
| 383 | |
Maxime Ripard | 92a39d9 | 2016-03-23 17:38:24 +0100 | [diff] [blame] | 384 | void clk_unregister_composite(struct clk *clk) |
| 385 | { |
| 386 | struct clk_composite *composite; |
| 387 | struct clk_hw *hw; |
| 388 | |
| 389 | hw = __clk_get_hw(clk); |
| 390 | if (!hw) |
| 391 | return; |
| 392 | |
| 393 | composite = to_clk_composite(hw); |
| 394 | |
| 395 | clk_unregister(clk); |
| 396 | kfree(composite); |
| 397 | } |
Manivannan Sadhasivam | d8549bc | 2019-11-15 21:58:56 +0530 | [diff] [blame] | 398 | |
| 399 | void clk_hw_unregister_composite(struct clk_hw *hw) |
| 400 | { |
| 401 | struct clk_composite *composite; |
| 402 | |
| 403 | composite = to_clk_composite(hw); |
| 404 | |
| 405 | clk_hw_unregister(hw); |
| 406 | kfree(composite); |
| 407 | } |
| 408 | EXPORT_SYMBOL_GPL(clk_hw_unregister_composite); |
Michael Walle | 0eba770 | 2020-11-05 20:27:45 +0100 | [diff] [blame] | 409 | |
| 410 | static void devm_clk_hw_release_composite(struct device *dev, void *res) |
| 411 | { |
| 412 | clk_hw_unregister_composite(*(struct clk_hw **)res); |
| 413 | } |
| 414 | |
| 415 | static struct clk_hw *__devm_clk_hw_register_composite(struct device *dev, |
| 416 | const char *name, const char * const *parent_names, |
| 417 | const struct clk_parent_data *pdata, int num_parents, |
| 418 | struct clk_hw *mux_hw, const struct clk_ops *mux_ops, |
| 419 | struct clk_hw *rate_hw, const struct clk_ops *rate_ops, |
| 420 | struct clk_hw *gate_hw, const struct clk_ops *gate_ops, |
| 421 | unsigned long flags) |
| 422 | { |
| 423 | struct clk_hw **ptr, *hw; |
| 424 | |
| 425 | ptr = devres_alloc(devm_clk_hw_release_composite, sizeof(*ptr), |
| 426 | GFP_KERNEL); |
| 427 | if (!ptr) |
| 428 | return ERR_PTR(-ENOMEM); |
| 429 | |
| 430 | hw = __clk_hw_register_composite(dev, name, parent_names, pdata, |
| 431 | num_parents, mux_hw, mux_ops, rate_hw, |
| 432 | rate_ops, gate_hw, gate_ops, flags); |
| 433 | |
| 434 | if (!IS_ERR(hw)) { |
| 435 | *ptr = hw; |
| 436 | devres_add(dev, ptr); |
| 437 | } else { |
| 438 | devres_free(ptr); |
| 439 | } |
| 440 | |
| 441 | return hw; |
| 442 | } |
| 443 | |
| 444 | struct clk_hw *devm_clk_hw_register_composite_pdata(struct device *dev, |
| 445 | const char *name, |
| 446 | const struct clk_parent_data *parent_data, |
| 447 | int num_parents, |
| 448 | struct clk_hw *mux_hw, const struct clk_ops *mux_ops, |
| 449 | struct clk_hw *rate_hw, const struct clk_ops *rate_ops, |
| 450 | struct clk_hw *gate_hw, const struct clk_ops *gate_ops, |
| 451 | unsigned long flags) |
| 452 | { |
| 453 | return __devm_clk_hw_register_composite(dev, name, NULL, parent_data, |
| 454 | num_parents, mux_hw, mux_ops, |
| 455 | rate_hw, rate_ops, gate_hw, |
| 456 | gate_ops, flags); |
| 457 | } |