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Stephen Boyde1bd55e2018-12-11 09:57:48 -08001// SPDX-License-Identifier: GPL-2.0
Prashant Gaikwadece70092013-03-20 17:30:34 +05302/*
3 * Copyright (c) 2013 NVIDIA CORPORATION. All rights reserved.
Prashant Gaikwadece70092013-03-20 17:30:34 +05304 */
5
Prashant Gaikwadece70092013-03-20 17:30:34 +05306#include <linux/clk-provider.h>
Michael Walle0eba7702020-11-05 20:27:45 +01007#include <linux/device.h>
Prashant Gaikwadece70092013-03-20 17:30:34 +05308#include <linux/err.h>
9#include <linux/slab.h>
10
Prashant Gaikwadece70092013-03-20 17:30:34 +053011static u8 clk_composite_get_parent(struct clk_hw *hw)
12{
13 struct clk_composite *composite = to_clk_composite(hw);
14 const struct clk_ops *mux_ops = composite->mux_ops;
15 struct clk_hw *mux_hw = composite->mux_hw;
16
Javier Martinez Canillas4e907ef2015-02-12 14:58:30 +010017 __clk_hw_set_clk(mux_hw, hw);
Prashant Gaikwadece70092013-03-20 17:30:34 +053018
19 return mux_ops->get_parent(mux_hw);
20}
21
22static int clk_composite_set_parent(struct clk_hw *hw, u8 index)
23{
24 struct clk_composite *composite = to_clk_composite(hw);
25 const struct clk_ops *mux_ops = composite->mux_ops;
26 struct clk_hw *mux_hw = composite->mux_hw;
27
Javier Martinez Canillas4e907ef2015-02-12 14:58:30 +010028 __clk_hw_set_clk(mux_hw, hw);
Prashant Gaikwadece70092013-03-20 17:30:34 +053029
30 return mux_ops->set_parent(mux_hw, index);
31}
32
33static unsigned long clk_composite_recalc_rate(struct clk_hw *hw,
34 unsigned long parent_rate)
35{
36 struct clk_composite *composite = to_clk_composite(hw);
Mike Turquetted3a1c7b2013-04-11 11:31:36 -070037 const struct clk_ops *rate_ops = composite->rate_ops;
38 struct clk_hw *rate_hw = composite->rate_hw;
Prashant Gaikwadece70092013-03-20 17:30:34 +053039
Javier Martinez Canillas4e907ef2015-02-12 14:58:30 +010040 __clk_hw_set_clk(rate_hw, hw);
Prashant Gaikwadece70092013-03-20 17:30:34 +053041
Mike Turquetted3a1c7b2013-04-11 11:31:36 -070042 return rate_ops->recalc_rate(rate_hw, parent_rate);
Prashant Gaikwadece70092013-03-20 17:30:34 +053043}
44
Boris Brezillon0817b622015-07-07 20:48:08 +020045static int clk_composite_determine_rate(struct clk_hw *hw,
46 struct clk_rate_request *req)
Emilio López107f3192013-09-14 21:37:59 -030047{
48 struct clk_composite *composite = to_clk_composite(hw);
49 const struct clk_ops *rate_ops = composite->rate_ops;
50 const struct clk_ops *mux_ops = composite->mux_ops;
51 struct clk_hw *rate_hw = composite->rate_hw;
52 struct clk_hw *mux_hw = composite->mux_hw;
Stephen Boyd2f508a92015-07-30 17:20:57 -070053 struct clk_hw *parent;
Boris BREZILLON3eb635f2014-07-03 01:56:45 +020054 unsigned long parent_rate;
55 long tmp_rate, best_rate = 0;
56 unsigned long rate_diff;
57 unsigned long best_rate_diff = ULONG_MAX;
Boris Brezillon0817b622015-07-07 20:48:08 +020058 long rate;
Boris BREZILLON3eb635f2014-07-03 01:56:45 +020059 int i;
Emilio López107f3192013-09-14 21:37:59 -030060
61 if (rate_hw && rate_ops && rate_ops->determine_rate) {
Javier Martinez Canillas4e907ef2015-02-12 14:58:30 +010062 __clk_hw_set_clk(rate_hw, hw);
Boris Brezillon0817b622015-07-07 20:48:08 +020063 return rate_ops->determine_rate(rate_hw, req);
Boris BREZILLON3eb635f2014-07-03 01:56:45 +020064 } else if (rate_hw && rate_ops && rate_ops->round_rate &&
65 mux_hw && mux_ops && mux_ops->set_parent) {
Boris Brezillon0817b622015-07-07 20:48:08 +020066 req->best_parent_hw = NULL;
Boris BREZILLON3eb635f2014-07-03 01:56:45 +020067
Stephen Boyd98d8a602015-06-29 16:56:30 -070068 if (clk_hw_get_flags(hw) & CLK_SET_RATE_NO_REPARENT) {
Stephen Boyd2f508a92015-07-30 17:20:57 -070069 parent = clk_hw_get_parent(mux_hw);
70 req->best_parent_hw = parent;
71 req->best_parent_rate = clk_hw_get_rate(parent);
Boris BREZILLON3eb635f2014-07-03 01:56:45 +020072
Boris Brezillon0817b622015-07-07 20:48:08 +020073 rate = rate_ops->round_rate(rate_hw, req->rate,
74 &req->best_parent_rate);
75 if (rate < 0)
76 return rate;
77
78 req->rate = rate;
79 return 0;
Boris BREZILLON3eb635f2014-07-03 01:56:45 +020080 }
81
Stephen Boyd497295a2015-06-25 16:53:23 -070082 for (i = 0; i < clk_hw_get_num_parents(mux_hw); i++) {
Stephen Boyd2f508a92015-07-30 17:20:57 -070083 parent = clk_hw_get_parent_by_index(mux_hw, i);
Boris BREZILLON3eb635f2014-07-03 01:56:45 +020084 if (!parent)
85 continue;
86
Stephen Boyd2f508a92015-07-30 17:20:57 -070087 parent_rate = clk_hw_get_rate(parent);
Boris BREZILLON3eb635f2014-07-03 01:56:45 +020088
Boris Brezillon0817b622015-07-07 20:48:08 +020089 tmp_rate = rate_ops->round_rate(rate_hw, req->rate,
Boris BREZILLON3eb635f2014-07-03 01:56:45 +020090 &parent_rate);
91 if (tmp_rate < 0)
92 continue;
93
Boris Brezillon0817b622015-07-07 20:48:08 +020094 rate_diff = abs(req->rate - tmp_rate);
Boris BREZILLON3eb635f2014-07-03 01:56:45 +020095
Boris Brezillon0817b622015-07-07 20:48:08 +020096 if (!rate_diff || !req->best_parent_hw
Boris BREZILLON3eb635f2014-07-03 01:56:45 +020097 || best_rate_diff > rate_diff) {
Stephen Boyd2f508a92015-07-30 17:20:57 -070098 req->best_parent_hw = parent;
Boris Brezillon0817b622015-07-07 20:48:08 +020099 req->best_parent_rate = parent_rate;
Boris BREZILLON3eb635f2014-07-03 01:56:45 +0200100 best_rate_diff = rate_diff;
101 best_rate = tmp_rate;
102 }
103
104 if (!rate_diff)
Boris Brezillon0817b622015-07-07 20:48:08 +0200105 return 0;
Boris BREZILLON3eb635f2014-07-03 01:56:45 +0200106 }
107
Boris Brezillon0817b622015-07-07 20:48:08 +0200108 req->rate = best_rate;
109 return 0;
Emilio López107f3192013-09-14 21:37:59 -0300110 } else if (mux_hw && mux_ops && mux_ops->determine_rate) {
Javier Martinez Canillas4e907ef2015-02-12 14:58:30 +0100111 __clk_hw_set_clk(mux_hw, hw);
Boris Brezillon0817b622015-07-07 20:48:08 +0200112 return mux_ops->determine_rate(mux_hw, req);
Emilio López107f3192013-09-14 21:37:59 -0300113 } else {
114 pr_err("clk: clk_composite_determine_rate function called, but no mux or rate callback set!\n");
Boris Brezillon57d866e2015-07-09 22:39:38 +0200115 return -EINVAL;
Emilio López107f3192013-09-14 21:37:59 -0300116 }
117}
118
Prashant Gaikwadece70092013-03-20 17:30:34 +0530119static long clk_composite_round_rate(struct clk_hw *hw, unsigned long rate,
120 unsigned long *prate)
121{
122 struct clk_composite *composite = to_clk_composite(hw);
Mike Turquetted3a1c7b2013-04-11 11:31:36 -0700123 const struct clk_ops *rate_ops = composite->rate_ops;
124 struct clk_hw *rate_hw = composite->rate_hw;
Prashant Gaikwadece70092013-03-20 17:30:34 +0530125
Javier Martinez Canillas4e907ef2015-02-12 14:58:30 +0100126 __clk_hw_set_clk(rate_hw, hw);
Prashant Gaikwadece70092013-03-20 17:30:34 +0530127
Mike Turquetted3a1c7b2013-04-11 11:31:36 -0700128 return rate_ops->round_rate(rate_hw, rate, prate);
Prashant Gaikwadece70092013-03-20 17:30:34 +0530129}
130
131static int clk_composite_set_rate(struct clk_hw *hw, unsigned long rate,
132 unsigned long parent_rate)
133{
134 struct clk_composite *composite = to_clk_composite(hw);
Mike Turquetted3a1c7b2013-04-11 11:31:36 -0700135 const struct clk_ops *rate_ops = composite->rate_ops;
136 struct clk_hw *rate_hw = composite->rate_hw;
Prashant Gaikwadece70092013-03-20 17:30:34 +0530137
Javier Martinez Canillas4e907ef2015-02-12 14:58:30 +0100138 __clk_hw_set_clk(rate_hw, hw);
Prashant Gaikwadece70092013-03-20 17:30:34 +0530139
Mike Turquetted3a1c7b2013-04-11 11:31:36 -0700140 return rate_ops->set_rate(rate_hw, rate, parent_rate);
Prashant Gaikwadece70092013-03-20 17:30:34 +0530141}
142
Finley Xiao9e52cec2016-04-12 16:43:39 +0800143static int clk_composite_set_rate_and_parent(struct clk_hw *hw,
144 unsigned long rate,
145 unsigned long parent_rate,
146 u8 index)
147{
148 struct clk_composite *composite = to_clk_composite(hw);
149 const struct clk_ops *rate_ops = composite->rate_ops;
150 const struct clk_ops *mux_ops = composite->mux_ops;
151 struct clk_hw *rate_hw = composite->rate_hw;
152 struct clk_hw *mux_hw = composite->mux_hw;
153 unsigned long temp_rate;
154
155 __clk_hw_set_clk(rate_hw, hw);
156 __clk_hw_set_clk(mux_hw, hw);
157
158 temp_rate = rate_ops->recalc_rate(rate_hw, parent_rate);
159 if (temp_rate > rate) {
160 rate_ops->set_rate(rate_hw, rate, parent_rate);
161 mux_ops->set_parent(mux_hw, index);
162 } else {
163 mux_ops->set_parent(mux_hw, index);
164 rate_ops->set_rate(rate_hw, rate, parent_rate);
165 }
166
167 return 0;
168}
169
Prashant Gaikwadece70092013-03-20 17:30:34 +0530170static int clk_composite_is_enabled(struct clk_hw *hw)
171{
172 struct clk_composite *composite = to_clk_composite(hw);
173 const struct clk_ops *gate_ops = composite->gate_ops;
174 struct clk_hw *gate_hw = composite->gate_hw;
175
Javier Martinez Canillas4e907ef2015-02-12 14:58:30 +0100176 __clk_hw_set_clk(gate_hw, hw);
Prashant Gaikwadece70092013-03-20 17:30:34 +0530177
178 return gate_ops->is_enabled(gate_hw);
179}
180
181static int clk_composite_enable(struct clk_hw *hw)
182{
183 struct clk_composite *composite = to_clk_composite(hw);
184 const struct clk_ops *gate_ops = composite->gate_ops;
185 struct clk_hw *gate_hw = composite->gate_hw;
186
Javier Martinez Canillas4e907ef2015-02-12 14:58:30 +0100187 __clk_hw_set_clk(gate_hw, hw);
Prashant Gaikwadece70092013-03-20 17:30:34 +0530188
189 return gate_ops->enable(gate_hw);
190}
191
192static void clk_composite_disable(struct clk_hw *hw)
193{
194 struct clk_composite *composite = to_clk_composite(hw);
195 const struct clk_ops *gate_ops = composite->gate_ops;
196 struct clk_hw *gate_hw = composite->gate_hw;
197
Javier Martinez Canillas4e907ef2015-02-12 14:58:30 +0100198 __clk_hw_set_clk(gate_hw, hw);
Prashant Gaikwadece70092013-03-20 17:30:34 +0530199
200 gate_ops->disable(gate_hw);
201}
202
Michael Walle73ef6572020-01-03 00:10:59 +0100203static struct clk_hw *__clk_hw_register_composite(struct device *dev,
204 const char *name, const char * const *parent_names,
205 const struct clk_parent_data *pdata, int num_parents,
Prashant Gaikwadece70092013-03-20 17:30:34 +0530206 struct clk_hw *mux_hw, const struct clk_ops *mux_ops,
Mike Turquetted3a1c7b2013-04-11 11:31:36 -0700207 struct clk_hw *rate_hw, const struct clk_ops *rate_ops,
Prashant Gaikwadece70092013-03-20 17:30:34 +0530208 struct clk_hw *gate_hw, const struct clk_ops *gate_ops,
209 unsigned long flags)
210{
Stephen Boyd49cb3922016-02-07 00:20:31 -0800211 struct clk_hw *hw;
Manivannan Sadhasivamcc819cf2019-11-15 21:58:55 +0530212 struct clk_init_data init = {};
Prashant Gaikwadece70092013-03-20 17:30:34 +0530213 struct clk_composite *composite;
214 struct clk_ops *clk_composite_ops;
Stephen Boyd49cb3922016-02-07 00:20:31 -0800215 int ret;
Prashant Gaikwadece70092013-03-20 17:30:34 +0530216
217 composite = kzalloc(sizeof(*composite), GFP_KERNEL);
Stephen Boydd122db72015-05-14 16:47:10 -0700218 if (!composite)
Prashant Gaikwadece70092013-03-20 17:30:34 +0530219 return ERR_PTR(-ENOMEM);
Prashant Gaikwadece70092013-03-20 17:30:34 +0530220
221 init.name = name;
Stephen Boyd90b6c5c2019-04-25 10:57:37 -0700222 init.flags = flags;
Michael Walle73ef6572020-01-03 00:10:59 +0100223 if (parent_names)
224 init.parent_names = parent_names;
225 else
226 init.parent_data = pdata;
Prashant Gaikwadece70092013-03-20 17:30:34 +0530227 init.num_parents = num_parents;
Stephen Boyd49cb3922016-02-07 00:20:31 -0800228 hw = &composite->hw;
Prashant Gaikwadece70092013-03-20 17:30:34 +0530229
230 clk_composite_ops = &composite->ops;
231
232 if (mux_hw && mux_ops) {
Heiko Stübner0c02cf22014-07-03 01:57:30 +0200233 if (!mux_ops->get_parent) {
Stephen Boyd49cb3922016-02-07 00:20:31 -0800234 hw = ERR_PTR(-EINVAL);
Prashant Gaikwadece70092013-03-20 17:30:34 +0530235 goto err;
236 }
237
238 composite->mux_hw = mux_hw;
239 composite->mux_ops = mux_ops;
240 clk_composite_ops->get_parent = clk_composite_get_parent;
Heiko Stübner0c02cf22014-07-03 01:57:30 +0200241 if (mux_ops->set_parent)
242 clk_composite_ops->set_parent = clk_composite_set_parent;
Emilio López107f3192013-09-14 21:37:59 -0300243 if (mux_ops->determine_rate)
244 clk_composite_ops->determine_rate = clk_composite_determine_rate;
Prashant Gaikwadece70092013-03-20 17:30:34 +0530245 }
246
Mike Turquetted3a1c7b2013-04-11 11:31:36 -0700247 if (rate_hw && rate_ops) {
Mike Turquettef363e212013-04-11 11:31:37 -0700248 if (!rate_ops->recalc_rate) {
Stephen Boyd49cb3922016-02-07 00:20:31 -0800249 hw = ERR_PTR(-EINVAL);
Prashant Gaikwadece70092013-03-20 17:30:34 +0530250 goto err;
251 }
Mike Turquette5a994e12014-07-03 01:58:14 +0200252 clk_composite_ops->recalc_rate = clk_composite_recalc_rate;
Prashant Gaikwadece70092013-03-20 17:30:34 +0530253
Mike Turquette5a994e12014-07-03 01:58:14 +0200254 if (rate_ops->determine_rate)
255 clk_composite_ops->determine_rate =
256 clk_composite_determine_rate;
257 else if (rate_ops->round_rate)
258 clk_composite_ops->round_rate =
259 clk_composite_round_rate;
260
261 /* .set_rate requires either .round_rate or .determine_rate */
262 if (rate_ops->set_rate) {
263 if (rate_ops->determine_rate || rate_ops->round_rate)
264 clk_composite_ops->set_rate =
265 clk_composite_set_rate;
266 else
267 WARN(1, "%s: missing round_rate op is required\n",
268 __func__);
Mike Turquettef363e212013-04-11 11:31:37 -0700269 }
270
Mike Turquetted3a1c7b2013-04-11 11:31:36 -0700271 composite->rate_hw = rate_hw;
272 composite->rate_ops = rate_ops;
Prashant Gaikwadece70092013-03-20 17:30:34 +0530273 }
274
Finley Xiao9e52cec2016-04-12 16:43:39 +0800275 if (mux_hw && mux_ops && rate_hw && rate_ops) {
276 if (mux_ops->set_parent && rate_ops->set_rate)
277 clk_composite_ops->set_rate_and_parent =
278 clk_composite_set_rate_and_parent;
279 }
280
Prashant Gaikwadece70092013-03-20 17:30:34 +0530281 if (gate_hw && gate_ops) {
282 if (!gate_ops->is_enabled || !gate_ops->enable ||
283 !gate_ops->disable) {
Stephen Boyd49cb3922016-02-07 00:20:31 -0800284 hw = ERR_PTR(-EINVAL);
Prashant Gaikwadece70092013-03-20 17:30:34 +0530285 goto err;
286 }
287
288 composite->gate_hw = gate_hw;
289 composite->gate_ops = gate_ops;
290 clk_composite_ops->is_enabled = clk_composite_is_enabled;
291 clk_composite_ops->enable = clk_composite_enable;
292 clk_composite_ops->disable = clk_composite_disable;
293 }
294
295 init.ops = clk_composite_ops;
296 composite->hw.init = &init;
297
Stephen Boyd49cb3922016-02-07 00:20:31 -0800298 ret = clk_hw_register(dev, hw);
299 if (ret) {
300 hw = ERR_PTR(ret);
Prashant Gaikwadece70092013-03-20 17:30:34 +0530301 goto err;
Stephen Boyd49cb3922016-02-07 00:20:31 -0800302 }
Prashant Gaikwadece70092013-03-20 17:30:34 +0530303
304 if (composite->mux_hw)
Stephen Boyd49cb3922016-02-07 00:20:31 -0800305 composite->mux_hw->clk = hw->clk;
Prashant Gaikwadece70092013-03-20 17:30:34 +0530306
Mike Turquetted3a1c7b2013-04-11 11:31:36 -0700307 if (composite->rate_hw)
Stephen Boyd49cb3922016-02-07 00:20:31 -0800308 composite->rate_hw->clk = hw->clk;
Prashant Gaikwadece70092013-03-20 17:30:34 +0530309
310 if (composite->gate_hw)
Stephen Boyd49cb3922016-02-07 00:20:31 -0800311 composite->gate_hw->clk = hw->clk;
Prashant Gaikwadece70092013-03-20 17:30:34 +0530312
Stephen Boyd49cb3922016-02-07 00:20:31 -0800313 return hw;
Prashant Gaikwadece70092013-03-20 17:30:34 +0530314
315err:
316 kfree(composite);
Stephen Boyd49cb3922016-02-07 00:20:31 -0800317 return hw;
318}
319
Michael Walle73ef6572020-01-03 00:10:59 +0100320struct clk_hw *clk_hw_register_composite(struct device *dev, const char *name,
321 const char * const *parent_names, int num_parents,
322 struct clk_hw *mux_hw, const struct clk_ops *mux_ops,
323 struct clk_hw *rate_hw, const struct clk_ops *rate_ops,
324 struct clk_hw *gate_hw, const struct clk_ops *gate_ops,
325 unsigned long flags)
326{
327 return __clk_hw_register_composite(dev, name, parent_names, NULL,
328 num_parents, mux_hw, mux_ops,
329 rate_hw, rate_ops, gate_hw,
330 gate_ops, flags);
331}
Anson Huangd7d75182020-07-30 09:22:50 +0800332EXPORT_SYMBOL_GPL(clk_hw_register_composite);
Michael Walle73ef6572020-01-03 00:10:59 +0100333
334struct clk_hw *clk_hw_register_composite_pdata(struct device *dev,
335 const char *name,
336 const struct clk_parent_data *parent_data,
337 int num_parents,
338 struct clk_hw *mux_hw, const struct clk_ops *mux_ops,
339 struct clk_hw *rate_hw, const struct clk_ops *rate_ops,
340 struct clk_hw *gate_hw, const struct clk_ops *gate_ops,
341 unsigned long flags)
342{
343 return __clk_hw_register_composite(dev, name, NULL, parent_data,
344 num_parents, mux_hw, mux_ops,
345 rate_hw, rate_ops, gate_hw,
346 gate_ops, flags);
347}
348
Stephen Boyd49cb3922016-02-07 00:20:31 -0800349struct clk *clk_register_composite(struct device *dev, const char *name,
350 const char * const *parent_names, int num_parents,
351 struct clk_hw *mux_hw, const struct clk_ops *mux_ops,
352 struct clk_hw *rate_hw, const struct clk_ops *rate_ops,
353 struct clk_hw *gate_hw, const struct clk_ops *gate_ops,
354 unsigned long flags)
355{
356 struct clk_hw *hw;
357
358 hw = clk_hw_register_composite(dev, name, parent_names, num_parents,
359 mux_hw, mux_ops, rate_hw, rate_ops, gate_hw, gate_ops,
360 flags);
361 if (IS_ERR(hw))
362 return ERR_CAST(hw);
363 return hw->clk;
Prashant Gaikwadece70092013-03-20 17:30:34 +0530364}
Maxime Ripard92a39d92016-03-23 17:38:24 +0100365
Michael Walle73ef6572020-01-03 00:10:59 +0100366struct clk *clk_register_composite_pdata(struct device *dev, const char *name,
367 const struct clk_parent_data *parent_data,
368 int num_parents,
369 struct clk_hw *mux_hw, const struct clk_ops *mux_ops,
370 struct clk_hw *rate_hw, const struct clk_ops *rate_ops,
371 struct clk_hw *gate_hw, const struct clk_ops *gate_ops,
372 unsigned long flags)
373{
374 struct clk_hw *hw;
375
376 hw = clk_hw_register_composite_pdata(dev, name, parent_data,
377 num_parents, mux_hw, mux_ops, rate_hw, rate_ops,
378 gate_hw, gate_ops, flags);
379 if (IS_ERR(hw))
380 return ERR_CAST(hw);
381 return hw->clk;
382}
383
Maxime Ripard92a39d92016-03-23 17:38:24 +0100384void clk_unregister_composite(struct clk *clk)
385{
386 struct clk_composite *composite;
387 struct clk_hw *hw;
388
389 hw = __clk_get_hw(clk);
390 if (!hw)
391 return;
392
393 composite = to_clk_composite(hw);
394
395 clk_unregister(clk);
396 kfree(composite);
397}
Manivannan Sadhasivamd8549bc2019-11-15 21:58:56 +0530398
399void clk_hw_unregister_composite(struct clk_hw *hw)
400{
401 struct clk_composite *composite;
402
403 composite = to_clk_composite(hw);
404
405 clk_hw_unregister(hw);
406 kfree(composite);
407}
408EXPORT_SYMBOL_GPL(clk_hw_unregister_composite);
Michael Walle0eba7702020-11-05 20:27:45 +0100409
410static void devm_clk_hw_release_composite(struct device *dev, void *res)
411{
412 clk_hw_unregister_composite(*(struct clk_hw **)res);
413}
414
415static struct clk_hw *__devm_clk_hw_register_composite(struct device *dev,
416 const char *name, const char * const *parent_names,
417 const struct clk_parent_data *pdata, int num_parents,
418 struct clk_hw *mux_hw, const struct clk_ops *mux_ops,
419 struct clk_hw *rate_hw, const struct clk_ops *rate_ops,
420 struct clk_hw *gate_hw, const struct clk_ops *gate_ops,
421 unsigned long flags)
422{
423 struct clk_hw **ptr, *hw;
424
425 ptr = devres_alloc(devm_clk_hw_release_composite, sizeof(*ptr),
426 GFP_KERNEL);
427 if (!ptr)
428 return ERR_PTR(-ENOMEM);
429
430 hw = __clk_hw_register_composite(dev, name, parent_names, pdata,
431 num_parents, mux_hw, mux_ops, rate_hw,
432 rate_ops, gate_hw, gate_ops, flags);
433
434 if (!IS_ERR(hw)) {
435 *ptr = hw;
436 devres_add(dev, ptr);
437 } else {
438 devres_free(ptr);
439 }
440
441 return hw;
442}
443
444struct clk_hw *devm_clk_hw_register_composite_pdata(struct device *dev,
445 const char *name,
446 const struct clk_parent_data *parent_data,
447 int num_parents,
448 struct clk_hw *mux_hw, const struct clk_ops *mux_ops,
449 struct clk_hw *rate_hw, const struct clk_ops *rate_ops,
450 struct clk_hw *gate_hw, const struct clk_ops *gate_ops,
451 unsigned long flags)
452{
453 return __devm_clk_hw_register_composite(dev, name, NULL, parent_data,
454 num_parents, mux_hw, mux_ops,
455 rate_hw, rate_ops, gate_hw,
456 gate_ops, flags);
457}