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Vineet Gupta82fea5a2014-09-10 19:05:38 +05301/*
2 * ARConnect IP Support (Multi core enabler: Cross core IPI, RTC ...)
3 *
4 * Copyright (C) 2014-15 Synopsys, Inc. (www.synopsys.com)
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
Vineet Gupta2d7f5c42016-10-31 11:27:08 -070011#ifndef __SOC_ARC_MCIP_H
12#define __SOC_ARC_MCIP_H
Vineet Gupta82fea5a2014-09-10 19:05:38 +053013
Vineet Guptac33a6052016-10-31 11:09:34 -070014#include <soc/arc/aux.h>
Vineet Gupta82fea5a2014-09-10 19:05:38 +053015
16#define ARC_REG_MCIP_BCR 0x0d0
17#define ARC_REG_MCIP_CMD 0x600
18#define ARC_REG_MCIP_WDATA 0x601
19#define ARC_REG_MCIP_READBACK 0x602
20
21struct mcip_cmd {
22#ifdef CONFIG_CPU_BIG_ENDIAN
23 unsigned int pad:8, param:16, cmd:8;
24#else
25 unsigned int cmd:8, param:16, pad:8;
26#endif
27
28#define CMD_INTRPT_GENERATE_IRQ 0x01
29#define CMD_INTRPT_GENERATE_ACK 0x02
30#define CMD_INTRPT_READ_STATUS 0x03
31#define CMD_INTRPT_CHECK_SOURCE 0x04
32
33/* Semaphore Commands */
34#define CMD_SEMA_CLAIM_AND_READ 0x11
35#define CMD_SEMA_RELEASE 0x12
36
37#define CMD_DEBUG_SET_MASK 0x34
38#define CMD_DEBUG_SET_SELECT 0x36
39
Vineet Guptad584f0f2016-01-22 14:27:50 +053040#define CMD_GFRC_READ_LO 0x42
41#define CMD_GFRC_READ_HI 0x43
Vineet Gupta72d72882014-12-24 18:41:55 +053042
Vineet Gupta82fea5a2014-09-10 19:05:38 +053043#define CMD_IDU_ENABLE 0x71
44#define CMD_IDU_DISABLE 0x72
45#define CMD_IDU_SET_MODE 0x74
46#define CMD_IDU_SET_DEST 0x76
47#define CMD_IDU_SET_MASK 0x7C
48
49#define IDU_M_TRIG_LEVEL 0x0
50#define IDU_M_TRIG_EDGE 0x1
51
52#define IDU_M_DISTRI_RR 0x0
53#define IDU_M_DISTRI_DEST 0x2
54};
55
Vineet Gupta3ce0fef2016-09-29 10:00:14 -070056struct mcip_bcr {
57#ifdef CONFIG_CPU_BIG_ENDIAN
58 unsigned int pad3:8,
59 idu:1, llm:1, num_cores:6,
60 iocoh:1, gfrc:1, dbg:1, pad2:1,
61 msg:1, sem:1, ipi:1, pad:1,
62 ver:8;
63#else
64 unsigned int ver:8,
65 pad:1, ipi:1, sem:1, msg:1,
66 pad2:1, dbg:1, gfrc:1, iocoh:1,
67 num_cores:6, llm:1, idu:1,
68 pad3:8;
69#endif
70};
71
Vineet Gupta82fea5a2014-09-10 19:05:38 +053072/*
73 * MCIP programming model
74 *
75 * - Simple commands write {cmd:8,param:16} to MCIP_CMD aux reg
76 * (param could be irq, common_irq, core_id ...)
77 * - More involved commands setup MCIP_WDATA with cmd specific data
78 * before invoking the simple command
79 */
80static inline void __mcip_cmd(unsigned int cmd, unsigned int param)
81{
82 struct mcip_cmd buf;
83
84 buf.pad = 0;
85 buf.cmd = cmd;
86 buf.param = param;
87
88 WRITE_AUX(ARC_REG_MCIP_CMD, buf);
89}
90
91/*
92 * Setup additional data for a cmd
93 * Callers need to lock to ensure atomicity
94 */
95static inline void __mcip_cmd_data(unsigned int cmd, unsigned int param,
96 unsigned int data)
97{
98 write_aux_reg(ARC_REG_MCIP_WDATA, data);
99
100 __mcip_cmd(cmd, param);
101}
102
Vineet Gupta82fea5a2014-09-10 19:05:38 +0530103#endif