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Jingchang Luc9e2e942013-06-07 09:20:40 +08001* Freescale low power universal asynchronous receiver/transmitter (lpuart)
2
3Required properties:
Jingchang Lu876496b2014-07-14 17:41:10 +08004- compatible :
5 - "fsl,vf610-lpuart" for lpuart compatible with the one integrated
6 on Vybrid vf610 SoC with 8-bit register organization
7 - "fsl,ls1021a-lpuart" for lpuart compatible with the one integrated
8 on LS1021A SoC with 32-bit big-endian register organization
Dong Aishengf2422fe2017-06-13 10:55:51 +08009 - "fsl,imx7ulp-lpuart" for lpuart compatible with the one integrated
10 on i.MX7ULP SoC with 32-bit little-endian register organization
Jingchang Luc9e2e942013-06-07 09:20:40 +080011- reg : Address and length of the register set for the device
12- interrupts : Should contain uart interrupt
Yuan Yao12f28782014-02-17 13:28:08 +080013- clocks : phandle + clock specifier pairs, one for each entry in clock-names
14- clock-names : should contain: "ipg" - the uart clock
Jingchang Luc9e2e942013-06-07 09:20:40 +080015
Yuan Yaof1cd8c82014-02-17 13:28:07 +080016Optional properties:
17- dmas: A list of two dma specifiers, one for each entry in dma-names.
18- dma-names: should contain "tx" and "rx".
19
20Note: Optional properties for DMA support. Write them both or both not.
21
Jingchang Luc9e2e942013-06-07 09:20:40 +080022Example:
23
24uart0: serial@40027000 {
Yuan Yaof1cd8c82014-02-17 13:28:07 +080025 compatible = "fsl,vf610-lpuart";
26 reg = <0x40027000 0x1000>;
27 interrupts = <0 61 0x00>;
Yuan Yao12f28782014-02-17 13:28:08 +080028 clocks = <&clks VF610_CLK_UART0>;
29 clock-names = "ipg";
Yuan Yaof1cd8c82014-02-17 13:28:07 +080030 dmas = <&edma0 0 2>,
31 <&edma0 0 3>;
32 dma-names = "rx","tx";
33 };