| Oder Chiou | 2b26dd4 | 2016-09-19 19:26:08 +0800 | [diff] [blame] | 1 | /* |
| 2 | * rt5660.h -- RT5660 ALSA SoC audio driver |
| 3 | * |
| 4 | * Copyright 2016 Realtek Semiconductor Corp. |
| 5 | * Author: Oder Chiou <oder_chiou@realtek.com> |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify |
| 8 | * it under the terms of the GNU General Public License version 2 as |
| 9 | * published by the Free Software Foundation. |
| 10 | */ |
| 11 | |
| 12 | #ifndef _RT5660_H |
| 13 | #define _RT5660_H |
| 14 | |
| 15 | #include <linux/clk.h> |
| 16 | #include <sound/rt5660.h> |
| 17 | |
| 18 | /* Info */ |
| 19 | #define RT5660_RESET 0x00 |
| 20 | #define RT5660_VENDOR_ID 0xfd |
| 21 | #define RT5660_VENDOR_ID1 0xfe |
| 22 | #define RT5660_VENDOR_ID2 0xff |
| 23 | /* I/O - Output */ |
| 24 | #define RT5660_SPK_VOL 0x01 |
| 25 | #define RT5660_LOUT_VOL 0x02 |
| 26 | /* I/O - Input */ |
| 27 | #define RT5660_IN1_IN2 0x0d |
| 28 | #define RT5660_IN3_IN4 0x0e |
| 29 | /* I/O - ADC/DAC/DMIC */ |
| 30 | #define RT5660_DAC1_DIG_VOL 0x19 |
| 31 | #define RT5660_STO1_ADC_DIG_VOL 0x1c |
| 32 | #define RT5660_ADC_BST_VOL1 0x1e |
| 33 | /* Mixer - D-D */ |
| 34 | #define RT5660_STO1_ADC_MIXER 0x27 |
| 35 | #define RT5660_AD_DA_MIXER 0x29 |
| 36 | #define RT5660_STO_DAC_MIXER 0x2a |
| 37 | #define RT5660_DIG_INF1_DATA 0x2f |
| 38 | /* Mixer - ADC */ |
| 39 | #define RT5660_REC_L1_MIXER 0x3b |
| 40 | #define RT5660_REC_L2_MIXER 0x3c |
| 41 | #define RT5660_REC_R1_MIXER 0x3d |
| 42 | #define RT5660_REC_R2_MIXER 0x3e |
| 43 | /* Mixer - DAC */ |
| 44 | #define RT5660_LOUT_MIXER 0x45 |
| 45 | #define RT5660_SPK_MIXER 0x46 |
| 46 | #define RT5660_SPO_MIXER 0x48 |
| 47 | #define RT5660_SPO_CLSD_RATIO 0x4a |
| 48 | #define RT5660_OUT_L_GAIN1 0x4d |
| 49 | #define RT5660_OUT_L_GAIN2 0x4e |
| 50 | #define RT5660_OUT_L1_MIXER 0x4f |
| 51 | #define RT5660_OUT_R_GAIN1 0x50 |
| 52 | #define RT5660_OUT_R_GAIN2 0x51 |
| 53 | #define RT5660_OUT_R1_MIXER 0x52 |
| 54 | /* Power */ |
| 55 | #define RT5660_PWR_DIG1 0x61 |
| 56 | #define RT5660_PWR_DIG2 0x62 |
| 57 | #define RT5660_PWR_ANLG1 0x63 |
| 58 | #define RT5660_PWR_ANLG2 0x64 |
| 59 | #define RT5660_PWR_MIXER 0x65 |
| 60 | #define RT5660_PWR_VOL 0x66 |
| 61 | /* Private Register Control */ |
| 62 | #define RT5660_PRIV_INDEX 0x6a |
| 63 | #define RT5660_PRIV_DATA 0x6c |
| 64 | /* Format - ADC/DAC */ |
| 65 | #define RT5660_I2S1_SDP 0x70 |
| 66 | #define RT5660_ADDA_CLK1 0x73 |
| 67 | #define RT5660_ADDA_CLK2 0x74 |
| 68 | #define RT5660_DMIC_CTRL1 0x75 |
| 69 | /* Function - Analog */ |
| 70 | #define RT5660_GLB_CLK 0x80 |
| 71 | #define RT5660_PLL_CTRL1 0x81 |
| 72 | #define RT5660_PLL_CTRL2 0x82 |
| 73 | #define RT5660_CLSD_AMP_OC_CTRL 0x8c |
| 74 | #define RT5660_CLSD_AMP_CTRL 0x8d |
| 75 | #define RT5660_LOUT_AMP_CTRL 0x8e |
| 76 | #define RT5660_SPK_AMP_SPKVDD 0x92 |
| 77 | #define RT5660_MICBIAS 0x93 |
| 78 | #define RT5660_CLSD_OUT_CTRL1 0xa1 |
| 79 | #define RT5660_CLSD_OUT_CTRL2 0xa2 |
| 80 | #define RT5660_DIPOLE_MIC_CTRL1 0xa3 |
| 81 | #define RT5660_DIPOLE_MIC_CTRL2 0xa4 |
| 82 | #define RT5660_DIPOLE_MIC_CTRL3 0xa5 |
| 83 | #define RT5660_DIPOLE_MIC_CTRL4 0xa6 |
| 84 | #define RT5660_DIPOLE_MIC_CTRL5 0xa7 |
| 85 | #define RT5660_DIPOLE_MIC_CTRL6 0xa8 |
| 86 | #define RT5660_DIPOLE_MIC_CTRL7 0xa9 |
| 87 | #define RT5660_DIPOLE_MIC_CTRL8 0xaa |
| 88 | #define RT5660_DIPOLE_MIC_CTRL9 0xab |
| 89 | #define RT5660_DIPOLE_MIC_CTRL10 0xac |
| 90 | #define RT5660_DIPOLE_MIC_CTRL11 0xad |
| 91 | #define RT5660_DIPOLE_MIC_CTRL12 0xae |
| 92 | /* Function - Digital */ |
| 93 | #define RT5660_EQ_CTRL1 0xb0 |
| 94 | #define RT5660_EQ_CTRL2 0xb1 |
| 95 | #define RT5660_DRC_AGC_CTRL1 0xb3 |
| 96 | #define RT5660_DRC_AGC_CTRL2 0xb4 |
| 97 | #define RT5660_DRC_AGC_CTRL3 0xb5 |
| 98 | #define RT5660_DRC_AGC_CTRL4 0xb6 |
| 99 | #define RT5660_DRC_AGC_CTRL5 0xb7 |
| 100 | #define RT5660_JD_CTRL 0xbb |
| 101 | #define RT5660_IRQ_CTRL1 0xbd |
| 102 | #define RT5660_IRQ_CTRL2 0xbe |
| 103 | #define RT5660_INT_IRQ_ST 0xbf |
| 104 | #define RT5660_GPIO_CTRL1 0xc0 |
| 105 | #define RT5660_GPIO_CTRL2 0xc2 |
| 106 | #define RT5660_WIND_FILTER_CTRL1 0xd3 |
| 107 | #define RT5660_SV_ZCD1 0xd9 |
| 108 | #define RT5660_SV_ZCD2 0xda |
| 109 | #define RT5660_DRC1_LM_CTRL1 0xe0 |
| 110 | #define RT5660_DRC1_LM_CTRL2 0xe1 |
| 111 | #define RT5660_DRC2_LM_CTRL1 0xe2 |
| 112 | #define RT5660_DRC2_LM_CTRL2 0xe3 |
| 113 | #define RT5660_MULTI_DRC_CTRL 0xe4 |
| 114 | #define RT5660_DRC2_CTRL1 0xe5 |
| 115 | #define RT5660_DRC2_CTRL2 0xe6 |
| 116 | #define RT5660_DRC2_CTRL3 0xe7 |
| 117 | #define RT5660_DRC2_CTRL4 0xe8 |
| 118 | #define RT5660_DRC2_CTRL5 0xe9 |
| 119 | #define RT5660_ALC_PGA_CTRL1 0xea |
| 120 | #define RT5660_ALC_PGA_CTRL2 0xeb |
| 121 | #define RT5660_ALC_PGA_CTRL3 0xec |
| 122 | #define RT5660_ALC_PGA_CTRL4 0xed |
| 123 | #define RT5660_ALC_PGA_CTRL5 0xee |
| 124 | #define RT5660_ALC_PGA_CTRL6 0xef |
| 125 | #define RT5660_ALC_PGA_CTRL7 0xf0 |
| 126 | |
| 127 | /* General Control */ |
| 128 | #define RT5660_GEN_CTRL1 0xfa |
| 129 | #define RT5660_GEN_CTRL2 0xfb |
| 130 | #define RT5660_GEN_CTRL3 0xfc |
| 131 | |
| 132 | /* Index of Codec Private Register definition */ |
| 133 | #define RT5660_CHOP_DAC_ADC 0x3d |
| 134 | |
| 135 | /* Global Definition */ |
| 136 | #define RT5660_L_MUTE (0x1 << 15) |
| 137 | #define RT5660_L_MUTE_SFT 15 |
| 138 | #define RT5660_VOL_L_MUTE (0x1 << 14) |
| 139 | #define RT5660_VOL_L_SFT 14 |
| 140 | #define RT5660_R_MUTE (0x1 << 7) |
| 141 | #define RT5660_R_MUTE_SFT 7 |
| 142 | #define RT5660_VOL_R_MUTE (0x1 << 6) |
| 143 | #define RT5660_VOL_R_SFT 6 |
| 144 | #define RT5660_L_VOL_MASK (0x3f << 8) |
| 145 | #define RT5660_L_VOL_SFT 8 |
| 146 | #define RT5660_R_VOL_MASK (0x3f) |
| 147 | #define RT5660_R_VOL_SFT 0 |
| 148 | |
| 149 | /* IN1 and IN2 Control (0x0d) */ |
| 150 | #define RT5660_IN_DF1 (0x1 << 15) |
| 151 | #define RT5660_IN_SFT1 15 |
| 152 | #define RT5660_BST_MASK1 (0x7f << 8) |
| 153 | #define RT5660_BST_SFT1 8 |
| 154 | #define RT5660_IN_DF2 (0x1 << 7) |
| 155 | #define RT5660_IN_SFT2 7 |
| 156 | #define RT5660_BST_MASK2 (0x7f << 0) |
| 157 | #define RT5660_BST_SFT2 0 |
| 158 | |
| 159 | /* IN3 and IN4 Control (0x0e) */ |
| 160 | #define RT5660_IN_DF3 (0x1 << 15) |
| 161 | #define RT5660_IN_SFT3 15 |
| 162 | #define RT5660_BST_MASK3 (0x7f << 8) |
| 163 | #define RT5660_BST_SFT3 8 |
| 164 | #define RT5660_IN_DF4 (0x1 << 7) |
| 165 | #define RT5660_IN_SFT4 7 |
| 166 | #define RT5660_BST_MASK4 (0x7f << 0) |
| 167 | #define RT5660_BST_SFT4 0 |
| 168 | |
| 169 | /* DAC1 Digital Volume (0x19) */ |
| 170 | #define RT5660_DAC_L1_VOL_MASK (0x7f << 9) |
| 171 | #define RT5660_DAC_L1_VOL_SFT 9 |
| 172 | #define RT5660_DAC_R1_VOL_MASK (0x7f << 1) |
| 173 | #define RT5660_DAC_R1_VOL_SFT 1 |
| 174 | |
| 175 | /* ADC Digital Volume Control (0x1c) */ |
| 176 | #define RT5660_ADC_L_VOL_MASK (0x3f << 9) |
| 177 | #define RT5660_ADC_L_VOL_SFT 9 |
| 178 | #define RT5660_ADC_R_VOL_MASK (0x3f << 1) |
| 179 | #define RT5660_ADC_R_VOL_SFT 1 |
| 180 | |
| 181 | /* ADC Boost Volume Control (0x1e) */ |
| 182 | #define RT5660_STO1_ADC_L_BST_MASK (0x3 << 14) |
| 183 | #define RT5660_STO1_ADC_L_BST_SFT 14 |
| 184 | #define RT5660_STO1_ADC_R_BST_MASK (0x3 << 12) |
| 185 | #define RT5660_STO1_ADC_R_BST_SFT 12 |
| 186 | |
| 187 | /* Stereo ADC Mixer Control (0x27) */ |
| 188 | #define RT5660_M_ADC_L1 (0x1 << 14) |
| 189 | #define RT5660_M_ADC_L1_SFT 14 |
| 190 | #define RT5660_M_ADC_L2 (0x1 << 13) |
| 191 | #define RT5660_M_ADC_L2_SFT 13 |
| 192 | #define RT5660_M_ADC_R1 (0x1 << 6) |
| 193 | #define RT5660_M_ADC_R1_SFT 6 |
| 194 | #define RT5660_M_ADC_R2 (0x1 << 5) |
| 195 | #define RT5660_M_ADC_R2_SFT 5 |
| 196 | |
| 197 | /* ADC Mixer to DAC Mixer Control (0x29) */ |
| 198 | #define RT5660_M_ADCMIX_L (0x1 << 15) |
| 199 | #define RT5660_M_ADCMIX_L_SFT 15 |
| 200 | #define RT5660_M_DAC1_L (0x1 << 14) |
| 201 | #define RT5660_M_DAC1_L_SFT 14 |
| 202 | #define RT5660_M_ADCMIX_R (0x1 << 7) |
| 203 | #define RT5660_M_ADCMIX_R_SFT 7 |
| 204 | #define RT5660_M_DAC1_R (0x1 << 6) |
| 205 | #define RT5660_M_DAC1_R_SFT 6 |
| 206 | |
| 207 | /* Stereo DAC Mixer Control (0x2a) */ |
| 208 | #define RT5660_M_DAC_L1 (0x1 << 14) |
| 209 | #define RT5660_M_DAC_L1_SFT 14 |
| 210 | #define RT5660_DAC_L1_STO_L_VOL_MASK (0x1 << 13) |
| 211 | #define RT5660_DAC_L1_STO_L_VOL_SFT 13 |
| 212 | #define RT5660_M_DAC_R1_STO_L (0x1 << 9) |
| 213 | #define RT5660_M_DAC_R1_STO_L_SFT 9 |
| 214 | #define RT5660_DAC_R1_STO_L_VOL_MASK (0x1 << 8) |
| 215 | #define RT5660_DAC_R1_STO_L_VOL_SFT 8 |
| 216 | #define RT5660_M_DAC_R1 (0x1 << 6) |
| 217 | #define RT5660_M_DAC_R1_SFT 6 |
| 218 | #define RT5660_DAC_R1_STO_R_VOL_MASK (0x1 << 5) |
| 219 | #define RT5660_DAC_R1_STO_R_VOL_SFT 5 |
| 220 | #define RT5660_M_DAC_L1_STO_R (0x1 << 1) |
| 221 | #define RT5660_M_DAC_L1_STO_R_SFT 1 |
| 222 | #define RT5660_DAC_L1_STO_R_VOL_MASK (0x1) |
| 223 | #define RT5660_DAC_L1_STO_R_VOL_SFT 0 |
| 224 | |
| 225 | /* Digital Interface Data Control (0x2f) */ |
| 226 | #define RT5660_IF1_DAC_IN_SEL (0x3 << 14) |
| 227 | #define RT5660_IF1_DAC_IN_SFT 14 |
| 228 | #define RT5660_IF1_ADC_IN_SEL (0x3 << 12) |
| 229 | #define RT5660_IF1_ADC_IN_SFT 12 |
| 230 | |
| 231 | /* REC Left Mixer Control 1 (0x3b) */ |
| 232 | #define RT5660_G_BST3_RM_L_MASK (0x7 << 4) |
| 233 | #define RT5660_G_BST3_RM_L_SFT 4 |
| 234 | #define RT5660_G_BST2_RM_L_MASK (0x7 << 1) |
| 235 | #define RT5660_G_BST2_RM_L_SFT 1 |
| 236 | |
| 237 | /* REC Left Mixer Control 2 (0x3c) */ |
| 238 | #define RT5660_G_BST1_RM_L_MASK (0x7 << 13) |
| 239 | #define RT5660_G_BST1_RM_L_SFT 13 |
| 240 | #define RT5660_G_OM_L_RM_L_MASK (0x7 << 10) |
| 241 | #define RT5660_G_OM_L_RM_L_SFT 10 |
| 242 | #define RT5660_M_BST3_RM_L (0x1 << 3) |
| 243 | #define RT5660_M_BST3_RM_L_SFT 3 |
| 244 | #define RT5660_M_BST2_RM_L (0x1 << 2) |
| 245 | #define RT5660_M_BST2_RM_L_SFT 2 |
| 246 | #define RT5660_M_BST1_RM_L (0x1 << 1) |
| 247 | #define RT5660_M_BST1_RM_L_SFT 1 |
| 248 | #define RT5660_M_OM_L_RM_L (0x1) |
| 249 | #define RT5660_M_OM_L_RM_L_SFT 0 |
| 250 | |
| 251 | /* REC Right Mixer Control 1 (0x3d) */ |
| 252 | #define RT5660_G_BST3_RM_R_MASK (0x7 << 4) |
| 253 | #define RT5660_G_BST3_RM_R_SFT 4 |
| 254 | #define RT5660_G_BST2_RM_R_MASK (0x7 << 1) |
| 255 | #define RT5660_G_BST2_RM_R_SFT 1 |
| 256 | |
| 257 | /* REC Right Mixer Control 2 (0x3e) */ |
| 258 | #define RT5660_G_BST1_RM_R_MASK (0x7 << 13) |
| 259 | #define RT5660_G_BST1_RM_R_SFT 13 |
| 260 | #define RT5660_G_OM_R_RM_R_MASK (0x7 << 10) |
| 261 | #define RT5660_G_OM_R_RM_R_SFT 10 |
| 262 | #define RT5660_M_BST3_RM_R (0x1 << 3) |
| 263 | #define RT5660_M_BST3_RM_R_SFT 3 |
| 264 | #define RT5660_M_BST2_RM_R (0x1 << 2) |
| 265 | #define RT5660_M_BST2_RM_R_SFT 2 |
| 266 | #define RT5660_M_BST1_RM_R (0x1 << 1) |
| 267 | #define RT5660_M_BST1_RM_R_SFT 1 |
| 268 | #define RT5660_M_OM_R_RM_R (0x1) |
| 269 | #define RT5660_M_OM_R_RM_R_SFT 0 |
| 270 | |
| 271 | /* LOUTMIX Control (0x45) */ |
| 272 | #define RT5660_M_DAC1_LM (0x1 << 14) |
| 273 | #define RT5660_M_DAC1_LM_SFT 14 |
| 274 | #define RT5660_M_LOVOL_M (0x1 << 13) |
| 275 | #define RT5660_M_LOVOL_LM_SFT 13 |
| 276 | |
| 277 | /* SPK Mixer Control (0x46) */ |
| 278 | #define RT5660_G_BST3_SM_MASK (0x3 << 14) |
| 279 | #define RT5660_G_BST3_SM_SFT 14 |
| 280 | #define RT5660_G_BST1_SM_MASK (0x3 << 12) |
| 281 | #define RT5660_G_BST1_SM_SFT 12 |
| 282 | #define RT5660_G_DACl_SM_MASK (0x3 << 10) |
| 283 | #define RT5660_G_DACl_SM_SFT 10 |
| 284 | #define RT5660_G_DACR_SM_MASK (0x3 << 8) |
| 285 | #define RT5660_G_DACR_SM_SFT 8 |
| 286 | #define RT5660_G_OM_L_SM_MASK (0x3 << 6) |
| 287 | #define RT5660_G_OM_L_SM_SFT 6 |
| 288 | #define RT5660_M_DACR_SM (0x1 << 5) |
| 289 | #define RT5660_M_DACR_SM_SFT 5 |
| 290 | #define RT5660_M_BST1_SM (0x1 << 4) |
| 291 | #define RT5660_M_BST1_SM_SFT 4 |
| 292 | #define RT5660_M_BST3_SM (0x1 << 3) |
| 293 | #define RT5660_M_BST3_SM_SFT 3 |
| 294 | #define RT5660_M_DACL_SM (0x1 << 2) |
| 295 | #define RT5660_M_DACL_SM_SFT 2 |
| 296 | #define RT5660_M_OM_L_SM (0x1 << 1) |
| 297 | #define RT5660_M_OM_L_SM_SFT 1 |
| 298 | |
| 299 | /* SPOMIX Control (0x48) */ |
| 300 | #define RT5660_M_DAC_R_SPM (0x1 << 14) |
| 301 | #define RT5660_M_DAC_R_SPM_SFT 14 |
| 302 | #define RT5660_M_DAC_L_SPM (0x1 << 13) |
| 303 | #define RT5660_M_DAC_L_SPM_SFT 13 |
| 304 | #define RT5660_M_SV_SPM (0x1 << 12) |
| 305 | #define RT5660_M_SV_SPM_SFT 12 |
| 306 | #define RT5660_M_BST1_SPM (0x1 << 11) |
| 307 | #define RT5660_M_BST1_SPM_SFT 11 |
| 308 | |
| 309 | /* Output Left Mixer Control 1 (0x4d) */ |
| 310 | #define RT5660_G_BST3_OM_L_MASK (0x7 << 13) |
| 311 | #define RT5660_G_BST3_OM_L_SFT 13 |
| 312 | #define RT5660_G_BST2_OM_L_MASK (0x7 << 10) |
| 313 | #define RT5660_G_BST2_OM_L_SFT 10 |
| 314 | #define RT5660_G_BST1_OM_L_MASK (0x7 << 7) |
| 315 | #define RT5660_G_BST1_OM_L_SFT 7 |
| 316 | #define RT5660_G_RM_L_OM_L_MASK (0x7 << 1) |
| 317 | #define RT5660_G_RM_L_OM_L_SFT 1 |
| 318 | |
| 319 | /* Output Left Mixer Control 2 (0x4e) */ |
| 320 | #define RT5660_G_DAC_R1_OM_L_MASK (0x7 << 10) |
| 321 | #define RT5660_G_DAC_R1_OM_L_SFT 10 |
| 322 | #define RT5660_G_DAC_L1_OM_L_MASK (0x7 << 7) |
| 323 | #define RT5660_G_DAC_L1_OM_L_SFT 7 |
| 324 | |
| 325 | /* Output Left Mixer Control 3 (0x4f) */ |
| 326 | #define RT5660_M_BST3_OM_L (0x1 << 5) |
| 327 | #define RT5660_M_BST3_OM_L_SFT 5 |
| 328 | #define RT5660_M_BST2_OM_L (0x1 << 4) |
| 329 | #define RT5660_M_BST2_OM_L_SFT 4 |
| 330 | #define RT5660_M_BST1_OM_L (0x1 << 3) |
| 331 | #define RT5660_M_BST1_OM_L_SFT 3 |
| 332 | #define RT5660_M_RM_L_OM_L (0x1 << 2) |
| 333 | #define RT5660_M_RM_L_OM_L_SFT 2 |
| 334 | #define RT5660_M_DAC_R_OM_L (0x1 << 1) |
| 335 | #define RT5660_M_DAC_R_OM_L_SFT 1 |
| 336 | #define RT5660_M_DAC_L_OM_L (0x1) |
| 337 | #define RT5660_M_DAC_L_OM_L_SFT 0 |
| 338 | |
| 339 | /* Output Right Mixer Control 1 (0x50) */ |
| 340 | #define RT5660_G_BST2_OM_R_MASK (0x7 << 10) |
| 341 | #define RT5660_G_BST2_OM_R_SFT 10 |
| 342 | #define RT5660_G_BST1_OM_R_MASK (0x7 << 7) |
| 343 | #define RT5660_G_BST1_OM_R_SFT 7 |
| 344 | #define RT5660_G_RM_R_OM_R_MASK (0x7 << 1) |
| 345 | #define RT5660_G_RM_R_OM_R_SFT 1 |
| 346 | |
| 347 | /* Output Right Mixer Control 2 (0x51) */ |
| 348 | #define RT5660_G_DAC_L_OM_R_MASK (0x7 << 10) |
| 349 | #define RT5660_G_DAC_L_OM_R_SFT 10 |
| 350 | #define RT5660_G_DAC_R_OM_R_MASK (0x7 << 7) |
| 351 | #define RT5660_G_DAC_R_OM_R_SFT 7 |
| 352 | |
| 353 | /* Output Right Mixer Control 3 (0x52) */ |
| 354 | #define RT5660_M_BST2_OM_R (0x1 << 4) |
| 355 | #define RT5660_M_BST2_OM_R_SFT 4 |
| 356 | #define RT5660_M_BST1_OM_R (0x1 << 3) |
| 357 | #define RT5660_M_BST1_OM_R_SFT 3 |
| 358 | #define RT5660_M_RM_R_OM_R (0x1 << 2) |
| 359 | #define RT5660_M_RM_R_OM_R_SFT 2 |
| 360 | #define RT5660_M_DAC_L_OM_R (0x1 << 1) |
| 361 | #define RT5660_M_DAC_L_OM_R_SFT 1 |
| 362 | #define RT5660_M_DAC_R_OM_R (0x1) |
| 363 | #define RT5660_M_DAC_R_OM_R_SFT 0 |
| 364 | |
| 365 | /* Power Management for Digital 1 (0x61) */ |
| 366 | #define RT5660_PWR_I2S1 (0x1 << 15) |
| 367 | #define RT5660_PWR_I2S1_BIT 15 |
| 368 | #define RT5660_PWR_DAC_L1 (0x1 << 12) |
| 369 | #define RT5660_PWR_DAC_L1_BIT 12 |
| 370 | #define RT5660_PWR_DAC_R1 (0x1 << 11) |
| 371 | #define RT5660_PWR_DAC_R1_BIT 11 |
| 372 | #define RT5660_PWR_ADC_L (0x1 << 2) |
| 373 | #define RT5660_PWR_ADC_L_BIT 2 |
| 374 | #define RT5660_PWR_ADC_R (0x1 << 1) |
| 375 | #define RT5660_PWR_ADC_R_BIT 1 |
| 376 | #define RT5660_PWR_CLS_D (0x1) |
| 377 | #define RT5660_PWR_CLS_D_BIT 0 |
| 378 | |
| 379 | /* Power Management for Digital 2 (0x62) */ |
| 380 | #define RT5660_PWR_ADC_S1F (0x1 << 15) |
| 381 | #define RT5660_PWR_ADC_S1F_BIT 15 |
| 382 | #define RT5660_PWR_DAC_S1F (0x1 << 11) |
| 383 | #define RT5660_PWR_DAC_S1F_BIT 11 |
| 384 | |
| 385 | /* Power Management for Analog 1 (0x63) */ |
| 386 | #define RT5660_PWR_VREF1 (0x1 << 15) |
| 387 | #define RT5660_PWR_VREF1_BIT 15 |
| 388 | #define RT5660_PWR_FV1 (0x1 << 14) |
| 389 | #define RT5660_PWR_FV1_BIT 14 |
| 390 | #define RT5660_PWR_MB (0x1 << 13) |
| 391 | #define RT5660_PWR_MB_BIT 13 |
| 392 | #define RT5660_PWR_BG (0x1 << 11) |
| 393 | #define RT5660_PWR_BG_BIT 11 |
| 394 | #define RT5660_PWR_HP_L (0x1 << 7) |
| 395 | #define RT5660_PWR_HP_L_BIT 7 |
| 396 | #define RT5660_PWR_HP_R (0x1 << 6) |
| 397 | #define RT5660_PWR_HP_R_BIT 6 |
| 398 | #define RT5660_PWR_HA (0x1 << 5) |
| 399 | #define RT5660_PWR_HA_BIT 5 |
| 400 | #define RT5660_PWR_VREF2 (0x1 << 4) |
| 401 | #define RT5660_PWR_VREF2_BIT 4 |
| 402 | #define RT5660_PWR_FV2 (0x1 << 3) |
| 403 | #define RT5660_PWR_FV2_BIT 3 |
| 404 | #define RT5660_PWR_LDO2 (0x1 << 2) |
| 405 | #define RT5660_PWR_LDO2_BIT 2 |
| 406 | |
| 407 | /* Power Management for Analog 2 (0x64) */ |
| 408 | #define RT5660_PWR_BST1 (0x1 << 15) |
| 409 | #define RT5660_PWR_BST1_BIT 15 |
| 410 | #define RT5660_PWR_BST2 (0x1 << 14) |
| 411 | #define RT5660_PWR_BST2_BIT 14 |
| 412 | #define RT5660_PWR_BST3 (0x1 << 13) |
| 413 | #define RT5660_PWR_BST3_BIT 13 |
| 414 | #define RT5660_PWR_MB1 (0x1 << 11) |
| 415 | #define RT5660_PWR_MB1_BIT 11 |
| 416 | #define RT5660_PWR_MB2 (0x1 << 10) |
| 417 | #define RT5660_PWR_MB2_BIT 10 |
| 418 | #define RT5660_PWR_PLL (0x1 << 9) |
| 419 | #define RT5660_PWR_PLL_BIT 9 |
| 420 | |
| 421 | /* Power Management for Mixer (0x65) */ |
| 422 | #define RT5660_PWR_OM_L (0x1 << 15) |
| 423 | #define RT5660_PWR_OM_L_BIT 15 |
| 424 | #define RT5660_PWR_OM_R (0x1 << 14) |
| 425 | #define RT5660_PWR_OM_R_BIT 14 |
| 426 | #define RT5660_PWR_SM (0x1 << 13) |
| 427 | #define RT5660_PWR_SM_BIT 13 |
| 428 | #define RT5660_PWR_RM_L (0x1 << 11) |
| 429 | #define RT5660_PWR_RM_L_BIT 11 |
| 430 | #define RT5660_PWR_RM_R (0x1 << 10) |
| 431 | #define RT5660_PWR_RM_R_BIT 10 |
| 432 | |
| 433 | /* Power Management for Volume (0x66) */ |
| 434 | #define RT5660_PWR_SV (0x1 << 15) |
| 435 | #define RT5660_PWR_SV_BIT 15 |
| 436 | #define RT5660_PWR_LV_L (0x1 << 11) |
| 437 | #define RT5660_PWR_LV_L_BIT 11 |
| 438 | #define RT5660_PWR_LV_R (0x1 << 10) |
| 439 | #define RT5660_PWR_LV_R_BIT 10 |
| 440 | |
| 441 | /* I2S1 Audio Serial Data Port Control (0x70) */ |
| 442 | #define RT5660_I2S_MS_MASK (0x1 << 15) |
| 443 | #define RT5660_I2S_MS_SFT 15 |
| 444 | #define RT5660_I2S_MS_M (0x0 << 15) |
| 445 | #define RT5660_I2S_MS_S (0x1 << 15) |
| 446 | #define RT5660_I2S_O_CP_MASK (0x3 << 10) |
| 447 | #define RT5660_I2S_O_CP_SFT 10 |
| 448 | #define RT5660_I2S_O_CP_OFF (0x0 << 10) |
| 449 | #define RT5660_I2S_O_CP_U_LAW (0x1 << 10) |
| 450 | #define RT5660_I2S_O_CP_A_LAW (0x2 << 10) |
| 451 | #define RT5660_I2S_I_CP_MASK (0x3 << 8) |
| 452 | #define RT5660_I2S_I_CP_SFT 8 |
| 453 | #define RT5660_I2S_I_CP_OFF (0x0 << 8) |
| 454 | #define RT5660_I2S_I_CP_U_LAW (0x1 << 8) |
| 455 | #define RT5660_I2S_I_CP_A_LAW (0x2 << 8) |
| 456 | #define RT5660_I2S_BP_MASK (0x1 << 7) |
| 457 | #define RT5660_I2S_BP_SFT 7 |
| 458 | #define RT5660_I2S_BP_NOR (0x0 << 7) |
| 459 | #define RT5660_I2S_BP_INV (0x1 << 7) |
| 460 | #define RT5660_I2S_DL_MASK (0x3 << 2) |
| 461 | #define RT5660_I2S_DL_SFT 2 |
| 462 | #define RT5660_I2S_DL_16 (0x0 << 2) |
| 463 | #define RT5660_I2S_DL_20 (0x1 << 2) |
| 464 | #define RT5660_I2S_DL_24 (0x2 << 2) |
| 465 | #define RT5660_I2S_DL_8 (0x3 << 2) |
| 466 | #define RT5660_I2S_DF_MASK (0x3) |
| 467 | #define RT5660_I2S_DF_SFT 0 |
| 468 | #define RT5660_I2S_DF_I2S (0x0) |
| 469 | #define RT5660_I2S_DF_LEFT (0x1) |
| 470 | #define RT5660_I2S_DF_PCM_A (0x2) |
| 471 | #define RT5660_I2S_DF_PCM_B (0x3) |
| 472 | |
| 473 | /* ADC/DAC Clock Control 1 (0x73) */ |
| 474 | #define RT5660_I2S_BCLK_MS1_MASK (0x1 << 15) |
| 475 | #define RT5660_I2S_BCLK_MS1_SFT 15 |
| 476 | #define RT5660_I2S_BCLK_MS1_32 (0x0 << 15) |
| 477 | #define RT5660_I2S_BCLK_MS1_64 (0x1 << 15) |
| 478 | #define RT5660_I2S_PD1_MASK (0x7 << 12) |
| 479 | #define RT5660_I2S_PD1_SFT 12 |
| 480 | #define RT5660_I2S_PD1_1 (0x0 << 12) |
| 481 | #define RT5660_I2S_PD1_2 (0x1 << 12) |
| 482 | #define RT5660_I2S_PD1_3 (0x2 << 12) |
| 483 | #define RT5660_I2S_PD1_4 (0x3 << 12) |
| 484 | #define RT5660_I2S_PD1_6 (0x4 << 12) |
| 485 | #define RT5660_I2S_PD1_8 (0x5 << 12) |
| 486 | #define RT5660_I2S_PD1_12 (0x6 << 12) |
| 487 | #define RT5660_I2S_PD1_16 (0x7 << 12) |
| 488 | #define RT5660_DAC_OSR_MASK (0x3 << 2) |
| 489 | #define RT5660_DAC_OSR_SFT 2 |
| 490 | #define RT5660_DAC_OSR_128 (0x0 << 2) |
| 491 | #define RT5660_DAC_OSR_64 (0x1 << 2) |
| 492 | #define RT5660_DAC_OSR_32 (0x2 << 2) |
| 493 | #define RT5660_DAC_OSR_16 (0x3 << 2) |
| 494 | #define RT5660_ADC_OSR_MASK (0x3) |
| 495 | #define RT5660_ADC_OSR_SFT 0 |
| 496 | #define RT5660_ADC_OSR_128 (0x0) |
| 497 | #define RT5660_ADC_OSR_64 (0x1) |
| 498 | #define RT5660_ADC_OSR_32 (0x2) |
| 499 | #define RT5660_ADC_OSR_16 (0x3) |
| 500 | |
| 501 | /* ADC/DAC Clock Control 2 (0x74) */ |
| 502 | #define RT5660_RESET_ADF (0x1 << 13) |
| 503 | #define RT5660_RESET_ADF_SFT 13 |
| 504 | #define RT5660_RESET_DAF (0x1 << 12) |
| 505 | #define RT5660_RESET_DAF_SFT 12 |
| 506 | #define RT5660_DAHPF_EN (0x1 << 11) |
| 507 | #define RT5660_DAHPF_EN_SFT 11 |
| 508 | #define RT5660_ADHPF_EN (0x1 << 10) |
| 509 | #define RT5660_ADHPF_EN_SFT 10 |
| 510 | |
| 511 | /* Digital Microphone Control (0x75) */ |
| 512 | #define RT5660_DMIC_1_EN_MASK (0x1 << 15) |
| 513 | #define RT5660_DMIC_1_EN_SFT 15 |
| 514 | #define RT5660_DMIC_1_DIS (0x0 << 15) |
| 515 | #define RT5660_DMIC_1_EN (0x1 << 15) |
| 516 | #define RT5660_DMIC_1L_LH_MASK (0x1 << 13) |
| 517 | #define RT5660_DMIC_1L_LH_SFT 13 |
| 518 | #define RT5660_DMIC_1L_LH_RISING (0x0 << 13) |
| 519 | #define RT5660_DMIC_1L_LH_FALLING (0x1 << 13) |
| 520 | #define RT5660_DMIC_1R_LH_MASK (0x1 << 12) |
| 521 | #define RT5660_DMIC_1R_LH_SFT 12 |
| 522 | #define RT5660_DMIC_1R_LH_RISING (0x0 << 12) |
| 523 | #define RT5660_DMIC_1R_LH_FALLING (0x1 << 12) |
| 524 | #define RT5660_SEL_DMIC_DATA_MASK (0x1 << 11) |
| 525 | #define RT5660_SEL_DMIC_DATA_SFT 11 |
| 526 | #define RT5660_SEL_DMIC_DATA_GPIO2 (0x0 << 11) |
| 527 | #define RT5660_SEL_DMIC_DATA_IN1P (0x1 << 11) |
| 528 | #define RT5660_DMIC_CLK_MASK (0x7 << 5) |
| 529 | #define RT5660_DMIC_CLK_SFT 5 |
| 530 | |
| 531 | /* Global Clock Control (0x80) */ |
| 532 | #define RT5660_SCLK_SRC_MASK (0x3 << 14) |
| 533 | #define RT5660_SCLK_SRC_SFT 14 |
| 534 | #define RT5660_SCLK_SRC_MCLK (0x0 << 14) |
| 535 | #define RT5660_SCLK_SRC_PLL1 (0x1 << 14) |
| 536 | #define RT5660_SCLK_SRC_RCCLK (0x2 << 14) |
| 537 | #define RT5660_PLL1_SRC_MASK (0x3 << 12) |
| 538 | #define RT5660_PLL1_SRC_SFT 12 |
| 539 | #define RT5660_PLL1_SRC_MCLK (0x0 << 12) |
| 540 | #define RT5660_PLL1_SRC_BCLK1 (0x1 << 12) |
| 541 | #define RT5660_PLL1_SRC_RCCLK (0x2 << 12) |
| 542 | #define RT5660_PLL1_PD_MASK (0x1 << 3) |
| 543 | #define RT5660_PLL1_PD_SFT 3 |
| 544 | #define RT5660_PLL1_PD_1 (0x0 << 3) |
| 545 | #define RT5660_PLL1_PD_2 (0x1 << 3) |
| 546 | |
| 547 | #define RT5660_PLL_INP_MAX 40000000 |
| 548 | #define RT5660_PLL_INP_MIN 256000 |
| 549 | /* PLL M/N/K Code Control 1 (0x81) */ |
| 550 | #define RT5660_PLL_N_MAX 0x1ff |
| 551 | #define RT5660_PLL_N_MASK (RT5660_PLL_N_MAX << 7) |
| 552 | #define RT5660_PLL_N_SFT 7 |
| 553 | #define RT5660_PLL_K_MAX 0x1f |
| 554 | #define RT5660_PLL_K_MASK (RT5660_PLL_K_MAX) |
| 555 | #define RT5660_PLL_K_SFT 0 |
| 556 | |
| 557 | /* PLL M/N/K Code Control 2 (0x82) */ |
| 558 | #define RT5660_PLL_M_MAX 0xf |
| 559 | #define RT5660_PLL_M_MASK (RT5660_PLL_M_MAX << 12) |
| 560 | #define RT5660_PLL_M_SFT 12 |
| 561 | #define RT5660_PLL_M_BP (0x1 << 11) |
| 562 | #define RT5660_PLL_M_BP_SFT 11 |
| 563 | |
| 564 | /* Class D Over Current Control (0x8c) */ |
| 565 | #define RT5660_CLSD_OC_MASK (0x1 << 9) |
| 566 | #define RT5660_CLSD_OC_SFT 9 |
| 567 | #define RT5660_CLSD_OC_PU (0x0 << 9) |
| 568 | #define RT5660_CLSD_OC_PD (0x1 << 9) |
| 569 | #define RT5660_AUTO_PD_MASK (0x1 << 8) |
| 570 | #define RT5660_AUTO_PD_SFT 8 |
| 571 | #define RT5660_AUTO_PD_DIS (0x0 << 8) |
| 572 | #define RT5660_AUTO_PD_EN (0x1 << 8) |
| 573 | #define RT5660_CLSD_OC_TH_MASK (0x3f) |
| 574 | #define RT5660_CLSD_OC_TH_SFT 0 |
| 575 | |
| 576 | /* Class D Output Control (0x8d) */ |
| 577 | #define RT5660_CLSD_RATIO_MASK (0xf << 12) |
| 578 | #define RT5660_CLSD_RATIO_SFT 12 |
| 579 | |
| 580 | /* Lout Amp Control 1 (0x8e) */ |
| 581 | #define RT5660_LOUT_CO_MASK (0x1 << 4) |
| 582 | #define RT5660_LOUT_CO_SFT 4 |
| 583 | #define RT5660_LOUT_CO_DIS (0x0 << 4) |
| 584 | #define RT5660_LOUT_CO_EN (0x1 << 4) |
| 585 | #define RT5660_LOUT_CB_MASK (0x1) |
| 586 | #define RT5660_LOUT_CB_SFT 0 |
| 587 | #define RT5660_LOUT_CB_PD (0x0) |
| 588 | #define RT5660_LOUT_CB_PU (0x1) |
| 589 | |
| 590 | /* SPKVDD detection control (0x92) */ |
| 591 | #define RT5660_SPKVDD_DET_MASK (0x1 << 15) |
| 592 | #define RT5660_SPKVDD_DET_SFT 15 |
| 593 | #define RT5660_SPKVDD_DET_DIS (0x0 << 15) |
| 594 | #define RT5660_SPKVDD_DET_EN (0x1 << 15) |
| 595 | #define RT5660_SPK_AG_MASK (0x1 << 14) |
| 596 | #define RT5660_SPK_AG_SFT 14 |
| 597 | #define RT5660_SPK_AG_DIS (0x0 << 14) |
| 598 | #define RT5660_SPK_AG_EN (0x1 << 14) |
| 599 | |
| 600 | /* Micbias Control (0x93) */ |
| 601 | #define RT5660_MIC1_BS_MASK (0x1 << 15) |
| 602 | #define RT5660_MIC1_BS_SFT 15 |
| 603 | #define RT5660_MIC1_BS_9AV (0x0 << 15) |
| 604 | #define RT5660_MIC1_BS_75AV (0x1 << 15) |
| 605 | #define RT5660_MIC2_BS_MASK (0x1 << 14) |
| 606 | #define RT5660_MIC2_BS_SFT 14 |
| 607 | #define RT5660_MIC2_BS_9AV (0x0 << 14) |
| 608 | #define RT5660_MIC2_BS_75AV (0x1 << 14) |
| 609 | #define RT5660_MIC1_OVCD_MASK (0x1 << 11) |
| 610 | #define RT5660_MIC1_OVCD_SFT 11 |
| 611 | #define RT5660_MIC1_OVCD_DIS (0x0 << 11) |
| 612 | #define RT5660_MIC1_OVCD_EN (0x1 << 11) |
| 613 | #define RT5660_MIC1_OVTH_MASK (0x3 << 9) |
| 614 | #define RT5660_MIC1_OVTH_SFT 9 |
| 615 | #define RT5660_MIC1_OVTH_600UA (0x0 << 9) |
| 616 | #define RT5660_MIC1_OVTH_1500UA (0x1 << 9) |
| 617 | #define RT5660_MIC1_OVTH_2000UA (0x2 << 9) |
| 618 | #define RT5660_MIC2_OVCD_MASK (0x1 << 8) |
| 619 | #define RT5660_MIC2_OVCD_SFT 8 |
| 620 | #define RT5660_MIC2_OVCD_DIS (0x0 << 8) |
| 621 | #define RT5660_MIC2_OVCD_EN (0x1 << 8) |
| 622 | #define RT5660_MIC2_OVTH_MASK (0x3 << 6) |
| 623 | #define RT5660_MIC2_OVTH_SFT 6 |
| 624 | #define RT5660_MIC2_OVTH_600UA (0x0 << 6) |
| 625 | #define RT5660_MIC2_OVTH_1500UA (0x1 << 6) |
| 626 | #define RT5660_MIC2_OVTH_2000UA (0x2 << 6) |
| 627 | #define RT5660_PWR_CLK25M_MASK (0x1 << 4) |
| 628 | #define RT5660_PWR_CLK25M_SFT 4 |
| 629 | #define RT5660_PWR_CLK25M_PD (0x0 << 4) |
| 630 | #define RT5660_PWR_CLK25M_PU (0x1 << 4) |
| 631 | |
| 632 | /* EQ Control 1 (0xb0) */ |
| 633 | #define RT5660_EQ_SRC_MASK (0x1 << 15) |
| 634 | #define RT5660_EQ_SRC_SFT 15 |
| 635 | #define RT5660_EQ_SRC_DAC (0x0 << 15) |
| 636 | #define RT5660_EQ_SRC_ADC (0x1 << 15) |
| 637 | #define RT5660_EQ_UPD (0x1 << 14) |
| 638 | #define RT5660_EQ_UPD_BIT 14 |
| 639 | |
| 640 | /* Jack Detect Control (0xbb) */ |
| 641 | #define RT5660_JD_MASK (0x3 << 14) |
| 642 | #define RT5660_JD_SFT 14 |
| 643 | #define RT5660_JD_DIS (0x0 << 14) |
| 644 | #define RT5660_JD_GPIO1 (0x1 << 14) |
| 645 | #define RT5660_JD_GPIO2 (0x2 << 14) |
| 646 | #define RT5660_JD_LOUT_MASK (0x1 << 11) |
| 647 | #define RT5660_JD_LOUT_SFT 11 |
| 648 | #define RT5660_JD_LOUT_DIS (0x0 << 11) |
| 649 | #define RT5660_JD_LOUT_EN (0x1 << 11) |
| 650 | #define RT5660_JD_LOUT_TRG_MASK (0x1 << 10) |
| 651 | #define RT5660_JD_LOUT_TRG_SFT 10 |
| 652 | #define RT5660_JD_LOUT_TRG_LO (0x0 << 10) |
| 653 | #define RT5660_JD_LOUT_TRG_HI (0x1 << 10) |
| 654 | #define RT5660_JD_SPO_MASK (0x1 << 9) |
| 655 | #define RT5660_JD_SPO_SFT 9 |
| 656 | #define RT5660_JD_SPO_DIS (0x0 << 9) |
| 657 | #define RT5660_JD_SPO_EN (0x1 << 9) |
| 658 | #define RT5660_JD_SPO_TRG_MASK (0x1 << 8) |
| 659 | #define RT5660_JD_SPO_TRG_SFT 8 |
| 660 | #define RT5660_JD_SPO_TRG_LO (0x0 << 8) |
| 661 | #define RT5660_JD_SPO_TRG_HI (0x1 << 8) |
| 662 | |
| 663 | /* IRQ Control 1 (0xbd) */ |
| 664 | #define RT5660_IRQ_JD_MASK (0x1 << 15) |
| 665 | #define RT5660_IRQ_JD_SFT 15 |
| 666 | #define RT5660_IRQ_JD_BP (0x0 << 15) |
| 667 | #define RT5660_IRQ_JD_NOR (0x1 << 15) |
| 668 | #define RT5660_IRQ_OT_MASK (0x1 << 14) |
| 669 | #define RT5660_IRQ_OT_SFT 14 |
| 670 | #define RT5660_IRQ_OT_BP (0x0 << 14) |
| 671 | #define RT5660_IRQ_OT_NOR (0x1 << 14) |
| 672 | #define RT5660_JD_STKY_MASK (0x1 << 13) |
| 673 | #define RT5660_JD_STKY_SFT 13 |
| 674 | #define RT5660_JD_STKY_DIS (0x0 << 13) |
| 675 | #define RT5660_JD_STKY_EN (0x1 << 13) |
| 676 | #define RT5660_OT_STKY_MASK (0x1 << 12) |
| 677 | #define RT5660_OT_STKY_SFT 12 |
| 678 | #define RT5660_OT_STKY_DIS (0x0 << 12) |
| 679 | #define RT5660_OT_STKY_EN (0x1 << 12) |
| 680 | #define RT5660_JD_P_MASK (0x1 << 11) |
| 681 | #define RT5660_JD_P_SFT 11 |
| 682 | #define RT5660_JD_P_NOR (0x0 << 11) |
| 683 | #define RT5660_JD_P_INV (0x1 << 11) |
| 684 | #define RT5660_OT_P_MASK (0x1 << 10) |
| 685 | #define RT5660_OT_P_SFT 10 |
| 686 | #define RT5660_OT_P_NOR (0x0 << 10) |
| 687 | #define RT5660_OT_P_INV (0x1 << 10) |
| 688 | |
| 689 | /* IRQ Control 2 (0xbe) */ |
| 690 | #define RT5660_IRQ_MB1_OC_MASK (0x1 << 15) |
| 691 | #define RT5660_IRQ_MB1_OC_SFT 15 |
| 692 | #define RT5660_IRQ_MB1_OC_BP (0x0 << 15) |
| 693 | #define RT5660_IRQ_MB1_OC_NOR (0x1 << 15) |
| 694 | #define RT5660_IRQ_MB2_OC_MASK (0x1 << 14) |
| 695 | #define RT5660_IRQ_MB2_OC_SFT 14 |
| 696 | #define RT5660_IRQ_MB2_OC_BP (0x0 << 14) |
| 697 | #define RT5660_IRQ_MB2_OC_NOR (0x1 << 14) |
| 698 | #define RT5660_MB1_OC_STKY_MASK (0x1 << 11) |
| 699 | #define RT5660_MB1_OC_STKY_SFT 11 |
| 700 | #define RT5660_MB1_OC_STKY_DIS (0x0 << 11) |
| 701 | #define RT5660_MB1_OC_STKY_EN (0x1 << 11) |
| 702 | #define RT5660_MB2_OC_STKY_MASK (0x1 << 10) |
| 703 | #define RT5660_MB2_OC_STKY_SFT 10 |
| 704 | #define RT5660_MB2_OC_STKY_DIS (0x0 << 10) |
| 705 | #define RT5660_MB2_OC_STKY_EN (0x1 << 10) |
| 706 | #define RT5660_MB1_OC_P_MASK (0x1 << 7) |
| 707 | #define RT5660_MB1_OC_P_SFT 7 |
| 708 | #define RT5660_MB1_OC_P_NOR (0x0 << 7) |
| 709 | #define RT5660_MB1_OC_P_INV (0x1 << 7) |
| 710 | #define RT5660_MB2_OC_P_MASK (0x1 << 6) |
| 711 | #define RT5660_MB2_OC_P_SFT 6 |
| 712 | #define RT5660_MB2_OC_P_NOR (0x0 << 6) |
| 713 | #define RT5660_MB2_OC_P_INV (0x1 << 6) |
| 714 | #define RT5660_MB1_OC_CLR (0x1 << 3) |
| 715 | #define RT5660_MB1_OC_CLR_SFT 3 |
| 716 | #define RT5660_MB2_OC_CLR (0x1 << 2) |
| 717 | #define RT5660_MB2_OC_CLR_SFT 2 |
| 718 | |
| 719 | /* GPIO Control 1 (0xc0) */ |
| 720 | #define RT5660_GP2_PIN_MASK (0x1 << 14) |
| 721 | #define RT5660_GP2_PIN_SFT 14 |
| 722 | #define RT5660_GP2_PIN_GPIO2 (0x0 << 14) |
| 723 | #define RT5660_GP2_PIN_DMIC1_SDA (0x1 << 14) |
| 724 | #define RT5660_GP1_PIN_MASK (0x3 << 12) |
| 725 | #define RT5660_GP1_PIN_SFT 12 |
| 726 | #define RT5660_GP1_PIN_GPIO1 (0x0 << 12) |
| 727 | #define RT5660_GP1_PIN_DMIC1_SCL (0x1 << 12) |
| 728 | #define RT5660_GP1_PIN_IRQ (0x2 << 12) |
| 729 | #define RT5660_GPIO_M_MASK (0x1 << 9) |
| 730 | #define RT5660_GPIO_M_SFT 9 |
| 731 | #define RT5660_GPIO_M_FLT (0x0 << 9) |
| 732 | #define RT5660_GPIO_M_PH (0x1 << 9) |
| 733 | |
| 734 | /* GPIO Control 3 (0xc2) */ |
| 735 | #define RT5660_GP2_PF_MASK (0x1 << 5) |
| 736 | #define RT5660_GP2_PF_SFT 5 |
| 737 | #define RT5660_GP2_PF_IN (0x0 << 5) |
| 738 | #define RT5660_GP2_PF_OUT (0x1 << 5) |
| 739 | #define RT5660_GP2_OUT_MASK (0x1 << 4) |
| 740 | #define RT5660_GP2_OUT_SFT 4 |
| 741 | #define RT5660_GP2_OUT_LO (0x0 << 4) |
| 742 | #define RT5660_GP2_OUT_HI (0x1 << 4) |
| 743 | #define RT5660_GP2_P_MASK (0x1 << 3) |
| 744 | #define RT5660_GP2_P_SFT 3 |
| 745 | #define RT5660_GP2_P_NOR (0x0 << 3) |
| 746 | #define RT5660_GP2_P_INV (0x1 << 3) |
| 747 | #define RT5660_GP1_PF_MASK (0x1 << 2) |
| 748 | #define RT5660_GP1_PF_SFT 2 |
| 749 | #define RT5660_GP1_PF_IN (0x0 << 2) |
| 750 | #define RT5660_GP1_PF_OUT (0x1 << 2) |
| 751 | #define RT5660_GP1_OUT_MASK (0x1 << 1) |
| 752 | #define RT5660_GP1_OUT_SFT 1 |
| 753 | #define RT5660_GP1_OUT_LO (0x0 << 1) |
| 754 | #define RT5660_GP1_OUT_HI (0x1 << 1) |
| 755 | #define RT5660_GP1_P_MASK (0x1) |
| 756 | #define RT5660_GP1_P_SFT 0 |
| 757 | #define RT5660_GP1_P_NOR (0x0) |
| 758 | #define RT5660_GP1_P_INV (0x1) |
| 759 | |
| 760 | /* Soft volume and zero cross control 1 (0xd9) */ |
| 761 | #define RT5660_SV_MASK (0x1 << 15) |
| 762 | #define RT5660_SV_SFT 15 |
| 763 | #define RT5660_SV_DIS (0x0 << 15) |
| 764 | #define RT5660_SV_EN (0x1 << 15) |
| 765 | #define RT5660_SPO_SV_MASK (0x1 << 14) |
| 766 | #define RT5660_SPO_SV_SFT 14 |
| 767 | #define RT5660_SPO_SV_DIS (0x0 << 14) |
| 768 | #define RT5660_SPO_SV_EN (0x1 << 14) |
| 769 | #define RT5660_OUT_SV_MASK (0x1 << 12) |
| 770 | #define RT5660_OUT_SV_SFT 12 |
| 771 | #define RT5660_OUT_SV_DIS (0x0 << 12) |
| 772 | #define RT5660_OUT_SV_EN (0x1 << 12) |
| 773 | #define RT5660_ZCD_DIG_MASK (0x1 << 11) |
| 774 | #define RT5660_ZCD_DIG_SFT 11 |
| 775 | #define RT5660_ZCD_DIG_DIS (0x0 << 11) |
| 776 | #define RT5660_ZCD_DIG_EN (0x1 << 11) |
| 777 | #define RT5660_ZCD_MASK (0x1 << 10) |
| 778 | #define RT5660_ZCD_SFT 10 |
| 779 | #define RT5660_ZCD_PD (0x0 << 10) |
| 780 | #define RT5660_ZCD_PU (0x1 << 10) |
| 781 | #define RT5660_SV_DLY_MASK (0xf) |
| 782 | #define RT5660_SV_DLY_SFT 0 |
| 783 | |
| 784 | /* Soft volume and zero cross control 2 (0xda) */ |
| 785 | #define RT5660_ZCD_SPO_MASK (0x1 << 15) |
| 786 | #define RT5660_ZCD_SPO_SFT 15 |
| 787 | #define RT5660_ZCD_SPO_DIS (0x0 << 15) |
| 788 | #define RT5660_ZCD_SPO_EN (0x1 << 15) |
| 789 | #define RT5660_ZCD_OMR_MASK (0x1 << 8) |
| 790 | #define RT5660_ZCD_OMR_SFT 8 |
| 791 | #define RT5660_ZCD_OMR_DIS (0x0 << 8) |
| 792 | #define RT5660_ZCD_OMR_EN (0x1 << 8) |
| 793 | #define RT5660_ZCD_OML_MASK (0x1 << 7) |
| 794 | #define RT5660_ZCD_OML_SFT 7 |
| 795 | #define RT5660_ZCD_OML_DIS (0x0 << 7) |
| 796 | #define RT5660_ZCD_OML_EN (0x1 << 7) |
| 797 | #define RT5660_ZCD_SPM_MASK (0x1 << 6) |
| 798 | #define RT5660_ZCD_SPM_SFT 6 |
| 799 | #define RT5660_ZCD_SPM_DIS (0x0 << 6) |
| 800 | #define RT5660_ZCD_SPM_EN (0x1 << 6) |
| 801 | #define RT5660_ZCD_RMR_MASK (0x1 << 5) |
| 802 | #define RT5660_ZCD_RMR_SFT 5 |
| 803 | #define RT5660_ZCD_RMR_DIS (0x0 << 5) |
| 804 | #define RT5660_ZCD_RMR_EN (0x1 << 5) |
| 805 | #define RT5660_ZCD_RML_MASK (0x1 << 4) |
| 806 | #define RT5660_ZCD_RML_SFT 4 |
| 807 | #define RT5660_ZCD_RML_DIS (0x0 << 4) |
| 808 | #define RT5660_ZCD_RML_EN (0x1 << 4) |
| 809 | |
| 810 | /* General Control 1 (0xfa) */ |
| 811 | #define RT5660_PWR_VREF_HP (0x1 << 11) |
| 812 | #define RT5660_PWR_VREF_HP_SFT 11 |
| Bard Liao | d01580c | 2016-10-20 10:13:44 +0800 | [diff] [blame^] | 813 | #define RT5660_AUTO_DIS_AMP (0x1 << 6) |
| 814 | #define RT5660_MCLK_DET (0x1 << 5) |
| 815 | #define RT5660_POW_CLKDET (0x1 << 1) |
| Oder Chiou | 2b26dd4 | 2016-09-19 19:26:08 +0800 | [diff] [blame] | 816 | #define RT5660_DIG_GATE_CTRL (0x1) |
| 817 | #define RT5660_DIG_GATE_CTRL_SFT 0 |
| 818 | |
| 819 | /* System Clock Source */ |
| 820 | #define RT5660_SCLK_S_MCLK 0 |
| 821 | #define RT5660_SCLK_S_PLL1 1 |
| 822 | #define RT5660_SCLK_S_RCCLK 2 |
| 823 | |
| 824 | /* PLL1 Source */ |
| 825 | #define RT5660_PLL1_S_MCLK 0 |
| 826 | #define RT5660_PLL1_S_BCLK 1 |
| 827 | |
| 828 | enum { |
| 829 | RT5660_AIF1, |
| 830 | RT5660_AIFS, |
| 831 | }; |
| 832 | |
| 833 | struct rt5660_priv { |
| 834 | struct snd_soc_codec *codec; |
| 835 | struct rt5660_platform_data pdata; |
| 836 | struct regmap *regmap; |
| 837 | struct clk *mclk; |
| 838 | |
| 839 | int sysclk; |
| 840 | int sysclk_src; |
| 841 | int lrck[RT5660_AIFS]; |
| 842 | int bclk[RT5660_AIFS]; |
| 843 | int master[RT5660_AIFS]; |
| 844 | |
| 845 | int pll_src; |
| 846 | int pll_in; |
| 847 | int pll_out; |
| 848 | }; |
| 849 | |
| 850 | #endif |