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review.shift-gmbh.com / SHIFTPHONES / mainline / linux / cd7bed00340475ee72a013a070e200e065085ef3 / . / drivers / spi / spi-pxa2xx.h
blob: 0a98905c916e89affcd9d1a3b68b43f71ea2a543 [file] [log] [blame]
Mika Westerbergcd7bed02013-01-22 12:26:28 +0200[diff] [blame^]1/*
2 * Copyright (C) 2005 Stephen Street / StreetFire Sound Labs
3 * Copyright (C) 2013, Intel Corporation
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 */
9
10#ifndef SPI_PXA2XX_H
11#define SPI_PXA2XX_H
12
13#include <linux/errno.h>
14#include <linux/io.h>
15#include <linux/interrupt.h>
16#include <linux/platform_device.h>
17#include <linux/pxa2xx_ssp.h>
18#include <linux/spi/spi.h>
19#include <linux/spi/pxa2xx_spi.h>
20
21struct driver_data {
22 /* Driver model hookup */
23 struct platform_device *pdev;
24
25 /* SSP Info */
26 struct ssp_device *ssp;
27
28 /* SPI framework hookup */
29 enum pxa_ssp_type ssp_type;
30 struct spi_master *master;
31
32 /* PXA hookup */
33 struct pxa2xx_spi_master *master_info;
34
35 /* PXA private DMA setup stuff */
36 int rx_channel;
37 int tx_channel;
38 u32 *null_dma_buf;
39
40 /* SSP register addresses */
41 void __iomem *ioaddr;
42 u32 ssdr_physical;
43
44 /* SSP masks*/
45 u32 dma_cr1;
46 u32 int_cr1;
47 u32 clear_sr;
48 u32 mask_sr;
49
50 /* Maximun clock rate */
51 unsigned long max_clk_rate;
52
53 /* Message Transfer pump */
54 struct tasklet_struct pump_transfers;
55
56 /* Current message transfer state info */
57 struct spi_message *cur_msg;
58 struct spi_transfer *cur_transfer;
59 struct chip_data *cur_chip;
60 size_t len;
61 void *tx;
62 void *tx_end;
63 void *rx;
64 void *rx_end;
65 int dma_mapped;
66 dma_addr_t rx_dma;
67 dma_addr_t tx_dma;
68 size_t rx_map_len;
69 size_t tx_map_len;
70 u8 n_bytes;
71 int (*write)(struct driver_data *drv_data);
72 int (*read)(struct driver_data *drv_data);
73 irqreturn_t (*transfer_handler)(struct driver_data *drv_data);
74 void (*cs_control)(u32 command);
75};
76
77struct chip_data {
78 u32 cr0;
79 u32 cr1;
80 u32 psp;
81 u32 timeout;
82 u8 n_bytes;
83 u32 dma_burst_size;
84 u32 threshold;
85 u32 dma_threshold;
86 u8 enable_dma;
87 u8 bits_per_word;
88 u32 speed_hz;
89 union {
90 int gpio_cs;
91 unsigned int frm;
92 };
93 int gpio_cs_inverted;
94 int (*write)(struct driver_data *drv_data);
95 int (*read)(struct driver_data *drv_data);
96 void (*cs_control)(u32 command);
97};
98
99#define DEFINE_SSP_REG(reg, off) \
100static inline u32 read_##reg(void const __iomem *p) \
101{ return __raw_readl(p + (off)); } \
102\
103static inline void write_##reg(u32 v, void __iomem *p) \
104{ __raw_writel(v, p + (off)); }
105
106DEFINE_SSP_REG(SSCR0, 0x00)
107DEFINE_SSP_REG(SSCR1, 0x04)
108DEFINE_SSP_REG(SSSR, 0x08)
109DEFINE_SSP_REG(SSITR, 0x0c)
110DEFINE_SSP_REG(SSDR, 0x10)
111DEFINE_SSP_REG(SSTO, 0x28)
112DEFINE_SSP_REG(SSPSP, 0x2c)
113
114#define START_STATE ((void *)0)
115#define RUNNING_STATE ((void *)1)
116#define DONE_STATE ((void *)2)
117#define ERROR_STATE ((void *)-1)
118
119#define MAX_DMA_LEN 8191
120#define IS_DMA_ALIGNED(x) IS_ALIGNED((unsigned long)(x), DMA_ALIGNMENT)
121#define DMA_ALIGNMENT 8
122
123static inline int pxa25x_ssp_comp(struct driver_data *drv_data)
124{
125 if (drv_data->ssp_type == PXA25x_SSP)
126 return 1;
127 if (drv_data->ssp_type == CE4100_SSP)
128 return 1;
129 return 0;
130}
131
132static inline void write_SSSR_CS(struct driver_data *drv_data, u32 val)
133{
134 void __iomem *reg = drv_data->ioaddr;
135
136 if (drv_data->ssp_type == CE4100_SSP)
137 val |= read_SSSR(reg) & SSSR_ALT_FRM_MASK;
138
139 write_SSSR(val, reg);
140}
141
142extern int pxa2xx_spi_flush(struct driver_data *drv_data);
143extern void *pxa2xx_spi_next_transfer(struct driver_data *drv_data);
144
145#if defined(CONFIG_SPI_PXA2XX_PXADMA)
146extern bool pxa2xx_spi_dma_is_possible(size_t len);
147extern int pxa2xx_spi_map_dma_buffers(struct driver_data *drv_data);
148extern irqreturn_t pxa2xx_spi_dma_transfer(struct driver_data *drv_data);
149extern int pxa2xx_spi_dma_prepare(struct driver_data *drv_data, u32 dma_burst);
150extern void pxa2xx_spi_dma_start(struct driver_data *drv_data);
151extern int pxa2xx_spi_dma_setup(struct driver_data *drv_data);
152extern void pxa2xx_spi_dma_release(struct driver_data *drv_data);
153extern void pxa2xx_spi_dma_resume(struct driver_data *drv_data);
154extern int pxa2xx_spi_set_dma_burst_and_threshold(struct chip_data *chip,
155 struct spi_device *spi,
156 u8 bits_per_word,
157 u32 *burst_code,
158 u32 *threshold);
159#else
160static inline bool pxa2xx_spi_dma_is_possible(size_t len) { return false; }
161static inline int pxa2xx_spi_map_dma_buffers(struct driver_data *drv_data)
162{
163 return 0;
164}
165#define pxa2xx_spi_dma_transfer NULL
166static inline void pxa2xx_spi_dma_prepare(struct driver_data *drv_data,
167 u32 dma_burst) {}
168static inline void pxa2xx_spi_dma_start(struct driver_data *drv_data) {}
169static inline int pxa2xx_spi_dma_setup(struct driver_data *drv_data)
170{
171 return 0;
172}
173static inline void pxa2xx_spi_dma_release(struct driver_data *drv_data) {}
174static inline void pxa2xx_spi_dma_resume(struct driver_data *drv_data) {}
175static inline int pxa2xx_spi_set_dma_burst_and_threshold(struct chip_data *chip,
176 struct spi_device *spi,
177 u8 bits_per_word,
178 u32 *burst_code,
179 u32 *threshold)
180{
181 return -ENODEV;
182}
183#endif
184
185#endif /* SPI_PXA2XX_H */