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review.shift-gmbh.com / SHIFTPHONES / mainline / linux / ccf51c1cedfd5bd1a0ecf6a33059dbdab3d3a9ef / . / Documentation / devicetree / bindings / phy / qcom,qmp-phy.yaml
blob: dcdb014d6d4de1a56483b4c3f6390a6f4574c57c [file] [log] [blame]
Sandeep Maheswaramccf51c12020-05-15 08:09:15 +0530[diff] [blame^]1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2
3%YAML 1.2
4---
5$id: "http://devicetree.org/schemas/phy/qcom,qmp-phy.yaml#"
6$schema: "http://devicetree.org/meta-schemas/core.yaml#"
7
8title: Qualcomm QMP PHY controller
9
10maintainers:
11 - Manu Gautam <mgautam@codeaurora.org>
12
13description:
14 QMP phy controller supports physical layer functionality for a number of
15 controllers on Qualcomm chipsets, such as, PCIe, UFS, and USB.
16
17properties:
18 compatible:
19 enum:
20 - qcom,ipq8074-qmp-pcie-phy
21 - qcom,msm8996-qmp-pcie-phy
22 - qcom,msm8996-qmp-ufs-phy
23 - qcom,msm8996-qmp-usb3-phy
24 - qcom,msm8998-qmp-pcie-phy
25 - qcom,msm8998-qmp-ufs-phy
26 - qcom,msm8998-qmp-usb3-phy
27 - qcom,sdm845-qhp-pcie-phy
28 - qcom,sdm845-qmp-pcie-phy
29 - qcom,sdm845-qmp-ufs-phy
30 - qcom,sdm845-qmp-usb3-phy
31 - qcom,sdm845-qmp-usb3-uni-phy
32 - qcom,sm8150-qmp-ufs-phy
33 - qcom,sm8250-qmp-ufs-phy
34
35 reg:
36 minItems: 1
37 items:
38 - description: Address and length of PHY's common serdes block.
39 - description: Address and length of the DP_COM control block.
40
41 reg-names:
42 items:
43 - const: reg-base
44 - const: dp_com
45
46 "#clock-cells":
47 enum: [ 1, 2 ]
48
49 "#address-cells":
50 enum: [ 1, 2 ]
51
52 "#size-cells":
53 enum: [ 1, 2 ]
54
55 clocks:
56 minItems: 1
57 maxItems: 4
58
59 clock-names:
60 minItems: 1
61 maxItems: 4
62
63 resets:
64 minItems: 1
65 maxItems: 3
66
67 reset-names:
68 minItems: 1
69 maxItems: 3
70
71 vdda-phy-supply:
72 description:
73 Phandle to a regulator supply to PHY core block.
74
75 vdda-pll-supply:
76 description:
77 Phandle to 1.8V regulator supply to PHY refclk pll block.
78
79 vddp-ref-clk-supply:
80 description:
81 Phandle to a regulator supply to any specific refclk
82 pll block.
83
84#Required nodes:
85patternProperties:
86 "^phy@[0-9a-f]+$":
87 type: object
88 description:
89 Each device node of QMP phy is required to have as many child nodes as
90 the number of lanes the PHY has.
91
92required:
93 - compatible
94 - reg
95 - "#clock-cells"
96 - "#address-cells"
97 - "#size-cells"
98 - clocks
99 - clock-names
100 - resets
101 - reset-names
102 - vdda-phy-supply
103 - vdda-pll-supply
104
105additionalProperties: false
106
107allOf:
108 - if:
109 properties:
110 compatible:
111 contains:
112 enum:
113 - qcom,sdm845-qmp-usb3-phy
114 - qcom,sdm845-qmp-usb3-uni-phy
115 then:
116 properties:
117 clocks:
118 items:
119 - description: Phy aux clock.
120 - description: Phy config clock.
121 - description: 19.2 MHz ref clk.
122 - description: Phy common block aux clock.
123 clock-names:
124 items:
125 - const: aux
126 - const: cfg_ahb
127 - const: ref
128 - const: com_aux
129 resets:
130 items:
131 - description: reset of phy block.
132 - description: phy common block reset.
133 reset-names:
134 items:
135 - const: phy
136 - const: common
137 - if:
138 properties:
139 compatible:
140 contains:
141 enum:
142 - qcom,msm8996-qmp-pcie-phy
143 then:
144 properties:
145 clocks:
146 items:
147 - description: Phy aux clock.
148 - description: Phy config clock.
149 - description: 19.2 MHz ref clk.
150 clock-names:
151 items:
152 - const: aux
153 - const: cfg_ahb
154 - const: ref
155 resets:
156 items:
157 - description: reset of phy block.
158 - description: phy common block reset.
159 - description: phy's ahb cfg block reset.
160 reset-names:
161 items:
162 - const: phy
163 - const: common
164 - const: cfg
165 - if:
166 properties:
167 compatible:
168 contains:
169 enum:
170 - qcom,msm8996-qmp-usb3-phy
171 - qcom,msm8998-qmp-pcie-phy
172 - qcom,msm8998-qmp-usb3-phy
173 then:
174 properties:
175 clocks:
176 items:
177 - description: Phy aux clock.
178 - description: Phy config clock.
179 - description: 19.2 MHz ref clk.
180 clock-names:
181 items:
182 - const: aux
183 - const: cfg_ahb
184 - const: ref
185 resets:
186 items:
187 - description: reset of phy block.
188 - description: phy common block reset.
189 reset-names:
190 items:
191 - const: phy
192 - const: common
193 - if:
194 properties:
195 compatible:
196 contains:
197 enum:
198 - qcom,msm8996-qmp-ufs-phy
199 then:
200 properties:
201 clocks:
202 items:
203 - description: 19.2 MHz ref clk.
204 clock-names:
205 items:
206 - const: ref
207 resets:
208 items:
209 - description: PHY reset in the UFS controller.
210 reset-names:
211 items:
212 - const: ufsphy
213 - if:
214 properties:
215 compatible:
216 contains:
217 enum:
218 - qcom,msm8998-qmp-ufs-phy
219 - qcom,sdm845-qmp-ufs-phy
220 - qcom,sm8150-qmp-ufs-phy
221 - qcom,sm8250-qmp-ufs-phy
222 then:
223 properties:
224 clocks:
225 items:
226 - description: 19.2 MHz ref clk.
227 - description: Phy reference aux clock.
228 clock-names:
229 items:
230 - const: ref
231 - const: ref_aux
232 resets:
233 items:
234 - description: PHY reset in the UFS controller.
235 reset-names:
236 items:
237 - const: ufsphy
238 - if:
239 properties:
240 compatible:
241 contains:
242 enum:
243 - qcom,ipq8074-qmp-pcie-phy
244 then:
245 properties:
246 clocks:
247 items:
248 - description: pipe clk.
249 clock-names:
250 items:
251 - const: pipe_clk
252 resets:
253 items:
254 - description: reset of phy block.
255 - description: phy common block reset.
256 reset-names:
257 items:
258 - const: phy
259 - const: common
260 - if:
261 properties:
262 compatible:
263 contains:
264 enum:
265 - qcom,sdm845-qhp-pcie-phy
266 - qcom,sdm845-qmp-pcie-phy
267 then:
268 properties:
269 clocks:
270 items:
271 - description: Phy aux clock.
272 - description: Phy config clock.
273 - description: 19.2 MHz ref clk.
274 - description: Phy refgen clk.
275 clock-names:
276 items:
277 - const: aux
278 - const: cfg_ahb
279 - const: ref
280 - const: refgen
281 resets:
282 items:
283 - description: reset of phy block.
284 reset-names:
285 items:
286 - const: phy
287 - if:
288 properties:
289 compatible:
290 contains:
291 const: qcom,sdm845-qmp-usb3-phy
292 then:
293 required:
294 - reg-names
295
296examples:
297 - |
298 #include <dt-bindings/clock/qcom,gcc-sdm845.h>
299 usb_1_qmpphy: phy-wrapper@88e9000 {
300 compatible = "qcom,sdm845-qmp-usb3-phy";
301 reg = <0 0x088e9000 0 0x18c>,
302 <0 0x088e8000 0 0x10>;
303 reg-names = "reg-base", "dp_com";
304 #clock-cells = <1>;
305 #address-cells = <2>;
306 #size-cells = <2>;
307
308 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
309 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
310 <&gcc GCC_USB3_PRIM_CLKREF_CLK>,
311 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>;
312 clock-names = "aux", "cfg_ahb", "ref", "com_aux";
313
314 resets = <&gcc GCC_USB3_PHY_PRIM_BCR>,
315 <&gcc GCC_USB3_DP_PHY_PRIM_BCR>;
316 reset-names = "phy", "common";
317
318 vdda-phy-supply = <&vdda_usb2_ss_1p2>;
319 vdda-pll-supply = <&vdda_usb2_ss_core>;
320
321 usb_1_ssphy: phy@88e9200 {
322 reg = <0 0x088e9200 0 0x128>,
323 <0 0x088e9400 0 0x200>,
324 <0 0x088e9c00 0 0x218>,
325 <0 0x088e9600 0 0x128>,
326 <0 0x088e9800 0 0x200>,
327 <0 0x088e9a00 0 0x100>;
328 #clock-cells = <0>;
329 #phy-cells = <0>;
330 clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
331 clock-names = "pipe0";
332 clock-output-names = "usb3_phy_pipe_clk_src";
333 };
334 };