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review.shift-gmbh.com / SHIFTPHONES / mainline / linux / c979dbf59987f4114fdbd491c8ad254343a430fd / . / drivers / reset / Kconfig
blob: 2c8c23db92fb29e8ebdd04212da41ab6ec2a7162 [file] [log] [blame]
Philipp Zabel61fc4132012-11-19 17:23:13 +0100[diff] [blame]1config ARCH_HAS_RESET_CONTROLLER
2 bool
3
4menuconfig RESET_CONTROLLER
5 bool "Reset Controller Support"
6 default y if ARCH_HAS_RESET_CONTROLLER
7 help
8 Generic Reset Controller support.
9
10 This framework is designed to abstract reset handling of devices
11 via GPIOs or SoC-internal reset controller modules.
12
13 If unsure, say no.
Stephen Gallimoree5d76072013-08-07 15:53:12 +0100[diff] [blame]14
Masahiro Yamada998cd462016-05-03 15:29:52 +0900[diff] [blame]15if RESET_CONTROLLER
16
Thor Thayer62700682017-02-22 11:10:17 -0600[diff] [blame]17config RESET_A10SR
18 tristate "Altera Arria10 System Resource Reset"
19 depends on MFD_ALTERA_A10SR
20 help
21 This option enables support for the external reset functions for
22 peripheral PHYs on the Altera Arria10 System Resource Chip.
23
Philipp Zabele27b4a62016-07-28 15:30:08 +0200[diff] [blame]24config RESET_ATH79
25 bool "AR71xx Reset Driver" if COMPILE_TEST
26 default ATH79
27 help
28 This enables the ATH79 reset controller driver that supports the
29 AR71xx SoC reset controller.
30
Eugeniy Paltsev37634922017-09-14 17:28:42 +0300[diff] [blame]31config RESET_AXS10X
32 bool "AXS10x Reset Driver" if COMPILE_TEST
33 default ARC_PLAT_AXS10X
34 help
35 This enables the reset controller driver for AXS10x.
36
Philipp Zabel70d467e2016-07-28 15:31:12 +0200[diff] [blame]37config RESET_BERLIN
38 bool "Berlin Reset Driver" if COMPILE_TEST
39 default ARCH_BERLIN
40 help
41 This enables the reset controller driver for Marvell Berlin SoCs.
42
Florian Fainelli77750bc2019-01-23 14:54:36 -0800[diff] [blame]43config RESET_BRCMSTB
44 tristate "Broadcom STB reset controller"
45 depends on ARCH_BRCMSTB || COMPILE_TEST
46 default ARCH_BRCMSTB
47 help
48 This enables the reset controller driver for Broadcom STB SoCs using
49 a SUN_TOP_CTRL_SW_INIT style controller.
50
Vineet Gupta13541222017-08-31 11:06:07 -0700[diff] [blame]51config RESET_HSDK
52 bool "Synopsys HSDK Reset Driver"
Thomas Meyer2d48a232017-09-09 06:02:46 +0200[diff] [blame]53 depends on HAS_IOMEM
Geert Uytterhoeven544e3bf2017-09-11 14:22:08 +0200[diff] [blame]54 depends on ARC_SOC_HSDK || COMPILE_TEST
Eugeniy Paltseve0be8642017-07-19 21:45:11 +0300[diff] [blame]55 help
Vineet Gupta13541222017-08-31 11:06:07 -0700[diff] [blame]56 This enables the reset controller driver for HSDK board.
Eugeniy Paltseve0be8642017-07-19 21:45:11 +0300[diff] [blame]57
Andrey Smirnovabf97752017-02-21 08:13:31 -0800[diff] [blame]58config RESET_IMX7
Andrey Smirnovc979dbf2019-01-21 18:10:43 -0800[diff] [blame^]59 bool "i.MX7/8 Reset Driver" if COMPILE_TEST
Masahiro Yamada8fa56622018-03-06 20:15:11 +0900[diff] [blame]60 depends on HAS_IOMEM
Andrey Smirnovc979dbf2019-01-21 18:10:43 -0800[diff] [blame^]61 default SOC_IMX7D || (ARM64 && ARCH_MXC)
Andrey Smirnovabf97752017-02-21 08:13:31 -0800[diff] [blame]62 select MFD_SYSCON
63 help
64 This enables the reset controller driver for i.MX7 SoCs.
65
Martin Blumenstingl79797b62017-08-20 00:18:17 +0200[diff] [blame]66config RESET_LANTIQ
67 bool "Lantiq XWAY Reset Driver" if COMPILE_TEST
68 default SOC_TYPE_XWAY
69 help
70 This enables the reset controller driver for Lantiq / Intel XWAY SoCs.
71
Philipp Zabelcd7f4b82016-07-28 15:32:01 +0200[diff] [blame]72config RESET_LPC18XX
73 bool "LPC18xx/43xx Reset Driver" if COMPILE_TEST
74 default ARCH_LPC18XX
75 help
76 This enables the reset controller driver for NXP LPC18xx/43xx SoCs.
77
Philipp Zabel44336c22016-07-28 15:32:36 +0200[diff] [blame]78config RESET_MESON
79 bool "Meson Reset Driver" if COMPILE_TEST
80 default ARCH_MESON
81 help
82 This enables the reset driver for Amlogic Meson SoCs.
83
Jerome Brunetd9037792018-07-20 17:26:33 +0200[diff] [blame]84config RESET_MESON_AUDIO_ARB
85 tristate "Meson Audio Memory Arbiter Reset Driver"
86 depends on ARCH_MESON || COMPILE_TEST
87 help
88 This enables the reset driver for Audio Memory Arbiter of
89 Amlogic's A113 based SoCs
90
Neil Armstrong6e667fa2016-04-01 16:16:13 +0200[diff] [blame]91config RESET_OXNAS
92 bool
93
Philipp Zabelfab3f732016-07-28 15:33:07 +0200[diff] [blame]94config RESET_PISTACHIO
95 bool "Pistachio Reset Driver" if COMPILE_TEST
96 default MACH_PISTACHIO
97 help
98 This enables the reset driver for ImgTec Pistachio SoCs.
99
Sibi Sankar5ecb0652018-06-27 19:54:43 +0530[diff] [blame]100config RESET_QCOM_AOSS
101 bool "Qcom AOSS Reset Driver"
102 depends on ARCH_QCOM || COMPILE_TEST
103 help
104 This enables the AOSS (always on subsystem) reset driver
105 for Qualcomm SDM845 SoCs. Say Y if you want to control
106 reset signals provided by AOSS for Modem, Venus, ADSP,
107 GPU, Camera, Wireless, Display subsystem. Otherwise, say N.
108
Sibi Sankareea29262018-08-30 00:42:11 +0530[diff] [blame]109config RESET_QCOM_PDC
110 tristate "Qualcomm PDC Reset Driver"
111 depends on ARCH_QCOM || COMPILE_TEST
112 help
113 This enables the PDC (Power Domain Controller) reset driver
114 for Qualcomm Technologies Inc SDM845 SoCs. Say Y if you want
115 to control reset signals provided by PDC for Modem, Compute,
116 Display, GPU, Debug, AOP, Sensors, Audio, SP and APPS.
117
Philipp Zabel81c22ad2017-08-11 12:58:43 +0200[diff] [blame]118config RESET_SIMPLE
119 bool "Simple Reset Controller Driver" if COMPILE_TEST
Dinh Nguyenb3ca9882018-11-13 12:50:48 -0600[diff] [blame]120 default ARCH_STM32 || ARCH_STRATIX10 || ARCH_SUNXI || ARCH_ZX || ARCH_ASPEED
Philipp Zabel81c22ad2017-08-11 12:58:43 +0200[diff] [blame]121 help
122 This enables a simple reset controller driver for reset lines that
123 that can be asserted and deasserted by toggling bits in a contiguous,
124 exclusive register space.
125
Joel Stanley1d7592f2018-02-20 12:13:29 +1030[diff] [blame]126 Currently this driver supports:
127 - Altera SoCFPGAs
128 - ASPEED BMC SoCs
129 - RCC reset controller in STM32 MCUs
130 - Allwinner SoCs
131 - ZTE's zx2967 family
Philipp Zabel7e0e9012016-07-28 15:34:15 +0200[diff] [blame]132
Gabriel Fernandez197858b2018-03-19 08:25:51 +0100[diff] [blame]133config RESET_STM32MP157
134 bool "STM32MP157 Reset Driver" if COMPILE_TEST
135 default MACH_STM32MP157
136 help
137 This enables the RCC reset controller driver for STM32 MPUs.
138
Dinh Nguyenb3ca9882018-11-13 12:50:48 -0600[diff] [blame]139config RESET_SOCFPGA
140 bool "SoCFPGA Reset Driver" if COMPILE_TEST && !ARCH_SOCFPGA
141 default ARCH_SOCFPGA
142 select RESET_SIMPLE
143 help
144 This enables the reset driver for the SoCFPGA ARMv7 platforms. This
145 driver gets initialized early during platform init calls.
146
Philipp Zabel0ae08412016-08-09 09:28:44 +0200[diff] [blame]147config RESET_SUNXI
148 bool "Allwinner SoCs Reset Driver" if COMPILE_TEST && !ARCH_SUNXI
149 default ARCH_SUNXI
Philipp Zabele13c2052017-08-11 12:58:43 +0200[diff] [blame]150 select RESET_SIMPLE
Philipp Zabel0ae08412016-08-09 09:28:44 +0200[diff] [blame]151 help
152 This enables the reset driver for Allwinner SoCs.
153
Andrew F. Davis28df1692017-05-24 13:09:30 -0500[diff] [blame]154config RESET_TI_SCI
155 tristate "TI System Control Interface (TI-SCI) reset driver"
156 depends on TI_SCI_PROTOCOL
157 help
158 This enables the reset driver support over TI System Control Interface
159 available on some new TI's SoCs. If you wish to use reset resources
160 managed by the TI System Controller, say Y here. Otherwise, say N.
161
Suman Annadd9bf862017-05-23 22:00:12 -0500[diff] [blame]162config RESET_TI_SYSCON
Andrew F. Daviscc7c2bb2016-06-27 12:12:17 -0500[diff] [blame]163 tristate "TI SYSCON Reset Driver"
164 depends on HAS_IOMEM
165 select MFD_SYSCON
166 help
167 This enables the reset driver support for TI devices with
168 memory-mapped reset registers as part of a syscon device node. If
169 you wish to use the reset framework for such memory-mapped devices,
170 say Y here. Otherwise, say N.
171
Masahiro Yamada54e991b2016-08-02 13:18:29 +0900[diff] [blame]172config RESET_UNIPHIER
173 tristate "Reset controller driver for UniPhier SoCs"
174 depends on ARCH_UNIPHIER || COMPILE_TEST
175 depends on OF && MFD_SYSCON
176 default ARCH_UNIPHIER
177 help
178 Support for reset controllers on UniPhier SoCs.
179 Say Y if you want to control reset signals provided by System Control
180 block, Media I/O block, Peripheral Block.
181
Kunihiko Hayashi3eb8f762018-11-09 10:42:05 +0900[diff] [blame]182config RESET_UNIPHIER_GLUE
183 tristate "Reset driver in glue layer for UniPhier SoCs"
Kunihiko Hayashi499fef02018-07-10 10:14:17 +0900[diff] [blame]184 depends on (ARCH_UNIPHIER || COMPILE_TEST) && OF
185 default ARCH_UNIPHIER
186 select RESET_SIMPLE
187 help
Kunihiko Hayashi3eb8f762018-11-09 10:42:05 +0900[diff] [blame]188 Support for peripheral core reset included in its own glue layer
189 on UniPhier SoCs. Say Y if you want to control reset signals
190 provided by the glue layer.
Kunihiko Hayashi499fef02018-07-10 10:14:17 +0900[diff] [blame]191
Philipp Zabel6f51b862016-08-09 09:28:54 +0200[diff] [blame]192config RESET_ZYNQ
193 bool "ZYNQ Reset Driver" if COMPILE_TEST
194 default ARCH_ZYNQ
195 help
196 This enables the reset controller driver for Xilinx Zynq SoCs.
197
Stephen Gallimoree5d76072013-08-07 15:53:12 +0100[diff] [blame]198source "drivers/reset/sti/Kconfig"
Chen Fengf59d23c2015-11-20 10:10:05 +0800[diff] [blame]199source "drivers/reset/hisilicon/Kconfig"
Thierry Redingdc606c52016-08-18 15:50:09 +0200[diff] [blame]200source "drivers/reset/tegra/Kconfig"
Masahiro Yamada998cd462016-05-03 15:29:52 +0900[diff] [blame]201
202endif